JP2006171913A - Information processor, information processing method, program and storage medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the scale of a circuit, and to reduce a verification load at the time of generating the circuit in an RT level described in HDL language based on an algorithm described in C language. <P>SOLUTION: This information processing method for converting a file described in C language into a file in a register transfer level described in HDL language comprises an extraction process (a step S201) for extracting functions included in a file described in the C language, a determination process (steps S202, 203) for determining whether or not a circuit in the register transfer level corresponding to the extracted functions is stored in a database and a generation process (steps S205, 206) for, when it is determined that the circuit in the register transfer level is stored in the database, generating the file in the register transfer level by replacing the extracted functions with a circuit stored in the database. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technology for conversion to a HDL language (Hardware Description Language (hardware description language)), which is a programming language used for circuit design of a semiconductor device.

  Conventionally, the HDL language, which is a dedicated programming language, has been used in the circuit design of semiconductor devices. On the other hand, C language is often used in algorithm development. For this reason, until now, after developing an algorithm using the C language, it was necessary to re-write the algorithm developed in the C language into the HDL language after considering the architecture at the time of hardware implementation. It was.

  On the other hand, with the development of semiconductor process technology, the realizable circuit scale has increased rapidly in recent years. However, the above-described design method has a limit to cope with the increased circuit scale even if the number of manpower for circuit design is increased. Therefore, improvement of circuit design productivity by a new method has been desired.

Against this background, a behavioral synthesis device having a behavioral synthesis function for converting a behavioral level algorithm described in C language into an RT level (register transfer level) circuit described in HDL language has been proposed. Some have begun to be put into practical use.
JP 2003-173270 A

  However, in the conventional technology, when an algorithm of an operation level described using a C language having a high level of abstraction is converted into an RT level circuit described in the HDL language, the algorithm is compared with a circuit described directly in the HDL language. There was a problem that the circuit scale would increase. Moreover, since the RT level circuit described in the HDL language has low readability, it cannot be determined from the description in the HDL language whether the circuit generated by the behavioral synthesis device is a desired circuit in terms of function and quality. There was also a problem that operation verification had to be performed.

  The present invention has been made in view of the above problems, and in generating an RT level circuit described in an HDL language based on an algorithm of an operation level described in a predetermined language, the circuit can be reduced in size. The purpose is to reduce the verification load.

In order to achieve the above object, an information processing apparatus according to the present invention comprises the following arrangement. That is,
An information processing apparatus for converting a file described in a predetermined language into a register transfer level file described in an HDL language,
Storage means for storing a register transfer level circuit described in the HDL language;
An extraction means for reading a file described in the predetermined language and extracting a function included in the file;
Determining means for determining whether or not a register transfer level circuit described in the HDL language corresponding to the function extracted by the extracting means is stored in the storage means;
If the determination means determines that the data is stored in the storage means, a register transfer level file described in the HDL language is generated using the circuit stored in the storage means. If the determination means determines that the function is not stored in the storage means, the function extracted by the extraction means is converted into a register transfer level circuit described in the HDL language. And generating means for generating a register transfer level file described in the HDL language.

  When generating an RT level circuit described in an HDL language based on an algorithm of an operation level described in a predetermined language, it is possible to reduce the size of the circuit and reduce the verification load.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings as necessary.

[First Embodiment]
<Configuration of behavioral synthesis device>
A configuration of a behavioral synthesis apparatus (information processing apparatus) according to an embodiment of the present invention will be described with reference to FIG. In FIG. 1, 101 is a control memory (ROM), 102 is a central processing unit, 103 is a memory (RAM), 104 is an input device, 105 is a display device, 106 is an external storage device, and 109 is a bus. A database 108 composed of a control program (behavior synthesis program 107) for realizing the behavioral synthesis function according to the present embodiment and data (HDL assets) used in the control program is stored in the external storage device 106. These control programs and data are appropriately fetched into the memory 103 through the bus 107 under the control of the central processing unit 102 and executed by the central processing unit 102.

<Flow of behavioral synthesis processing in behavioral synthesis device>
FIG. 2 shows a behavioral synthesis apparatus according to an embodiment of the present invention, in which the “HDL language” described in the HDL language from the “C language behavior level description file” describing the algorithm of the behavioral level to be circuit designed in the C language. It is the flowchart which showed the procedure of the behavioral synthesis process which produces | generates "RT level description file".

  As shown in the figure, in step S201, a C language behavior level description file is first read. This C language behavior level description file may be a C circuit described with a specific circuit described in the HDL language, or may be described with a higher level of abstraction. I do not care. Further, the C language used in the C language behavior level description file may be a C language conforming to general ANSI-C. Therefore, this C language behavior level description file can be used as it is even if it is described for study at the time of algorithm development.

  In step S202, a function defined by “function” is extracted from the C language behavior level description file, and an HDL asset (RT described in HDL language is checked for a circuit having the same name as the extracted function. Level circuit) 108 is searched.

  As a result of the database 108 search in step S202, when it is determined that the HDL asset having the same name as the extracted function exists in the database 108 (in the case of “Yes” in step S203), the process proceeds to step S205. An RT level circuit described in the HDL language is selected and instantiated.

  On the other hand, as a result of searching the database 108 in step S202, if it is determined that there is no HDL asset having the same name as the extracted function in the database 108 (in the case of “No” in step S203), the process proceeds to step S204. Then, by normal behavioral synthesis, the function extracted from the C language behavior level description file is converted into an RT level circuit described in the HDL language.

  In step S206, the connections between the respective circuits are behaviorally synthesized using the RT level circuits for the respective functions thus obtained, and an HDL language RT level description file is generated.

<Specific example of behavioral synthesis processing>
FIG. 3 is a diagram specifically showing the relationship among the C language behavior level description file, the HDL language RT level description file, and the database in the behavioral synthesis process. In this figure, 301 is an example of a C language operation description file, 302 is an example of an HDL language RT level description file, 108 is described in HDL language, and is written in HDL language having a track record as a circuit. An example of each circuit database is shown. The details of the behavioral synthesis process will be described below with reference to FIG.

  As shown in the figure, a function defined by “function” is extracted from the C language behavior level description file 301, and each of the HDL assets (RT described in the HDL language) registered with the same name in the database 108 is extracted. Search for level circuit). Then, switching between generating an RT level circuit described in the HDL language by circuit replacement or generating an RT level circuit described in the HDL language by behavioral synthesis is performed according to the search result.

  As for “IP_A3, IP_B5” defined by “function” in the C language behavior level description file 301, HDL assets (RT level circuits described in the HDL language) having the same name exist in the database 108. In generating the HDL language RT level description file 302, the corresponding circuit on the database 108 is instantiated, and behavioral synthesis is not performed (see 303 and 304).

  On the other hand, for “IP_A9, IP_C3” defined as “function” in the C language behavior level description file 301, there is an HDL resource (RT level circuit described in the HDL language) with the same name in the database 108. Therefore, RT-level circuits described in the HDL language are generated by performing behavioral synthesis (see 305 and 306).

  Next, the connection between each circuit in the HDL language RT level description file 302 is determined from the description of the argument and return value of each function in the C language behavior level description file 301, and the final HDL language RT level description file 302 is completed. To do.

  It should be noted that the HDL assets stored in the database 108 are designed for architecture, and even if they are RT level circuits described in the HDL language from the beginning, the behavioral synthesis device previously synthesized the behavior from the C language behavior level description file. It doesn't matter if it is the one that was made.

  In the former case, it is possible to prevent the hang-up of the behavioral synthesis apparatus in the difficult part of the behavioral synthesis and the decrease in development efficiency due to the generation of the impractical circuit, and immediately realize the practical circuit generation. In the latter case, the behavioral synthesis time can be shortened. In either case, efficient hardware automatic design can be performed.

<GUI of behavioral synthesis device>
FIG. 4 is a view showing a part of the GUI displayed on the display device 105 of the behavioral synthesis device according to the embodiment of the present invention. In the figure, at the top of the screen (400) is a "file" button (401) for performing file input / output relations, end of behavioral synthesis, etc., and a "setting" button (402) for performing various behavioral synthesis settings. In addition to a “behavior synthesis” button (403) for performing behavioral synthesis processing, a “report” button (404), a “management” button (405), and a “help” button (406) are prepared.

  Further, in the middle stage, a C language behavior level description file to be subjected to behavioral synthesis processing, an HDL language RT level description file that is an output file, a clock frequency that is a prerequisite for behavioral synthesis processing, an arithmetic unit library used for behavioral synthesis processing, a memory Library, an arithmetic unit constraint file that is a constraint of behavioral synthesis processing, and memory constraint files are displayed (see 407).

  In the lower row, a “C display” button (408) for displaying a C language behavior level description file to be subjected to behavioral synthesis, and an “HDL display” button for displaying a behaviorally synthesized HDL language RT level description file. (409) is prepared, and each source code is displayed by clicking. Furthermore, a “synthesis option” button (410), a “circuit replacement option” button (411), and a “circuit registration option” button (412) are prepared so that detailed settings can be made.

  FIG. 5 shows a part of the contents included in the “file” button (401) (see 501). When “Open synthesis target file (O)...” Is selected, the behavioral synthesis process is performed. A GUI for specifying a target file (C language behavior level description file) appears, and it is possible to specify a file (HDL language RT level description file) to be subjected to behavioral synthesis processing by operating according to the instruction. it can. Similarly, an output file can be specified by selecting “Save As (A)...” And performing operations according to instructions.

  FIG. 6 shows a part of the contents included in the above-mentioned “setting” button (402) (see 601). HDL language to be output by selecting “HDL selection” and operating in accordance with the instruction An RT level description file can be specified. Similarly, by selecting “CLK frequency” and operating in accordance with the instruction, it is possible to designate the clock frequency that is the premise of the behavioral synthesis process. Furthermore, the “arithmetic unit library” and “memory library” can specify the arithmetic unit and the memory library that are the premise of the behavioral synthesis process, and the “arithmetic unit constraint file” and “memory constraint file” are the premise of the behavioral synthesis process. An arithmetic unit and a memory constraint file can be specified.

  FIG. 7 shows a C language behavior level description file and an output file to be subjected to behavioral synthesis processing in a “file” button (401), and an HDL language RT level description file output by a “setting” button (402). In addition, an example in which the clock frequency which is a precondition for the behavioral synthesis process is determined and displayed in the middle stage of the screen is shown (see 407).

  FIG. 8 shows a pop-up window that appears when the “C display” button (408) and the “HDL display” button (409) are clicked after the behavioral synthesis process is performed via the screen (400) shown in FIG. (A reference numeral 801 represents a pop-up window that appears when the “Display C” button 408 is clicked, and a reference numeral 802 represents a pop-up window that appears when the “HDL display” button 409 is clicked). Here, if a part of the C language behavior level description file described in C language (the shaded part 801) is specified, the corresponding part (802 network in the HDL language RT level description file described in the HDL language). If a part of the HDL language RT level description file described in HDL language (802 shaded part) is specified, a C language behavior level description file described in C language is displayed. , The corresponding portion (shaded portion of 801) is highlighted.

  FIGS. 9 and 10 show a part of the behavior synthesis window displayed when the “behavior synthesis” button (403) is selected. When the circuit replacement is automatically performed when there is an HDL asset having the same name on the database 108, the circuit replacement is automatically performed by clicking “Auto” in the window 902 as shown in FIG.

  On the other hand, when only the function defined by a specific function is to be replaced by the HDL asset on the database 108, as shown in FIG. 10, “Specify” is clicked in the window 1002, and the function name (circuit name) is displayed in the sub window 1003. A function for replacing a circuit can be specified by entering.

  Similarly, FIGS. 11 and 12 show a part of the behavioral synthesis window displayed when the “behavioral synthesis” button (403) is selected. In the behavioral synthesis device according to the present embodiment, a registration method for registering the HDL language RT level description file obtained by behavioral synthesis processing of the C language behavior level description file described in C language in the database 108 can be selected. By clicking “Automatic” in the window 1102 of FIG. 11, the circuit in the generated HDL language RT level description file is automatically registered in the database 108.

  When a circuit having the same name as the generated HDL language RT level description file already exists in the database 108 by clicking “Do not overwrite” in the window 1102, a newly generated HDL language RT level description is generated. The file circuit is not registered in the database 108.

  Also, if “designation” is clicked in the window 1102 and only the circuit of the HDL language RT level description file to be registered in the sub-window 1201 is entered, only IP_A9 is registered, and simultaneously generated IP_C3 is not registered. Also, by clicking “Overwrite” in the window 1102, even if the circuit of the HDL language RT level description file with the same name exists in the database 108, the newly generated circuit IP_A9 is stored in the database 108. The circuit IP_A9 that has been registered and has been registered so far is deleted.

  As described above, according to the present embodiment, it is possible to automatically or appropriately specify whether the replacement by the circuit in the database or the behavioral synthesis by the behavioral synthesis device is performed for each function of the C language behavior level description file. Thus, it is possible to efficiently reduce the behavioral synthesis time and optimize / scale down the circuit. Moreover, since the circuit used for circuit replacement is a circuit with a track record, the verification load can be greatly reduced.

  As described above, in the present embodiment, a more practical circuit can be quickly created by properly using replacement in the database and behavioral synthesis by the behavioral synthesis device for each function included in the C language behavior level description file. Is possible. In addition, since the conventional HDL assets can be utilized according to the use record as a circuit, an optimal circuit can be obtained more efficiently and the circuit design period can be greatly shortened as the database is enhanced.

[Second Embodiment]
13 and 14 are diagrams showing a GUI of the behavioral synthesis device according to the second embodiment of the present invention. As shown in these figures, the present embodiment is configured such that circuit parameter settings can be selected during the behavioral synthesis process.

  As shown in FIG. 13, when the circuit parameter setting is “automatic”, when the circuit parameter is extracted from the C language behavior level description file, the circuit parameter of the circuit registered in the database 108 is changed. It was supposed to be set automatically.

  On the other hand, when the circuit parameter setting is “specified” as shown in FIG. 14, the circuit parameter is entered for each function (see 1401) and is registered in the database 108. The circuit parameters of the circuit are set.

  In FIG. 14, in IP_A3, the number of components which are circuit parameters is comp_num = 2 and the input data bit width is dt_width = 8, and a circuit corresponding to the circuit parameters is generated.

  In IP_B5, the number of components, which are circuit parameters, is comp_num = 1, the input data bit width is dt_width = 10, and the coefficients are coeff0 = 4, coeff1 = 2, and coeff2 = −1, which correspond to this circuit parameter. A circuit is generated.

  As described above, in the present embodiment, whether the part described by using the circuit parameter in the function unit of the C language behavior level description file is automatically reflected in the HDL language RT level description file or is appropriately reflected by designation. Can be selected and reused in an optimum manner according to the requirements of the system that wants to use a behavioral description that is generally described using circuit parameters.

[Other Embodiments]
Note that the present invention can be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, and a printer), and a device (for example, a copying machine and a facsimile device) including a single device. You may apply to.

  Another object of the present invention is to supply a storage medium storing software program codes for implementing the functions of the above-described embodiments to a system or apparatus, and the computer (or CPU or MPU) of the system or apparatus stores the storage medium. Needless to say, this can also be achieved by reading and executing the program code stored in the.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention.

  As a storage medium for supplying the program code, for example, a floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD-R, magnetic tape, nonvolatile memory card, ROM, or the like is used. be able to.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) operating on the computer based on the instruction of the program code. It goes without saying that a case where the function of the above-described embodiment is realized by performing part or all of the actual processing and the processing is included.

  Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. It goes without saying that the CPU or the like provided in the board or the function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

It is a figure which shows the structure of the behavioral synthesis apparatus (information processing apparatus) concerning one Embodiment of this invention. 6 is a flowchart illustrating a procedure of behavioral synthesis processing for generating an RT level description file described in HDL language from a behavioral description file described in C language in the behavioral synthesis device according to the embodiment of the present invention. It is the figure which showed concretely the relationship between the C language action description file, RT level description file, and database in the description action synthesis process. FIG. 3 is a diagram showing a part of a GUI of a behavioral synthesis device according to an embodiment of the present invention. It is the figure which showed a part of content contained in a file button. It is the figure which showed a part of content contained in a setting button. The C language action description file and output file to be synthesized are determined by the file button, the RT level description file to be output by the setting button and the clock frequency which is a precondition for behavioral synthesis are determined and displayed in the middle of the screen. FIG. It is the figure which showed the mode of the pop-up window which appears when a C display button and an HDL display button are clicked after performing behavioral synthesis on the screen shown in FIG. It is the figure which showed a part of behavioral synthesis window displayed when a behavioral synthesis button is selected. It is the figure which showed a part of behavioral synthesis window displayed when a behavioral synthesis button is selected. It is the figure which showed a part of behavioral synthesis window displayed when the behavioral synthesis button is selected. It is the figure which showed a part of behavioral synthesis window displayed when the behavioral synthesis button is selected. It is the figure which showed GUI of the behavioral synthesis apparatus concerning the 2nd Embodiment of this invention. It is the figure which showed GUI of the behavioral synthesis apparatus concerning the 2nd Embodiment of this invention.

Claims (14)

An information processing apparatus for converting a file described in a predetermined language into a register transfer level file described in an HDL language,
Storage means for storing a register transfer level circuit described in the HDL language;
An extraction means for reading a file described in the predetermined language and extracting a function included in the file;
Determining means for determining whether or not a register transfer level circuit described in the HDL language corresponding to the function extracted by the extracting means is stored in the storage means;
If the determination means determines that the data is stored in the storage means, a register transfer level file described in the HDL language is generated using the circuit stored in the storage means. If the determination means determines that the function is not stored in the storage means, the function extracted by the extraction means is converted into a register transfer level circuit described in the HDL language. An information processing apparatus comprising: generating means for generating a register transfer level file described in the HDL language. The determination means includes
2. The information processing apparatus according to claim 1, wherein the determination is made based on whether or not a circuit having the same name as the name of the function extracted by the extraction unit is stored in the storage unit. First specifying means for specifying a predetermined function is further provided, and the generating means is a case where the determining means determines that the function is stored in the storage means, and the first specifying means The register transfer level file described in the HDL language is generated by using a circuit stored in the storage means when the function specified by the function (1) is supported. The information processing apparatus described. In the generating means, the function extracted by the extracting means is converted into a register transfer level circuit described in the HDL language, so that a register transfer level file described in the HDL language is obtained. The information processing apparatus according to claim 1, further comprising: a registering unit that registers the converted register transfer level circuit in the storage unit when it is generated. Second register means for designating a predetermined function is further provided, wherein the registering means is a circuit corresponding to the function designated by the second designate means among the converted register transfer level circuits. The information processing apparatus according to claim 4, wherein the information processing apparatus is registered in the storage unit. A display unit for displaying the file described in the predetermined language and the register transfer level file described in the HDL language generated by the generation unit;
The display means can clearly indicate a correspondence relationship between a function included in a file described in the predetermined language and a circuit included in a register transfer level file described in the HDL language. The information processing apparatus according to claim 1. An information processing method for converting a file described in a predetermined language into a register transfer level file described in an HDL language,
A storage step of storing a register transfer level circuit described in the HDL language in a storage means;
An extraction step of reading a file described in the predetermined language and extracting a function included in the file;
A determination step of determining whether or not a register transfer level circuit described in the HDL language corresponding to the function extracted in the extraction step is stored in the storage unit;
If it is determined by the determination step that the data is stored in the storage unit, a register transfer level file written in the HDL language is generated using the circuit stored in the storage unit. When the determination step determines that the function is not stored in the storage unit, the function extracted by the extraction step is converted into a register transfer level circuit described in the HDL language. And a generating step of generating a register transfer level file described in the HDL language. The determination step includes
8. The information processing method according to claim 7, wherein the determination is made based on whether or not a circuit having the same name as the name of the function extracted in the extraction step is stored in the storage unit. A first designating step of designating a predetermined function, wherein the generating step is a case where it is judged by the judging step that the data is stored in the storage means, and the first designating step; The register transfer level file described in the HDL language is generated by using the circuit stored in the storage means when the function specified by the function (1) is supported. The information processing method described. In the generation step, the function extracted in the extraction step is converted into a register transfer level circuit described in the HDL language, so that a register transfer level file described in the HDL language is obtained. 8. The information processing method according to claim 7, further comprising a registration step of registering the converted register transfer level circuit in the storage means when it is generated. A second designating step for designating a predetermined function, wherein the registering step is for a circuit corresponding to the function designated in the second designating step among the converted register transfer level circuits; The information processing method according to claim 10, wherein the information processing method is registered in the storage unit. A display step of displaying the file described in the predetermined language and the register transfer level file described in the HDL language generated by the generation step;
In the display step, a correspondence relationship between a function included in the file described in the predetermined language and a circuit included in the register transfer level file described in the HDL language can be clearly indicated. The information processing method according to claim 7. A storage medium storing a control program for realizing the information processing method according to any one of claims 7 to 12 by a computer. A control program for realizing the information processing method according to any one of claims 7 to 12 by a computer.

Images