JP2006259805A - Processor design equipment, processor design method, and processor design program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently generate a processor model suiting execution of a particular application. <P>SOLUTION: When an application program 1 is inputted into a compile means 2, and object code 3 operating on a logic synthesis possible base processor model 6 is generated, hardware resource information 5 necessary for operating the application program 1 is extracted by a hardware resource information extracting means 4, and by removing hardware resources unnecessary for execution of the application program 1 from the logic synthesis possible base processor model 6 by an unnecessary hardware resource removing means 7 on the basis of the hardware resource information 5, a logic synthesis possible target processor model 8 suiting execution of the application program 1 is generated. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a processor design apparatus, a processor design method, and a processor design program, and is particularly suitable when applied to a processor model generation method suitable for execution of a specific application.

Traditional processor design methods are based on a logic-synthesizable processor model with a basic instruction set, and designers are required to design a processor model that performs a specific application more efficiently. There is a system that defines an instruction set, automatically generates a compilable compiler including the defined instruction set, and automatically adds hardware resources for executing the defined instruction to the processor model (Patent Document) 1).
Special table 2003-518280 gazette

However, in the conventional processor design method, the designer needs to define a new instruction set. Therefore, it is necessary to investigate the processing contents of a specific application in detail and find the most effective operation to improve performance. There is a problem that the design work takes time.
It is also necessary to prepare a compiler that can generate code including a newly defined instruction set, and to add special notation in the program code in order to use the defined instruction set. There is a problem that the design work takes time.

In addition, since the newly defined instruction set must be added to the logic model that can be synthesized, if the defined instruction set is complex, it will not operate at the operating frequency that the synthesized processor model was supposed to have. As a result, there is a problem that the target performance cannot be achieved.
Accordingly, an object of the present invention is to provide a processor design apparatus, a processor design method, and a processor design program capable of efficiently generating a processor model suitable for execution of a specific application.

  In order to solve the above-described problem, according to a processor design device according to one aspect of the present invention, hardware resource information extraction means for extracting hardware resource information necessary for operating an application program, and logic synthesis Hardware resource deletion for deleting a hardware resource provided in the base processor model based on a base processor model as a possible base and hardware resource information extracted by the hardware resource information extraction means And a target processor model generation unit that generates a target processor model that is a target that can be logically synthesized based on the base processor model from which the hardware resource has been deleted by the hardware resource deletion unit. The And butterflies.

  As a result, it is possible to generate a target processor model suitable for execution of a specific application by selecting hardware resources provided in advance in the base processor model. This allows designers to define a new instruction set or to generate code that includes a newly defined instruction set to generate a target processor model suitable for the execution of a specific application. It is not necessary to prepare a compiler, and the burden on the design work of the target processor model can be reduced.

  In addition, according to the processor design apparatus of one aspect of the present invention, a base processor model that is a base capable of logic synthesis, a compiling unit that generates a program that operates on the base processor model, and the compiling unit include: Hardware resource information extracting means for extracting hardware resource information unnecessary for operation on the base processor model from at least one or more specified application programs compiled by using the hardware resource information; And a target processor model generating means for generating a target processor model for suppressing logical synthesis of unnecessary hardware resources from the base processor model.

  As a result, it is suitable for execution of a specific application by using the hardware resources prepared in advance in the base processor model after suppressing unnecessary hardware resources from being logically synthesized from the base processor model. A target processor model can be generated. This allows designers to define a new instruction set or to generate code that includes a newly defined instruction set to generate a target processor model suitable for the execution of a specific application. It is not necessary to prepare a compiler, and the burden on the design work of the target processor model can be reduced.

Further, according to the processor design device according to an aspect of the present invention, the hardware resource information extraction unit includes, from the object code of at least one specific application program operating in the base processor model, the It is characterized by extracting hardware resource information unnecessary for operation on the base processor model.
Thus, by examining the instruction codes extracted from the object code one by one, the hardware resource information can be extracted, and the hardware resource information extraction process can be performed efficiently.

  Further, according to the processor design apparatus according to one aspect of the present invention, the target processor model generation means acquires RTL source code acquisition means for acquiring RTL source code of a base processor model in which hardware resources are described. And enabling the hardware resource described in the RTL source code by inserting an include file in which the name of the hardware resource is described at the beginning of the RTL source code. Means.

  As a result, the base processor model include file in which the name of the hardware resource is described is inserted at the beginning of the RTL source code, thereby suppressing logical synthesis of unnecessary hardware resources from the base processor model. A target processor model can be generated. Therefore, it is possible to generate a target processor model suitable for executing a specific application while reducing the burden on the design work.

  Further, according to the processor design method according to an aspect of the present invention, the object code of the application program is generated by compiling at least one specific application program that operates in the base processor model. Extracting hardware resource information unnecessary for operation on the base processor model from the object code of the application program, and based on the extracted hardware resource information, the base processor Generating a target processor model that suppresses logical synthesis of unnecessary hardware resources from the model.

This allows the designer to define a new instruction set, or a target suitable for running a specific application without having to prepare a compiler that can generate code including the newly defined instruction set. It becomes possible to generate a processor model, and it is possible to reduce the burden on the design work of the target processor model.
Further, according to the processor design method according to an aspect of the present invention, the step of generating the target processor model includes the step of acquiring an RTL source code of a base processor model in which the hardware resource is described; Enabling the hardware resource described in the RTL source code by inserting an include file in which the name of the hardware resource is described at the head of the RTL source code. And

This makes it possible to generate a target processor model that suppresses the logical synthesis of unnecessary hardware resources from the base processor model in a simple way, while reducing the burden on design work, while specifying A target processor model suitable for execution of the current application can be generated.
Further, according to the processor design program according to one aspect of the present invention, the object code of the application program is generated by compiling at least one specific application program that operates in the base processor model. Extracting hardware resource information unnecessary for operation on the base processor model from the object code of the application program, and based on the extracted hardware resource information, the base processor Generating a target processor model that suppresses the logical synthesis of unnecessary hardware resources from the model.

As a result, by causing the computer to execute the processor design program, it is possible to generate a target processor model suitable for executing a specific application while reducing the burden on the design work.
Further, according to the processor design program according to one aspect of the present invention, the step of generating the target processor model includes the step of acquiring the RTL source code of the base processor model in which the hardware resource is described; Enabling the hardware resource described in the RTL source code by inserting an include file in which the name of the hardware resource is described at the head of the RTL source code. And

  Thus, by causing the computer to execute the processor design program, it is possible to generate a target processor model that suppresses logical synthesis of unnecessary hardware resources from the base processor model by a simple method.

Hereinafter, a processor design apparatus and method according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a functional configuration of a processor design apparatus according to an embodiment of the present invention.
In FIG. 1, the processor design apparatus is provided with a compiling unit 2, a hardware resource information extracting unit 4 and an unnecessary hardware resource deleting unit 7, and a logic synthesizable base processor model 6 is prepared in advance. Here, in the logically synthesizable base processor model 6, general-purpose hardware resources such as an instruction set and a register file can be determined in advance. A set instruction can be provided. The compiling means 2 can generate a program that operates on the logically synthesizable base processor model 6. The hardware resource information extracting unit 4 can extract hardware resource information 5 necessary for operating the application program 1. Examples of the hardware resource information 5 include an instruction set, a register file, an input / output port to the register file, and the like. The unnecessary hardware resource deletion means 7 deletes the hardware resources provided in the logically synthesizable base processor model 6 based on the hardware resource information 5 extracted by the hardware resource information extraction means 4. The logic synthesis target processor model 8 suitable for executing the application program 1 can be generated.

  That is, when the application program (source code) 1 is input to the compiling means 2, the application program 1 is compiled, and object code 3 that operates on the logically synthesizable base processor model 6 is generated. Then, the object code 3 of the application program 1 is input to the hardware resource information extracting means 4 and the hardware resource information 5 necessary for operating the application program 1 is extracted. The hardware resource information 5 extracted by the hardware resource information extracting unit 4 is input to the unnecessary hardware resource deleting unit 7. The unnecessary hardware resource deleting means 7 is suitable for executing the application program 1 by deleting the hardware resources provided in the logically synthesizable base processor model 6 based on the hardware resource information 5. The logically synthesizable target processor model 8 is generated.

  Thus, by selecting a hardware resource provided in advance in the logically synthesizable base processor model 6, it is possible to generate a logically synthesizable target processor model 8 suitable for execution of the specific application program 1. It becomes. For this reason, in order to generate a logically synthesizable target processor model 8 suitable for execution of a specific application program 1, a designer defines a new instruction set or code including a newly defined instruction set. It is no longer necessary to prepare a compiler capable of generating the data, and it is possible to reduce the burden on the design work of the target processor model 8 capable of logic synthesis.

FIG. 2 is a block diagram illustrating a schematic configuration of a processor design apparatus according to an embodiment.
In FIG. 2, the processor design apparatus is provided with compiling means 12, hardware resource information extracting means 14, unnecessary hardware resource deleting means 17 and logic synthesizing means 18, and unnecessary hardware resource deleting means 17 is provided with logic synthesis. A possible base processor model 16 is provided in advance. Here, the compiling means 12 can generate a program that operates on the logically synthesizable base processor model 16. The hardware resource information extracting unit 14 can extract hardware resource information 15 necessary for operating the application program 11. The unnecessary hardware resource deleting unit 17 may delete the hardware resource provided in the logically synthesizable base processor model 16 based on the hardware resource information 15 extracted by the hardware resource information extracting unit 14. it can. The logic synthesis means 18 generates a target processor netlist 19 suitable for execution of the application program 11 based on the logic synthesis capable base processor model 16 from which hardware resources unnecessary for execution of the application program 11 are deleted. Can be generated.

  That is, when the application program 11 is input to the compiling unit 12, the application program 11 is compiled, and object code 13 that operates on the logically synthesizable base processor model 16 is generated. Then, the object code 13 of the application program 11 is input to the hardware resource information extracting unit 14 and the hardware resource information 15 necessary for operating the application program 11 is extracted. The hardware resource information 15 extracted by the hardware resource information extraction unit 14 is input to the unnecessary hardware resource deletion unit 17. Then, the unnecessary hardware resource deleting means 17 deletes the hardware resources provided in the logically synthesizable base processor model 16 based on the hardware resource information 15, and the hardware unnecessary for executing the application program 11. The logically synthesizable base processor model 16 from which the resource has been deleted is output to the logical synthesis unit 18. The logic synthesis unit 18 then selects a target processor netlist suitable for executing the application program 11 based on the logic synthesizable base processor model 16 from which hardware resources unnecessary for executing the application program 11 are deleted. 19 is generated.

Note that the hardware resource information extracting unit 14 can extract the hardware resource information 15 by taking out the instruction codes one by one from the object code 13 and examining them.
FIG. 3 is a diagram showing an example of an instruction code format according to an embodiment of the present invention.
In FIG. 3, for example, the format of an instruction code having a 32-bit fixed length instruction includes an R format for defining an operation between registers, an I format having an immediate value, and a J format. here,
op: Op code (instruction operation code)
rs: first source operand register (operation target storage destination)
rt: second source operand register (operation target storage destination)
rd: Destination operand register (operation result storage destination)
shamt: Shift amount funct: Function extension code.

The type of instruction used in the object code 13 can be extracted by confirming the operation code op or the function extension code func.
FIG. 4 is a flowchart illustrating a method for generating hardware resource information according to an embodiment of the present invention.
In FIG. 4, after a flag indicating whether or not the object code 13 has an instruction code is initialized to 0 (steps S1 to S4), the instruction code is sequentially read from the object code 13, and the flag corresponding to the instruction code is set to 1. (Steps S5 to S7). If the flag corresponding to the instruction code is set to 1, the instruction code is output as hardware resource information 15 (steps S8 to S12).

In order to delete the hardware resource provided in the logically synthesizable base processor model 16 based on the hardware resource information 15, for example, a compile identifier can be used.
For example, when an ADD instruction is extracted as the hardware resource information 15, a description “define ADD” can be output to a text file. That is, as the hardware resource information 15, for example, the following description can be output to a text file.
'define ADD
'define SUB
'define LW
・
・
・
When a text file defined as “define” is output as the hardware resource information 15, only the instruction defined as “define” in the logically synthesizable base processor model 16 is enabled by using the compile identifier. The logically synthesizable base processor model 16 from which hardware resources unnecessary for executing the application program 11 are deleted can be constructed.

FIG. 5 is a diagram illustrating a method for enabling hardware resources on RTL source code of a logic synthesizable base processor model according to an embodiment of the present invention.
In FIG. 5, RTL source code K in which a hardware resource (for example, the name is XXX) is described between 'ifdef XXX and' endif is prepared as a logically synthesizable base processor model 16. In order to validate the hardware resource XXX, 'define XXX' is described in the include file inserted at the head of the RTL source code K. On the other hand, in order to invalidate the hardware resource XXX, nothing is described in the include file inserted at the head of the RTL source code K.

  By doing so, if 'define XXX' is described in the include file, the hardware resource XXX described between 'ifdef XXX and' endif becomes valid, and the hardware resource XXX is logically synthesized. The circuit can be synthesized by means 18. On the other hand, if 'define XXX' is not described in the include file, the hardware resource XXX described between 'ifdef XXX and' endif may be regarded as not described in the RTL source code K. Therefore, it is possible to prevent the hardware composition of XXX from being synthesized by the logic synthesis means 18.

  For example, in the RTL source code K, it is assumed that the operation of the ADD instruction is described between 'ifdef ADD and' endif, and the operation of the SUB instruction is described between 'ifdef SUB and' endif. The ADD instruction described in the RTL source code K can be validated by describing 'define ADD' in the include file inserted at the beginning of the RTL source code K. Further, the SUB instruction described in the RTL source code K can be validated by describing 'define SUB' in the include file inserted at the head of the RTL source code K.

The block diagram which shows the functional structure of the processor design apparatus which concerns on one Embodiment. 1 is a block diagram showing a schematic configuration of a processor design apparatus according to an embodiment. The figure which shows the example of the format of the instruction code which concerns on one Embodiment. The flowchart which shows the production | generation method of hardware resource information. The figure which shows the method of enabling a hardware resource on the RTL source code of a logic synthesis possible base processor model.

Explanation of symbols

  1, 11 application program, 2, 12 compiling means, 3, 13 object code, 4, 14 hardware resource information extracting means, 5, 15 hardware resource information, 6, 16 logically synthesizable base processor model, 7, 17 Unnecessary hardware resource deletion means, 8 logic synthesis possible target processor model, 18 logic synthesis means, 19 target processor net list, K RTL source code

Claims (8)

Hardware resource information extraction means for extracting hardware resource information necessary for operating an application program;
A base processor model that is a base that can be synthesized, and
Hardware resource deletion means for deleting hardware resources provided in the base processor model based on the hardware resource information extracted by the hardware resource information extraction means;
And a target processor model generation unit that generates a target processor model that is a target that can be logically synthesized based on the base processor model from which the hardware resource has been deleted by the hardware resource deletion unit. Processor design equipment. A base processor model that is a base that can be synthesized, and
Compiling means for generating a program that operates on the base processor model;
Hardware resource information extracting means for extracting hardware resource information unnecessary for operation on the base processor model from at least one or more specified application programs compiled using the compiling means;
A processor design comprising: target processor model generation means for generating a target processor model for suppressing logical synthesis of unnecessary hardware resources from the base processor model based on the hardware resource information apparatus.   The hardware resource information extracting means extracts hardware resource information unnecessary for operation on the base processor model from the object code of at least one specific application program operating on the base processor model. 3. The processor design device according to claim 1, wherein the processor design device is extracted. The target processor model generation means includes:
RTL source code acquisition means for acquiring RTL source code of a base processor model in which hardware resources are described;
Hardware resource enabling means for enabling the hardware resource described in the RTL source code by inserting an include file in which the name of the hardware resource is described at the head of the RTL source code; 4. The processor design device according to claim 1, further comprising: Generating object code for said application program by compiling at least one particular application program running on a base processor model;
Extracting hardware resource information unnecessary for operation on the base processor model from the object code of the application program;
Generating a target processor model that suppresses logical synthesis of unnecessary hardware resources from the base processor model based on the extracted hardware resource information. Generating the target processor model comprises:
Obtaining RTL source code of a base processor model in which the hardware resource is described;
Enabling the hardware resource described in the RTL source code by inserting an include file in which the name of the hardware resource is described at the head of the RTL source code. The processor design method according to claim 5. Generating object code for said application program by compiling at least one particular application program running on a base processor model;
Extracting hardware resource information unnecessary for operation on the base processor model from the object code of the application program;
Generating a target processor model that suppresses logical synthesis of unnecessary hardware resources from the base processor model based on the extracted hardware resource information. Design program. Generating the target processor model comprises:
Obtaining RTL source code of a base processor model in which the hardware resource is described;
Enabling the hardware resource described in the RTL source code by inserting an include file in which the name of the hardware resource is described at the head of the RTL source code. A processor design program according to claim 7.

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