WO2010110194A1

WO2010110194A1 - Motion synthesis device, motion synthesis method, and program

Info

Publication number: WO2010110194A1
Application number: PCT/JP2010/054761
Authority: WO
Inventors: 野田真一
Original assignee: 日本電気株式会社
Priority date: 2009-03-24
Filing date: 2010-03-15
Publication date: 2010-09-30
Also published as: JPWO2010110194A1; JP5692063B2

Abstract

Provided are a motion synthesis device, a motion synthesis method, and a program capable of leaving a parameter as it is in the RT description, and capable for appropriate optimization. An input device to input motion level description in which circuit specification with a high level of abstraction is described; a data processing device which performs conversion to the internal expression for the motion synthesis, classifies the parameters contained in the motion level description into a plurality of classifications, and treats the parameter as a variable or a constant in accordance with the classification; a storage device to store the motion level description and the respective parameters; and an output device to output the RT description, are provided.

Description

Behavioral synthesis apparatus, behavioral synthesis method, and program

The present invention relates to a behavioral synthesis device, a behavioral synthesis method, and a program.

Behavioral synthesis systems are used in the design of integrated circuits.
The related behavioral synthesis system includes language analysis means (apparatus), internal structure normalization means (apparatus), CDFG generation means (apparatus), scheduling means (apparatus), binding means (apparatus), and RT description generation. And means (apparatus).
Here, CDFG is an abbreviation for Control Data Flow Graph, and is a kind of data structure. RT is an abbreviation for Register Transfer and is a kind of circuit description. Scheduling refers to determining a cycle for performing each process. Binding is to determine which computing unit or memory is actually used for each processing operation or memory access.
The behavioral synthesis system having such a configuration operates as follows.
This behavioral synthesis system analyzes behavioral descriptions given from the input device of this system, and normalizes structures such as functions and loops for generating CDFG. Further, the behavioral synthesis system generates a CDFG after normalization, then proceeds with scheduling and binding, and repeats these steps a plurality of times as necessary to generate an RT description.
In this type of behavioral synthesis system, parameters that are treated as constants in the final LSI circuit are regarded as constant parameters at the input stage from the input device to the behavioral synthesis system , and the behavioral synthesis system side sets the values of the parameters. It was usual to optimize as a constant. Conversely, if the user wants to keep the parameters until after the behavioral synthesis is completed, there is no choice but to treat all parameters as variables, and as a result, optimization is significantly suppressed. It was. LSI is an abbreviation for Large Scale Integration, and means a large-scale integrated circuit.
Techniques related to this type of behavioral synthesis system are disclosed in Japanese Patent Application Laid-Open No. 2001-350809 (hereinafter referred to as Patent Document 1) and Japanese Patent Application Laid-Open Publication No. 2006-079226 (hereinafter referred to as Patent Document 2). The invention described in Patent Document 1 is an invention relating to a method for designing a data driven information processing apparatus employing self-synchronous pipeline control. Specifically, the present invention creates a library file that generally describes design parameters, sets parameter values for each design parameter, and creates a register transfer level design description. And a step including the step of:
According to the invention described in Patent Document 1, a designer can automatically create a register transfer level design description that conforms to a design specification, thereby shortening the design period, and also for various specifications. It is said that it can be easily handled and designed.
The invention described in Patent Document 2 is an invention related to a hardware description language synthesis tool and an integrated circuit design method using the same. More specifically, the present invention causes a computer to execute a procedure for analyzing a program, a procedure for converting an instruction code into a processor software file, and a procedure for outputting a processor hardware file and a processor software file. It is invention regarding the computer program.
According to the invention described in Patent Document 2, since the instruction code of the assembly level language program corresponds to a hardware component, if the assembly level language program is used, the hardware described in the hardware description language is 1: 1. It can be replaced with a hardware design file, which is practical for users.

However, in the technique related to the present invention described above, when the input device gives a parameter to the behavioral synthesis system in the behavioral synthesis, there is no option other than treating all the parameters as constants or treating them as variables. Therefore, when both the treatments are required, there is a problem that the related technology described above cannot promote the optimization.
The reason is that, in the above-described behavioral synthesis, values handled internally are limited to only constants or variables, and thus a method for specially handling only parameters has not been invented.
Accordingly, an object of the present invention is to provide a behavioral synthesis device, behavioral synthesis method, and program that can leave parameters in the RT description as parameters and can perform appropriate optimization.

The apparatus of the present invention includes an input device for inputting a behavior level description in which a circuit specification having a high level of abstraction is described, and converts the behavior level description into an internal representation for behavioral synthesis, and is included in the behavior level description. A data processing device that classifies the parameter into a plurality of parameters and treats the value of the parameter as a constant or a variable according to a result of the classification;
A storage device for storing the behavior level description and each parameter;
And an output device for outputting the RT description.
Here, the internal expression indicates an expression when the result of analyzing the behavioral level circuit description is saved in an abstract syntax tree (AST) or a data structure called CDFG.
According to the method of the present invention, a language analysis unit converts a behavior level description in which a circuit specification having a high degree of abstraction prepared by a user is described into an internal representation for behavioral synthesis by language analysis processing. The parameter classification means classifies the parameters included in the behavior level description into a plurality of parameters, and the parameter constant conversion means regards the combined parameters as the maximum value that the parameters can take among the classified parameters. For the changed parameter use location, the parameter is converted to the maximum constant value by the parameter constant processing, and the original parameter name is set to be recorded. For parameter use points that are supposed to be synthesized as parameters, parameters are set to their respective values by parameter specialization processing. The internal structure normalization means performs normalization processing of the internal structure individually for each specialized parameter, normalizes the loops and functions of the internal structure, and the CDFG generation means converts to CDFG by the CDFG generation processing, A scheduling means is applied to the CDFG generated by the binding means, the binding process is performed, and the parameter merge means performs a parameter merge process for branching together the binding process results that have been executed specialized for each parameter value. The parameter variableizing means performs parameter variableization to return the converted parameter to a variable, and the RT description generating means generates an RT level description by RT level description generating processing.
The program of the present invention includes a computer that converts a behavior level description in which a circuit specification with a high degree of abstraction prepared by a user is described into an internal representation for behavioral synthesis by language analysis processing, and is included in the behavior level description. The parameter is converted to the maximum value by the parameter constantization process for the parameter use part that is considered to be the maximum value of the possible values of the parameter among the classified parameters. In addition to replacing with a constant value, the parameter setting process is performed for the parameter use location that is to be synthesized as a means for setting the original parameter name to be recorded and the value that can be taken by the parameter. A means to specialize each value, normalize the internal structure for each specialized parameter, Means for normalizing loops and functions of substructures, converting into CDFG by CDFG generation processing, applying scheduling processing to the generated CDFG, performing binding processing, and executing for each parameter value A means for performing a parameter merge process for branching the binding processing results collectively, a means for performing a parameter variable for returning a constant parameter to a variable, and a means for generating an RT level description by an RT level description generation process It is characterized by that.

According to the present invention, it is possible to provide a behavioral synthesis apparatus, a behavioral synthesis method, and a program that can leave parameters in the RT description as parameters and can perform appropriate optimization.

It is a block diagram which shows one Embodiment of the behavioral synthesis apparatus which concerns on this invention. It is an example of the flowchart for demonstrating operation | movement of the behavioral synthesis apparatus shown in FIG. It is a block diagram which shows other embodiment of the behavioral synthesis apparatus which concerns on this invention. It is a block diagram which shows other embodiment of the behavioral synthesis apparatus which concerns on this invention. It is a block diagram which shows other embodiment of the behavioral synthesis apparatus which concerns on this invention. It is an example of the flowchart for demonstrating operation | movement of the behavioral synthesis apparatus shown in FIG. It is an example of the flowchart for demonstrating operation | movement of the behavioral synthesis apparatus shown in FIG. It is an example of the flowchart for demonstrating operation | movement of the behavioral synthesis apparatus shown in FIG.

<Configuration>
Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of a behavioral synthesis device according to the present invention.
Referring to FIG. 1, the behavioral synthesis device includes a data processing device 2 that operates under program control, an input device 1, a storage device 3, and an output device 4.
Examples of the input device 1 include a keyboard, a mouse, and a pointing device.
The data processing device 2 includes a language analysis unit 2a, a parameter classification unit 2b, an internal structure normalization unit 2e, a parameter constant conversion unit 2c, a parameter specialization unit 2d, a CDFG generation unit 2f, a scheduling unit 2g, a binding unit 2h, a parameter merge A unit 2i, a parameter variable unit 2j, and an RT description generation unit 2k.
Examples of the storage device 3 include an HDD (Hard Disc Drive: hard disk) and a flash memory.
Examples of the output device 4 include a liquid crystal display device, a plasma display, a printer, and a plotter.
The language analysis unit 2a to RT description generation unit 2k are configured by software, and operate as follows.
The language analysis unit 2a analyzes the behavior level description including the parameter given by the input device 1 and converts it into an internal representation. Here, the language is, for example, a software language (also referred to as behavior level description) describing the behavior level of the design parameter. The parameter is, for example, an LSI design parameter that is handled as a constant or a variable.
The parameter classification unit 2b considers the internal description of the behavioral description given by the language analysis unit 2a, the parameters, and the parameter processing method designation by the user, and treats the parameters as variables, and the values that the parameters can take. They are classified into three types: those that are considered to be the maximum value, and those that are synthesized by values that can be taken by the parameter.
The parameter constant conversion unit 2c replaces the parameter use location, which the parameter classification unit 2b considers as the maximum value of the parameter, and synthesizes it with the constant value of the maximum value, and records the original parameter name. Set to be.
In the parameter specialization unit 2d, an internal representation (or internal structure) that is actually specialized with a plurality of possible values for the parameter use location determined by the parameter classification unit 2b to be specialized with the possible values of the parameters. ) Each.
The internal structure normalization unit 2e normalizes each internal representation specialized for the parameter by the parameter specialization unit 2d, for example, by appropriately expanding a part corresponding to a function or a loop.
The CDFG generation unit 2f converts each normalized internal representation into a CDFG (control data flow graph).
The scheduling unit 2g schedules resources and input / output on each CDFG generated by the CDFG generation unit 2f.
The binding unit 2h allocates resources such as computing units based on the scheduling result realized by repeating the scheduling unit 2g.
The parameter merging unit 2i specializes each possible value of the parameter by the parameter specializing unit 2d, and merges the ones that have been implemented up to the binding by the binding unit 2h based on the respective parameter values so as to branch by the parameter value. To do.
The parameter variable conversion unit 2j restores the parameter converted to the maximum constant by the parameter constant conversion unit 2c to the original parameter. Further, the parameter variable conversion unit 2j generates an RT description by the RT description generation unit 2k based on the result, and outputs the RT description to the output device 4.
Each processing means writes and reads the conversion result to the system internal representation storage unit 3a belonging to the storage device 3 of the system as necessary.
<Operation>
Next, the overall operation of this embodiment will be described in detail with reference to FIG.
FIG. 2 is an example of a flowchart for explaining the operation of the behavioral synthesis device shown in FIG.
First, the user prepares a behavior level description in which a circuit specification having a high degree of abstraction such as C language is described (block A1 in FIG. 2). This behavioral description is a description including parameters, which is a target of the embodiment of the present invention.
Next, the language analysis unit 2a converts the behavior level description of A1 into an internal expression for behavioral synthesis by language analysis processing (block A2 in FIG. 2). The converted internal representation is represented by a data structure such as AST (abstract syntax tree).
Next, the parameter classification unit 2b uses parameter classification processing (block A3 in FIG. 2) to treat the parameter in the behavior level description as a variable, to synthesize the parameter as the maximum value that the parameter can take, It is classified into three types, specializing in possible values. Of the classified parameters, the parameter constant conversion unit 2c executes the parameter constant conversion process (block A4 in FIG. 2) for the parameter use location that is to be combined as the maximum value that the parameter can take. That is, the parameter constant conversion unit 2c replaces the parameter with the maximum constant value and sets the original parameter name to be recorded. Further, the parameter specializing unit 2d performs a parameter specialization process (block A5 in FIG. 2) on the used part of the parameter that is to be synthesized as a specialization with a possible value of the parameter. That is, the parameter specialization unit 2d generates an internal representation (internal structure) that specializes a parameter with a plurality of possible values for each parameter usage location. Thereafter, the internal structure normalization unit 2e, the CDFG generation unit 2f, the scheduling unit 2g, and the binding unit 2h individually execute the respective processes for each specialized parameter. This process can be executed in parallel in time by a plurality of processors or sequentially by a single processor. The processes in the internal structure normalization unit 2e, the CDFG generation unit 2f, the scheduling unit 2g, and the binding unit 2h will be described in this order.
The internal structure normalization unit 2e performs normalization processing (block A6 in FIG. 2) on the internal structure generated by the parameter specialization unit 2d to normalize loops and functions of the internal structure.
Next, the CDFG generation unit 2f converts the normalized internal structure into CDFG by a CDFG generation process (block A7 in FIG. 2). Next, the scheduling unit 2g performs scheduling (block A8 in FIG. 2) on the generated CDFG, and the binding unit 2h performs binding processing (block A9 in FIG. 2). That is, the binding unit 2h allocates a resource such as an arithmetic unit to each normalized internal structure based on the scheduling result in the scheduling unit 2g.
Subsequently, the parameter merging unit 2i performs a parameter merging process (block A10 in FIG. 2) for collecting the binding process results specialized for each parameter value and branching by the parameter value.
The parameter variableizing unit 2j performs the parameter variableizing process (block A11 in FIG. 2) for returning the parameter to the original parameter for the parameter constantized by the parameter constantizing unit 2c. Do.
Finally, the RT description generation unit 2k generates an RT level description (block A13 in FIG. 2) by RT level description generation processing (block A12 in FIG. 2).
<Effect of Embodiment>
Next, the effect of this embodiment will be described.
In this embodiment, the parameters are classified into variables, constants based on maximum values, and specialized constants, and then converted, so that the effect of differences in parameter processing on scheduling and binding, which is the main processing in the behavioral synthesis system, is achieved. As a result, it is possible to achieve the object of the present invention to reflect the parameters in the operation description in the RT level description while suppressing the deterioration of the circuit performance. This is because the parameter classification unit classifies the parameters included in the behavior level description into a plurality of parameters, and the data processing apparatus outputs the RT description according to the result of the classification.
In the embodiment of the present invention, the process related to the parameter is realized by placing the process before the normalization of the internal structure and after the binding process. However, the embodiment of the present invention realizes processing related to parameters as a part of another means such as language analysis means, internal structure normalization means, CDFG generation means, and scheduling means, depending on the behavioral synthesis realization method. Is also possible. In the embodiment of the present invention, it is also possible to realize processing relating to parameters at a plurality of processing positions as a part of the plurality of means described above.
<Program and storage medium>
The behavioral synthesis apparatus according to the present invention described above is realized by a program that causes a computer to execute processing. Examples of the computer include general-purpose computers such as personal computers and workstations, but the present invention is not limited to this. As an example, a case where the behavioral synthesis device according to the above-described embodiment is realized by executing a software program in a computer will be described below.
Computer
(1) Means for converting a behavior level description prepared by a user describing a high-level circuit specification into an internal representation for behavioral synthesis by language analysis processing and classifying it into a plurality of
(2) Of the classified parameters, the parameter use point that is supposed to be synthesized as the maximum value that can be taken by the parameter is replaced with the constant value of the maximum value by the parameter constant processing, and originally Means to record the parameter name of
(3) Means for specializing a parameter to each value by a parameter specialization process for a parameter use location that is to be synthesized as a specialization with a possible value of the parameter;
(4) perform specialized normalization process of the internal structure individually for each parameter, it means for normalizing the loop and a function of an internal structure,
(5) means for converting into CDFG by CDFG generation processing, applying scheduling processing to the generated CDFG, and performing binding processing;
(6) Means for performing a parameter merge process for branching together the binding process results that are specialized for each parameter value;
(7) Means for parameterization to return a constant parameter to a variable,
(8) means for generating an RT level description by RT level description generation processing;
As a program for making it function.
Thus, the behavioral synthesis apparatus according to the present invention can be realized anywhere as long as there is a computer environment capable of executing the program.
Such a program may be stored in a computer-readable storage medium.
Here, examples of the storage medium include a computer-readable storage medium such as a CD-ROM (Compact Disc Read Only Memory), a flexible disk (FD), and a CD-R (CD-Recordable), a flash memory, and a RAM (RAM). Examples thereof include a semiconductor memory such as a random access memory (ROM), a read only memory (ROM), and a FeRAM (ferroelectric memory) and an HDD.
In the above-described embodiment, the case has been described in which the parameters are classified into those to be synthesized by regarding them as the maximum value, and those to be specifically executed for each possible value of the parameter. Specifically, the data processing device converts the parameter into a constant value of the maximum value for the parameter use location that is considered to be the maximum value that can be taken by the parameter among the classified parameters. Yes. At this time, the data processing apparatus is set to record the original parameter name. The data processing apparatus specializes the parameter for each value and executes the parameter for each parameter value at a parameter use location that is to be synthesized as a special value that can be taken by the parameter. The data processing apparatus performs parameter merge processing for branching these specialized binding processing results collectively. Finally, the data processing apparatus performs a parameter variable process for returning the constant parameter to a variable.
The embodiment described above shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. Other embodiments will be described below.
FIG. 3 is a block diagram showing another embodiment of the behavioral synthesis device according to the present invention.
FIG. 4 is a block diagram showing another embodiment of the behavioral synthesis device according to the present invention.
FIG. 5 is a block diagram showing another embodiment of the behavioral synthesis device according to the present invention.
FIG. 6 is an example of a flowchart for explaining the operation of the behavioral synthesis device shown in FIG.
FIG. 7 is an example of a flowchart for explaining the operation of the behavioral synthesis device shown in FIG.
FIG. 8 is an example of a flowchart for explaining the operation of the behavioral synthesis device shown in FIG.
The present invention may be any of the following embodiments (a) to (c) described with reference to FIGS.
(A) Among the classified parameters, regarding the parameter use location that is supposed to be synthesized as the maximum value that the parameter can take, the parameter is converted into a constant value of the maximum value, and the converted parameter is used as a variable. Perform parameter variableization processing to return (FIGS. 4 and 7),
(B) The parameter name is set so that the original parameter name is recorded, and the parameter is used for each parameter value for the parameter use location that is to be synthesized as a special value that can be taken by the parameter. A parameter merging process for branching together the results of the binding process executed in a specialized manner (FIGS. 3 and 6),
(C) Neither (a) nor (b) is performed (FIGS. 5 and 8).
Next, the operation of the best mode for carrying out the present invention will be described using a specific example.
In the following description examples 1 to 17, the operation description conforms to the notation in the SystemC language, and the RT description conforms to the Verilog HDL notation.
Here, the designer uses #pragma PARAMETER (N)
Can specify that the argument of PARAMETER (N in this case) is a parameter, and the range of values and discrete values such as #pragma PARAMETER (N; 0-3, 5, 7-8, 10) A value can be specified. In this case, 0, 1, 2, 3, 5, 7, 8, and 10 are possible parameter values. The value specified by the parameter is used for comparison, substitution, and calculation in the circuit to be designed, and is mainly used for the word length (number of elements) of the array, the bit width of the variable, the number of loop executions, and the like.
The description example 1 is an example of a behavior description when a parameter is used for the word length of the array, which is input to the input device 1 of the behavioral synthesis device according to the embodiment of the present invention.
Description example 1

When the data processing device 2 synthesizes the parameters shown in the description example 1 as variables, the RT description generation unit 2k sets N as a parameter (parameter) as the final Verilog HDL as in the description example 2. The synthesized result is generated.
Description example 2

Description example 2 is one example of a conversion result by the behavioral synthesis device shown in description example 1.
Further, when the data processing apparatus 2 regards the parameter shown in the description example 1 as a maximum value in the parameter range and combines them, it is handled as N = 8. Therefore, the parameter constant converting unit 2c sets the description example 1 as in the description example 3, and finally the parameter variable converting unit 2j is Verilog HDL (8) and returns 8 to N. As a result, the RT description generation unit 2k generates description example 4.
Description example 3

Description example 4

The description example 3 is one of conversion examples by the behavioral synthesis device shown in FIG. 1, and the description example 4 is one of conversion results by the behavioral synthesis device shown in FIG.
When specializing with possible values of parameters, the parameter specializing unit 2d regards the description example 1 as three types of patterns like the description example 5, and the data processing device 2 synthesizes each of these three types of patterns. It will be.
Description example 5

The description example 5 is one example of conversion in progress by the behavioral synthesis device shown in FIG.
After the parameter merge unit 2i merges the parameters, the RT description generation unit 2k generates an RT description as shown in the description example 6 as the final Verilog HDL.
Description example 6

In the description example 6, according to the value of N, the value to be defined is changed instead of the parameter. Description example 6 is one example of a conversion result by the behavioral synthesis device shown in FIG.
The description example 7 is an example of a behavior description when a parameter is used for the bit width of a variable that is input to the input device 1 of the behavioral synthesis device according to the embodiment of the present invention.
Description example 7

That is, the description example 7 is an example of a behavior description that becomes an input of the behavioral synthesis device illustrated in FIG. When the data processing apparatus 2 treats the parameter shown in the description example 7 as a variable and synthesizes it, the RT description generation unit 2k sets the final Verilog HDL as a description result in which N is a parameter as in the description example 8. Become.
Description example 8

The description example 8 is one example of a conversion result by the behavioral synthesis device shown in FIG.
Further, the adder INST_ADD of the description example 7 replaces the bit width BITW with this value by rewriting the value of N. In this way, an efficient circuit can be generated for each parameter by using an adder in which the bit width can be adjusted by a parameter.
In addition, when the data processing apparatus 2 regards the parameter shown in the description example 7 as a maximum value in the parameter range and synthesizes the parameter, the parameter constantizing unit 2c treats the description example 7 as the description example 9. Finally, the parameter variableizing unit 2i is Verilog HDL, 8 is returned to N, and the RT description generating unit 2k generates the description example 10.
Description example 9

Description example 10

Description example 9 is one example of conversion in progress by the behavioral synthesis device shown in FIG.
The description example 10 is one example of the conversion result by the behavioral synthesis device shown in FIG.
In this case, the range affected by N varies depending on how far the information that 8 is a parameter is propagated during synthesis.
In the description example 10, only the bit width of the variable itself is an N controllable range, so the bit width of the adder depends on the maximum value 8 of N.
Also, when specializing with possible values of parameters, the parameter specializing unit 2d regards the description example 7 as three types of patterns like the description example 11, and the data processing apparatus synthesizes each of these three types of patterns. Will do.
Description example 11

The description example 11 is one example of conversion in progress by the behavioral synthesis device shown in FIG.
After the parameter merging unit 2i merges the parameters, the RT description generating unit 2k generates (in) the RT description as in the description example 12 as the final Verilog HDL.
Description example 12

The description example 12 is one example of the conversion result by the behavioral synthesis device shown in FIG. In the description example 12, the same part of the result synthesized according to the value of N is shared and output. However, since sharing is not essential, the whole sentence is output separately, and 'ifdef It is also possible to switch with.
The description example 13 is an example of a behavior description in the case where a parameter is used for the number of loop executions, which is input to the input device of the behavioral synthesis device of the present invention.
Description example 13

When the data processing device 2 treats the parameters shown in the description example 13 as variables and synthesizes them, the loop may be expanded by adding a condition for each possible value of the loop execution number as in the description example 14. The RT description generation unit 2k generates a synthesis result with N as a parameter as described in the description example 15 as the final Verilog HDL.
Description example 14

The description example 13 is an example of a behavior description that is input to the behavioral synthesis device illustrated in FIG. 1, and the description example 14 is one example of an intermediate conversion by the behavioral synthesis device illustrated in FIG. 1. The description example 15 is one of conversion result examples by the behavioral synthesis device shown in FIG.
Description example 15

On the other hand, since the synthesis with the maximum value in the parameter range is impossible when parameters are involved in the control logic such as the number of loop executions, this method cannot be selected. When specializing with possible values of parameters, the data processing apparatus 2 regards the description example 13 as three types of patterns as in the description example 16, and the parameter specialization unit 2d synthesizes each of these three types of patterns. It will be. Then, after the parameter merge unit 2i merges the parameters, the RT description generation unit 2k generates an RT description as shown in the description example 17 as the final Verilog HDL.
Description Example 16

Description example 17

The description example 16 is one example of conversion in progress by the behavioral synthesis device shown in FIG. The description example 17 is one example of the conversion result by the behavioral synthesis device shown in FIG.
As described above, the behavioral synthesis system of this embodiment includes a language analysis unit, an internal structure normalization unit, a CDFG generation unit, a scheduling unit, a binding unit, and an RT description generation unit. Adopting such a configuration, depending on the location of use, 1) treat it as a variable, and share it appropriately among variables using the same parameter, etc. 2) Combining it as the maximum value of the parameter range, By selecting a synthesis method, such as returning to a parameter after synthesis, 3) separately synthesizing a circuit specialized for a possible value of the parameter, and switching the portion with a 'ifdef directive of Verilog HDL, etc. Can achieve the purpose.
According to this embodiment, the reusability of the synthesized circuit is enhanced.
The reason is that when a behavioral synthesis device changes parameters such as bit width in a circuit after behavioral synthesis, the quality of the circuit is sacrificed by retaining the parameter as a variable in the synthesized RT description. On the other hand, while it was required to change the parameters and perform behavioral synthesis again, in the present embodiment, while changing the parameters on the RT description, the sacrifice of circuit quality is suppressed. This is because it is possible to avoid performing behavioral synthesis again.
Here, the difference between the behavioral synthesis system according to the above-described embodiment and the patent document will be described. The invention described in Patent Document 1 can parameterize only objects in a predetermined range such as packet data width, memory type, memory capacity, and number of parallel data paths. On the other hand, in the present embodiment, the parameters are synthesized by the post-processing of the parameter classification unit 2b, the parameter constant conversion unit 2c, the parameter specialization unit 2d, the parameter merge unit 2i, and the parameter variable conversion unit 2j in FIG. It differs from the invention described in Patent Document 1 in that the mechanism has room for changing parameters even in the RT description, which is the final output, after being optimized.
While the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.
This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2009-073021 for which it applied on March 24, 2009, and takes in those the indications of all here.

The present invention can be applied to a behavioral synthesis device that synthesizes a circuit description with a low abstraction level from a circuit description with a high abstraction level.

DESCRIPTION OF SYMBOLS 1 Input device 2 Data processor 2a Language analysis part 2b Parameter classification part 2c Parameter constantization part 2d Parameter specialization part 2e Internal structure normalization part 2f CDFG generation part 2g Scheduling part 2h Binding part 2i Parameter merge part 2j Parameter variable part 2k RT description generation unit 3 storage device 3a system internal representation storage unit 4 output device

Claims

An input device for inputting a behavior level description in which a circuit specification having a high level of abstraction is described;
A data processing device that converts the behavior level description into an internal representation for behavioral synthesis, classifies the parameters included in the behavior level description into a plurality, and treats the value of the parameter as a constant or a variable according to a result of the classification; ,
A storage device for storing the behavior level description and each parameter;
An output device for outputting the RT description;
A behavioral synthesis device comprising:
The data processing device individually performs normalization processing of the internal structure for each classified parameter, normalizes internal structure loops and functions, converts them into CDFG, and applies scheduling means to the generated CDFG. Then, the binding process is performed to generate the RT level description, and the parameter is set to the constant value of the maximum value for the part where the parameter is to be synthesized by regarding the maximum value of the parameter that can be taken by the classification. 2. The behavioral synthesis apparatus according to claim 1, wherein parameter variableization processing is performed to return a parameter that has been converted to a constant before the RT level description to a variable.
The data processing device individually performs normalization processing of the internal structure for each classified parameter, normalizes internal structure loops and functions, converts them into CDFG, and applies scheduling means to the generated CDFG. Then, the binding process is performed, the RT level description is generated, the original parameter name is set to be recorded, and the parameter use point that is to be synthesized to be specialized with the value that the parameter can take The behavioral synthesis apparatus according to claim 1, wherein parameter merging processing is performed to specialize each value and branch the processing result of the binding processing specialized for each parameter value.
The data processing apparatus performs normalization processing of the internal structure individually for each parameter, normalizes loops and functions of the internal structure, converts them to CDFG, applies scheduling means to the generated CDFG, Performs processing, generates an RT level description, and sets the parameter to the constant value of the maximum value for the parameter use location that is considered to be the maximum value that can be taken by the parameter among the classified parameters. The parameter name is set to record the original parameter name, and the parameter used for the parameter use location that is to be synthesized as a specialization with the possible value of the parameter Parameter merge processing that branches the binding processing results that have been specialized for each Was carried out, the operation synthesizing apparatus according to claim 1, characterized in that the parameter variable process that returns the parameter constants into variables.
The language analysis means converts the behavior level description in which the circuit specification having a high degree of abstraction is described into an internal representation for behavioral synthesis by language analysis processing, classifies the parameters included in the behavior level description into a plurality of parameters,
The parameter constant conversion means replaces the parameter with the constant value of the maximum value by the parameter constant conversion processing for the parameter use portion that is supposed to be synthesized as the maximum value that can be taken by the parameter among the classified parameters. And set it to record the original parameter name,
The parameter specialization means specializes the parameter to each value by the parameter specialization process for the parameter usage part that was to be synthesized as the specialization by the value that the parameter can take.
The internal structure normalization means performs normalization processing of the internal structure individually for each specialized parameter, normalizes the loops and functions of the internal structure,
CDFG generation means converts to CDFG by the CDFG generation process,
The binding means applies the scheduling means to the generated CDFG, performs the binding process,
The parameter merging means performs a parameter merging process that branches the binding process results specially executed for each parameter value.
The parameter variableization means performs parameter variable conversion that returns the parameter converted to a constant to the variable,
A behavioral synthesis method, wherein the RT description generation means generates an RT level description by RT level description generation processing.
When classifying into a plurality of parameters, the parameters are treated as variables by the parameter classification process, the parameters are considered to be the maximum value that can be taken by the parameter, the parameter values are synthesized, and the parameters can be specialized The behavioral synthesis method according to claim 5, wherein the behavioral synthesis method is classified into three types.
7. The behavioral synthesis method according to claim 6, wherein the parameter classification processing is executed in parallel in time by a plurality of processors or sequentially executed by a single processor.
7. The behavioral synthesis method according to claim 6, wherein a parameter variable process for returning to the original parameter is performed on the parameter obtained by synthesizing the parameter value as the maximum value that can be taken.
A means for converting a behavior level description in which a circuit specification having a high level of abstraction is described into an internal representation for behavioral synthesis by language analysis processing, and classifying parameters included in the behavior level description into a plurality Of the parameters, the parameter use point that is considered to be the maximum value of the parameter that can be synthesized is replaced with the constant value of the maximum value by the parameter constant processing, and the original parameter A means to set the name to be recorded, parameter use processing where the parameter value is to be synthesized as a specialization by the value that the parameter can take, specialize the parameter to each value by parameter specialization processing The internal structure normalization process is performed individually for each specialized parameter. Means for normalizing loops and functions, converting to CDFG by CDFG generation processing, applying scheduling processing to the generated CDFG, performing binding processing, specially executed for each parameter value A function for performing a parameter merge process for branching the binding process results together, a means for performing a parameter variable to return a constant parameter to a variable, and a means for generating an RT level description by an RT level description generation process. program.