JP5692063B2 - Behavioral synthesis apparatus, behavioral synthesis method, and program - Google Patents

Description

The present invention relates to a behavioral synthesis device, a behavioral synthesis method, and a program.

Behavioral synthesis systems are used in the design of integrated circuits.
The related behavioral synthesis system includes language analysis means (apparatus), internal structure normalization means (apparatus), CDFG generation means (apparatus), scheduling means (apparatus), binding means (apparatus), and RT description generation. And means (apparatus).
Here, CDFG is an abbreviation for Control Data Flow Graph, and is a kind of data structure. RT is an abbreviation for Register Transfer and is a kind of circuit description. Scheduling refers to determining a cycle for performing each process. Binding is to determine which computing unit or memory is actually used for each processing operation or memory access.
The behavioral synthesis system having such a configuration operates as follows.
This behavioral synthesis system analyzes behavioral descriptions given from the input device of this system, and normalizes structures such as functions and loops for generating CDFG. Further, the behavioral synthesis system generates a CDFG after normalization, then proceeds with scheduling and binding, and repeats these steps a plurality of times as necessary to generate an RT description.
In this type of behavioral synthesis system, parameters that are treated as constants in the final LSI circuit are regarded as constant parameters at the input stage from the input device to the behavioral synthesis system , and the behavioral synthesis system side sets the values of the parameters It was usual to optimize as a constant. Conversely, if the user wants to keep the parameters until after the behavioral synthesis is completed, there is no choice but to treat all parameters as variables, and as a result, optimization is significantly suppressed. It was. LSI is an abbreviation for Large Scale Integration, and means a large-scale integrated circuit.
Techniques related to this type of behavioral synthesis system are disclosed in Japanese Patent Application Laid-Open No. 2001-350809 (hereinafter referred to as Patent Document 1) and Japanese Patent Application Laid-Open Publication No. 2006-079226 (hereinafter referred to as Patent Document 2). The invention described in Patent Document 1 is an invention relating to a method for designing a data driven information processing apparatus employing self-synchronous pipeline control. Specifically, the present invention creates a library file that generally describes design parameters, sets parameter values for each design parameter, and creates a register transfer level design description. And a step including the step of:
According to the invention described in Patent Document 1, a designer can automatically create a register transfer level design description that conforms to a design specification, thereby shortening the design period, and also for various specifications. It is said that it can be easily handled and designed.
The invention described in Patent Document 2 is an invention related to a hardware description language synthesis tool and an integrated circuit design method using the same. More specifically, the present invention causes a computer to execute a procedure for analyzing a program, a procedure for converting an instruction code into a processor software file, and a procedure for outputting a processor hardware file and a processor software file. It is invention regarding the computer program.
According to the invention described in Patent Document 2, since the instruction code of the assembly level language program corresponds to a hardware component, if the assembly level language program is used, the hardware described in the hardware description language is 1: 1. It can be replaced with a hardware design file, which is practical for users.

However, in the technique related to the present invention described above, when the input device gives a parameter to the behavioral synthesis system in the behavioral synthesis, there is no option other than treating all the parameters as constants or treating them as variables. Therefore, when both the treatments are required, there is a problem that the related technology described above cannot promote the optimization.
The reason is that, in the above-described behavioral synthesis, values handled internally are limited to only constants or variables, and thus a method for specially handling only parameters has not been invented.
Accordingly, an object of the present invention is to provide a behavioral synthesis device, behavioral synthesis method, and program that can leave parameters in the RT description as parameters and can perform appropriate optimization.

The apparatus of the present invention includes an input device for inputting a behavior level description in which a circuit specification having a high level of abstraction is described, and converts the behavior level description into an internal representation for behavioral synthesis, and is included in the behavior level description. A data processing device that classifies the parameter into a plurality of parameters and treats the value of the parameter as a constant or a variable according to a result of the classification;
A storage device for storing the behavior level description and each parameter;
And an output device for outputting the RT description.
Here, the internal expression indicates an expression when the result of analyzing the behavioral level circuit description is saved in an abstract syntax tree (AST) or a data structure called CDFG.
According to the method of the present invention, a language analysis unit converts a behavior level description in which a circuit specification having a high degree of abstraction prepared by a user is described into an internal representation for behavioral synthesis by language analysis processing. The parameter classification means classifies the parameters included in the behavior level description into a plurality of parameters, and the parameter constant conversion means regards the combined parameters as the maximum value that the parameters can take among the classified parameters. For the changed parameter use location, the parameter is converted to the maximum constant value by the parameter constant processing, and the original parameter name is set to be recorded. For parameter use points that are supposed to be synthesized as parameters, parameters are set to their respective values by parameter specialization processing. The internal structure normalization means performs normalization processing of the internal structure individually for each specialized parameter, normalizes the loops and functions of the internal structure, and the CDFG generation means converts to CDFG by the CDFG generation processing, The scheduling means is applied to the CDFG generated by the binding means, the binding process is performed, and the parameter merge means performs a parameter merge process for branching together the binding process results that have been executed specialized for each parameter value. The parameter variableizing means performs parameter variableization to return the converted parameter to a variable, and the RT description generating means generates an RT level description by RT level description generating processing.
The program of the present invention includes a computer that converts a behavior level description in which a circuit specification with a high degree of abstraction prepared by a user is described into an internal representation for behavioral synthesis by language analysis processing, and is included in the behavior level description. The parameter is converted to the maximum value by the parameter constantization process for the parameter use part that is considered to be the maximum value of the possible values of the parameter among the classified parameters. In addition to replacing with a constant value, the parameter setting process is performed for the parameter use location that is to be synthesized as a means for setting the original parameter name to be recorded and the value that can be taken by the parameter. A means to specialize each value, normalize the internal structure for each specialized parameter, Means for normalizing loops and functions of substructures, converting into CDFG by CDFG generation processing, applying scheduling processing to the generated CDFG, performing binding processing, and executing for each parameter value A means for performing a parameter merge process for branching the binding processing results collectively, a means for performing a parameter variable for returning a constant parameter to a variable, and a means for generating an RT level description by an RT level description generation process It is characterized by that.

  According to the present invention, it is possible to provide a behavioral synthesis device, a behavioral synthesis method, and a program that can leave parameters in the RT description as parameters and can perform appropriate optimization.

It is a block diagram which shows one Embodiment of the behavioral synthesis apparatus which concerns on this invention. It is an example of the flowchart for demonstrating operation | movement of the behavioral synthesis apparatus shown in FIG. It is a block diagram which shows other embodiment of the behavioral synthesis apparatus which concerns on this invention. It is a block diagram which shows other embodiment of the behavioral synthesis apparatus which concerns on this invention. It is a block diagram which shows other embodiment of the behavioral synthesis apparatus which concerns on this invention. It is an example of the flowchart for demonstrating operation | movement of the behavioral synthesis apparatus shown in FIG. It is an example of the flowchart for demonstrating operation | movement of the behavioral synthesis apparatus shown in FIG. It is an example of the flowchart for demonstrating operation | movement of the behavioral synthesis apparatus shown in FIG.

データ処理装置２が、記述例１に示したパラメータを変数として扱って合成した場合、ＲＴ記述生成部２ｋは、最終的なＶｅｒｉｌｏｇ ＨＤＬとして、記述例２のように、Ｎをｐａｒａｍｅｔｅｒ（パラメータ）とした合成結果を発生する。
記述例２

記述例２は、記述例１に示した動作合成装置による変換結果例の一つである。
また、データ処理装置２が記述例１に示したパラメータを、パラメータの範囲での最大値としてみなして合成した場合、Ｎ＝８として扱う。したがって、パラメータ定数化部２ｃは記述例１を記述例３のように設定し、最終的にパラメータ変数化部２ｊはＶｅｒｉｌｏｇ ＨＤＬで（は）、８をＮに戻す。この結果、ＲＴ記述生成部２ｋは記述例４を発生する。
記述例３

記述例４

記述例３は、図１に示した動作合成装置による変換途中例の一つであり、記述例４は、図１に示した動作合成装置による変換結果例の一つである。
パラメータの取り得る値で特化した場合、パラメータ特化部２ｄは、記述例１を記述例５のような３種類のパターンとみなし、データ処理装置２がこの３種類のパターンのそれぞれを合成することになる。
記述例５

記述例５は、図１に示した動作合成装置による変換途中例の一つである。
パラメータマージ部２ｉが、パラメータをマージした後、ＲＴ記述生成部２ｋが最終的なＶｅｒｉｌｏｇ ＨＤＬとして、記述例６に示すようなＲＴ記述を発生する。
記述例６

記述例６では、Ｎの値に応じて、ｐａｒａｍｅｔｅｒではなく‘ｄｅｆｉｎｅする値を変えることになる。記述例６は、図１に示した動作合成装置による変換結果例の一つである。
記述例７は、本発明の実施の形態の動作合成装置の入力装置１に入力される、変数のビット幅にパラメータを用いた場合の動作記述の一例である。
記述例７

すなわち、記述例７は、図１に示した動作合成装置の入力となる動作記述の一例である。データ処理装置２が、記述例７に示したパラメータを変数として扱って合成した場合、ＲＴ記述生成部２ｋは、最終的なＶｅｒｉｌｏｇＨＤＬとして、記述例８のように、Ｎをｐａｒａｍｅｔｅｒとした合成結果となる。
記述例８

記述例８は、図１に示した動作合成装置による変換結果例の一つである。
また、記述例７の加算器ＩＮＳＴ＿ＡＤＤは、Ｎの値を書き換えることによってビット幅ＢＩＴＷがこの値で置き換えられる。このように、ｐａｒａｍｅｔｅｒでビット幅を調整可能な加算器とすることにより、パラメータごとに効率的な回路を生成可能となる。
また、データ処理装置２が記述例７に示したパラメータを、パラメータの範囲での最大値としてみなして合成した場合、Ｎ＝８として扱うため、パラメータ定数化部２ｃが記述例７を記述例９のようにみなし、最終的にパラメータ変数化部２ｉがＶｅｒｉｌｏｇ ＨＤＬで、８をＮに戻して、ＲＴ記述生成部２ｋは記述例１０を発生する。
記述例９

記述例１０

記述例９は、図１に示した動作合成装置による変換途中例の一つであり、
記述例１０は、図１に示した動作合成装置による変換結果例の一つである。
この場合、８がパラメータであったという情報を合成中にどこまで伝播させるかにより、Ｎの影響を受ける範囲が変わることになる。
記述例１０では、変数のビット幅そのものだけをＮでの制御可能範囲とした例であるため、加算器のビット幅はＮの最大値８に依存したものになっている。
また、パラメータの取り得る値で特化した場合、パラメータ特化部２ｄは、記述例７を記述例１１のように３種類のパターンとみなし、データ処理装置がこの３種類のパターンのそれぞれを合成することになる。
記述例１１

記述例１１は、図１に示した動作合成装置による変換途中例の一つである。
パラメータマージ部２ｉが、パラメータをマージした後、ＲＴ記述生成部２ｋが最終的なＶｅｒｉｌｏｇ ＨＤＬとして（では）、記述例１２のようなＲＴ記述を発生する。
記述例１２

記述例１２は、図１に示した動作合成装置による変換結果例の一つである。記述例１２において、Ｎの値に応じて特化して合成した結果のうち、同じ部分を一共有化して出力しているが、共有化は必須ではないため、全文をばらばらに出して、‘ｉｆｄｅｆで切り替えることも可能である。
記述例１３は、本発明の動作合成装置の入力装置に入力される、ループの実行回数にパラメータを用いた場合の動作記述の一例である。
記述例１３

データ処理装置２が、記述例１３に示したパラメータを変数として扱って合成した場合、記述例１４のように、ループの実行回数の取り得る値ごとに条件を付加してループを展開することができ、ＲＴ記述生成部２ｋは、最終的なＶｅｒｉｌｏｇ ＨＤＬとして、記述例１５のように、Ｎをｐａｒａｍｅｔｅｒとした合成結果を発生する。
記述例１４

記述例１３は、図１に示した動作合成装置の入力となる動作記述の一例であり、記述例１４は、図１に示した動作合成装置による変換途中例の一つである。記述例１５は、図１に示した動作合成装置による変換結果例の一つである。
記述例１５

一方、パラメータの範囲での最大値とした合成は、ループの実行回数など制御論理にパラメータが関わるときは不可能であるためこの手法を選択することはできない。パラメータの取り得る値で特化した場合、データ処理装置２は、記述例１３を記述例１６のように３種類のパターンとみなし、パラメータ特化部２ｄがこの３種類のパターンのそれぞれを合成することになる。そして、パラメータマージ部２ｉが、パラメータをマージした後、ＲＴ記述生成部２ｋが最終的なＶｅｒｉｌｏｇＨＤＬとして、記述例１７に示すようなＲＴ記述を発生する。
記述例１６

記述例１７

記述例１６は、図１に示した動作合成装置による変換途中例の一つである。記述例１７は、図１に示した動作合成装置による変換結果例の一つである。
このように、本実施形態の動作合成システムは、言語解析部と、内部構造正規化部と、ＣＤＦＧ生成部と、スケジューリング部と、バインディング部と、ＲＴ記述生成部とを備える。このような構成を採用し、パラメータを使用箇所に応じて、１）変数として扱い、同じパラメータを用いている変数同士などで適宜共有する、２）パラメータの範囲の最大値とみなして合成し、合成後にパラメータに戻す、３）パラメータの取り得る値に特化した回路を別個に合成して、その部分をＶｅｒｉｌｏｇ ＨＤＬの‘ｉｆｄｅｆディレクティブなどで切り替える、などの合成方法を選択することにより、本発明の目的を達成することができる。
本実施形態によれば、合成された回路の再利用性が高まる。
その理由は、一般的な動作合成装置は、動作合成後の回路で、ビット幅などのパラメータを変更した場合、パラメータを合成されたＲＴ記述にも変数として保持することで回路の品質を犠牲にするか、パラメータを変更して、再度、動作合成を実施することが求められていたのに対し、本実施形態では、ＲＴ記述上で、パラメータを変更するだけで、回路品質の犠牲を抑えつつ、再度、動作合成を実施することを避けられるためである。
ここで、上述した実施形態に係る動作合成システムと、特許文献との相違点について述べる。特許文献１に記載の発明は、パケットデータ幅、メモリタイプ、メモリ容量、並列データパス数など、予め決められた範囲の対象しかパラメタライズできない。これに対し、本実施形態は、図１のパラメータ分類部２ｂ、パラメータ定数化部２ｃ、パラメータ特化部２ｄ、パラメータマージ部２ｉ、及びパラメータ変数化部２ｊの後処理により、パラメータを動作合成で利用して最適化した上で、さらに最終出力であるＲＴ記述でもパラメータを変更する余地がある機構となっている点で特許文献１に記載の発明と相違する。
以上、実施形態を参照して本願発明を説明したが、本願発明は上記実施形態に限定されるものではない。本願発明の構成や詳細には、本願発明のスコープ内で当業者が理解し得る様々な変更をすることができる。
この出願は、２００９年３月２４日に出願された日本出願特願２００９−０７２３０１を基礎とする優先権を主張し、その開示の全てをここに取り込む。<Configuration>
Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of a behavioral synthesis device according to the present invention.
Referring to FIG. 1, the behavioral synthesis device includes a data processing device 2 that operates under program control, an input device 1, a storage device 3, and an output device 4.
Examples of the input device 1 include a keyboard, a mouse, and a pointing device.
The data processing device 2 includes a language analysis unit 2a, a parameter classification unit 2b, an internal structure normalization unit 2e, a parameter constant conversion unit 2c, a parameter specialization unit 2d, a CDFG generation unit 2f, a scheduling unit 2g, a binding unit 2h, a parameter merge A unit 2i, a parameter variable unit 2j, and an RT description generation unit 2k.
Examples of the storage device 3 include an HDD (Hard Disc Drive: hard disk) and a flash memory.
Examples of the output device 4 include a liquid crystal display device, a plasma display, a printer, and a plotter.
These language analysis units 2a to RT description generation unit 2k are configured by software and operate as follows.
The language analysis unit 2a analyzes the behavior level description including the parameter given by the input device 1 and converts it into an internal representation. Here, the language is, for example, a software language (also referred to as behavior level description) describing the behavior level of the design parameter. The parameter is, for example, an LSI design parameter that is handled as a constant or a variable.
The parameter classification unit 2b considers the internal description of the behavioral description given by the language analysis unit 2a, the parameters, and the parameter processing method designation by the user, and treats the parameters as variables, and the values that the parameters can take. They are classified into three types: those that are considered to be the maximum value, and those that are synthesized by values that can be taken by the parameter.
The parameter constant conversion unit 2c replaces the parameter use location, which the parameter classification unit 2b considers as the maximum value of the parameter, and synthesizes it with the constant value of the maximum value, and records the original parameter name. Set to be.
In the parameter specialization unit 2d, an internal representation (or internal structure) that is actually specialized with a plurality of possible values for the parameter use location determined by the parameter classification unit 2b to be specialized with the possible values of the parameters. ) Each.
The internal structure normalization unit 2e normalizes each internal representation specialized for the parameter by the parameter specialization unit 2d, for example, by appropriately expanding a part corresponding to a function or a loop.
The CDFG generation unit 2f converts each normalized internal representation into a CDFG (control data flow graph).
The scheduling unit 2g schedules resources and input / output on each CDFG generated by the CDFG generation unit 2f.
The binding unit 2h allocates resources such as computing units based on the scheduling result realized by repeating the scheduling unit 2g.
The parameter merging unit 2i specializes each possible value of the parameter by the parameter specializing unit 2d, and merges the ones that have been implemented up to the binding by the binding unit 2h based on the respective parameter values so as to branch by the parameter value. To do.
The parameter variable conversion unit 2j restores the parameter converted to the maximum constant by the parameter constant conversion unit 2c to the original parameter. Further, the parameter variable conversion unit 2j generates an RT description by the RT description generation unit 2k based on the result, and outputs the RT description to the output device 4.
Each processing means writes and reads the conversion result to the system internal representation storage unit 3a belonging to the storage device 3 of the system as necessary.
<Operation>
Next, the overall operation of this embodiment will be described in detail with reference to FIG.
FIG. 2 is an example of a flowchart for explaining the operation of the behavioral synthesis device shown in FIG.
First, the user prepares a behavior level description in which a circuit specification having a high degree of abstraction such as C language is described (block A1 in FIG. 2). This behavioral description is a description including parameters, which is a target of the embodiment of the present invention.
Next, the language analysis unit 2a converts the behavior level description of A1 into an internal expression for behavioral synthesis by language analysis processing (block A2 in FIG. 2). The converted internal representation is represented by a data structure such as AST (abstract syntax tree).
Next, the parameter classification unit 2b uses parameter classification processing (block A3 in FIG. 2) to treat the parameter in the behavior level description as a variable, to synthesize the parameter as the maximum value that the parameter can take, It is classified into three types, specializing in possible values. Of the classified parameters, the parameter constant conversion unit 2c executes the parameter constant conversion process (block A4 in FIG. 2) for the parameter use location that is to be combined as the maximum value that the parameter can take. That is, the parameter constant conversion unit 2c replaces the parameter with the maximum constant value and sets the original parameter name to be recorded. Further, the parameter specializing unit 2d performs a parameter specialization process (block A5 in FIG. 2) on the used part of the parameter that is to be synthesized as a specialization with a possible value of the parameter. That is, the parameter specialization unit 2d generates an internal representation (internal structure) that specializes a parameter with a plurality of possible values for each parameter usage location. Thereafter, the internal structure normalization unit 2e, the CDFG generation unit 2f, the scheduling unit 2g, and the binding unit 2h individually execute the respective processes for each specialized parameter. This process can be executed in parallel in time by a plurality of processors or sequentially by a single processor. The processes in the internal structure normalization unit 2e, the CDFG generation unit 2f, the scheduling unit 2g, and the binding unit 2h will be described in this order.
The internal structure normalization unit 2e performs normalization processing (block A6 in FIG. 2) on the internal structure generated by the parameter specialization unit 2d to normalize loops and functions of the internal structure.
Next, the CDFG generation unit 2f converts the normalized internal structure into CDFG by a CDFG generation process (block A7 in FIG. 2). Next, the scheduling unit 2g performs scheduling (block A8 in FIG. 2) on the generated CDFG, and the binding unit 2h performs binding processing (block A9 in FIG. 2). That is, the binding unit 2h allocates a resource such as an arithmetic unit to each normalized internal structure based on the scheduling result in the scheduling unit 2g.
Subsequently, the parameter merging unit 2i performs a parameter merging process (block A10 in FIG. 2) for collecting the binding process results specialized for each parameter value and branching by the parameter value.
The parameter variableizing unit 2j performs the parameter variableizing process (block A11 in FIG. 2) for returning the parameter to the original parameter for the parameter constantized by the parameter constantizing unit 2c. Do.
Finally, the RT description generation unit 2k generates an RT level description (block A13 in FIG. 2) by RT level description generation processing (block A12 in FIG. 2).
<Effect of Embodiment>
Next, the effect of this embodiment will be described.
In this embodiment, the parameters are classified into variables, constants based on maximum values, and specialized constants, and then converted, so that the effect of differences in parameter processing on scheduling and binding, which is the main processing in the behavioral synthesis system, is achieved. As a result, it is possible to achieve the object of the present invention to reflect the parameters in the operation description in the RT level description while suppressing the deterioration of the circuit performance. This is because the parameter classification unit classifies the parameters included in the behavior level description into a plurality of parameters, and the data processing apparatus outputs the RT description according to the result of the classification.
In the embodiment of the present invention, the process related to the parameter is realized by placing the process before the normalization of the internal structure and after the binding process. However, the embodiment of the present invention realizes processing related to parameters as a part of another means such as language analysis means, internal structure normalization means, CDFG generation means, and scheduling means, depending on the behavioral synthesis realization method. Is also possible. In the embodiment of the present invention, it is also possible to realize processing relating to parameters at a plurality of processing positions as a part of the plurality of means described above.
<Program and storage medium>
The behavioral synthesis apparatus according to the present invention described above is realized by a program that causes a computer to execute processing. Examples of the computer include general-purpose computers such as personal computers and workstations, but the present invention is not limited to this. As an example, a case where the behavioral synthesis device according to the above-described embodiment is realized by executing a software program on a computer will be described below.
Computer
(1) Means for converting a behavior level description prepared by a user describing a high-level circuit specification into an internal representation for behavioral synthesis by language analysis processing and classifying it into a plurality of
(2) Of the classified parameters, the parameter use point that is supposed to be synthesized as the maximum value that can be taken by the parameter is replaced with the constant value of the maximum value by the parameter constant processing, and originally Means to record the parameter name of
(3) Means for specializing a parameter to each value by a parameter specialization process for a parameter use location that is to be synthesized as a specialization with a possible value of the parameter;
(4) perform specialized normalization process of the internal structure individually for each parameter, it means for normalizing the loop and a function of an internal structure,
(5) means for converting into CDFG by CDFG generation processing, applying scheduling processing to the generated CDFG, and performing binding processing;
(6) Means for performing a parameter merge process for branching together the binding process results that are specialized for each parameter value;
(7) Means for parameterization to return a constant parameter to a variable,
(8) means for generating an RT level description by RT level description generation processing;
As a program for making it function.
Thus, the behavioral synthesis apparatus according to the present invention can be realized anywhere as long as there is a computer environment capable of executing the program.
Such a program may be stored in a computer-readable storage medium.
Here, examples of the storage medium include a computer-readable storage medium such as a CD-ROM (Compact Disc Read Only Memory), a flexible disk (FD), and a CD-R (CD-Recordable), a flash memory, and a RAM (RAM). Examples thereof include a semiconductor memory such as a random access memory (ROM), a read only memory (ROM), and a FeRAM (ferroelectric memory) and an HDD.
In the above-described embodiment, the case has been described in which the parameters are classified into those to be synthesized by regarding them as the maximum value, and those to be specifically executed for each possible value of the parameter. Specifically, the data processing device converts the parameter into a constant value of the maximum value for the parameter use location that is considered to be the maximum value that can be taken by the parameter among the classified parameters. Yes. At this time, the data processing apparatus is set to record the original parameter name. The data processing apparatus specializes the parameter for each value and executes the parameter for each parameter value at a parameter use location that is to be synthesized as a special value that can be taken by the parameter. The data processing apparatus performs parameter merge processing for branching these specialized binding processing results collectively. Finally, the data processing apparatus performs a parameter variable process for returning the constant parameter to a variable.
The embodiment described above shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. Other embodiments will be described below.
FIG. 3 is a block diagram showing another embodiment of the behavioral synthesis device according to the present invention.
FIG. 4 is a block diagram showing another embodiment of the behavioral synthesis device according to the present invention.
FIG. 5 is a block diagram showing another embodiment of the behavioral synthesis device according to the present invention.
FIG. 6 is an example of a flowchart for explaining the operation of the behavioral synthesis device shown in FIG.
FIG. 7 is an example of a flowchart for explaining the operation of the behavioral synthesis device shown in FIG.
FIG. 8 is an example of a flowchart for explaining the operation of the behavioral synthesis device shown in FIG.
The present invention may be any of the following embodiments (a) to (c) described in FIGS.
(A) Among the classified parameters, regarding the parameter use location that is supposed to be synthesized as the maximum value that the parameter can take, the parameter is converted into a constant value of the maximum value, and the converted parameter is used as a variable. Perform parameter variableization processing to return (FIGS. 4 and 7),
(B) The parameter name is set so that the original parameter name is recorded, and the parameter is used for each parameter value for the parameter use location that is to be synthesized as a special value that can be taken by the parameter. A parameter merging process for branching together the results of the binding process executed in a specialized manner (FIGS. 3 and 6),
(C) Neither (a) nor (b) is performed (FIGS. 5 and 8).
Next, the operation of the best mode for carrying out the present invention will be described using a specific example.
In the following description examples 1 to 17, the operation description conforms to the notation in the SystemC language, and the RT description conforms to the Verilog HDL notation.
Here, the designer uses #pragma PARAMETER (N)
Can specify that the argument of PARAMETER (N in this case) is a parameter, and the range of values and discrete values such as #pragma PARAMETER (N; 0-3, 5, 7-8, 10) A value can be specified. In this case, 0, 1, 2, 3, 5, 7, 8, and 10 are possible parameter values. The value specified by the parameter is used for comparison, substitution, and calculation in the circuit to be designed, and is mainly used for the word length (number of elements) of the array, the bit width of the variable, the number of loop executions, and the like.
The description example 1 is an example of a behavior description when a parameter is used for the word length of the array, which is input to the input device 1 of the behavioral synthesis device according to the embodiment of the present invention.
Description example 1

When the data processing device 2 synthesizes the parameters shown in the description example 1 as variables, the RT description generation unit 2k sets N as a parameter (parameter) as the final Verilog HDL as in the description example 2. The synthesized result is generated.
Description example 2

Description example 2 is one example of a conversion result by the behavioral synthesis device shown in description example 1.
Further, when the data processing apparatus 2 regards the parameter shown in the description example 1 as a maximum value in the parameter range and combines them, it is handled as N = 8. Therefore, the parameter constant conversion unit 2c sets the description example 1 as in the description example 3, and finally the parameter variable conversion unit 2j is Verilog HDL (8) and returns 8 to N. As a result, the RT description generation unit 2k generates description example 4.
Description example 3

Description example 4

The description example 3 is one of conversion examples by the behavioral synthesis device shown in FIG. 1, and the description example 4 is one of conversion results by the behavioral synthesis device shown in FIG.
When specializing with possible values of parameters, the parameter specializing unit 2d regards the description example 1 as three types of patterns like the description example 5, and the data processing device 2 synthesizes each of these three types of patterns. It will be.
Description example 5

The description example 5 is one example of conversion in progress by the behavioral synthesis device shown in FIG.
After the parameter merge unit 2i merges the parameters, the RT description generation unit 2k generates an RT description as shown in the description example 6 as the final Verilog HDL.
Description example 6

In the description example 6, according to the value of N, the value to be defined is changed instead of the parameter. Description example 6 is one example of a conversion result by the behavioral synthesis device shown in FIG.
The description example 7 is an example of a behavior description when a parameter is used for the bit width of a variable that is input to the input device 1 of the behavioral synthesis device according to the embodiment of the present invention.
Description example 7

That is, the description example 7 is an example of a behavior description that becomes an input of the behavioral synthesis device illustrated in FIG. When the data processing apparatus 2 treats the parameter shown in the description example 7 as a variable and synthesizes it, the RT description generation unit 2k sets the final Verilog HDL as a description result in which N is a parameter as in the description example 8. Become.
Description example 8

The description example 8 is one example of a conversion result by the behavioral synthesis device shown in FIG.
Further, the adder INST_ADD of the description example 7 replaces the bit width BITW with this value by rewriting the value of N. In this way, an efficient circuit can be generated for each parameter by using an adder in which the bit width can be adjusted by a parameter.
In addition, when the data processing apparatus 2 regards the parameter shown in the description example 7 as a maximum value in the parameter range and synthesizes the parameter, the parameter constantizing unit 2c treats the description example 7 as the description example 9. Finally, the parameter variableizing unit 2i is Verilog HDL, 8 is returned to N, and the RT description generating unit 2k generates the description example 10.
Description example 9

Description example 10

Description example 9 is one example of conversion in progress by the behavioral synthesis device shown in FIG.
The description example 10 is one example of the conversion result by the behavioral synthesis device shown in FIG.
In this case, the range affected by N varies depending on how far the information that 8 is a parameter is propagated during synthesis.
In the description example 10, only the bit width of the variable itself is an N controllable range, so the bit width of the adder depends on the maximum value 8 of N.
Also, when specializing with possible values of parameters, the parameter specializing unit 2d regards the description example 7 as three types of patterns like the description example 11, and the data processing apparatus synthesizes each of these three types of patterns. Will do.
Description example 11

The description example 11 is one example of conversion in progress by the behavioral synthesis device shown in FIG.
After the parameter merging unit 2i merges the parameters, the RT description generating unit 2k generates (in) the RT description as in the description example 12 as the final Verilog HDL.
Description example 12

The description example 12 is one example of the conversion result by the behavioral synthesis device shown in FIG. In the description example 12, the same part of the result synthesized according to the value of N is shared and output. However, since sharing is not essential, the whole sentence is output separately, and 'ifdef It is also possible to switch with.
The description example 13 is an example of a behavior description in the case where a parameter is used for the number of loop executions, which is input to the input device of the behavioral synthesis device of the present invention.
Description example 13

When the data processing device 2 treats the parameters shown in the description example 13 as variables and synthesizes them, the loop may be expanded by adding a condition for each possible value of the loop execution number as in the description example 14. The RT description generation unit 2k generates a synthesis result with N as a parameter as described in the description example 15 as the final Verilog HDL.
Description example 14

The description example 13 is an example of a behavior description that is input to the behavioral synthesis device illustrated in FIG. 1, and the description example 14 is one example of an intermediate conversion by the behavioral synthesis device illustrated in FIG. 1. The description example 15 is one of conversion result examples by the behavioral synthesis device shown in FIG.
Description example 15

On the other hand, since the synthesis with the maximum value in the parameter range is impossible when parameters are involved in the control logic such as the number of loop executions, this method cannot be selected. When specializing with possible values of parameters, the data processing apparatus 2 regards the description example 13 as three types of patterns as in the description example 16, and the parameter specialization unit 2d synthesizes each of these three types of patterns. It will be. Then, after the parameter merge unit 2i merges the parameters, the RT description generation unit 2k generates an RT description as shown in the description example 17 as the final Verilog HDL.
Description Example 16

Description example 17

The description example 16 is one example of conversion in progress by the behavioral synthesis device shown in FIG. The description example 17 is one example of the conversion result by the behavioral synthesis device shown in FIG.
As described above, the behavioral synthesis system of this embodiment includes a language analysis unit, an internal structure normalization unit, a CDFG generation unit, a scheduling unit, a binding unit, and an RT description generation unit. Adopting such a configuration, depending on the location of use, 1) treat it as a variable, and share it appropriately among variables using the same parameter, etc. 2) Combining it as the maximum value of the parameter range, By selecting a synthesis method, such as returning to a parameter after synthesis, 3) separately synthesizing a circuit specialized for a possible value of the parameter, and switching the portion with a 'ifdef directive of Verilog HDL, etc. Can achieve the purpose.
According to this embodiment, the reusability of the synthesized circuit is enhanced.
The reason is that when a behavioral synthesis device changes parameters such as bit width in a circuit after behavioral synthesis, the quality of the circuit is sacrificed by retaining the parameter as a variable in the synthesized RT description. On the other hand, while it was required to change the parameters and perform behavioral synthesis again, in the present embodiment, while changing the parameters on the RT description, the sacrifice of circuit quality is suppressed. This is because it is possible to avoid performing behavioral synthesis again.
Here, the difference between the behavioral synthesis system according to the above-described embodiment and the patent document will be described. The invention described in Patent Document 1 can parameterize only objects in a predetermined range such as packet data width, memory type, memory capacity, and number of parallel data paths. On the other hand, in the present embodiment, the parameters are synthesized by the post-processing of the parameter classification unit 2b, the parameter constant conversion unit 2c, the parameter specialization unit 2d, the parameter merge unit 2i, and the parameter variable conversion unit 2j in FIG. It differs from the invention described in Patent Document 1 in that the mechanism has room for changing parameters even in the RT description, which is the final output, after being optimized.
While the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.
This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2009-073021 for which it applied on March 24, 2009, and takes in those the indications of all here.

  The present invention can be applied to a behavioral synthesis device that synthesizes a circuit description with a low level of abstraction from a circuit description with a high level of abstraction.

DESCRIPTION OF SYMBOLS 1 Input device 2 Data processor 2a Language analysis part 2b Parameter classification part 2c Parameter constantization part 2d Parameter specialization part 2e Internal structure normalization part 2f CDFG generation part 2g Scheduling part 2h Binding part 2i Parameter merge part 2j Parameter variable part 2k RT description generation unit 3 storage device 3a system internal representation storage unit 4 output device

Claims (12)

An input means for inputting a behavior level description in which a circuit specification having a high level of abstraction is described;
The behavior level description is converted into an internal representation for behavioral synthesis by language analysis processing, and the parameter is converted into a variable based on the internal representation, the parameter included in the behavior level description, and the parameter processing method specification by the user. Language analysis means for classifying into three types, those that are handled as they are, those that are considered as the maximum value that can be taken by the parameter, those that are synthesized, and those that are specialized by the value that can be taken by the parameter,
Among the classified parameters, the parameter values before normalization are determined by the parameter constant processing for the use points in the internal representation of the parameters that are considered to be the maximum values that can be taken by the parameters. A parameter constant means for replacing the numerical value and recording the original parameter name,
For the parameter replaced with the constant value of the maximum value, for each parameter, the internal representation normalization processing is performed individually, and the internal structure normalizing means for normalizing the loop and function of the internal representation,
CDFG generation means for converting each of the normalized internal representations into CDFG by CDFG generation processing;
Binding means for applying a binding process to each generated CDFG by applying a scheduling means;
Parameter variableizing means for performing parameter variable processing for returning the constant parameter in each binding processing result to a variable;
RT description generation means for generating an RT level description based on each binding processing result subjected to the parameter variable processing by RT level description generation processing;
Storage means for storing the behavior level description and each parameter;
Output means for outputting the RT level description;
A behavioral synthesis device comprising: An input means for inputting a behavior level description in which a circuit specification having a high level of abstraction is described;
The behavior level description is converted into an internal representation for behavioral synthesis by language analysis processing, and the parameter is converted into a variable based on the internal representation, the parameter included in the behavior level description, and the parameter processing method specification by the user. Language analysis means for classifying into three types, those that are handled as they are, those that are considered as the maximum value that can be taken by the parameter, those that are synthesized, and those that are specialized by the value that can be taken by the parameter,
Among the classified parameters, parameters that specialize the parameter to each value by the parameter specialization process for the use location in the internal representation of the parameter that is to be synthesized as a specialization by the value that the parameter can take Specialized means,
For the specialized parameter, for each specialized value, the internal representation normalization processing is performed individually, and the internal structure normalizing means for normalizing the loop and function of the internal representation;
CDFG generation means for converting each of the normalized internal representations into CDFG by CDFG generation processing;
Binding means for applying a binding process to each generated CDFG by applying a scheduling means;
Parameter merging means for performing parameter merging processing for branching together the binding processing results executed for the specialized values of the parameters;
RT description generation means for generating an RT level description based on the result of each binding process subjected to the parameter merge process by an RT level description generation process;
Storage means for storing the behavior level description and each parameter;
A behavioral synthesis device comprising: output means for outputting the RT level description. An input means for inputting a behavior level description in which a circuit specification having a high level of abstraction is described;
The behavior level description is converted into an internal representation for behavioral synthesis by language analysis processing, and the parameter is converted into a variable based on the internal representation, the parameter included in the behavior level description, and the parameter processing method specification by the user. Language analysis means for classifying into three types, those that are handled as they are, those that are considered as the maximum value that can be taken by the parameter, those that are synthesized, and those that are specialized by the value that can be taken by the parameter,
Among the classified parameters, the parameter values before normalization are determined by the parameter constant processing for the use points in the internal representation of the parameters that are considered to be the maximum values that can be taken by the parameters. A parameter constant means for replacing the numerical value and recording the original parameter name,
Among the classified parameters, parameters that specialize the parameter to each value by the parameter specialization process for the use location in the internal representation of the parameter that is to be synthesized as a specialization by the value that the parameter can take Specialized means,
For the parameter replaced with the constant value of the maximum value, the internal expression is normalized individually for each parameter, the loop and function of the internal expression are normalized, and the specialized parameter is Internal structure normalization means for performing normalization processing of the internal representation individually for each of the converted values and normalizing loops and functions of the internal representation;
A CDFG generating means for converting each normalized internal expression into a CDFG by a CDFG generating process;
Binding means for applying a binding process to each generated CDFG by applying a scheduling means;
Parameter variableizing means for performing parameter variable processing for returning the constant parameter in each binding processing result to a variable;
Parameter merging means for performing parameter merging processing for branching together the binding processing results executed for the specialized values of the parameters;
RT description generation means for generating an RT level description based on each binding processing result subjected to the parameter variable processing and each binding processing result executed for a specific value of the parameter by RT level description generating processing When,
Storage means for storing the behavior level description and each parameter;
A behavioral synthesis device comprising: output means for outputting the RT level description.   4. The operation according to claim 1, wherein the language analysis unit executes the classification of the parameters in parallel in time by a plurality of processors, or sequentially by a single processor. Synthesizer. Computer
Enter the behavior level description that describes the circuit specification with a high level of abstraction.
The behavior level description is converted into an internal representation for behavioral synthesis by language analysis processing, and the parameter is converted into a variable based on the internal representation, the parameter included in the behavior level description, and the parameter processing method specification by the user. It is classified into three types: those that are handled as they are, those that are synthesized as the maximum value that can be taken by the parameter, and those that are specialized by the value that can be taken by the parameter.
Among the classified parameters, the parameter values before normalization are determined by the parameter constant processing for the use points in the internal representation of the parameters that are considered to be the maximum values that can be taken by the parameters. Replace it with a numerical value and record the original parameter name.
For each parameter that has been replaced with the constant value of the maximum value, for each parameter, perform the normalization processing of the internal representation individually, normalize the loop and function of the internal representation,
Converting each normalized internal representation into CDFG by CDFG generation processing,
A binding process is performed on each generated CDFG by applying a scheduling means,
Perform parameter variable processing to return the constant parameter in each binding processing result to a variable,
RT level description generation processing generates an RT level description based on each binding processing result subjected to the parameter variable processing,
Storing the behavior level description and each parameter;
A behavioral synthesis method for outputting the RT level description. Computer
Enter the behavior level description that describes the circuit specification with a high level of abstraction.
The behavior level description is converted into an internal representation for behavioral synthesis by language analysis processing, and the parameter is converted into a variable based on the internal representation, the parameter included in the behavior level description, and the parameter processing method specification by the user. It is classified into three types: those that are handled as they are, those that are synthesized as the maximum value that can be taken by the parameter, and those that are specialized by the value that can be taken by the parameter.
Among the categorized parameters, the parameter specialization process is used to specialize the parameter to each value for the use location in the internal representation of the parameter that is supposed to be synthesized as a value that can be taken by the parameter,
For the specialized parameter, for each specialized value, the internal representation is individually normalized, the internal representation loop and function are normalized,
Converting each normalized internal representation into CDFG by CDFG generation processing,
A binding process is performed on each generated CDFG by applying a scheduling means,
Perform a parameter merge process to branch together the binding process results executed for the specialized values of the parameters,
The RT level description generation process generates an RT level description based on the result of each binding process subjected to the parameter merge process,
Storing the behavior level description and each parameter;
A behavioral synthesis method for outputting the RT level description. Computer
Enter the behavior level description that describes the circuit specification with a high level of abstraction.
The behavior level description is converted into an internal representation for behavioral synthesis by language analysis processing, and the parameter is converted into a variable based on the internal representation, the parameter included in the behavior level description, and the parameter processing method specification by the user. It is classified into three types: those that are handled as they are, those that are synthesized as the maximum value that can be taken by the parameter, and those that are specialized by the value that can be taken by the parameter.
Among the classified parameters, the parameter values before normalization are determined by the parameter constant processing for the use points in the internal representation of the parameters that are considered to be the maximum values that can be taken by the parameters. Replace it with a numerical value and record the original parameter name.
Among the categorized parameters, the parameter specialization process is used to specialize the parameter to each value for the use location in the internal representation of the parameter that is supposed to be synthesized as a value that can be taken by the parameter,
For the parameter replaced with the constant value of the maximum value, the internal expression is normalized individually for each parameter, the loop and function of the internal expression are normalized, and the specialized parameter is For each value, the normalization of the internal representation is performed individually, and the loop and function of the internal representation are normalized,
Converting each normalized internal representation into CDFG by CDFG generation processing,
A binding process is performed on each generated CDFG by applying a scheduling means,
Perform parameter variable processing to return the constant parameter in each binding processing result to a variable,
Perform a parameter merge process to branch together the binding process results executed for the specialized values of the parameters,
RT level description generation processing generates an RT level description based on each binding processing result subjected to the parameter variable processing and each binding processing result executed for a specialized value of the parameter,
Storing the behavior level description and each parameter;
A behavioral synthesis method for outputting the RT level description.   The behavioral synthesis method according to any one of claims 5 to 7, wherein the parameter classification is executed in parallel in time by a plurality of processors or sequentially by a single processor. Input processing for inputting a behavior level description in which a circuit specification having a high level of abstraction is described;
Converting the behavior level description into an internal representation for behavioral synthesis, and treating the parameter as a variable based on the internal representation, the parameter included in the behavior level description, and the parameter processing method designation by the user; Language analysis processing classified into three types, one that is considered as the maximum value that can be taken by the parameter, and one that is synthesized by the value that can be taken by the parameter,
Among the classified parameters, the parameter values before normalization are determined by the parameter constant processing for the use points in the internal representation of the parameters that are considered to be the maximum values that can be taken by the parameters. Parameter constant processing that replaces with numerical values and records the original parameter name,
For the parameter replaced with the constant value of the maximum value, for each parameter, the internal representation normalization process is performed individually, and the internal structure normalization process for normalizing the loop and function of the internal representation;
CDFG generation processing for converting each normalized internal representation into CDFG;
A binding process for applying a scheduling process to each generated CDFG by applying a scheduling means;
A parameter variableizing process for performing a parameter variable process for returning the constant parameter in each binding process result to a variable;
RT description generation processing for generating an RT level description based on each binding processing result subjected to the parameter variable processing, and storage processing for storing the behavior level description and each parameter in a storage device;
A behavioral synthesis program for causing a computer to execute output processing for outputting the RT level description. Input processing for inputting a behavior level description in which a circuit specification having a high level of abstraction is described;
Converting the behavior level description into an internal representation for behavioral synthesis, and treating the parameter as a variable based on the internal representation, the parameter included in the behavior level description, and the parameter processing method designation by the user; Language analysis processing classified into three types, one that is considered as the maximum value that can be taken by the parameter, and one that is synthesized by the value that can be taken by the parameter,
Among the classified parameters, parameters that specialize the parameter to each value by the parameter specialization process for the use location in the internal representation of the parameter that is to be synthesized as a specialization by the value that the parameter can take Specialized processing,
For the specialized parameter, for each specialized value, the internal representation normalization processing is performed individually, and the internal structure normalization processing for normalizing the loop and function of the internal representation;
CDFG generation processing for converting each normalized internal representation into CDFG;
A binding process for applying a scheduling process to each generated CDFG by applying a scheduling means;
A parameter merge process for branching together the binding process results executed for the specialized values of the parameters;
RT description generation processing for generating an RT level description based on each binding processing result subjected to the parameter merge processing by RT level description generation processing;
A storage process for storing the behavior level description and each parameter in a storage device;
A behavioral synthesis program for causing a computer to execute output processing for outputting the RT level description. Input processing for inputting a behavior level description in which a circuit specification having a high level of abstraction is described;
Converting the behavior level description into an internal representation for behavioral synthesis, and treating the parameter as a variable based on the internal representation, the parameter included in the behavior level description, and the parameter processing method designation by the user; Language analysis processing classified into three types, one that is considered as the maximum value that can be taken by the parameter, and one that is synthesized by the value that can be taken by the parameter,
Among the classified parameters, regarding the use location in the internal representation of the parameter that is considered to be the maximum value of the parameter, the parameter before normalization is replaced with the constant value of the maximum value, and originally A parameter constant process that records the parameter name of
Among the classified parameters, the parameter specialization process that specializes the parameter to each value for the use location in the internal representation of the parameter that is supposed to be synthesized as a value that can be taken by the parameter,
For the parameter replaced with the constant value of the maximum value, normalization processing of the internal representation is performed for each parameter individually, and for the specialized parameter, the internal representation is individually performed for each specialized value. An internal structure normalization process for normalizing the internal expression loop and function,
CDFG generation processing for converting each normalized internal representation into CDFG;
A binding process for applying a scheduling process to each generated CDFG by applying a scheduling means;
A parameter variable process for returning the constant parameter in each binding process result to a variable;
A parameter merge process for branching together the binding process results executed for the specialized values of the parameters;
RT description generation processing for generating an RT level description based on each binding processing result subjected to the parameter variable processing and each binding processing result subjected to the parameter merge processing; and the behavior level description and each parameter in a storage device A storage process to store;
An output process for outputting the RT level description;
Is a behavioral synthesis program that runs a computer. The operation according to any one of claims 9 to 11 , wherein the language analysis processing is performed by executing the parameter classification in parallel in time by a plurality of processors or sequentially by a single processor. Synthesis program.

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