JP2006171099A - Manufacturing method for wiring board, the wiring board, manufacturing method for semiconductor substrate, the semiconductor substrate and manufacturing method for elecro-optical apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a wiring board, a wiring substrate, a manufacturing method for a semiconductor substrate, a semiconductor substrate and a manufacturing method for an electro-optical apparatus, where conductivity between conductive patterns are surely obtained. <P>SOLUTION: The manufacturing method for the wiring substrate 1, including a connection process of the plurality of conductive patterns 12 and 13 which are provided with a gap between them, comprises a conductive pattern forming process for forming a plurality of conductive patterns 12 and 13, so that a narrow sections 16 and 17 whose widths are narrower than those of pattern bodies 14 and 15 is formed at an edge section of a connection side, of at least one conductive pattern of the plurality of conductive patterns 12 and 13; and a connection process of electrically connecting the plurality of conductive patterns 12 and 13 by electroless plating. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a wiring substrate, a wiring substrate, a method for manufacturing a semiconductor substrate, a method for manufacturing a semiconductor substrate, and an electro-optical device.

  In general, as an electro-optical device such as a liquid crystal display device or an organic electroluminescence (hereinafter referred to as EL) device, a device including a structure in which a semiconductor element such as a thin film transistor (hereinafter referred to as a TFT) is provided on a substrate is known. Yes. When manufacturing a semiconductor substrate including such a semiconductor element, a high-temperature process is often required. Therefore, when the semiconductor element is formed on the substrate to constitute an electro-optical device, thermal deformation of the substrate and peripheral circuits There is a possibility that the element is destroyed and the life is shortened, and as a result, the characteristics of the electro-optical device are deteriorated.

Therefore, in recent years, after forming a semiconductor element such as a TFT on a heat-resistant basic substrate using conventional semiconductor manufacturing technology including a high-temperature process, an element forming film (layer) in which the TFT is formed from the basic substrate. A transfer technique has been proposed in which an electro-optical device is manufactured by peeling the film and affixing the film to a wiring board (see, for example, Patent Document 1). By using such a transfer technique, a semiconductor element can be formed on a plastic substrate having a relatively low heat resistance, and the design range of the electro-optical device is widened. As a result, thermal deformation of the substrate and destruction of the circuit elements can be suppressed, and a suitable electro-optical device can be provided.
JP 2003-031778 A

In the transfer technique described above, in order to mount the semiconductor element on the wiring board, the conductive particles are printed and arranged on the bumps formed on the wiring board, and after the semiconductor element is transferred via the curable resin, The wiring board and the semiconductor element are bonded by heating and pressing. However, if the amount of heat and pressure is increased to avoid open defects, the semiconductor element may be broken or damaged.
In view of this, a method has been proposed in which a connection terminal (conductive pattern) of a semiconductor element is transferred onto a wiring board so that the upper surface faces the upper surface. As a mounting method in this case, a method is adopted in which plating is grown by electroless plating from both the connection terminal (conductive pattern) of the wiring board and the connection terminal of the semiconductor element, and the two are made conductive. Further, an electroless plating method is adopted as a method for connecting a plurality of conductive patterns arranged on the wiring board.

However, since the shape of the connection terminal is generally rectangular, a minute gap is formed between both platings at the plating contact portion (contact part) grown from different connection terminals. It becomes difficult to join. In addition, with the narrowing of the pitch of the connection terminals, it is difficult for the plating solution to flow from the side into the mating portions of both platings. And when both plating grows with a gap kept at the mating part, there arises a problem that conduction between the connection terminals cannot be obtained or connection reliability cannot be ensured. Further, since the mating portions of the plating grown from different connection terminals are in surface (line) contact, an interface is generated at the mating portion, and there is a problem that the plating peels off at this interface.
The present invention has been made in view of the above-described problems, and a wiring board manufacturing method, a wiring board, a semiconductor substrate manufacturing method, a semiconductor substrate, and an electro-optical device capable of reliably obtaining conduction between conductive patterns. The object is to provide a manufacturing method.

In order to achieve the above object, the present invention provides the following means.
A method of manufacturing a wiring board according to the present invention is a method of manufacturing a wiring board including a step of connecting a plurality of conductive patterns provided at intervals, and the method of manufacturing at least one of the plurality of conductive patterns. A conductive pattern forming step for forming the plurality of conductive patterns so that the end portion on the side to be connected has a narrower width than the pattern main body, and the plurality of conductive patterns are electroplated by electroless plating. And a step of connecting them to each other.

  In the method for manufacturing a wiring board according to the present invention, after forming a shape having a narrow portion at an end of at least one of a plurality of conductive patterns to be connected, the conductive patterns are electrically connected by electroless plating. It is supposed to take At this time, since the plated metal grown from the narrow portion of the conductive pattern grows along the shape of the narrow portion, when contacting with the plated metal grown from another conductive pattern, the contact area of these plated metals is conventionally It is smaller than For this reason, it becomes easy to supply a plating solution to the contact part of a plating metal, and it can aim at shortening of the processing time at the time of connecting conductive patterns. In addition, since the contact area of the plated metal grown from each conductive pattern can be reduced, it is possible to suppress the generation of the interface and minute space at the contact portion of the plated metal, and peeling of the plated metal at the conventional interface Can be prevented. Therefore, it is possible to reliably ensure conduction between the conductive patterns and obtain high connection reliability.

In the method for manufacturing a wiring board according to the present invention, it is preferable that the narrow portion has a sharp shape while becoming narrower toward the tip.
In the method for manufacturing a wiring board according to the present invention, since the narrow portion becomes narrower toward the tip and has a sharp shape, the plating metal grown from the narrow portion is plated metal grown from another conductive pattern. When it contacts, it will be in the state close | similar to a point contact, Therefore A contact area can be made the smallest. Therefore, it is possible to further ensure the conduction between the conductive patterns.

  Further, in the method for manufacturing a wiring board according to the present invention, in the conductive pattern forming step, the plurality of conductive layers are formed so that a plurality of the narrow portions are formed at an end portion on a side connected to the at least one conductive pattern. It is preferable to form a pattern.

  In the method for manufacturing a wiring board according to the present invention, after forming a shape having a plurality of narrow portions at the end of at least one of the conductive patterns to be connected, a conductive metal is grown when a plated metal is grown from each conductive pattern. Since a plurality of narrow portions are formed in the pattern, the contact area of the plated metal can be reduced at a plurality of locations. That is, since the plating solution is easily supplied at a plurality of locations, conduction of the plating metal grown from each conductive pattern can be reliably obtained.

  Further, in the method for manufacturing a wiring board according to the present invention, in the conductive pattern forming step, the narrow portion is provided at each end of the pair of opposing conductive patterns that are connected to each other. It is preferable to form the pair of conductive patterns so that the narrow portion and the concave portion between the narrow portions of the other conductive pattern are arranged to face each other.

  In the method for manufacturing a wiring board according to the present invention, after forming the narrow portion of one conductive pattern of the pair of conductive patterns and the concave portion between the narrow portions of the other conductive pattern in a shape to face each other, A plated metal is grown from the conductive pattern. At this time, when the plating metal grown from the narrow portion of one conductive pattern comes into contact with the plating metal grown from the concave portion between the narrow portions of the other conductive pattern, the contact area of these plating metals can be reduced. it can. As the plating metal grows, the contact area gradually increases, so that it is possible to reliably ensure conduction and obtain high connection reliability.

The wiring board of the present invention is manufactured by the above-described manufacturing method of a wiring board.
In the wiring board according to the present invention, since the conductive patterns can be reliably conducted by using the above-described method for manufacturing a wiring board, a highly reliable board can be obtained.

  The method of manufacturing a semiconductor substrate according to the present invention includes a step of electrically connecting a substrate-side conductive pattern on the wiring substrate and an element-side conductive pattern on the semiconductor element, wherein the semiconductor element is mounted on the wiring substrate. A method for manufacturing a semiconductor substrate including a shape having a narrower portion narrower than a pattern main body at an end connected to at least one other conductive pattern of the substrate-side conductive pattern and the element-side conductive pattern A conductive pattern forming step for forming each conductive pattern, an element mounting step for mounting a semiconductor element on the wiring board, and the substrate-side conductive pattern and the element-side conductive pattern by electroless plating. And a step of electrical connection.

  In the method for manufacturing a semiconductor substrate according to the present invention, a semiconductor element is formed on a wiring substrate after forming a shape having a narrow portion at an end of at least one of the substrate-side conductive pattern and the element-side conductive pattern. Is implemented. The substrate-side conductive pattern and the element-side conductive pattern are electrically connected by plating metal. At this time, similarly to the above-described method for manufacturing a wiring board, the contact area of the plated metal grown from each conductive pattern can be reduced, so that the plating metal can be prevented from peeling off. Therefore, since the conduction between the substrate-side conductive pattern and the element-side conductive pattern can be reliably ensured, a semiconductor substrate having high connection reliability can be manufactured.

In the method for manufacturing a semiconductor substrate according to the present invention, it is preferable that the narrow portion has a sharp shape while becoming narrower toward the tip.
In the method for manufacturing a semiconductor substrate according to the present invention, since the plated metals grown from each of them are in a state close to point contact, as in the above-described method for manufacturing a wiring substrate, the conduction between the conductive patterns is further ensured. It becomes possible to do.

  In the method for manufacturing a semiconductor substrate according to the present invention, in the conductive pattern forming step, the plurality of narrow portions are provided at an end portion on a side connected to at least one of the substrate side conductive pattern and the element side conductive pattern. It is preferable to form each of the conductive patterns so as to have a shape.

  In the method for manufacturing a semiconductor substrate according to the present invention, the substrate-side conductive pattern and the element are formed after forming at least one of the substrate-side conductive pattern and the element-side conductive pattern at the end of the connection side. When plating metal is grown from the side conductive pattern, it is easy to supply the plating solution at a plurality of locations, as in the above-described method for manufacturing a wiring board. Therefore, growth is performed from the substrate side conductive pattern and the element side conductive pattern. Conductivity of the plated metal can be obtained with certainty.

  Further, in the method for manufacturing a semiconductor substrate of the present invention, in the conductive pattern formation step, the narrow portion is provided at each end of the pair of the substrate-side conductive pattern and the element-side conductive pattern facing each other. A pair of the substrate-side conductive pattern and the element-side conductive pattern so that the narrow portion of one of the conductive patterns and the concave portion between the narrow portions of the other conductive pattern are opposed to each other. It is preferable to form.

  In the method for manufacturing a semiconductor substrate according to the present invention, one conductive pattern narrow portion of the pair of substrate-side conductive patterns and element-side conductive patterns and the concave portion between the narrow portions of the other conductive pattern are arranged to face each other. After the formation, a plated metal is grown from the pair of substrate side conductive patterns and element side conductive patterns. At this time, as with the above-described method for manufacturing a wiring board, the contact area gradually increases as the growth of the plated metal progresses. Therefore, it is possible to reliably ensure conduction and obtain high connection reliability.

The semiconductor substrate of the present invention is manufactured by the above-described method for manufacturing a semiconductor substrate.
In the semiconductor substrate according to the present invention, the substrate-side conductive pattern and the element-side conductive pattern can be reliably conducted by using the semiconductor substrate manufacturing method. As a result, a highly reliable semiconductor substrate can be manufactured.

  The electro-optical device according to the present invention is a method for manufacturing an electro-optical device in which a switching element for driving a light emitting element is mounted on a wiring board, wherein the semiconductor element is used as the switching element. As a step of mounting on the wiring board, the above-described method for manufacturing a semiconductor substrate is used.

With the method for manufacturing an electro-optical device according to the present invention, an electro-optical device having excellent element characteristics and extremely high reliability can be obtained.
In the invention of the present application, the electro-optical device includes not only an electro-optical effect that changes the light transmittance by changing the refractive index of a substance by an electric field, but also those that convert electric energy into optical energy. Collectively. Specifically, a liquid crystal display device using liquid crystal as an electro-optical material, an organic EL device using organic EL (Electro-Luminescence), an inorganic EL device using inorganic EL, a plasma display device using plasma gas as an electro-optical material, etc. There is. Furthermore, there are an electrophoretic display device (EPD), a field emission display device (FED: Field Emission Display device), and the like.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In each drawing used for the following description, the scale of each member is appropriately changed to make each member a recognizable size.

[First Embodiment]
First, the configuration of the wiring board 1 manufactured by using the wiring board manufacturing method according to the first embodiment of the present invention will be described with reference to FIG.
1 is a plan view showing the configuration of the wiring board 1 (FIG. 1A) and its AA ′ cross-sectional view (FIG. 1B), and FIG. 2 shows the wiring board 1 after the conductive pattern is connected. It is a top view (Drawing 2 (a)) and its BB 'sectional view (Drawing 2 (b)). In the wiring board 1 of the present embodiment, the conductive pattern 11 is formed on the surface 10 a of the glass substrate 10.

(1-1. Formation process of conductive pattern)
First, the process of forming the conductive pattern 11 on the wiring substrate 1 shown in FIG. 1 will be described.
First, the glass substrate 10 is prepared. The glass substrate 10 is preferably a translucent heat-resistant substrate made of quartz glass, soda glass or the like. Then, a metal conductive material such as Al or Cu is formed on the surface 10a of the glass substrate 10 by using a sputtering method or a vacuum evaporation method. In this manner, the glass substrate over which the metal conductive material is formed is processed using photolithography. First, a photoresist (not shown) such as an ultraviolet reactive resist is applied on the metal conductive material film to form a resist layer (not shown). Then, the photoresist layer is exposed using a light source such as ultraviolet light with a photomask having a predetermined shape placed on the resist layer. In this embodiment, a negative photoresist is used.

Then, after the exposure process is completed, development processing is performed. Here, since the negative photoresist has a property of being dissolved in a solvent, the resist layer irradiated with light by a photochemical reaction becomes insoluble in the solvent and remains.
Further, the metal conductive material film on which the mask pattern is formed is etched to form a conductive pattern 11 having a desired shape on the glass substrate 10.

As shown in FIG. 1, the conductive pattern 11 includes a first conductive pattern (conductive pattern) 12 and a second conductive pattern (conductive pattern) 13 which are arranged to face each other. The conductive patterns 12 and 13 have shapes having narrow portions 16 and 17 having a width narrower than the width L of the pattern bodies 14 and 15 at the end portions 12a and 13a on the connecting side. Here, the width is the length in the direction (Y direction shown in FIG. 1) perpendicular to the direction (X direction shown in FIG. 1) connecting the first conductive pattern 12 and the second conductive pattern 13. Is shown.
The narrow portions 16 and 17 are directed in the direction of opposing conductive patterns (the first conductive pattern 12 is the direction of the second conductive pattern 13 and the second conductive pattern 13 is the direction of the second conductive pattern 12). As the width gradually decreases, the tip has a sharp shape.

(1-2. Conductive pattern connection step)
After the conductive pattern 11 is formed, the conductive patterns 12 and 13 are electrically connected. Here, the connection is made using an electroless plating method. First, in order to improve the wettability of the surfaces of the conductive patterns 12 and 13 and remove the residue, the conductive patterns 12 and 13 are immersed in a processing solution. In this embodiment, impregnation is performed for 1 minute to 5 minutes in an aqueous solution containing 0.01% to 0.1% hydrofluoric acid and 0.01% to 0.1% sulfuric acid. Alternatively, the substrate may be immersed in an alkali-based aqueous solution such as 0.1% to 10% sodium hydroxide for 1 minute to 10 minutes.

Next, an alkaline aqueous solution having a pH of 9 to 13 based on sodium hydroxide is immersed in 20 ° C. to 60 ° C. for 1 second to 5 minutes to remove the oxide film on the surface. Alternatively, an acidic aqueous solution having a pH of 1 to 3 based on 5% to 30% nitric acid may be immersed for 1 second to 5 minutes while being heated to 20 ° C to 60 ° C.
Further, it is immersed in a zincate solution having a pH of 11 to 13 containing ZnO for 1 second to 2 minutes to replace the terminal surface with Zn. Then, it is immersed in a 5% to 30% nitric acid aqueous solution for 1 second to 60 seconds to strip Zn. Then, it is again immersed in the zincate bath for 1 second to 2 minutes to precipitate dense Zn particles on the Al surface. Thereafter, it is immersed in an electroless Ni plating bath to form Ni plating.
The plating height is about 2 μm to 10 μm. The plating bath is a bath using hypophosphorous acid as a reducing agent, and has a pH of 4 to 5 and a bath temperature of 80 ° C to 95 ° C.

  In such a process, since a hypophosphorous acid bath is performed, phosphorus (P) co-deposits. Since the plating metal isotropically grows from both the first conductive pattern 12 and the second conductive pattern 13, the shapes of the narrow portions 16 and 17 of both the first and second conductive patterns 12 and 13 are formed. The plating metal that has grown along the surface of the glass substrate 10 comes into contact by growing up to an intermediate point between the first conductive pattern 12 and the second conductive pattern 13 on the surface 10 a of the glass substrate 10. Then, as shown in FIG. 2, the plating solution is further supplied to the contact portions 18 of the plating metals 19 and 20 grown from the first and second conductive patterns 12 and 13, and the contact area increases.

When the first and second conductive patterns 12 and 13 are connected to each other, they are finally immersed in a replacement Au plating bath to change the Ni surface to Au. Au is formed to have a thickness of about 0.05 μm to 0.3 μm. As the Au bath, a cyan-free type is used, and immersion is performed at a pH of 6 to 8 and a bath temperature of 50 to 80 ° C. for 1 to 30 minutes. In this manner, Ni—Au plating bumps are formed on both the first and second conductive patterns 12 and 13.
As described above, both the first and second conductive patterns 12 and 13 are electrically connected to each other by the bumps grown by electroless plating.

  Thus, in this embodiment, since it has the shape which has the narrow parts 16 and 17 in the edge parts 12a and 13a of the 1st, 2nd conductive patterns 12, 13, it grows from the 1st conductive pattern 12. When the plated metal 19 and the plated metal 20 grown from the second conductive pattern 13 come into contact, the contact area of the plated metals 19 and 20 grows from the conventional conductive patterns 21 and 22 as shown in FIG. The contact area of the plated metals 23 and 24 is smaller. Therefore, the generation of the interface and the minute space at the contact portion 18 of the plated metals 19 and 20 can be suppressed, and peeling of the plated metals 19 and 20 can be prevented. That is, it becomes possible to obtain the wiring board 1 that ensures the conduction between the conductive patterns 12 and 13 and obtains high connection reliability.

[Second Embodiment]
Next, a second embodiment according to the present invention will be described with reference to FIGS. In each embodiment described below, portions having the same configuration as those of the wiring substrate 1 according to the first embodiment described above are denoted by the same reference numerals and description thereof is omitted.
The wiring board 30 according to this embodiment differs from the first embodiment in the shape of the conductive pattern 31.

FIG. 4 is a plan view showing the configuration of the wiring board 30 (FIG. 4A) and its AA ′ sectional view (FIG. 4B), and FIG. 5 shows the wiring board 30 after the conductive pattern is connected. It is a top view (Drawing 5 (a)) and its BB 'sectional view (Drawing 5 (b)). The wiring board 30 of the present embodiment has a conductive pattern 31 formed on the surface 30b of a glass substrate 30a.
As shown in FIG. 4, the conductive pattern 31 includes a first conductive pattern (conductive pattern) 32 and a second conductive pattern (conductive pattern) 33 that are arranged to face each other. The conductive patterns 32 and 33 have a shape having a plurality (three in this embodiment) of narrow portions 36 and 37 having a width narrower than the width M of the pattern bodies 34 and 35 at the connecting end portions 32a and 33a. ing.
As in the first embodiment, the plurality of narrow portions 36 and 37 are gradually narrower in the direction of the opposing second and first conductive patterns 33 and 32.

First, similarly to the first embodiment, after forming the conductive pattern 31 using photolithography, the conductive patterns 32 and 33 are electrically connected. As in the first embodiment, when immersed in an electroless plating Ni plating bath, the plating metal grows isotropically from both the first conductive pattern 32 and the second conductive pattern 33. A plurality of plating metals grown along the shapes of the plurality of narrow portions 36 and 37 of the first and second conductive patterns 32 and 33 are provided on the first conductive pattern 32 on the surface 30b of the glass substrate 30a. By growing up to an intermediate point between the narrow portion 36 and the plurality of narrow portions 37 provided in the second conductive pattern 33, contact is made at a plurality of locations. Then, as shown in FIG. 5, the plating solution is further supplied to the contact portions 40 of the plated metals 38 and 39 grown from the first and second conductive patterns 32 and 33, and the contact area increases.
In this way, Ni—Au plating bumps were formed on both the first and second conductive patterns 32 and 33, and both the first and second conductive patterns 32 and 33 were grown by electroless plating. They are electrically connected to each other by bumps.

  Thus, in this embodiment, since it has the shape which has two or more narrow parts 36 and 37 in the edge parts 32a and 33a of the 1st, 2nd conductive patterns 32 and 33, it contacts a plating metal in several places. The area can be reduced. That is, since the plating solution is easily supplied at a plurality of locations, the conduction of the plating metal grown from each of the first and second conductive patterns 32 and 33 can be reliably obtained.

[Third Embodiment]
Next, a third embodiment according to the present invention will be described with reference to FIGS.
The wiring board 40 according to the present embodiment differs from the first embodiment in the shape of the conductive pattern 41.

6 is a plan view showing the configuration of the wiring board 40 (FIG. 6A) and its AA ′ sectional view (FIG. 6B), and FIG. 7 shows the wiring board 40 after the conductive pattern is connected. It is a top view (Drawing 7 (a)) and its BB 'sectional view (Drawing 7 (b)). The wiring board 40 of the present embodiment has a conductive pattern 41 formed on a surface 40b of a glass substrate 40a.
As shown in FIG. 6, the conductive pattern 41 includes a pair of first conductive patterns 42 (one conductive pattern) and a second conductive pattern (the other conductive pattern) 43 arranged to face each other. ing. These conductive patterns 42 and 43 have a shape having a plurality of narrow portions 46 and 47 having a width narrower than the width N of the pattern bodies 44 and 45 at the end portions 42a and 43a on the connecting side.
The plurality of narrow portions 46 and 47 are gradually narrower in the direction of the opposing second and first conductive patterns 43 and 42 as in the first embodiment.
In addition, the conductive pattern 41 is formed in a shape in which the narrow portion 46 of the first conductive pattern 42 and the concave portion 47 a between the narrow portions 47 of the second conductive pattern 43 are opposed to each other.

First, similarly to the first embodiment, after forming the conductive pattern 41 using photolithography, the conductive patterns 42 and 43 are electrically connected. As in the first embodiment, when immersed in an electroless plating Ni plating bath, the plated metal grows isotropically from both the first conductive pattern 42 and the second conductive pattern 43. Plating metals 48 and 49 grown along the shapes of the plurality of narrow portions 46 and 47 of the first and second conductive patterns 42 and 43 are provided on the first conductive pattern 42 on the surface 40b of the glass substrate 40a. Further, the contact is made by growing up to an intermediate point between the plurality of narrow portions 46 and the recesses 47 a between the plurality of narrow portions 47 provided in the first conductive pattern 43. When the plated metals 48 and 49 are further grown, the plated metals 48 and 49 are supplied to all of the first conductive pattern 42 and the second conductive pattern 43 as shown in FIG.
In this way, Ni—Au plating bumps were formed on both the first and second conductive patterns 42 and 43, and both the first and second conductive patterns 42 and 43 were grown by electroless plating. They are electrically connected to each other by bumps.

Thus, in this embodiment, since the narrow part 46 of the 1st conductive pattern 42 and the recessed part 47a between the narrow parts 47 of the 2nd conductive pattern 43 are formed in the shape which opposes, When the plating metal 48 grown from the narrow portion 46 of the first conductive pattern 42 comes into contact with the plating metal 49 grown from the recess 47 a between the narrow portions 47 of the second conductive pattern 43, the contact of these plating metals The area can be reduced. As the plating metal grows, the contact area gradually increases, so that it is possible to reliably ensure conduction and obtain high connection reliability.
In the present embodiment, a plurality of narrow portions 46 and 47 are provided in the first and second conductive patterns 42 and 43. However, as shown in FIG. The same effect can be obtained even if the narrow portion 52 is provided and the other electrode pattern 53 is provided with the concave portion 54 corresponding to the narrow portion 52.

[Fourth Embodiment]
Next, a fourth embodiment according to the present invention will be described with reference to FIGS.
First, the configuration of an electro-optical device manufactured by using the method for manufacturing a semiconductor substrate according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a cross-sectional view illustrating a schematic configuration of the electro-optical device. The electro-optical device 55 includes at least a substrate bonded body 56, and the substrate bonded body 56 is bonded to a semiconductor substrate 60 and an organic EL substrate 57. It has a combined configuration.

10 is a plan view showing the configuration of the semiconductor substrate 60 (FIG. 10A) and its AA ′ sectional view (FIG. 10B), and FIG. 11 shows the semiconductor substrate 60 after the conductive pattern is connected. It is a top view.
As shown in FIGS. 9 and 10, the semiconductor substrate 60 is a TFT that drives a wiring substrate 61, a conductive pattern (substrate-side conductive pattern) 62 formed on the wiring substrate 61, an organic EL element 58, and the like. (Semiconductor element) 63 and a conductive pattern (element-side conductive pattern) 64 having a predetermined shape formed on the TFT 63. The conductive pattern 62 is formed according to the conductive pattern 64 formed on the TFT 63.

  First, in the manufacturing process of the semiconductor substrate 61, a method of transferring a plurality of TFTs, which are semiconductor elements, to the wiring board 10 is adopted as a method of forming the semiconductor elements. That is, a semiconductor substrate 61 is obtained by bonding a substrate having a TFT 63 (hereinafter referred to as “element substrate”) to a wiring substrate 61 having a conductive pattern 62 and transferring the TFT 63 to the wiring substrate 61 side. .

First, a process of forming the conductive pattern 62 on the wiring substrate 61 shown in FIG. 10 will be described.
First, after preparing a glass substrate 65 and forming a metal conductive material in the same manner as in the first embodiment, using photolithography, the first and second layers shown in FIG. 1 are used as shown in FIG. A conductive pattern 62 having the same shape as the conductive patterns 12 and 13 is formed. The conductive pattern 62 is disposed so as to face each other with the bonding region 63a of the TFT 63 interposed therebetween. Further, the conductive pattern 62 has a narrow width portion 66 provided at the end portion 62 a on the connection side gradually narrowing toward the TFT 63.

Next, the manufacturing process of the element substrate will be described.
First, a glass substrate (not shown) is prepared. As the glass substrate, a translucent heat-resistant substrate made of quartz glass, soda glass or the like is preferable. Then, a TFT 63 is formed on the surface of the glass substrate. Since a known technique including a high temperature process is adopted for the manufacturing method of the TFT 63, description thereof is omitted. Here, the TFT 63 is formed by a known high-temperature process technique so that the conductive pattern 64 of the TFT 63 is positioned immediately above the glass substrate, that is, the conductive pattern 64 of the TFT 63 faces the surface of the glass substrate. It is said. Further, as shown in FIG. 10, the conductive pattern 64 is formed with the same shape as the first and second conductive patterns 12 and 13 shown in FIG. The conductive pattern 64 is provided at a position facing the conductive pattern 62 formed on the wiring substrate 61, and the narrow portion 67 provided at the end portion 64 a on the side to which the conductive pattern 64 is connected is the end of the TFT 63. The width gradually decreases toward the portion, that is, the conductive pattern 62.

  A release layer (not shown) is formed on the surface of the glass substrate on which the TFT 13 is formed. The peeling layer is made of a material that causes peeling (also referred to as “in-layer peeling” or “interfacial peeling”) in the layer or at the interface when irradiated with a laser beam or the like. That is, by irradiating with a certain intensity of light, the bonding force between atoms or molecules in the atoms or molecules constituting the constituent material disappears or decreases, causing ablation or the like and causing separation. is there. In addition, when the component contained in the release layer is released as a gas due to irradiation with irradiation light, the separation layer absorbs light to become a gas, and the vapor is released to cause separation. There are cases.

An adhesive 59 is applied to the bonding region 63a of the wiring substrate 61 manufactured by the method described above, and an element substrate (not shown) is bonded.
Thereafter, laser light is irradiated from the back surface side of the glass substrate 65 (the surface of the element substrate on which the TFT 63 is not formed). Then, the bonds of atoms and molecules in the peeling layer are weakened, and the hydrogen in the peeling layer is molecularized and separated from the crystal bonds, that is, the bonding force between the TFT 63 and the glass substrate is completely lost, and the laser beam is irradiated. It becomes possible to easily remove the bond (adhesion) between the glass substrate and the TFT 63 in the formed portion.
By peeling the glass substrate from the TFT 63 by the laser beam irradiation as described above, the surface of the conductive pattern 62 of the wiring substrate 61 and the surface of the conductive pattern 64 of the TFT 63 are separated as shown in FIG. These are arranged so as to be directed in the same direction (upward direction).

As described above, after mounting the TFT 63 on the wiring substrate 61, the conductive pattern 62 formed on the wiring substrate 61 and the conductive pattern 64 formed on the TFT 63 are electrically connected. In this case as well, when immersed in an electroless plating Ni plating bath in the same manner as in the first embodiment, the plating metal grows isotropically from both the conductive pattern 62 and the conductive pattern 64. The plated metals 68 and 69 grown along the shape of the 64 narrow portions 66 and 67 are joined to each other by growing to a position that is approximately half the height of the side surface 63 b of the TFT 63. Then, as shown in FIG. 11, the plating solution is further supplied to the contact portions 70 of the plating metals 68 and 69 grown from the conductive patterns 62 and 64, and the contact area increases.
In this way, Ni—Au plating bumps are formed on both the conductive patterns 62 and 64, and both the conductive patterns 62 and 64 are electrically connected to each other by bumps grown by electroless plating.

  Thus, in the present embodiment, the contact areas of the plated metals 68 and 69 can be reduced by forming the narrow portions 66 and 67 at the ends 62a and 64a of the conductive patterns 62 and 64, respectively. For this reason, the plating solution is easily supplied to the contact portions of the plating metals 68 and 69, and the processing time for connecting the conductive pattern 62 on the wiring board 61 side and the conductive pattern 64 on the TFT 63 side is shortened. Can do. In addition, since the conduction between the conductive pattern 62 on the wiring board 61 side and the conductive pattern 64 on the TFT 63 side can be reliably ensured, the semiconductor substrate 60 having high connection reliability can be manufactured.

  In the present embodiment, one narrow portion is provided at the ends of the conductive pattern 62 on the wiring substrate 61 side and the conductive pattern 64 on the TFT 63 side. However, as shown in the second embodiment, a plurality of shapes are provided. Furthermore, as shown in the third embodiment, the narrow portion of one conductive pattern of the conductive pattern 62 on the wiring board 61 side and the conductive pattern 64 on the TFT 63 side and the other conductive pattern The shape which arrange | positions the recessed part between narrow parts may be sufficient.

Next, as an electronic apparatus using the electro-optical device, for example, an electronic apparatus including an organic EL device will be described with reference to FIG. FIG. 12 is a perspective view of the mobile phone 1000. The organic EL device has a configuration in which an organic EL element is provided on a semiconductor substrate, and the semiconductor substrate of the present invention is used as the semiconductor substrate.
The semiconductor substrate of this embodiment is not limited to the mobile phone, but is an electronic book, personal computer, digital still camera, liquid crystal television, viewfinder type or monitor direct view type video tape recorder, car navigation device, pager, electronic notebook, calculator. It can be applied to various electronic devices such as a word processor, a workstation, a videophone, a POS terminal, and a device having a touch panel. In any electronic device, a high-performance electronic device can be manufactured by applying the semiconductor substrate of the present invention.

The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.
For example, in each of the above-described embodiments, the conductive pattern is not limited to a shape with a sharp tip, and may be narrower than the pattern body. For example, as shown in FIG. The shape in which the narrower protrusion part 77 was formed may be sufficient. Moreover, in all the conductive patterns, although it was made the shape which provided the narrow part, if the narrow part is formed in the edge part by the side of the connection of the at least 1 conductive pattern of the several conductive patterns to connect. good.
Further, as a material constituting the conductive patterns 12, 13, 32, 33, 42, 43, 62, 64, for example, a metal nitride film such as TiN may be used in addition to a metal conductive material such as Al or Cu.

  Further, in the first to third embodiments, the conductive patterns 12, 13, 32, 33, 42, and 43 are formed on the same plane of the wiring board 10. However, as shown in FIG. A wiring substrate 80 in which conductive patterns 82 and 83 are provided on the substrate 81 may be used. Also in this configuration, the contact area of the plated metal grown from the respective conductive patterns 81 and 82 can be reduced.

The top view (a) and sectional drawing (b) which show the wiring board which concerns on 1st Embodiment of this invention. The top view (a) and sectional drawing (b) which show after the conductive pattern connection of the wiring board which concerns on 1st Embodiment of this invention. The top view which shows the conventional conductive pattern. The top view (a) and sectional drawing (b) which show the wiring board which concerns on 2nd Embodiment of this invention. The top view (a) and sectional drawing (b) which show after the conductive pattern connection of the wiring board which concerns on 2nd Embodiment of this invention. The top view (a) and sectional drawing (b) which show the wiring board which concerns on 3rd Embodiment of this invention. The top view (a) and sectional drawing (b) which show after the conductive pattern connection of the wiring board which concerns on 3rd Embodiment of this invention. The top view which shows the modification of the wiring board which concerns on 3rd Embodiment of this invention. Sectional drawing which shows schematic structure of the semiconductor substrate and electro-optical apparatus which concern on 4th Embodiment of this invention. The top view (a) and sectional drawing (b) which show the semiconductor substrate which concerns on 4th Embodiment of this invention. Sectional drawing which shows after the conductive pattern connection of the wiring board which concerns on 4th Embodiment of this invention. FIG. 11 is a perspective view illustrating an embodiment of an electronic apparatus according to the invention. The top view which shows the modification of the conductive pattern which concerns on the said embodiment. Sectional drawing which shows the modification of the wiring board which concerns on the said embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10,61,80 ... Wiring board, 12 ... 1st conductive pattern (conductive pattern), 13 ... 2nd conductive pattern (conductive pattern), 14, 15, 34, 35, 44, 45 ... pattern main body, 16, 17, 36, 37, 46, 47, 52, 66, 67 ... narrow portion, 32 ... first conductive pattern (conductive pattern), 33 ... second conductive pattern (conductive pattern), 42 ... first conductive Pattern (one conductive pattern), 43 ... second conductive pattern (the other conductive pattern), 62 ... conductive pattern (substrate side conductive pattern), 63 ... TFT (semiconductor element), 64 ... conductive pattern (element side conductive pattern) )

Claims (11)

A method of manufacturing a wiring board including a step of connecting a plurality of conductive patterns provided at intervals,
Conductive pattern formation for forming the plurality of conductive patterns so as to have a shape having a narrower portion narrower than the pattern body at an end portion on the side to which at least one of the plurality of conductive patterns is connected. Process,
And a step of electrically connecting the plurality of conductive patterns by electroless plating.   The method for manufacturing a wiring board according to claim 1, wherein the narrow portion is tapered toward the tip and has a sharp shape.   The plurality of conductive patterns are formed in the conductive pattern forming step so as to have a shape having a plurality of the narrow portions at an end portion on a side connected to the at least one conductive pattern. Or the manufacturing method of the wiring board of Claim 2.   In the conductive pattern forming step, the narrow portion is provided at each end of the pair of conductive patterns facing each other, the narrow portion of one of the conductive patterns and the width of the other conductive pattern. The method for manufacturing a wiring board according to any one of claims 1 to 3, wherein the pair of conductive patterns are formed so as to have a shape in which the concave portions between the narrow portions are arranged to face each other.   A wiring board manufactured by the method for manufacturing a wiring board according to any one of claims 1 to 4. A method for manufacturing a semiconductor substrate comprising a step of electrically connecting a substrate-side conductive pattern on the wiring substrate and an element-side conductive pattern on the semiconductor element, wherein a semiconductor element is mounted on the wiring substrate,
Each conductive pattern is formed so as to have a shape having a narrower portion narrower than the pattern main body at the end connected to at least one other conductive pattern of the substrate side conductive pattern and the element side conductive pattern. A conductive pattern forming step to be formed;
An element mounting step of mounting a semiconductor element on the wiring board;
And a step of electrically connecting the substrate-side conductive pattern and the element-side conductive pattern by electroless plating.   The method for manufacturing a semiconductor substrate according to claim 6, wherein the narrow portion is tapered toward the tip and has a sharp shape.   In the conductive pattern forming step, each conductive pattern is formed so as to have a shape having a plurality of the narrow portions at an end portion on a side connected to at least one of the substrate side conductive pattern and the element side conductive pattern. 8. The method of manufacturing a semiconductor substrate according to claim 6, wherein the semiconductor substrate is formed.   In the conductive pattern forming step, the narrow portion is provided at each end of the pair of the substrate side conductive pattern and the element side conductive pattern facing each other, and the narrow portion of one of the conductive patterns The pair of the substrate-side conductive pattern and the element-side conductive pattern are formed so that the concave portions between the narrow portions of the other conductive pattern are arranged to face each other. Item 9. The method for manufacturing a semiconductor substrate according to any one of Items 8 to 9.   A semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 6.   An electro-optical device manufacturing method in which a switching element for driving a light emitting element is mounted on a wiring board, wherein the semiconductor element is used as the switching element, and the semiconductor element is mounted on the wiring board. An electro-optical device manufacturing method using the method for manufacturing a semiconductor substrate according to any one of claims 6 to 9.

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