JP2006166391A - Switching amplifier and switching amplifier driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce unnecessary heat generation and power consumption in a high sound-quality switching amplifier. <P>SOLUTION: An amplifier output means is connected to both output ends of a first push-pull circuit in which a transistor having a first on-resistance is push-pull connected; and a second push-pull circuit in which a transistor having a second on-resistance lower than the first on-resistance is push-pull connected, and comprises a low pass filter LPF for smoothing the outputs from the first and second push-pull circuits. A driving voltage according to an input signal S1 from the outside is supplied to the amplifier output means, and the first or second push-pull circuit is selectively switched depending on the determination result on whether the input signal S1 is a no-signal or a small signal. When the input signal S1 is a no-signal or a small signal, a first push-pull circuit having a small input capacity is used to prevent the increase of unnecessary heat generation and power consumption. When the input signal S1 is other than that, a second push-pull circuit having a small on-resistance is used to achieve the high sound quality. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a switching amplifier and a driving method of the switching amplifier, and is suitable for application to, for example, a PWM (Pulse Wide Modulation) amplifier.

  Conventionally, in a PWM amplifier, a MOS (Metal Oxide Semiconductor) -FET (Field Effect Transistor) is used as a switching element in an amplifier output stage. There is a demand for minimizing the on-resistance (resistance when the switching element is turned on) in an FET).

On the other hand, some class D amplifiers are configured to improve power supply efficiency by configuring a switching circuit with CMOS transistors whose on-resistance is low (see, for example, Patent Document 1).
JP 2004-146981 A

  By the way, in the PWM amplifier having such a configuration, by arranging a plurality of FETs used as switching elements in parallel or by increasing the chip size, the so-called on-resistance can be reduced. The input capacitance of the gate of the FET becomes larger by the amount of current flowing.

  In practice, in the PWM amplifier, the duty ratio of the PWM pulse when there is no signal is 50%, whereas the duty ratio of the PWM pulse changes when there is a signal, but the switching operation is not when there is no signal. Even so, the FET is turned on and off at a duty ratio of 50%, and a slight amount of power is consumed.

  Since this power consumption increases in proportion to the input capacitance, increasing the chip size to reduce the on-resistance in a PWM amplifier leads to an increase in the current of the pre-driver stage that operates the FET by the increase in the input capacitance. As a result, the power consumption is increased, and the amount of heat generated by the switching operation of the FET is increased.

  The present invention has been made in view of the above points, and intends to propose a high-quality switching amplifier and a switching amplifier driving method capable of reducing wasteful heat generation and power consumption.

  In order to solve such a problem, in the present invention, a first output stage configured by push-pull connection of transistors having a first on-resistance, and a second on-resistance lower than the first on-resistance are provided. A second output stage configured by push-pull connection of transistors, and connected to both output terminals of the first output stage and the second output stage, and the first output stage and the second output stage Smoothing means for smoothing the output from the output stage, drive voltage supply means for supplying a drive voltage corresponding to the input signal to the first output stage and the second output stage, and no input signal or a predetermined input signal By providing a determination unit that determines whether or not the signal is a small signal of a level or less, and a control unit that selectively switches the first output stage or the second output stage according to the determination result by the determination unit, Enter When the signal is no signal or small signal, the first output stage with high on-resistance but low input capacity is used to prevent wasteful heat generation and increase in power consumption, and to improve efficiency, and the input signal is other than that In this case, the sound quality of the switching amplifier can be improved by using the second output stage having a large input capacitance but a smaller on-resistance than the first output means.

  Further, in the present invention, the first output stage configured by push-pull connection of the transistors having the first on-resistance and the transistor having the second on-resistance lower than the first on-resistance are pushed-pull. A plurality of output stage groups connected in parallel to each other, and a smoothing means connected to each output stage in the output stage group for smoothing the output from each output stage; Drive voltage supply means for supplying a drive voltage corresponding to the input signal to each output stage in the output stage group, determination means for determining the state of the input signal, and each output in the output stage group according to the determination result by the determination means By providing selector means for selectively switching the stages, it is possible to use each output stage in the output stage group in a state optimized by any combination according to the state of the input signal. Kill Therefore, while achieving high efficiency and prevent an increase in wasteful heat generation and power consumption, it is possible to achieve high sound quality of the switching amplifier.

  According to the present invention, the first output stage configured by push-pull connection of a transistor having a first on-resistance and the transistor having a second on-resistance lower than the first on-resistance are connected by push-pull connection. Amplifier output means connected to both output terminals of the second output stage constituted by the first output stage and smoothing means for smoothing the output from the second output stage. On the other hand, a drive voltage supply step for supplying a drive voltage according to an external input signal, a determination step for determining whether the input signal is a no signal or the input signal is a small signal below a predetermined level, A control step of selectively switching the first output stage or the second output stage according to the determination result of the determination step, or when the input signal is no signal or The first output stage with high on-resistance but low input capacity is used for signals to prevent wasteful heat generation and increase in power consumption, thereby achieving high efficiency and large input capacity for other input signals However, it is possible to achieve a higher sound quality of the amplifier output means by using the second output stage having a smaller on-resistance than the first output means.

  According to the present invention, when the input signal is no signal or a small signal, the first output stage having a large on-resistance but a small input capacitance is used to prevent unnecessary heat generation and increase in power consumption, thereby improving efficiency. Switching amplifier capable of achieving high sound quality by using the second output stage whose input capacitance is large but the on-resistance is smaller than that of the first output means when the input signal is other than that, and driving of the switching amplifier A method can be realized.

  Further, according to the present invention, each output stage in the output stage group can be used in an optimized state by an arbitrary combination according to the state of the input signal, so that it is possible to prevent unnecessary heat generation and increase in power consumption. It is possible to realize a switching amplifier that can achieve higher sound quality of the switching amplifier while improving efficiency.

  Hereinafter, an embodiment of the invention will be described in detail with reference to the drawings.

(1) First Embodiment In FIG. 1, reference numeral 1 generally indicates the configuration of a PWM amplifier according to the first embodiment. In the PWM amplifier 1, an input signal S <b> 1 supplied from an input terminal 2 is used as a PWM processor 3. To enter.

  The PWM processor 3 performs pulse width modulation on the input signal S1 to convert it into a PWM pulse having a duty ratio corresponding to the input signal S1, and predrivers the positive drive voltage signal and the negative drive voltage signal in the PWM pulse. 4 is supplied.

  The pre-driver 4 turns on the FET Q1 by applying a drive voltage corresponding to the positive drive voltage signal to the gate of the FET Q1 via the switch circuit SW1, and switches the drive voltage corresponding to the negative drive voltage signal. The FET Q3 is turned on by being applied to the gate of the FET Q3 via the circuit SW2.

  The FETs Q1 and Q3 are mainly used as switching elements. When the FET Q1 is turned on, the FET Q3 is turned off. When the FET Q3 is turned on, the FET Q1 is turned off. It is made to constitute.

  Bias resistors R1 and R3 are connected to the gates of the FETs Q1 and Q3, respectively, so that when the switching terminals SW1A and SW2A of the switch circuits SW1 and SW2 are connected to the terminals T1 and T3, a driving voltage having a predetermined potential is generated. When the switching terminals SW1A and SW2A of the switch circuits SW1 and SW2 are connected to the terminals T2 and T4, the gate carriers of the FETs Q1 and Q3 are quickly pulled out and the FETs Q1 and Q3 continue to operate. To prevent that.

  The FETQ1 and Q3 are connected to the source of the FETQ1 and the source of the FETQ3, the midpoint of the connection is connected to the speaker output via a low-pass filter LPF composed of the coil L1 and the capacitor C1, and the drain of the FETQ1 is positive. The drain of the FET Q3 is connected to the negative power source Vss.

  By the way, the terminals T2 and T4 are connected to the gate of the FET Q2 and the gate of the FET Q4, and the bias resistors R2 and R4 are connected to the gate of the FET Q2 and the gate of the FET Q4, respectively, similarly to the FETs Q1 and Q3.

  The FETs Q2 and Q4 are connected to the source of the FET Q2 and the source of the FET Q4, and the midpoint of the connection is connected to the speaker output via a low-pass filter LPF including a coil L1 and a capacitor C1.

  In this case, the drain of the FET Q2 is also connected to the plus power source Vcc as in the FET Q1, and the drain of the FET Q4 is connected to the minus power source Vss as in the FET Q3.

  The FETs Q2 and Q4 are also used as switching elements. When the FET Q2 is turned on, the FET Q4 is turned off. Conversely, when the FET Q4 is turned on, the FET Q2 is turned off, thereby forming a second push-pull circuit. It is made to do.

  In this PWM amplifier 1, the output of the first push-pull circuit composed of FETs Q1 and Q3 and the output amplified by the second push-pull circuit composed of FETs Q2 and Q4 are smoothed by a low-pass filter LPF, and then output as a speaker output. It is supplied to a speaker (not shown).

  That is, in the PWM amplifier 1, an amplifier output stage is configured by the first push-pull circuit composed of the FETs Q1 and Q3, the second push-pull circuit composed of the FETs Q2 and Q4, and the low-pass filter LPF.

  Here, FETs Q1 and Q3 are composed of a chip having a larger on-resistance and a smaller gate input capacitance than FETs Q2 and Q4, whereas FETs Q2 and Q4 have a smaller on-resistance than FETs Q1 and Q3 and a gate input capacitance. Is made up of big chips.

  Therefore, the microcomputer 5 monitors the input signal S1 input from the input terminal 2, and corresponds to the case where there is no signal input or the input signal S1 is a weak small signal of 2 to 3 [W], for example. When the input signal S1 is recognized as a no signal or a small signal, the switching terminals SW1A and SW2A of the switch circuits SW1 and SW2 are connected to the terminals T1 and T3 in consideration of the efficiency. Only the first push-pull circuit having a small gate input capacitance is operated by driving the FET Q1 or Q3.

  When the microcomputer 5 recognizes that the input signal S1 is a large signal of, for example, about 50 to 100 [W] as a result of monitoring the input signal S1, the switching of the switch circuits SW1 and SW2 is considered in consideration of sound quality. By connecting the terminals SW1A and SW2A to the terminals T2 and T4, the operation of the first push-pull circuit composed of the FETs Q1 and Q3 is stopped, and then the FET Q2 or Q4 is driven to operate only the second push-pull circuit. It is made to let you.

  In the above configuration, the PWM amplifier 1 has FETs Q1 and Q3 having a large on-resistance but a small gate input capacitance, and FETs Q2 and Q4 having a large gate input capacitance but a small on-resistance as switching elements, and the input signal S1 is not present. When it is a signal or a small signal, the switching terminals SW1A and SW2A of the switch circuits SW1 and SW2 are connected to the terminals T1 and T3, and the FET Q1 or Q3 having a small input capacitance is driven to operate only the first push-pull circuit. By doing so, unnecessary and wasteful drive current can be reduced, power consumption can be increased, wasteful heat generation can be prevented, and high efficiency can be achieved.

  Further, in the PWM amplifier 1, when the input signal S1 is a large signal, the switching terminals SW1A and SW2A of the switch circuits SW1 and SW2 are switched to the terminals T2 and T4 to drive the FET Q2 or Q4 having a smaller on-resistance than the FETs Q1 and Q3. Thus, by turning on only the second push-pull circuit, the gates of the FETs Q2 and Q4 can be charged / discharged in a short time, and thus high sound quality can be achieved by reducing the on-resistance.

  According to the above configuration, the PWM amplifier 1 switches between the first push-pull circuit composed of the FETs Q1 and Q3 and the second push-pull circuit composed of the FETs Q2 and Q4 according to the monitoring result of the input signal S1. By doing so, it is possible to prevent wasteful heat generation and increase in power consumption, and realize high sound quality.

(2) Second Embodiment In FIG. 2, in which parts corresponding to those in FIG. 1 are assigned the same reference numerals, 11 indicates the overall configuration of the PWM amplifier in the second embodiment. Similarly to the first embodiment, the input signal S1 supplied from the input terminal 2 is input to the PWM processor 3.

  The PWM processor 3 performs pulse width modulation on the input signal S1 to convert it into a PWM pulse having a duty ratio corresponding to the input signal S1, and predrivers the positive drive voltage signal and the negative drive voltage signal in the PWM pulse. 4 is supplied.

  The pre-driver 4 turns on the FET Q1 by directly applying a drive voltage corresponding to the positive drive voltage signal to the gate of the FET Q1, and directly applies a drive voltage corresponding to the negative drive voltage signal to the gate of the FET Q3. By doing so, the FET Q3 is turned on.

  That is, the pre-driver 4 is configured to always apply a drive voltage to the FETs Q1 and Q3, and thereby operate the first push-pull circuit composed of the FETs Q1 and Q3 at all times.

  Incidentally, in the PWM amplifier 11 in the second embodiment, unlike the first embodiment, the output of the pre-driver 4 and the gates of the FETs Q1 and Q3 are directly connected, and a bias is applied to the gates of the FETs Q1 and Q3. Resistor is not connected.

  FETs Q1 and Q3 are connected to the source of FET Q1 and the source of FET Q3 as in the first embodiment, and the midpoint of the connection is connected to the speaker output via a low-pass filter LPF comprising a coil L1 and a capacitor C1. At the same time, the drain of the FET Q1 is connected to the positive power source Vcc, and the drain of the FET Q3 is connected to the negative power source Vss.

  By the way, the output of the pre-driver 4 is also supplied to the terminals T5 and T6. When the switching terminals SW3A and SW4A of the switch circuits SW3 and SW4 are connected to the terminals T5 and T6, they are connected to the gates of the FETs Q2 and Q4. In contrast, a driving voltage is applied.

  In the FET Q2 and FET Q4, bias resistors R2 and R4 are connected to the gate of the FET Q2 and the gate of the FET Q4, as in the first embodiment.

  The FET Q2 and FET Q4 are connected to the source of the FET Q2 and the source of the FET Q4, and the midpoint of the connection is connected to the speaker output via a low-pass filter LPF composed of a coil L1 and a capacitor C1.

  In this case, the drain of the FET Q2 is also connected to the positive power source Vcc as in the FET Q1, and the drain of the FET Q4 is connected to the negative power source Vss as in the FET Q3.

  The FETs Q2 and Q4 are used as switching elements similarly to the FETs Q1 and Q3. When the FET Q2 is turned on, the FET Q4 is turned off. When the FET Q4 is turned on, the FET Q2 is turned off. The push-pull circuit is configured.

  In this PWM amplifier 11, the outputs of the first push-pull circuit composed of FETs Q1 and Q3 and the second push-pull circuit composed of FETs Q2 and Q4 are smoothed by a low-pass filter LPF, and then a speaker (not shown) is output as a speaker. )).

  That is, also in the PWM amplifier 11, an amplifier output stage is configured by the first push-pull circuit composed of FETs Q1 and Q3, the second push-pull circuit composed of FETs Q2 and Q4, and the low-pass filter LPF.

  Here, the FETs Q1 and Q3 are chips having a larger on-resistance and a smaller input capacitance than the FETs Q2 and Q4 as in the first embodiment, whereas the FETs Q2 and Q4 are similar to those in the first embodiment. This is a chip with smaller on-resistance and larger input capacitance than FETs Q1 and Q3.

  Therefore, the microcomputer 5 monitors the input signal S1 input from the input terminal 2, and whether there is no signal input or whether the input signal S1 is a weak small signal of, for example, 2 to 3 [W]. When the input signal S1 is no signal or a small signal, the switch terminals SW3A and SW4A of the switch circuits SW3 and SW4 are disconnected from the terminals T5 and T6 in consideration of efficiency, and the first push-pull composed of the FETs Q1 and Q3 Only the circuit is operated.

  When the input signal S1 is a large signal of, for example, about 50 to 100 [W] as a result of monitoring the input signal S1, the microcomputer 5 considers the sound quality and switches the switching terminals SW3A and SW3A of the switch circuits SW3 and SW4. By connecting the SW4A to the terminals T5 and T6, the first push-pull circuit composed of the FETs Q1 and Q3 is continuously operated, and the FET Q2 or Q4 is also driven to operate the second push-pull circuit. The first push-pull circuit and the second push-pull circuit are used in combination.

  In the above configuration, the PWM amplifier 11 has FETs Q1 and Q3 having a large on-resistance and a small input capacitance, and FETs Q2 and Q4 having a small on-resistance and a large input capacitance as switching elements, and the input signal S1 is a no-signal or small signal. When it is time, the switching terminals SW3A and SW4A of the switch circuits SW3 and SW4 are disconnected from the terminals T5 and T6, and the FET Q1 or Q3 having a small input capacitance is driven to operate only the first push-pull circuit. It is possible to reduce wasteful drive current, increase power consumption, and prevent wasteful heat generation and increase efficiency.

  In the PWM amplifier 11, when the input signal S1 is a large signal, the switching terminals SW3A and SW4A of the switch circuits SW3 and SW4 are connected to the terminals T5 and T6, and the first push-pull circuit composed of the FET Q1 or Q3 is continuously operated. In addition, by driving the FET Q2 or Q4 having a low on-resistance and a large input capacitance so that the second push-pull circuit is also operated, the gates of the FETs Q2 and Q4 are charged and discharged in a short time. The use of the first push-pull circuit and the second push-pull circuit together can achieve high sound quality.

  According to the above configuration, the PWM amplifier 1 operates only the first push-pull circuit composed of the FETs Q1 and Q3 according to the monitoring result of the input signal S1, and the FET Q2 and the FET Q2 in addition to the first push-pull circuit. By switching the operation of the second push-pull circuit composed of Q4 together, it is possible to prevent wasteful heat generation and increase in power consumption and realize high sound quality. .

(3) Third Embodiment In FIG. 3, in which parts corresponding to those in FIG. 1 are assigned the same reference numerals, 21 indicates the overall configuration of the PWM amplifier in the third embodiment. The input signal S1 supplied from the input terminal 2 is input to the PWM processor 3 as in the first embodiment.

  The PWM processor 3 converts the input signal S1 into a PWM pulse having a duty ratio corresponding to the input signal S1 by pulse width modulation, and switches the positive drive voltage signal and the negative drive voltage signal in the PWM pulse to a switch circuit. Output to terminals T7, T8 or terminals T9, T10 via SW5 and SW6.

  The switch circuits SW5 and SW6 can be switched to terminals T7 and T8 or terminals T9 and T10. The switch terminals SW5A and SW6A of the switch circuits SW5 and SW6 are connected to the first driver circuit 22.

  The first driver circuit 22 applies a drive voltage corresponding to a positive drive voltage signal supplied from the PWM processor 3 via the switch circuits SW5 and SW6 by the internal pre-driver 22A to the gate of the FET Q1. Is turned on, and a drive voltage corresponding to a negative drive voltage signal is applied to the gate of the FET Q3 to turn on the FET Q3.

  The FETs Q1 and Q3 constitute a first push-pull circuit as in the first embodiment, and the output of the first push-pull circuit is output to the speaker via a low-pass filter LPF comprising a coil L1 and a capacitor C1. It is connected to the.

  On the other hand, the terminals T9 and T10 are connected to the second driver circuit 23. The second driver circuit 23 is supplied from the PWM processor 3 via the switch circuits SW5 and SW6 by the internal predriver 23A. The FET Q2 is turned on by applying a drive voltage corresponding to the drive voltage signal to the gate of the FET Q2, and the FET Q4 is turned on by applying a drive voltage corresponding to the minus drive voltage signal to the gate of the FET Q4. Let

  The FETs Q2 and Q4 also form a second push-pull circuit as in the first embodiment, and the output of the second push-pull circuit is a speaker via a low-pass filter LPF composed of a coil L1 and a capacitor C1. Connected to the output.

  Also in this PWM amplifier 21, the outputs of the first push-pull circuit composed of FETs Q1 and Q3 and the second push-pull circuit composed of FETs Q2 and Q4 are smoothed by a low-pass filter LPF, and then a speaker (not shown) is output as a speaker. ).

  That is, in the PWM amplifier 21, an amplifier output stage is configured by the first push-pull circuit composed of FETs Q1 and Q3, the second push-pull circuit composed of FETs Q2 and Q4, and the low-pass filter LPF.

  Here, the FETs Q1 and Q3 are chips having a larger on-resistance and a smaller input capacitance than the FETs Q2 and Q4 as in the first embodiment, whereas the FETs Q2 and Q4 are similar to those in the first embodiment. This is a chip with smaller on-resistance and larger input capacitance than FETs Q1 and Q3.

  Therefore, the microcomputer 5 monitors the input signal S1 input from the input terminal 2, determines whether there is no signal input or a small signal, and the input signal S1 is no signal or small. When the signal is recognized as a signal, the switching terminals SW5A and SW6A of the switch circuits SW5 and SW6 are connected to the terminals T7 and T8 in consideration of efficiency, and the first push-pull circuit including the FET Q1 or Q3 of the first driver circuit 22 is connected. It has been made to work only.

  When the microcomputer 5 recognizes that the input signal S1 is a large signal of, for example, about 50 to 100 [W] as a result of monitoring the input signal S1, the switching terminals of the switch circuits SW5 and SW6 are considered in consideration of sound quality. By connecting SW5A and SW6A to terminals T9 and T10, the FET Q2 or Q4 is driven to operate only the second push-pull circuit.

  In the above configuration, the PWM amplifier 21 includes the first driver circuit 22 in which the FETs Q1 and Q3 having large on-resistance and small input capacitance and the pre-driver 22A are integrated, and the FETs Q2 and Q4 having small on-resistance and large input capacitance. A second driver circuit 23 integrated with the pre-driver 23A, and when the input signal S1 is no signal or a small signal, the switching terminals SW5A and SW6A of the switch circuits SW5 and SW6 are connected to the terminals T7 and T8. Since the first driver circuit 22 operates only the first push-pull circuit composed of the FETs Q1 and Q3 having a small input capacitance, it is possible to reduce useless drive current and increase power consumption and uselessness. Heat generation can be prevented and high efficiency can be achieved.

  In the PWM amplifier 21, when the input signal S1 is a large signal, the switching terminals SW5A and SW6A of the switch circuits SW5 and SW6 are connected to the terminals T9 and T10, and the second driver circuit 23 has a small on-resistance and a large input capacitance. By operating only the second push-pull circuit composed of the FET Q2 or Q4, charging / discharging of the gates of the FETs Q2 and Q4 can be performed in a short time to achieve high sound quality.

  According to the above configuration, in the PWM amplifier 21, the first driver circuit 22 in which the pre-driver 22A and the FETs Q1 and Q3 are integrated according to the monitoring result of the input signal S1, and the pre-driver 23A and the FETs Q2 and Q4 are integrated. By switching and using the second driver circuit 23, useless heat generation and increase in power consumption can be prevented, and high sound quality can be realized.

(4) Fourth Embodiment In FIG. 4, in which parts corresponding to those in FIG. 3 are assigned the same reference numerals, 31 indicates the overall configuration of the PWM amplifier in the fourth embodiment. The input signal S1 supplied from the input terminal 2 is input to the PWM processor 3 as in the first embodiment.

  The PWM processor 3 performs pulse width modulation on the input signal S1 to convert the input signal S1 into a PWM pulse having a duty ratio corresponding to the input signal S1, and converts the positive drive voltage signal and the negative drive voltage signal in the PWM pulse to the first. Output directly to the driver circuit 22.

  The first driver circuit 22 turns on the FET Q1 by applying a driving voltage corresponding to the positive driving voltage signal to the gate of the FET Q1 by the internal pre-driver 22A, and driving according to the negative driving voltage signal. The FET Q3 is turned on by applying a voltage to the gate of the FET Q3.

  That is, the first driver circuit 22 is configured to always apply a drive voltage to the FETs Q1 and Q3, and to always operate the first push-pull circuit including the FETs Q1 and Q3.

  Incidentally, in the PWM amplifier 31 in the fourth embodiment, unlike the third embodiment, the output of the PWM processor 3 and the first driver circuit 22 are directly connected, and the first driver circuit 22 is connected. Bias resistors are not connected to the gates of the FETs Q1 and Q3.

  In the FETs Q1 and Q3, the source of the FET Q1 and the source of the FET Q3 are connected as in the third embodiment, the drain of the FET Q1 is connected to the positive power source Vcc, and the drain of the FET Q3 is connected to the negative power source Vss. ing.

  The FETs Q1 and Q3 constitute a first push-pull circuit as in the third embodiment, and the output of the first push-pull circuit is output to a speaker via a low-pass filter LPF composed of a coil L1 and a capacitor C1. It is connected to the.

  By the way, the output of the PWM processor 3 is also supplied to the switch circuits SW7 and SW8, and when the switching terminals SW7A and SW8A of the switch circuits SW7 and SW8 are connected to the terminals T11 and T12, the first driver circuit. The drive voltage is applied not only to the gate 22 but also to the gates of the FETs Q2 and Q4 via the pre-driver 23A of the second driver circuit 23.

  The second driver circuit 23 turns on the FET Q2 by applying a driving voltage corresponding to the positive driving voltage signal to the gate of the FET Q2 by the internal pre-driver 23A, and driving according to the negative driving voltage signal. The FET Q4 is turned on by applying a voltage to the gate of the FET Q4.

  That is, the second driver circuit 23 includes the FETs Q2 and Q4 by applying a driving voltage to the FETs Q2 and Q4 only when the switching terminals SW7A and SW8A of the switch circuits SW7 and SW8 are connected to the terminals T11 and T12. The second push-pull circuit is operated.

  The output of the second push-pull circuit is also connected to the speaker output via a low-pass filter LPF composed of a coil L1 and a capacitor C1.

  Also in this PWM amplifier 31, the outputs of the first push-pull circuit composed of FETs Q1 and Q3 and the second push-pull circuit composed of FETs Q2 and Q4 are smoothed by a low-pass filter LPF, and then a speaker (not shown) is output as a speaker. )).

  That is, also in the PWM amplifier 31, an amplifier output stage is configured by the first push-pull circuit composed of FETs Q1 and Q3, the second push-pull circuit composed of FETs Q2 and Q4, and the low-pass filter LPF.

  Here, FETs Q1 and Q3 are chips having a larger on-resistance and a smaller input capacitance than FETs Q2 and Q4 as in the third embodiment, whereas FETs Q2 and Q4 are similar to those in the third embodiment. This is a chip with smaller on-resistance and larger input capacitance than FETs Q1 and Q3.

  Therefore, the microcomputer 5 monitors the input signal S1 input from the input terminal 2, determines whether there is no signal input or a small signal, and the input signal S1 is a no signal or a small signal. When it is recognized that the switching terminals SW7A and SW8A of the switch circuits SW7 and SW8 are disconnected from the terminals T11 and T12 in consideration of efficiency, only the first push-pull circuit including the FET Q1 or Q3 in the first driver circuit 22 is operated. It is made to let you.

  When the microcomputer 5 recognizes that the input signal S1 is a large signal of, for example, about 50 to 100 [W] as a result of monitoring the input signal S1, the switching terminal SW7A of the switch circuits SW7 and SW8 is considered in consideration of sound quality. And the SW8A are connected to the terminals T11 and T12, the first push-pull circuit composed of the FETs Q1 and Q3 is continuously operated, and the FET Q2 or Q4 is also driven to operate the second push-pull circuit. The first push-pull circuit and the second push-pull circuit are used in combination.

  In the above configuration, the PWM amplifier 31 includes the first driver circuit 22 in which the pre-driver 22A and the FETs Q1 and Q3 having large on-resistance and small input capacitance are integrated, and the FETs Q2 and Q4 having small on-resistance and large input capacitance. And the second driver circuit 23 integrated with the pre-driver 23A. When the input signal S1 is no signal or small signal, the switching terminals SW7A and SW8A of the switch circuits SW7 and SW8 are disconnected from the terminals T11 and T12. Since only the first push-pull circuit composed of the FETs Q1 and Q3 having a small input capacitance is operated by the first driver circuit 22, useless drive current is reduced, power consumption is increased, and useless heat generation is performed. Can be prevented and high efficiency can be achieved.

  In the PWM amplifier 31, when the input signal S1 is a large signal, the switching terminals SW7A and SW8A of the switch circuits SW7 and SW8 are connected to the terminals T11 and T12, and the first driver circuit 22 uses the FETs Q1 and Q3 having small input capacitances. The first push-pull circuit is continuously operated, and the second driver circuit 23 is also operated for the second push-pull circuit composed of the FET Q2 or Q4 having a low on-resistance and a large input capacitance. And charging / discharging with respect to the gate of Q4 can be performed in a short time, and high sound quality of the speaker output can be achieved by using the first push-pull circuit and the second push-pull circuit together.

  According to the above configuration, the PWM amplifier 31 operates only the first push-pull circuit in the first driver circuit 22 according to the monitoring result of the input signal S1, and in addition to the first driver circuit 22. By switching between the second push-pull circuit and the second push-pull circuit in the second driver circuit 23, it is possible to prevent wasteful heat generation and increase in power consumption and realize high sound quality. Can do.

(5) Fifth Embodiment In FIG. 5, in which parts corresponding to those in FIG. 1 are assigned the same reference numerals, 41 indicates the overall configuration of the PWM amplifier in the fifth embodiment. The input signal S 1 supplied from the input terminal 2 is input to the PWM processor 3.

  The PWM processor 3 performs pulse width modulation on the input signal S1 to convert it into a PWM pulse having a duty ratio corresponding to the input signal S1, and predrivers the positive drive voltage signal and the negative drive voltage signal in the PWM pulse. 4 is supplied.

  The pre-driver 4 applies a drive voltage corresponding to the positive drive voltage signal to the gates of the FET Q1, FET Q2, FET Q5, and FET Q6 via the selector 42, thereby turning on the FET Q1, FET Q2, FET Q5, and FET Q6, and minus operation. By applying a drive voltage corresponding to the drive voltage signal to the gates of the FET Q3, FET Q4, FET Q7 and FET Q8 via the selector 42, the FET Q3, FET Q4, FET Q7 and FET Q8 are turned on.

  The FETs Q1 and Q3 are mainly used as switching elements. When the FET Q1 is turned on, the FET Q3 is turned off. When the FET Q3 is turned on, the FET Q1 is turned off. It is made to compose.

  The FETs Q2 and Q4 are also used as switching elements, and when the FET Q2 is turned on, the FET Q4 is turned off. Conversely, when the FET Q4 is turned on, the FET Q2 is turned off to constitute a second push-pull circuit. It is made like that.

  Similarly, FETs Q5 and Q7, FETQ6 and FETQ8 are also used as switching elements. When the FETQ5 and FETQ6 are turned on, the FETQ7 and FETQ8 are turned off. When the FETQ7 and FETQ8 are turned on, the FETQ5 and FETQ6 are turned on. The third push-pull circuit and the fourth push-pull circuit are configured by performing the off operation.

  FETs Q1 and Q3, FETs Q2 and Q4, FETs Q5 and Q7, and FETs Q6 and Q8 are connected to the sources of the FETs Q1, Q2, Q5, and Q6 and the sources of the FETs Q3, Q4, Q7, and Q8, and the connection middle point is the coil L1. And the drain of FETs Q1, Q2, Q5, and Q6 are connected to a positive power source Vcc, and the drains of FETs Q3, Q4, Q7, and Q8 are connected to a negative power source Vss. It is connected.

  The PWM amplifier 41 includes a first push-pull circuit composed of FETs Q1 and Q3, a second push-pull circuit composed of FETs Q2 and Q4, a third push-pull circuit composed of FETs Q5 and Q7, and FETs Q6 and Q8. The output amplified by the fourth push-pull circuit is smoothed by the low-pass filter LPF, and then supplied to a speaker (not shown) as a speaker output.

  That is, in the PWM amplifier 41, a first push-pull circuit consisting of FETs Q1 and Q3, a second push-pull circuit consisting of FETs Q2 and Q4, a third push-pull circuit consisting of FETs Q5 and Q7, and a fourth push-pull circuit consisting of FETs Q6 and Q8. The push-pull circuit and the low-pass filter LPF constitute an amplifier output stage.

  Here, FETs Q1 and Q3 are composed of a chip having a larger on-resistance and a smaller gate input capacitance than FETs Q2 and Q4, whereas FETs Q2 and Q4 have a smaller on-resistance than FETs Q1 and Q3 and a gate input capacitance. Is made up of big chips.

  Further, the FETs Q5 and Q7 and the FETs Q6 and Q8 are configured by a chip having a smaller on-resistance and a larger gate input capacitance than the FETs Q1 and Q3, like the FETs Q2 and Q4.

  Therefore, the microcomputer 5 monitors the state of the input signal S1 input from the input terminal 2, and when there is no signal input or when the input signal S1 is a weak small signal of 2 to 3 [W], for example. When the input signal S1 is recognized as a no signal or a small signal, the FET Q1 or Q3 is driven through the selector 42 in consideration of the efficiency, and the gate input capacitance is small. Only the push-pull circuit is operated.

  When the microcomputer 5 recognizes that the input signal S1 is a large signal of, for example, about 50 to 100 [W] as a result of monitoring the input signal S1, the FET Q1 and the FET Q1 are selected via the selector 42 in consideration of sound quality. After stopping the operation of the first push-pull circuit composed of Q3, the FET Q2 or Q4 is driven to operate only the second push-pull circuit, or the FET Q2 or Q4, the FET Q5 or Q7, the FET Q6 or the FET Q8 are all driven. Thus, the second push-pull circuit to the fourth push-pull circuit are operated.

  Furthermore, when the microcomputer 5 recognizes that the volume level of the input signal S1 has increased more rapidly than before as a result of monitoring the state of the input signal S1, or the amplitude level of the input signal S1 is higher than before. When it is recognized that it has increased rapidly, for example, FETQ1 or FETQ3, FETQ2 or Q4, FETQ5 or Q7, FETQ6 or FETQ8 are all driven to operate all of the first to fourth push-pull circuits. It can also be made.

  That is, the microcomputer 5 appropriately determines in which combination the first push-pull circuit to the fourth push-pull circuit are best used according to the state of the input signal S1, and selects the combination that is considered to be the best. The first push-pull circuit to the fourth push-pull circuit are operated.

  Incidentally, the microcomputer 5 prepares a table indicating whether any one or all of the first push-pull circuit to the fourth push-pull circuit are used in accordance with the state of the input signal S1. A combination in one push-pull circuit to a fourth push-pull circuit can also be determined.

  In the above configuration, the PWM amplifier 41 has a first push-pull circuit composed of FETs Q1 and Q3 having a large on-resistance but a small gate input capacitance, and FETs Q2 and Q4, FET Q5 having a large gate input capacitance but a small on-resistance. The second push-pull circuit to the fourth push-pull circuit including the FET Q7, the FET Q6, and the FET Q8 are used, and the first push-pull circuit to the fourth push-pull circuit are appropriately combined according to the state of the input signal S1. By doing so, it is possible to reduce unnecessary and useless drive current and increase power consumption, to prevent wasteful heat generation, destruction of FETQ1 to FETQ8 due to large current, and the like.

  In the PWM amplifier 41, when the input signal S1 is a weak small signal, only the first push-pull circuit composed of the FETs Q1 and Q3 is operated via the selector 42, and the second push-pull circuit to the fourth push-pull circuit are operated. Since the operation of the circuit can also be stopped, power consumption can be reduced and higher efficiency can be achieved as in the first embodiment.

  According to the above configuration, the PWM amplifier 41 can use the first push-pull circuit to the fourth push-pull circuit by an optimal combination in accordance with the state of the input signal S1, so that the state of the input signal S1 is maintained. Combined optimum amplification processing can be executed.

(6) Other Embodiments In the first to fifth embodiments described above, FETs Q1, Q2, Q3, Q4, Q5, Q6, Q7 and Q8 made of MOS-FETs are used as switching elements. However, the present invention is not limited to this, and a bipolar transistor, a simple FET, or the like may be used.

  In the first to fifth embodiments described above, the case where one PWM amplifier 1, 11, 21, 31, 41 is provided for the speaker output has been described. Not limited to this, as shown in FIG. 6, the speaker output may be doubled by connecting the PWM amplifier 51 and the PWM amplifier 61 that simultaneously operate in reverse with respect to the speaker output by BTL (balanced transformer-less) connection. good.

  Furthermore, in the above-described first to fifth embodiments, the case where the switching amplifier of the present invention is applied to a PWM amplifier has been described. However, the present invention is not limited to this, and is applied to a class D amplifier. You may do it.

  Furthermore, in the fifth embodiment described above, the FETs Q2 and Q4, the FETs Q5 and Q7, and the FETs Q6 and Q8 in the second to fourth push-pull circuits have higher on-resistance than the FETs Q1 and Q3 in the first push-pull circuit. Although the case where all of the chips having the same characteristics are described as having a small and large input capacitance of the gate has been described, the present invention is not limited to this. You may make it comprise with the chip | tip of arbitrary characteristics, such as making it from the chip | tip of a different characteristic.

  Further, in the fifth embodiment described above, the case where four first to fourth push-pull circuits are used has been described. However, the present invention is not limited to this, and an arbitrary number of push-pull circuits are used. You may make it use properly by the selector 42 using a push pull circuit.

  Furthermore, in the above-described first to fourth embodiments, the first push-pull circuit as the first output stage, the second push-pull circuit as the second output stage, and the low-pass as the smoothing means PWM amplifiers 1, 11, 21, and 31 as switching amplifiers are configured by the filter LPF, pre-drivers 4, 22A and 23A as drive voltage supply means, and the microcomputer 5 as determination means and control means. Although the case has been described, the present invention is not limited to this, and the switching amplifier may be configured by various other circuit configurations.

  Further, in the fifth embodiment described above, the first to fourth push-pull circuits as output stage groups, the low-pass filter LPF as smoothing means, the pre-driver 4 as drive voltage supply means, and the determination means The case where the PWM amplifier 41 as the switching amplifier is constituted by the microcomputer 5 as the selector and the selector 42 as the selector means has been described, but the present invention is not limited to this, and the switching amplifier is not limited to this by various circuit configurations. You may make it comprise.

  The switching amplifier and the switching amplifier driving method of the present invention can be applied to an amplifier that performs an amplification operation based on a pulse waveform, for example.

1 is a schematic block diagram illustrating a configuration of a PWM amplifier according to a first embodiment. FIG. 6 is a schematic block diagram illustrating a configuration of a PWM amplifier according to a second embodiment. It is a basic block diagram which shows the structure of the PWM amplifier in 3rd Embodiment. It is a basic block diagram which shows the structure of the PWM amplifier in 4th Embodiment. It is a basic block diagram which shows the structure of the PWM amplifier in 5th Embodiment. It is a basic block diagram which shows the structure of the PWM amplifier in other embodiment.

Explanation of symbols

1, 11, 21, 31, 41, 51, 61 ... PWM amplifier, 2 ... input terminal, 3 ... PWM processor, 4 ... pre-driver, 5 ... microcomputer, 42 ... selector, SW1 to SW8 Switch circuit, T1 to T12 terminal, Q1 to Q4 FET, R1 to R4 bias resistance, L1 coil, C1 capacitor.

Claims (7)

A first output stage configured by push-pull connection of transistors having a first on-resistance;
A second output stage configured by push-pull connection of transistors having a second on-resistance lower than the first on-resistance;
Smoothing means connected to both output terminals of the first output stage and the second output stage and smoothing the output from the first output stage and the second output stage;
Drive voltage supply means for supplying a drive voltage according to an input signal to the first output stage and the second output stage;
Determining means for determining whether the input signal is no signal or the input signal is a small signal of a predetermined level or less;
A switching amplifier comprising: control means for selectively switching the first output stage or the second output stage according to a judgment result by the judgment means. The control means switches to the first output stage when it recognizes that the input signal is no signal or the small signal based on the determination result, and switches to the second output stage otherwise. The switching amplifier according to claim 1. The control means switches to the first output stage when recognizing that the input signal is no signal or the small signal based on the determination result, and otherwise controls the first output stage and the first output stage. The switching amplifier according to claim 1, wherein both of the two output stages are switched to be used together. 2. The switching amplifier according to claim 1, wherein the drive voltage supply means is provided for each of the first output stage and the second output stage. 2. The switching amplifier according to claim 1, wherein the switching amplifier is connected to another switching amplifier that operates reversely with respect to the switching amplifier in a BTL (balanced transformer-less) connection. A first output stage configured by push-pull connection of a transistor having a first on-resistance, and a push-pull connection of a transistor having a second on-resistance lower than the first on-resistance. An output stage group in which a plurality of second output stages are connected in parallel;
Smoothing means connected to each output stage in the output stage group and smoothing the output from each output stage;
Drive voltage supply means for supplying a drive voltage corresponding to the input signal to each output stage in the output stage group;
Determining means for determining the state of the input signal;
A switching amplifier comprising: selector means for selectively switching each output stage in the output stage group according to a judgment result by the judging means. A first output stage configured by push-pull connection of a transistor having a first on-resistance, and a push-pull connection of a transistor having a second on-resistance lower than the first on-resistance. The amplifier output means connected to the output terminals of both of the second output stage and the smoothing means for smoothing the output from the first output stage and the second output stage is external to the amplifier output means. A drive voltage supply step for supplying a drive voltage in accordance with an input signal from;
A determination step of determining whether the input signal is no signal or the input signal is a small signal of a predetermined level or less;
And a control step of selectively switching the first output stage or the second output stage according to the determination result of the determination step.

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