100 放大器 102 增益放大器 114 差動放大器 116a、116b 比較器 120 全橋式輸出電路 120a、120b 半橋電路 122 剩σ八 1334268 八、 本案若有化學式時，請揭示最能顯示發明特徵的化學 式： (無） 九、 發明說明： 【發明所屬之技術領域】 本發明係關於一種可產生脈衝寬度調變訊號的裝置以及 應用此裝置之放大器，尤指一種D類音源放大器以及其調變方 法。 【先前技術】 脈衝寬度調變（PWM)放大器，亦被習知為D類放大器， 其工作原理與交換式電源供應器（switching power supply)相 似，其不同點僅為脈衝寬度調變放大器的參考電源係為一變動 的訊號，而交換式電源供應器為一固定電壓值。通常D類放大 器可分類為類比輸入與數位輸入兩種，後者亦可稱為全數位輸 入之音源放大器。 D類放大器的功率效率（power efficiency)遠優於傳統的 A、B以及AB類放大器，因為它的高效率，D類放大器只需要較 1334268 小的電源供應器並且可以不使用散熱片（或者減少散熱片的面 積），如此-來大大降低了整個系統的成本、尺寸以及重量。 其他優點還包含了較長的電池使用時間、較安靜優質的粉聽 境以及此積體化的音源放大器具有大輸出功率（每聲道大於^ 瓦）等。-般的D類放大器需要—輸出據波器，因此增加了 統的體積以及成本，_其在特裝置上的剌，益〉慮波器 ⑽eriess)式D類放大器可省去輸域波器卻仍可保留原來高100 amplifier 102 gain amplifier 114 differential amplifier 116a, 116b comparator 120 full-bridge output circuit 120a, 120b half-bridge circuit 122 σ 八 1334268 八. Nine, the invention relates to: [Technical Field] The present invention relates to a device capable of generating a pulse width modulation signal and an amplifier using the same, and more particularly to a class D sound source amplifier and a modulation method thereof. [Prior Art] A pulse width modulation (PWM) amplifier, also known as a class D amplifier, operates in a similar manner to a switching power supply, and differs only in the reference of a pulse width modulation amplifier. The power supply is a varying signal and the switched power supply is a fixed voltage value. Usually Class D amplifiers can be classified into analog input and digital input. The latter can also be called the audio amplifier of the full digital input. Class D amplifiers have much better power efficiency than traditional Class A, B, and Class AB amplifiers because of their high efficiency. Class D amplifiers require only a small power supply that is smaller than 1334268 and can be used without heat sinks (or reduced). The area of the heat sink), so - greatly reduces the cost, size and weight of the entire system. Other advantages include longer battery life, quieter, better-quality powder hearing, and the integrated output amplifier with high output power (greater than ^W per channel). - Class D amplifiers need to - output the data filter, thus increasing the size and cost of the system, _ its special device, the benefits of the classifier (10) eriess class D amplifier can save the domain filter but Still retain the original high
• 效率的^點，也就是說’採用無遽波器式的調變方案可使得D 類放大器在成本及尺寸上幾乎等於八3類放大器但卻具有更好 的效率。 一種達成無滤波器式D類放大器的設計為只有當需要時才 v 將電流輸人至負載’而—但輸人後便讓電流保持住，使得能量 不會在無輸入訊號時因為電流從負載流出而衰減或浪費掉。達 - 成上述設計的一種方法是採用具有四種操作態樣的四元調變 (quaternarymodulation)方式’其根據音源輪入訊號以利用四 φ 種操作態樣來驅動如剩°八等負載，例如在美國專利US6262632 中詳細介紹了此種方法。 然而，省去濾波器有可能使得D類放大器幅射出較強的電 磁干擾（EMI) ’此現象在美國專利US6614297中被探討並且 提出了 一種採用三元（ternary)脈衝寬度調變編碼（c〇ding) 以取代傳統二元或四元脈衝寬度調變編碼的系統，由於負載兩 端在三元脈衝寬度調變時的電壓差值只會是電源VDD，而不是 二元脈衝寬度調變所出現的2VDD，因此電磁干擾可獲得改 善，雖然二元脈衝寬度調變編碼可由四元脈衝寬度調變編碼所 控制的開關經由適當切換而產生，但是此方法 干擾元件在雜上的縣會高於直接_三元脈衝紐調= 碼的電路。 上述採用三元脈衝寬度調變方法之放大器改善了電磁干 擾現象並且鱗無舰H操作咖触，但是卻需要—邏輯模 組將四態樣的切換訊號（四元脈衝寬度調變編碼）轉換成三態 樣的切換訊號（三元脈衝寬度調變編碼）來達成其目的。因此， 成要-種改良的調變方案來產生三元脈衝寬度調變編碼以提供 給D類放大器使用’尤其是類比輸入式d類放大器。 【發明内容】 本發明揭露一種可產生脈衝寬度調變訊號的裝置與應用 此裝置之放大器，包含有第一、第二比較器以及輸出級，第一、 第二比較器用來分別將一對差動訊號（differential signal)與一 半波（half-swing)調變訊號做比較以產生第一、第二脈衝寬度 調變（PWM)控制訊號’其中半波調變訊號之電壓振幅小於該 對差動訊號之電壓振幅；以及輸出級包含有一對輸入端耦合至 第一、第二脈衝寬度調變控制訊號以提供對應於第一、第二脈 衝寬度調變控制訊號之一三元編碼(ternary encoded )輸出訊號。• The efficiency of the ^ point, that is, the use of a chopper-free modulation scheme allows Class D amplifiers to be almost equal in cost and size to eight Class 3 amplifiers but with better efficiency. A filterless Class D amplifier is designed to pass current to the load only when needed. - But after input, the current is held so that the energy is not in the absence of an input signal because the current is flowing from the load. Attenuate or waste by flowing out. One way to achieve the above design is to use a quaternary modulation method with four operating modes, which is based on the sound source wheeling signal to drive the load such as the remaining eight octaves, for example This method is described in detail in U.S. Patent 6,262,632. However, the elimination of the filter may cause the Class D amplifier to emit strong electromagnetic interference (EMI). This phenomenon is discussed in U.S. Patent No. 6,614,297 and a ternary pulse width modulation coding is proposed (c). 〇ding) In order to replace the traditional binary or quaternary pulse width modulation coding system, the voltage difference between the two ends of the load during the ternary pulse width modulation will only be the power supply VDD, not the binary pulse width modulation. The 2VDD appears, so the electromagnetic interference can be improved. Although the binary pulse width modulation code can be generated by the switch controlled by the quaternary pulse width modulation code, the interference component of this method will be higher than the county. Direct _ three-element pulse adjustment = code circuit. The above-mentioned amplifier using the ternary pulse width modulation method improves the electromagnetic interference phenomenon and scales without the ship H operation, but requires a logic module to convert the four-state switching signal (quaternary pulse width modulation coding) into A three-state switching signal (ternary pulse width modulation coding) is used to achieve its purpose. Therefore, an improved modulation scheme is used to generate ternary pulse width modulation coding to provide for use in class D amplifiers, particularly analog input type d-type amplifiers. SUMMARY OF THE INVENTION The present invention discloses an apparatus for generating a pulse width modulation signal and an amplifier using the same, comprising a first and a second comparator and an output stage, wherein the first and second comparators are respectively used to respectively perform a pair of differences The differential signal is compared with a half-swing modulation signal to generate first and second pulse width modulation (PWM) control signals, wherein the voltage amplitude of the half-wave modulation signal is less than the pair of differentials a voltage amplitude of the signal; and the output stage includes a pair of inputs coupled to the first and second pulse width modulation control signals to provide one of the first and second pulse width modulation control signals (ternary encoded) Output signal.
在實施例中’該放大器係為D類音源放大器，包含有用來 接收音源輸入訊號並將其轉換成一對差動訊號的差動放大器， 以及用來分別將該對差動訊號與一半波調變訊號做比較以產生 第一、第二脈衝寬度調變控制訊號的第一、第二比較器，其中 半波調變訊號之電壓振幅小於該對差動訊號之電壓振幅。該D 類音源放大器另包含有全橋式（H-bridge)輸出電路，用來接 收脈衝寬度調變控制訊號並藉由一對輸出端提供放大之三元編 碼音源輸出訊號至一負載。 【實施方式】 第1A圖和第1B圖為一類比輸入訊號與其三元（temary)脈 衝寬度s周變（PWM)訊號的示意圖’經過三元脈衝寬度調變， 該編碼後的訊號只會出現對應於原類比訊號振幅的三種態樣之 一’亦即（1)+VDD、（2)接地電壓以及(3)-VDD。美國專利 US5077539揭露一個使用三元脈衝寬度調變的d類放大器實施 例’請參考第2圖，第2圖為習知技術中採用三元脈衝寬度調變 編碼之類比輸入式D類放大器10的電路圖，放大器1〇包含有一 對差動§孔號’標示為Vip與Vjn ’分別搞合至固定增益放大器i2a 與12b，增益放大器12a與12b係為前置放大器（pre_ampiifier) 且並非必要元件’若類比輸入訊號太小，則可藉由增益放大器 12a與12b放大’在某些情況下增益放大器12&與121>的增益值被 設計成可選擇以適應不同的輸入訊號範圍，然而，無論使用前 置放大器與否’都不會影響D類放大器10脈衝寬度調變的操 作。增益放大器12a與12b的輸出端經由電阻1^耦合至差動式運 算放大器14的正輸入端與負輸入端，運算放大器14結合輸入訊 號與回授訊號形成閉迴路架構以增進系統的頻率響應以降低非 線性誤差以及雜訊失真。 運算放大器14輪出的差動訊號提供給一對比較器i6a與16b 用來與一時間訊號做調變，例如在〇¥與乂〇1：)間振盪的一全波 1334268 (fbll-swing)二角波（亦即差動訊號的最大撼幅度），並產 生脈衝見度調變輸峻制訊號，此訊號為數位訊號並提供給三 ，編碼驅動邏輯模組18來控制輪出開關電路的切換狀態，也就 =，全橋式（H.bridge)輸出電路戰做域的輸出訊號 。至一負載，例如喇队22，全橋式輸出電路2〇搞合至一單極 (unipolar)電源供應器（VDD2 )，利用開關的切換來提供放 =的輸出訊鼓督Λ22，該輸纽號係為—與輸人訊號近似的 複製訊號’但是具有由電賴絲提供魄大轉，亦即可被 視為功較域的輸人減，請參考幻圖，輸㈣三元編碼之 脈衝寬度調變波形縣兩脈衝寬度調變齡峨（標示為^ 與v0N)的差，亦即v〇p_v〇N。 ^由於第三態樣，亦即零輸出態樣的導入，輸出電路的功率 =耗會與輸出訊號成比例，如此一來，對於小輸入訊號其功 率損，亦小’而在無輸人訊餅職乎沒有電流流㈣|σΛ22， 所以沒有損耗發生，功率損耗的降低減少了熱雜，在放大器 的封裝上可以仙較小的散熱元件，在某些情況下甚至允許直 接使用而不必使用散熱元件。然而，第2圖中的放大器10有一個 缺點，它的三元脈衝寬度調變編碼需要有一個三元編碼驅動邏 輯模組18來執行，比較器16a與16b的訊號輸出端不能夠直接連 接全橋式輪出電路2〇來提供三元編碼之脈衝寬度調變輸出訊 號。，外’電磁干擾（EMI)的降低是D類放大器設計時重要 的考量，直接採用比較器16a與16b的輸出對於全橋式輸出電路 20來說是一四元切換訊號，與三元切換訊號相比，需要有性能 較佳的抗共模電磁干擾元件。 1334268 第3圖為本發明一實施例之利用半波式脈衝寬度調變之類 比輸入式D類音源放大器100的電路圖，放大器100具有一對差 動輸入端，用來接收一對差動訊號VIP與V!N並經由電阻r3提供 給具有回授電阻R4的增益放大器102,其作用如同上述之增益放 大器12a與12b，放大器102的差動輸出端經由電阻元件Ri提供訊 號給運算放大器114的輸入端，雷同上述第2圖放大器1〇的電 路，放大器100中的運算放大器114結合輸入訊號與回授訊號形 成一閉迴路架構以減少雜訊失真’該閉迴路包含有一差動積分 器’其係由電阻氏、電阻&、電容C以及運算放大器114組成， 請注意，回授閉迴路結構可改善輸出訊號品質，但在本發明中 並非必要。 如同放大器10,放大器100也包含有一對比較器1163與1161) 用來分別接收運算放大器114的差動輸出訊號以及一調變訊 號’以下將詳細描述。放大器100的輸出級也包含有一全橋式輸 出電路120 ’其包含有一第一半橋i2〇a (或稱正半橋）以及一第 二半橋120b (或稱負半橋），全橋式輸出電路12〇的每個半橋包 含有一對電晶體串接於電源VDD2與地（GND)之間，熟知技 藝者可輕易知道该對電晶體可以是兩n型金屬氧化物半導體 (NMOS)電晶體、兩p型金屬氧化物半導體（pM〇s)電晶體 或者是一個PMOS電晶體配一個NM0S電晶體。不同組態的全 橋電路需要不同的驅動電路來麵合比較器的輸出至全橋電路， 與PMOS電晶體相比，NMOS電晶體具有較低的導通電阻，所 以最有效率的MOS電晶體組態是在高壓側（high side)與低壓 側（low side )皆使用NMOS電晶體’然而此種設計會較為複雜， 9 1334268 因為基本上糾需要-個電荷泵電路來驅動高壓側M〇s電晶 體的閘極。第3圖實施例中的全橋式輸出電路12〇的兩個半橋部 份120a與120b皆由一個NM〇s電晶體與一個pM〇s電晶體組合 而成，來放大比較器的輸出至一想達到的電壓準位。In the embodiment, the amplifier is a class D source amplifier, and includes a differential amplifier for receiving the input signal of the sound source and converting it into a pair of differential signals, and for respectively modulating the pair of differential signals with half of the waves. The signals are compared to generate first and second comparators for the first and second pulse width modulation control signals, wherein the voltage amplitude of the half-wave modulation signal is less than the voltage amplitude of the pair of differential signals. The Class D source amplifier further includes a full-bridge (H-bridge) output circuit for receiving the pulse width modulation control signal and providing an amplified ternary coded source output signal to a load via a pair of outputs. [Embodiment] FIG. 1A and FIG. 1B are schematic diagrams of an analog input signal and its ternary pulse width s-cycle (PWM) signal. After the ternary pulse width modulation, the encoded signal will only appear. One of the three aspects corresponding to the amplitude of the original analog signal' is (1) + VDD, (2) ground voltage, and (3) - VDD. US Patent No. 5,077, 539 discloses an embodiment of a class D amplifier using ternary pulse width modulation. Please refer to FIG. 2, which is an analog input type D amplifier 10 using ternary pulse width modulation coding in the prior art. In the circuit diagram, the amplifier 1〇 includes a pair of differential § hole numbers 'labeled as Vip and Vjn' respectively coupled to the fixed gain amplifiers i2a and 12b, and the gain amplifiers 12a and 12b are pre-amplifiers and are not necessary components. If the analog input signal is too small, the gain amplifiers 12a and 12b can be amplified by the gain amplifiers 12a and 12b. In some cases, the gain values of the gain amplifiers 12 & and 121> are designed to be selectable to accommodate different input signal ranges, however, regardless of before use. Whether the amplifier is turned on or not will not affect the operation of the Class D amplifier 10 pulse width modulation. The output terminals of the gain amplifiers 12a and 12b are coupled to the positive input terminal and the negative input terminal of the differential operational amplifier 14 via a resistor 1 . The operational amplifier 14 forms a closed loop architecture in combination with the input signal and the feedback signal to improve the frequency response of the system. Reduce nonlinear errors and noise distortion. The differential signal rotated by the operational amplifier 14 is supplied to a pair of comparators i6a and 16b for modulation with a time signal, for example, a full wave 1334268 (fbll-swing) oscillating between 〇¥ and 乂〇1:) The two-corner wave (that is, the maximum amplitude of the differential signal) generates a pulse-sensing modulation signal, and the signal is a digital signal and is supplied to the third, and the code driving logic module 18 controls the wheel-out switching circuit. Switching state, that is, the full-bridge (H.bridge) output circuit fights the output signal of the domain. To a load, such as the racquet 22, the full-bridge output circuit 2 is coupled to a unipolar power supply (VDD2), and the switching of the switch is used to provide the output of the output controller. The number is - the copy signal similar to the input signal' but with the big turn provided by the electric lyrics, it can be regarded as the input reduction of the field. Please refer to the phantom, the input (four) ternary code pulse The width modulation waveform counts the difference between the two pulse widths (labeled as ^ and v0N), that is, v〇p_v〇N. ^Because of the third aspect, that is, the introduction of the zero output state, the power of the output circuit = the power consumption will be proportional to the output signal, so that the power loss for the small input signal is small, and there is no loss. There is no current flow (4)|σΛ22, so there is no loss, the reduction of power loss reduces the heat, and the smaller heat sink components can be used in the package of the amplifier. In some cases, it can even be used directly without using heat dissipation. element. However, the amplifier 10 of Fig. 2 has a disadvantage that its ternary pulse width modulation coding requires a ternary code drive logic module 18 to be executed, and the signal outputs of the comparators 16a and 16b cannot be directly connected. The bridge wheel circuit 2 provides a ternary coded pulse width modulated output signal. The external 'electromagnetic interference (EMI) reduction is an important consideration in the design of the class D amplifier. The output of the comparators 16a and 16b is directly used as a four-element switching signal for the full-bridge output circuit 20, and the three-way switching signal In comparison, a better anti-common mode electromagnetic interference component is required. 1334268 FIG. 3 is a circuit diagram of an analog input type D source amplifier 100 using a half-wave pulse width modulation according to an embodiment of the present invention. The amplifier 100 has a pair of differential inputs for receiving a pair of differential signals VIP. And V!N is supplied to the gain amplifier 102 having the feedback resistor R4 via the resistor r3, which functions as the gain amplifiers 12a and 12b described above, and the differential output of the amplifier 102 provides a signal to the input of the operational amplifier 114 via the resistive element Ri. In the circuit of the second amplifier of the second embodiment, the operational amplifier 114 in the amplifier 100 combines the input signal and the feedback signal to form a closed loop architecture to reduce noise distortion. The closed loop includes a differential integrator. It consists of a resistor, a resistor & a capacitor C and an operational amplifier 114. Note that the feedback closed loop structure improves the output signal quality, but is not necessary in the present invention. Like amplifier 10, amplifier 100 also includes a pair of comparators 1163 and 1161) for receiving the differential output signal of operational amplifier 114 and a modulation signal, respectively, which will be described in detail below. The output stage of amplifier 100 also includes a full bridge output circuit 120' which includes a first half bridge i2〇a (or positive half bridge) and a second half bridge 120b (or negative half bridge), full bridge Each of the half bridges of the output circuit 12A includes a pair of transistors connected in series between the power supply VDD2 and the ground (GND). It is well known to those skilled in the art that the pair of transistors can be two n-type metal oxide semiconductor (NMOS) devices. The crystal, two p-type metal oxide semiconductor (pM〇s) transistors or a PMOS transistor with an NM0S transistor. Different configurations of full-bridge circuits require different drive circuits to interface the output of the comparator to the full-bridge circuit. Compared to PMOS transistors, NMOS transistors have lower on-resistance, so the most efficient MOS transistor group The state uses NMOS transistors on both the high side and the low side. However, this design is more complicated. 9 1334268 basically requires a charge pump circuit to drive the high side M〇s. The gate of the crystal. The two half bridge portions 120a and 120b of the full bridge output circuit 12A in the embodiment of Fig. 3 are combined by an NM〇s transistor and a pM〇s transistor to amplify the output of the comparator to A voltage level that you want to achieve.
與使用全波二角波作為調變訊號相比，第3圖中的放大器 100使用半波二角波（圖中vSAW所示）作為調變訊號，而「半 波」意思是指調變訊號的電壓振幅不會介於整個VDD到地之 間’亦即會小於差動訊號的電壓振幅’以下將詳細說明。調變 訊號的電壓振幅會介於電壓vCM與最大供應電壓（若是雙極 (bipolar)電源，則是正電壓最大值）之間，或者是介於電壓 Vcm與最小供應電壓（若是雙極（bipolar)電源，則是負電壓 最大值）之間，其中VCM可以是最大與最小供應電壓間的任一 準位’為了獲付最大的訊號動態區間（dynamjc range )，vcMCompared with the use of a full-wave binary wave as a modulation signal, the amplifier 100 in FIG. 3 uses a half-wave two-angle wave (shown as vSAW in the figure) as a modulation signal, and "half-wave" means a modulation signal. The voltage amplitude will not be between VDD and ground 'that is, will be less than the voltage amplitude of the differential signal' below. The voltage amplitude of the modulation signal will be between the voltage vCM and the maximum supply voltage (or a positive voltage maximum if it is a bipolar power supply), or between the voltage Vcm and the minimum supply voltage (if bipolar) The power supply is between the negative voltage maximum), where VCM can be any level between the maximum and minimum supply voltages. In order to receive the largest signal dynamic range (dynamjc range), vcM
通常设為差動訊號對的共模電壓。雖然半波調變訊號的振幅小 於差動訊號峰值與峰值間（peak-to-peak)的振幅即可，然而， 將調變訊號的振幅設為電源供應器電壓區間的一半並且設定 VCM為積分器的共模電壓會具有較佳的效能，特別是如本實施 例中將調變訊號VSAW設為一三角波’且其振盪範圍為(a)介於 Vcm與(VCM+VSW)間’其中VCM為共模電壓而vsw為三角波振 幅’或者(b)介於VCM與(VCM-Vsw)間。如前所述，雖然共模電壓 可以是任何值，但是若供應電源電壓範圍從0V到VDD，設計者 會選擇VDD/2為共模電壓以獲得最大訊號動態區間，本實施例 中VCM設為VDD/2，三角波振幅Vsw介於VDD/2至VDD或者 VDD/2至0V之間’本發明調變方法的原理繪於第4A圖與第4B ⑧ 1334268 功率祕以及熱處理等問題。另外，假設使用相同的三角波頻 率’傳統的全波式賴技術每―:欠脈衝寬度織轉換會產生兩 個脈衝（pulse) ’而採用本發明提出之半波式調變技術則每一 次脈衝寬度峨轉換只會產生—個脈衝，換句話說，進行脈衝 寬度調變時_換鮮減少—半，因此由於嫌損耗所造成的 功率損耗便降低了。 請參考第3圖’全橋式輸出電路12〇的第一半橋12〇a與第二 半橋120b的輸出綱合至一負載元件（例如督八122)以提供放 大後的二元編碼之脈衝寬度調變輸出訊號，如之前所述，此種 作法移除了習知技術中需要的三元編碼驅動邏輯模組而減少電 路複雜度，另外，在半波調變技術中，因為三角波電壓振幅只 介於VDD至VCM或VCM至地之間（亦即振幅為vdd/2)，比較 器116a與116b不需軌對執（raii-t0-rail)輸入級，也就是說比較 器不須接收訊號振幅從VDD至地的執對執輸入訊號，軌對軌比 較器同時需要NMOS輸入級以及PMOS輸入級來處理執對軌訊 號，所以執對軌比較器設計的複雜度會高於只使用NM〇S輸入 級或只使用PMOS輸入級的比較器。對比於習知技術全波式調 變因為三角波的正半週期與負半週期不匹配（mismatch)所造 成的失真’本設計對三角波的非線性失真較不敏感。 第5A圖與第5B圖進一步解釋了為何半波式脈衝寬度調變 技術可行’如第5A圖所示’在進行半波脈衝寬度調變時，每一 個脈衝寬度調變週期中運算放大器兩差動回授途徑只會有一個 是實際將輸出訊號回授至輸入端的，然而因為運算放大器採羞 動操作的關係，另一路徑會自動產生一反向訊號，所以閉迴路 12 山4268 回授在此半波調變技術中仍可正常 器，上述半波脈衝寬度調變操作時放大 雖然上述_法狀理差域 上而不而做改{，另外，半波式脈衝ζ_變亦可 ==π需要回授元件，然而，採用_架Usually set to the common mode voltage of the differential signal pair. Although the amplitude of the half-wave modulation signal is smaller than the peak-to-peak amplitude of the differential signal, the amplitude of the modulation signal is set to half of the power supply voltage interval and VCM is set as the integral. The common mode voltage of the device will have better performance, especially as in this embodiment, the modulation signal VSAW is set to a triangular wave 'and its oscillation range is (a) between Vcm and (VCM+VSW), where VCM For the common mode voltage, vsw is the triangular wave amplitude ' or (b) is between VCM and (VCM-Vsw). As mentioned before, although the common mode voltage can be any value, if the supply voltage range is from 0V to VDD, the designer will choose VDD/2 as the common mode voltage to obtain the maximum signal dynamic interval. In this embodiment, VCM is set to VDD/2, the triangular wave amplitude Vsw is between VDD/2 to VDD or VDD/2 to 0V. The principle of the modulation method of the present invention is shown in Fig. 4A and Fig. 4B 8 1334268. In addition, it is assumed that the same triangular wave frequency is used. 'Traditional full-wave-type technology—every--------------------------------------------------------------- The 峨 conversion will only produce one pulse. In other words, when the pulse width modulation is performed, the _ fresh-reduction is reduced by half, so the power loss due to the susceptibility loss is reduced. Please refer to FIG. 3 for the output of the first half bridge 12〇a and the second half bridge 120b of the full bridge output circuit 12〇 to a load component (for example, supervisor 82) to provide an amplified binary code. Pulse width modulation output signal, as described above, this method removes the ternary code drive logic module required in the prior art to reduce circuit complexity, and in the half wave modulation technique, because of the triangular wave voltage The amplitude is only between VDD to VCM or VCM to ground (ie, the amplitude is vdd/2), and the comparators 116a and 116b do not require a rail-to-rail (raii-t0-rail) input stage, that is, the comparator does not need to The input signal amplitude is from VDD to ground. The rail-to-rail comparator requires both the NMOS input stage and the PMOS input stage to process the rail-to-rail signal. Therefore, the complexity of the rail-to-rail comparator design is higher than that. NM〇S input stage or comparator using only PMOS input stage. Compared to the conventional technique, full-wave modulation is caused by the mismatch caused by the mismatch between the positive half cycle and the negative half cycle of the triangular wave. This design is less sensitive to the nonlinear distortion of the triangular wave. 5A and 5B further explain why the half-wave pulse width modulation technique is feasible 'as shown in Fig. 5A'. When performing half-wave pulse width modulation, the operational amplifier has two differences in each pulse width modulation period. Only one of the feedback channels will actually return the output signal to the input. However, because the op amp is in a shy operation, another path will automatically generate a reverse signal, so the closed loop 12 In the half-wave modulation technique, the normal operation can still be performed, and the above-mentioned half-wave pulse width modulation operation is enlarged, although the above-mentioned _normality difference domain is not changed, and the half-wave type pulse ζ _ can also be changed. =π needs to feedback the component, however, using _ frame
告變輯，但也可峨料波錢或半波鑛 =變訊號°另―點，利用—數位類比轉換器 m 放大器獅卩可應財數⑽人訊號上， 類音職大器。在魏朗上，D齡源放大器被使 ，器以及音響等3C產品上，除了音源放大=提 及之D類放大器獨態樣_換方式亦可應祕冷卻器 路或馬達控制電路等領域。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定 ^發明，任何熟f此技藝者’在不脫離本發明之精神和範圍内， =可作些許之更動朗飾，·本發明之鑛細#視後 申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖為為一類比輸入訊號與其三元脈衝寬度調變訊號之示意 圖。 第2圖為習知技術中採用三元脈衝寬度調變編碼之類比輸入式 1334268 D類放大器的電路圖。 第3圖為本發明一實施例利用半波式脈衝寬度調變之類比輸入 式D類音源放大器的電路圖。 第4圖為本發明調變方法與習知調變方法之比較圖。 第5圖為差動式運算放大器單端輸入時之電路圖及其小訊號模 型。 第6圖為三角波產生器之電路圖。Report the change, but you can also pick up the wave or half-wave mine = change signal ° another point, use - digital analog converter m amplifier gryphon can count the number of (10) people signal, class sounds. In Weilang, the D-age source amplifier is used in 3C products such as amps, amplifiers and stereos, except for the amplification of the source = the type D amplifier that is mentioned in the __ mode can also be used in the field of cooler circuit or motor control circuit. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and the skilled artisan can make a few more modifications without departing from the spirit and scope of the invention. The invention of the fines # is subject to the definition of the patent application scope. [Simple description of the diagram] Figure 1 is a schematic diagram of an analog input signal and its ternary pulse width modulation signal. Figure 2 is a circuit diagram of an analog input type 1334268 Class D amplifier using ternary pulse width modulation coding in the prior art. Fig. 3 is a circuit diagram showing an analog input type D source amplifier using a half-wave type pulse width modulation according to an embodiment of the present invention. Figure 4 is a comparison diagram of the modulation method of the present invention and the conventional modulation method. Figure 5 shows the circuit diagram and its small signal model for a single-ended input of a differential op amp. Figure 6 is a circuit diagram of a triangular wave generator.
【主要元件符號說明】 10、100放大器 14、114運算放大器 18驅動邏輯模組 22、122 制 〇八 200三角波產生器 12a、12b、102增益放大器 16a、16b、116a、116b 比較器 20、120全橋式輸出電路 120a、120b半橋電路 202高/低電壓準位限定模組 十、申請專利範園： 1. 一種產生脈衝寬度調變的裝置，其包含有： 一第一與一第二比較器，分別用來將一對差動訊號 (differential signal)與一半波（half-swing )調變訊號做比較 以產生一第一與一第二脈衝寬度調變（PWM)控制訊號，其 中該半波調變訊號之電壓振幅小於該對差動訊號之電壓振 幅；以及 一輸出級，其包含有一對輸入端耦合至該第一與該第二脈 衝寬度調變控制訊號以提供對應於該第一與該第二脈衝寬度 14[Description of main component symbols] 10. 100 amplifiers 14, 114 operational amplifiers 18 drive logic modules 22, 122 〇 eight 200 triangular wave generators 12a, 12b, 102 gain amplifiers 16a, 16b, 116a, 116b comparators 20, 120 Bridge output circuit 120a, 120b half bridge circuit 202 high / low voltage level limit module ten, application for patent garden: 1. A device for generating pulse width modulation, comprising: a first and a second comparison And respectively for comparing a pair of differential signals with a half-swing modulation signal to generate a first and a second pulse width modulation (PWM) control signal, wherein the half The voltage amplitude of the wave modulation signal is less than the voltage amplitude of the pair of differential signals; and an output stage including a pair of inputs coupled to the first and second pulse width modulation control signals to provide corresponding to the first With the second pulse width 14