JP2906564B2 - PWM amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a PWM (Pulse Pulse) used for an audio output circuit or the like.
The present invention relates to a Width Modulation (pulse width modulation) amplifier, and more particularly to a PWM amplifier with reduced power loss.

[Conventional technology]

FIG. 8 is a block diagram showing a conventional PWM amplifier disclosed in, for example, Japanese Patent Application Laid-Open No. 54-13345.
(1) a music signal source input to the PWM amplifier, (2) a carrier generator, (3) a voltage comparator using the output of the music signal source (1) and the carrier generator (2) as an input signal,
Reference numeral (4) denotes a power MOS / FET drive circuit using the output of the voltage comparator (3) as an input signal, and is composed of an npn transistor, a pnp transistor, a resistor, and the like. (5) and (6) are power MOS FETs acting as switching controlled by the output of the drive circuit (4), and (7) is a power MOS
-A low-pass filter commonly connected to the drains of the FETs (5) and (6), (8) is a speaker serving as a load of a PWM amplifier connected between the low-pass filter (7) and the ground, and (9) is a power MOS. A first DC voltage source connected to the source of the FET (5) and the driving circuit (4), and (10) a second DC voltage source connected to the source of the power MOS FET (6) and the driving circuit (4). DC voltage source.

Operation of Figure 8 may compare the magnitude of the voltage of the carrier signal e _c generated by the music signal as shown in the operation waveforms of FIG. 9 e _i and a carrier generator (2) by a voltage comparator (3) , the voltage comparator (3) PWM wave e _s (i.e., control signal) that is proportional to the level of the music signal e _i to the output of give, power MOS via the PWM wave e _s a driving circuit (4)・ FETs (5) and (6)
Control the DC voltage by turning
Power amplify waves. Here, the PWM wave e ′ _s amplifies the power of the PWM wave. Here PWM wave e _'s are obtained by power-amplifying the PWM wave e _s, the PWM wave e' _s are can show the sum of an integral multiple of the components and their sideband components of the music signal component and the carrier frequency. Therefore, removing the carrier by a low-pass filter (7), passed through only the music signal components, to obtain a similar output e _o and music signal e _i that is input to the voltage comparator (3), a music signal by the speaker (8) Reproduce.

In the above-described PWM amplifier, in order to suppress power loss and obtain high power efficiency, it is desired that the ON resistance of the output switch element is small and the drive thereof is easy to drive. Conventionally, power MOSFETs are often used as this switch element, but as is well known, in power MOSFETs (especially those with a relatively low withstand voltage used in PWM amplifiers), the on-resistance is the resistance of the channel region. Therefore, a large number of micro FET elements are formed on a single chip and are connected in parallel, so that the on-resistance is reduced when the channel region is effectively increased. However, a low on-resistance element having a large channel region in this manner has a problem that the gate input capacitance is inevitably increased due to its structure, and the power for driving the gate input capacitance is increased.

Here, when R _ON in the on-resistance of the power MOS · FET (5) and (6) to be equal to each other, the power loss P _r indicated by the equation (1) by R _ON is generated.

However, R _L, as the resistance component P _OUT of the speaker (8) of Figure 8 is the output power P _r of a speaker (8) of Figure 8 seen from equation (1), proportional to the output power P _OUT Then it gets bigger.

On the other hand the power MOS · FET (5) and as a equal to each other gate input capacitance (6), if C _IN, the power loss P _c by charging and discharging of C _IN is can show in the (2) equation.

Where f _c is the carrier frequency of the carrier generator (2) in FIG. 8 V _gs is the amplitude of the gate-source voltage of the power MOS-FET From equation (2), P _c is the output regardless of the output power P _OUT Power loss occurs even when the power is OW. To reduce P _c , it is only necessary to reduce C _IN. However, as described above, a power MOS • FET having a small C _IN has a large on-resistance and a large power loss at a large output.

Here, a power MOS FET that opens and closes as a switch
(5) and (6) the power loss P _l that occurs in represented by _{P l = P r + P c} ... (3).

[Problems to be solved by the invention]

Since the conventional PWM amplifier is configured as described above, if the power loss at small output is reduced,
The power loss increases, and conversely, if the power loss is reduced and the efficiency is improved at the time of high output, there is a problem that the power loss at the time of low output increases.

That is, it has been difficult to reduce power loss and improve efficiency over the entire range from the small output region to the large output region.

The present invention has been made to solve the above problems, and has as its object to obtain a highly efficient PWM amplifier with small power loss regardless of the magnitude of output power.

[Means for solving the problem]

In the PWM amplifier according to the present invention, switching means using a power MOS-FET having a small gate input capacitance and switching means using a power MOS-FET having a small on-resistance are connected in parallel, and the output power is detected. , The switching means having the smaller power loss is selectively operated.

Also, when the output power is small, the switching means using the power MOS / FET with small gate input capacitance is operated,
As the output power increases, the power at which the gate input capacitance decreases
The switching means using a MOS-FET and the switching means using a power MOS-FET with a low on-resistance connected in parallel with the switching means are operated simultaneously.

[Action]

The output power of the PWM amplifier according to the present invention is small,
In the region where the power MOSFET gate input capacity charge / discharge power accounts for a large proportion of the power loss, the small input capacity power MOS ・ F
ET operates as an output switch to reduce the gate input capacitance charge / discharge power, and in the large output region where the loss ratio due to the ON resistance of the output switch element increases, a power MOS / FET with low ON resistance is used as the output stage switch. By operating it, increase in power loss is suppressed.

Power MOS ・ F with low on-resistance in large output area
By simultaneously operating the switching means using ET and the switching means using a power MOS / FET with a small gate input capacitance connected in parallel, the ON resistance is further reduced, and the power is further increased in the large output area. Loss is reduced.

(Example of the invention)

 An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, (1) is a music signal source input to a PWM amplifier, (2) is a carrier generator, and (3) is a voltage comparator using a music signal and an output of the carrier generator (2) as input signals. , (4) and (16) represent the output e of the voltage comparator (3).
Power MOS FET with _s (ie control signal) as input signal
The first and second drive circuits (11) detect the output power of the speaker and change the output voltage from "L" level to "H" level when the output power exceeds a certain set level. Detecting means; (12) first switching means which turns on when the output of the detecting means (11) is at "L" level and turns off when the output of the detecting means (11) is at "H"level; This is a second switching means that turns on when the output of 11) is at "H" level and turns off when the output is at "L" level. (14) is a P-channel power MOS ・ F with small gate input capacitance and large on-resistance
A first MOS-FET (14a) using an ET and a second MOS-FET (14b) using an n-channel power MOS-FET with a small gate input capacitance and a high on-resistance are connected in series. When the first switching means (12) is on, the control signal e _s is input via the first drive circuit (4). (15) uses a third MOS-FET (15a) using a P-channel power MOS-FET with a small on-resistance and a large gate input capacitance and an n-channel power MOS-FET with a small on-resistance and a large gate input capacitance. A second switching means configured by connecting a fourth MOS-FET (15b) in series, wherein the second switching means (13) is turned on via a second driving circuit (16) when the second switching means (13) is on; hand,
The control signal e _s is input.

Also, (7) shows the drain of the first MOSFET (14a), the drain of the second MOSFET (14b), and the third MOSFET (1).
A low-pass filter whose input terminal is connected to a common connection point between the drain of 5a) and the drain of the fourth MOS-FET (15b), and (8) a PWM connected between this low-pass filter (7) and the ground. This is a speaker that acts as a load on the amplifier.
Further, (9) shows a first MOS-FET (14a) and a third MOS-FET (14a).
A first DC voltage source connected to the source of the FET (15a),
(10) is the second MOSFET (14b) and the fourth MOSFET (15
A second DC voltage source whose negative side is connected to the source of b).

In the above configuration, the output power P _OUT of the speaker (8)
Is smaller than the predetermined level set by the detecting means (11), the output of the detecting means (11) becomes "L" level,
The first switching means (12) is turned on, and the control signal e _s is input to the first switching means (14) via the first drive circuit (4). The first input means has a small input gate capacitance and a large on-resistance. MOS FET (14a) and the second MOS FET (14
b) is driven. At this time, the second switching means (13)
Is off and the second switching means (15) is
The control signal e _s is not input via the drive circuit (16).
That is, when the output power P _OUT is small, the input gate capacitance is small and the power MOSFET (14a) (14a) (14
b) works as a switching element. Next, when the output power P _OUT of the speaker (8) increases and exceeds a predetermined set level, the output of the detecting means (11) becomes “H” level, and the first switching means (12) is turned off. The control signal is not input to the first switching means via the first drive circuit (4). On the other hand, the second switching means (13) is turned on, a control signal e _s is input to the second switching means (15) via the second drive circuit (16), and the second switching means (15) And the third MOS-FET (15a) and the fourth MOS-FET (15b) having a small on-resistance and a large gate input capacitance function as switching elements.

FIG. 2 is a diagram showing an example of a specific circuit configuration for realizing the detecting means (11) in FIG. This operation will be described briefly. The input terminal A is input voltage across the speaker (8), the reference voltage V _S which corresponds to the output power is set to a predetermined value of this rectified to direct current was voltage V _D and the speaker (8) comparing the door, V _D is the output of the "L" level if less than V _S, if V _D is larger than V _S is "H" level is output to the output terminal B.

FIG. 3 is a diagram showing an example of a specific circuit configuration for realizing the first switching means (12) and the second switching means (13). The outline of this operation will be described.

When the output of the detection means (11) is at the "L" level (-VCC), the transistor (30a) is turned on, so that the gate voltage of the MOSFET (30b) becomes "H" level and the MOSFET (30b) Turn on. Therefore, the gate voltages of the MOSFETs (13a) and (13b) connected to the drain of the MOSFET (30b) become "L" level, and the MOSFETs (13a) and (13b) are turned off. . That is, the second switching means (13) is turned off.

On the other hand, when the output of the detection means (11) is at the "L" level, the transistor (30c) is in the off state, so that the MOS-FET (3
0d) is at the “L” level, and the MOS FET (30
d) is off. Therefore, the gate voltages of the MOSFETs (12a) and (12b) connected to the drain of the MOSFET (30d) are at the “H” level, and the MOSFETs (12a) and (12b) are turned on. ing. That is, the first switching means (12) is on. Therefore, the output of the detection means (11) is "L".
At the time of the level, a control signal is input to the first switching means (14) via the first drive circuit (4).

The output of the detection means (11) is at "H" level (+ VCC)
, The transistor (30a) is turned off.
The gate voltage of OS • FET (30b) becomes “L” level and MOS
・ FET (30b) turns off. Therefore, MOS ・ FET （30b）
The gate voltage of the MOSFETs (13a) and (13b) connected to the drain of the MOS FETs (13a) and (13b) becomes “H” level,
b) is turned on. That is, the second switching means (13)
Is turned on, and the second driving circuit (16)
The control signal is input to the switching means (15).

On the other hand, when the output of the detection means (11) is at the "H" level, the transistor (30c) is in the ON state, and thus the MOS-FET (3
0d) is at the “H” level, and the MOS FET (30
d) is in the ON state. Therefore, the gate voltages of the MOSFETs (12a) and (12b) connected to the drain of the MOSFET (30d) are at the "L" level, and the MOSFETs (12a) and (12b) are off. . That is, the first switching means is off.

As described above, the switching means (12) and (13)
One of the switching means (14) and (15) can be selectively operated in accordance with the output "L" or "H" of the detection means (11).

The diodes (12c), (12d), (13c) and (13d) constituting the switching means (12) and (13) are MOS-F
It shows what the ET has structurally and what is intentionally provided inside the element to prevent destruction. The directions of the diodes (12c), (12d), (13c), and (13d) are n-channel MOS FETs (12a), (12b), (13
When a) and (13b) are off, the power MOS FET (14
a), (14b), (15a), and (15b) are determined so that they do not turn on. For example, when the first drive circuit (4) is at "L" level, the diode (12c) is in an open state because it is reverse biased. When the first drive circuit (4) is at "H" level, the diode (12c) is forward biased.
The channel MOS FET (14a) is in the off state because the gate is at the "H" level. When the n-channel MOS-FET (12a) is off, the MOS-FET (14a) only needs to be in the off state at all times, and operates properly even with the diode (12c). On the other hand, when the diode (12c) is in the reverse direction, the diode (12c) becomes forward biased when the first drive circuit (4) is at the "L" level. For this reason, P-channel MOSFETs (12
Even when a) is off, the first drive circuit (4) is connected to the gate of the MOS-FET (14a) through the diode (12c),
The P-channel MOS FET (14a) is turned on, and the n-channel MOS FET (12a) does not have a function as a switch. Therefore, the diodes (12c), (12
d), (13c) and (13d) are connected in parallel with the n-channel MOS FETs (12a), (12b), (13a) and (13b) in the direction shown in FIG.

FIG. 4 is an explanatory diagram showing the output versus loss characteristics of the PWM amplifier. The loss of the PWM amplifier is almost irrelevant to the output represented by the power loss _Pc due to charging and discharging of the input capacitance of the gate when driving the power MOSFET, and the power MOSFET
Loss that is almost proportional to the output, such as the loss due to the on-resistance of
Because it is composed of a P _r, losses in the conventional PWM amplifier a characteristic as shown in approximately 4 (100) or (101). (100) is the characteristic when using a power MOSFET with low on-resistance and large gate input capacitance, (10
1) Power M with small gate input capacitance and large on-resistance
This is the characteristic when OS / FET is used.

In the PWM amplifier according to the present invention, the characteristic curve (10
1) Power M with small gate input capacitance and large on-resistance
First MOS-FET (14a) and second MO using OS-FET
This is equivalent to operating the S • FET (14b), and the characteristic curve (1
00) is a power with small on-resistance and large gate input capacitance
Third MOS-FET (15a) using MOS-FET and fourth M
This is equivalent to operating the OS FET (15b).

Here, the output power of two characteristic curves (100) (101) intersects a P _x, when the output of the detection means (11) of P _OUT ≦ P _x when the "L" level P _OUT> P _x It is possible to set the detection means (11) so as to be at the "H" level, whereby the power loss of the PWM amplifier of the present invention becomes the shaded portion in FIG.

As described above, according to the present invention, it is apparent that the power loss is reduced as compared with the conventional PWM amplifier, and a highly efficient PWM amplifier is obtained.

FIG. 5 shows another embodiment of the present invention. This eliminates the first switching means as shown in the figure, and always controls the control signal e _s via the first drive circuit (4) regardless of the output of the detection means (11). By inputting to (14), in a region where the output power is large, the power loss can be further reduced as compared with the embodiment shown in FIG.

The operation of the embodiment shown in FIG. 5 will be described. Now, when the output power is small and the output of the detection means (11) is at "L" level, the second switching means (13) is off and the control signal e _s
Is not inputted to the second switching means (15), and therefore, the first switching means composed of a power MOS-FET having a small input capacitance is used.
Only the switching means (14) operates. Next, when the output power increases and the input signal to the detection means (11) corresponding to the magnitude of the output power exceeds a predetermined set level,
The output of the detection means (11) becomes "H" level, the second switching means (13) is turned on, and the power MO having a small on-resistance is turned on.
The second switching means (15) composed of an S-FET also performs a switching operation. That is, in the region where the output power is large, the power MOSFETs (15a) and (14a) and the power MOSFET
Since the ETs (15b) and (14b) are connected in parallel and operate, the on-resistance is further reduced than when the power MOS FETs (15a) and (15b) are operating, and therefore the power Losses are also reduced.

FIG. 6 is an explanatory diagram showing the output versus loss characteristics of the PWM amplifier shown in FIG.

In the figure, the characteristic curve (101) shows the power MOSFETs (14a) and (14b) with small gate input capacitance and large on-resistance.
Operating the first switching means (14), which is composed of a power MO having a small on-resistance and a large gate input capacitance.
This is a characteristic when the second switching means (15) constituted by the S-FETs (15a) and (15b) is not operated.

A characteristic curve (102) is a characteristic when the first switching means (14) and the second switching (15) are simultaneously operated.

The characteristic curve (100) shows the characteristic when only the second switching means is operated for reference.

Here, the output power at which the two characteristic curves (101) and (102) intersect is P _Y, and the output of the detection means is “L” when P _OUT ≦ P _Y and “H” when P _OUT > P _Y It is possible to set the detection means (11) so as to be at a level, whereby the power loss of the PWM amplifier shown in FIG. 5 becomes the shaded portion in FIG.

As apparent from FIG. 6, as compared with the examples of the invention shown in Figure 1, (a region shown in DerutaABC) region slightly power loss increases in the vicinity of the output power P _Y, but which high power In the region, power loss is reduced.

FIG. 7 is a view showing still another embodiment of the present invention, in which the first switching means and the second switching means are provided.
An example is shown in the case of a configuration including a MOS-FET and a resistor.
In the figure, (40) is the first switching means, and (50) is the second switching means.
Switching means. This means that the first drive circuit (4) and the second drive circuit (16), to which the control signal e _s is input, are selectively operated in accordance with the magnitude of the output power. Power MO with small input capacitance and low on-resistance
A control signal is input to the first switching means (14) composed of an S-FET, and as the output power increases, the second switching element composed of a power MOS-FET having a small on-resistance and a large input capacitance.
The control signal is input to the switching (15) of the above.

The operation of FIG. 7 will be described. When the output of the detection means (11) is at the "L" level in a region where the output power is small, the first
N-channel MOS-FET constituting switching means (40)
(40a) is off, and the voltage across the resistors (40b) and (40c) is almost 0V. Therefore, P-channel MOSFET
(40d) and n-channel MOSFET (40e) are turned off,
A voltage proportional to the control signal e _s is generated in the resistors (4a) and (4b) of the first drive circuit (4), the first drive circuit (4) operates, and the control signal e _s is transmitted to the first drive circuit (4). 1 switching means (1
4) to operate the first switching means (14).

On the other hand, when the output of the detection means (11) is at "L" level,
P-channel MOS • F constituting the second switching means (50)
The ET (50a) is on, and the voltage across the resistors (50b) and (50c) is almost equal to the DC power supply voltage VCC. Therefore P
Channel MOSFET (50d) and n-channel MOSFET (5
0e) is turned on, and the resistance (16) of the second drive circuit (16) is turned on.
Since the voltage between both ends of a) and (16b) becomes almost 0 V regardless of the input control signal e _s , the second switching means (15)
The P-channel power MOS-FET (15a) and the n-channel power MOS-FET (15b), which are included in the above, are off. That is, the second switching means (15) is not operating.

Further, when the output power increases and the input to the detection means (11) exceeds a predetermined set level and the output of the detection means (11) goes to the "H" level, the first and second switching means are switched. The operation is reversed, the first switching means (14) is turned off without _{receiving the} control signal e _s , and the second switching means (15) is operated with the control signal e _s input.

As is apparent from FIG. 7, the switching means in this PWM amplifier has a simpler circuit configuration than the switching means shown in FIG. 3, and stable operation is expected, so that it can be more easily applied to an actual PWM amplifier. Switching means can be realized.

In the embodiment shown in FIGS. 1, 5 and 7, the output power P _OUT is detected from the terminal of the speaker (8). However, the output power P _OUT is detected from a music signal source, a PWM modulation signal, or the like. You can also.

Also, the output power of the PEM amplifier can generally be changed by the volume, and it is almost determined by the volume setting.
The output power detection may be determined by estimating from the setting of the volume.

Further, in the above embodiment, the n-channel and the p-channel are used as the power MOS-FETs. However, since the resistance of the n-channel is generally smaller, the switching circuit may be constituted only by the n-channel power MOS-FET.

Also, to reduce the on-resistance, multiple power MOSFETs
ETs may be connected in parallel.

In the description so far, a low-on-resistance power MOS-FET element in which the drain and source electrodes are connected to each other and a low-input-capacity power MOS-FET element have been referred to as separate elements for the sake of convenience. Units FE that share electrodes and are configured on the same chip and have different numbers from each other
An apparently single element having two gate electrodes to which T is connected may be used.

In the detection means (11) shown in FIG. 2, the polarity of the four rectifier diodes is connected in reverse, and when the input to the detection means (11) is smaller than a predetermined level, the "H" level is set to a predetermined level. , The detection means for outputting the "L" level may be used to implement the PWM amplifier of the present invention.

〔The invention's effect〕

As described above, according to the present invention, when the output power is small, the first switching circuit using the power MOSFET having a small gate input capacitance is operated, and when the output power is large, the on-resistance is reduced. Since the configuration is such that the second switching circuit using the small power MOSFET is operated, there is an effect that a highly efficient PWM amplifier can be obtained regardless of the magnitude of the output power.

When the output power is small, the first switching circuit using the power MOSFET having a small gate input capacitance is operated, and when the output power is large, the first switching circuit is connected in parallel to the first switching circuit. A high-efficiency PWM that simplifies the circuit by simultaneously operating the second switching circuit using a power MOSFET with low on-resistance, and can further reduce power loss in a large output power area. An amplifier is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PWM amplifier according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a concrete circuit of a detecting means in FIG. 1, and FIG. 3 is a concrete example of a switching means in FIG. FIG. 4 is a diagram showing an example of a dynamic circuit, FIG. 4 is a diagram showing output power versus power loss in the output stage of the PWM amplifier according to the embodiment of FIG. 1, and FIG. 5 is a diagram showing another embodiment of the present invention. Block diagram of a PWM amplifier in which the first switching means is removed and a control signal is directly input to the first switching means via a drive circuit. FIG. 6 is based on the embodiment of FIG.
FIG. 7 shows output power versus power loss at the output stage of a PWM amplifier. FIG. 7 shows still another embodiment of the present invention, and is a diagram showing a specific circuit of a simplified and easy-to-realize switching means. FIG. 1 is a block diagram of a conventional PWM amplifier, and FIG. 9 is a waveform diagram for explaining the operation of FIG. In the figure, (1) is a music signal source, (4) is a first drive circuit, (7) is a low-pass filter, (8) is a speaker as a load, (9) and (10) are DC voltage sources, ( 11) is detection means, (12) is first switching means, (13) is second switching means, (14) is first switching means, (14a)
Is the first MOSFET, (14b) is the second MOSFET, (15)
Is the second switching means, (15a) is the third MOS-FE
T, (15b) is a fourth MOSFET, and (16) is a second drive circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. A PWM (P / P) configured to control switching of a DC voltage by a control signal obtained by pulse-modulating an input signal to be amplified and to obtain a demodulated output through a low-pass filter.
In an amplifier (ulse Width Modulation), a. A signal corresponding to the magnitude of the demodulated output is input, and a detecting means for detecting the level of the signal. b. First switching means configured by connecting a first MOS-FET and a second MOS-FET in series and controlling switching of a DC voltage by a control signal, a third MOS-FET and a fourth MOS
A second switching means for switching the DC voltage by a control signal, wherein the first and second MOSFETs are connected to the third and fourth MOSFETs. A switching means in which the gate input capacitance is smaller and the third and fourth MOS-FETs have a smaller on-resistance than the first and second MOS-FETs; c. The switching means is selected such that a control signal is input to the first switching means when the input signal is smaller than a predetermined level, and a control signal is input to the second switching means when the input to the detection means is higher than the predetermined level. PWM amplifier provided with switching means for operating automatically. 2. The PWM amplifier according to claim 1, wherein the control signal is input to the first switching means regardless of the magnitude of the signal corresponding to the magnitude of the demodulation output.