JP2006165405A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that decreases the influence of parasitic resistance generated in a semiconductor film itself that becomes an electrode, while employing a semiconductor device manufacturing method that easily fits a process requiring bipolar transistors and forms neither a semiconductor substrate nor a contact portion, i.e., prevents the parasitic capacitance. <P>SOLUTION: This semiconductor device has a structure where a semiconductor film working as a lower extraction electrode is provided with an opening, a capacitance film is created at the bottom of the opening window and sidewall, and a contact consisting of the capacitance film and silicide layer 126 is adjoined. In this way, it is possible not only to reduce the influence of parasitic resistance of the semiconductor film that becomes the lower extraction electrode but also to obtain a capacitance device that suppresses the parasitic resistance for the semiconductor substrate because neither the semiconductor substrate nor contact portion is formed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a capacitive element and a bipolar transistor and a method for manufacturing the semiconductor device.

In recent years, the miniaturization of semiconductors has progressed, and low parasitic resistance and low parasitic capacitance have been demanded for capacitive elements mounted on LSIs.
As means for satisfying such a requirement, a dielectric film is formed on the polycrystalline silicon film and a polycrystalline silicon film is further disposed on the dielectric film as shown in the schematic structural diagram of the conventional capacitive element in FIG. There are many proposals for forming a capacitive element having a structure (see, for example, Patent Document 1).

In addition, as mobile communication devices become more sophisticated and smaller in size, LSIs in the high frequency field require capacitive transistors that can be integrated with bipolar transistors that can operate at high speed.
JP-A-5-299578

  However, in the above-described conventional capacitive element, the lower electrode is formed of the first polycrystalline silicon film 4 and the upper electrode is formed with the second polycrystalline silicon film 6 flat. Therefore, the resistance of the first polycrystalline silicon film 4 and the second polycrystalline silicon film 6 itself is generated as a parasitic resistance. Further, since the second electrode film 9 has a structure in which a contact is made directly to the P-type diffusion layer without forming a silicide layer for reducing the resistance in the semiconductor substrate 1, contact resistance is added, and further, the parasitic resistance of the semiconductor substrate 1 is increased. There was a problem that resistance and parasitic capacitance were added.

  The present invention solves the above-described problems, and the influence of parasitic resistance generated in the semiconductor film itself serving as an electrode while using a method of manufacturing a semiconductor device that can be easily adapted to a process that requires a bipolar transistor. It is an object of the present invention to provide a semiconductor device in which a contact portion is not formed with a semiconductor substrate, that is, parasitic capacitance is suppressed.

  In order to achieve the above object, a semiconductor device according to claim 1 of the present invention is a semiconductor device in which a capacitive element and a bipolar transistor coexist, and the capacitive element is formed around an element formation region of a semiconductor substrate. A separated insulating layer, a semiconductor layer formed on the semiconductor substrate, and a capacitive element formed over the semiconductor layer and the insulator layer leaving an opening window on the center of the semiconductor layer A lead electrode, an insulating film formed on the lead electrode of the capacitive element along the periphery of the opening window, a capacitive film formed on the bottom and side walls of the open window, and the capacitive film through the capacitive film A sidewall formed on a sidewall of the opening window; a semiconductor film formed on the sidewall, the capacitor film, and the insulating film; and a silicide layer formed on a surface of the extraction electrode of the capacitor element. , Wherein the capacitive film and the silicide layer is closer.

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, wherein the width of the opening window is larger than twice the film thickness of the sidewall.
The semiconductor device according to claim 3 is a semiconductor device in which a capacitive element and a bipolar transistor coexist, wherein the capacitive element is formed on an isolation insulator layer formed around an element formation region of the semiconductor substrate, and on the semiconductor substrate. A semiconductor layer formed on the semiconductor layer, a lead electrode of a capacitive element formed over the semiconductor layer and the insulator layer, leaving an opening window on a center of the semiconductor layer, and along a periphery of the opening window An insulating film formed on the extraction electrode of the capacitive element, a capacitive film formed on the bottom and side walls of the opening window, and a sidewall formed on the side wall of the opening window through the capacitive film, A semiconductor film formed on the sidewalls and the insulating film; and a silicide layer formed on a surface of the extraction electrode of the capacitive element, wherein the silicide layer and the capacitive film are close to each other. And it features.

According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the width of the opening window is smaller than twice the film thickness of the sidewall.
6. The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device has a capacitor element and a bipolar transistor, and a step of forming an isolation insulator layer around a semiconductor substrate to be a collector region and a capacitor element region. A step of forming a semiconductor layer to be a base region and a lower electrode on the semiconductor substrate, a step of forming a first capacitance film on the semiconductor layer, the first capacitance film, the semiconductor layer, and the A step of forming an external base and a lead electrode of the capacitive element across the isolation insulator layer; a step of forming an insulating film on the lead electrode of the capacitive element; and the insulating film on the center of the semiconductor layer; Etching an extraction electrode of the capacitive element to form an opening window that becomes an emitter region and a capacitive region; forming a second capacitive film in the opening window; and Forming a sidewall on the side wall of the opening window via the step, etching the first capacitor film and the second capacitor film in the emitter region, the semiconductor layer in the emitter region, and the capacitor Covering the first capacitor film in the region and forming a semiconductor film on the insulating film; forming an emitter layer on the semiconductor layer; a lead electrode of the capacitor element; and a surface of the semiconductor film Forming a silicide layer, and in the etching step of the first capacitor film and the second capacitor film, selective etching is performed using a resist mask.

  According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the fifth aspect, wherein the opening window of the capacitor region is wider than the opening window of the emitter region.

  8. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor device includes a capacitor element and a bipolar transistor, and a step of forming an isolation insulator layer around a semiconductor substrate to be a collector region and a capacitor element region. A step of forming a semiconductor layer to be a base region and a lower electrode on the semiconductor substrate, a step of forming a first capacitance film on the semiconductor layer, the first capacitance film, the semiconductor layer, and the A step of forming an external base and a lead electrode of the capacitive element across the isolation insulator layer; a step of forming an insulating film on the lead electrode of the capacitive element; and the insulating film on the center of the semiconductor layer; Etching an extraction electrode of the capacitive element to form an opening window that becomes an emitter region and a capacitive region; forming a second capacitive film in the opening window; and Forming a sidewall on the side wall of the opening window via the step, etching the first capacitor film and the second capacitor film in the emitter region, the semiconductor layer in the emitter region, and the capacitor Forming a semiconductor film on the insulating film, covering the first capacitor film and the second capacitor film in a region, forming an emitter layer on the semiconductor layer, and drawing out the capacitor element A step of forming a silicide layer on the surface of the electrode and the semiconductor film. In the etching process of the first capacitor film and the second capacitor film, the opening window of the capacitor region is filled with the sidewall. It is characterized by.

  The method for manufacturing a semiconductor device according to claim 8 is the method for manufacturing a semiconductor device according to claim 7, wherein the opening window of the capacitor region is smaller than the opening window of the emitter region.

  A method for manufacturing a semiconductor device according to claim 9 is the method for manufacturing a semiconductor device according to claim 5, claim 6, claim 7, or claim 8, wherein the lead electrode of the capacitor element, the side wall The semiconductor film is a polycrystalline silicon film.

  The method for manufacturing a semiconductor device according to claim 10 is the method for manufacturing a semiconductor device according to claim 5, claim 6, claim 7, or claim 8, wherein the semiconductor layer is an alloy of silicon and germanium or It is a mixed semiconductor layer of an alloy of silicon and germanium containing carbon.

  As described above, while using a method for manufacturing a semiconductor device that can be easily adapted to a process that requires a bipolar transistor, the influence of parasitic resistance generated in the semiconductor film itself that serves as an electrode is reduced, and the semiconductor substrate and the contact portion are reduced. Thus, a semiconductor device in which parasitic capacitance is suppressed can be provided.

  According to the semiconductor device of the present invention, the semiconductor film as the lower extraction electrode is opened, the capacitive film is formed on the bottom and the side wall of the opening window, and the contact portion composed of the capacitive film and the silicide layer is brought into proximity. In addition, the influence of the parasitic resistance of the semiconductor film itself serving as the lower lead electrode can be reduced, and since the contact portion is not formed with the semiconductor substrate, a capacitive element with reduced parasitic capacitance with respect to the semiconductor substrate can be obtained.

  In addition, according to the method for manufacturing a semiconductor device of the present invention, it is possible to form a capacitor element having an arbitrary opening width by adding a mask process for protecting the capacitor formation region, and a process that requires a bipolar transistor. While using a method of manufacturing a semiconductor device that can be easily adapted to the above, the influence of the parasitic resistance generated in the semiconductor film itself as an electrode is reduced, and the contact portion is not formed with the semiconductor substrate, that is, the parasitic capacitance is suppressed. A semiconductor device can be provided.

(Embodiment 1)
Embodiment 1 of the present invention will be described below with reference to the drawings. 1 to 15 are process cross-sectional views illustrating the manufacturing process of the semiconductor device according to the first embodiment. Note that the description of the resist film removal process is omitted in some places.

First, as shown in the process cross-sectional view showing the deep trench formation process of the semiconductor device in the first embodiment of FIG. 1, a silicon single crystal mainly having a (100) plane with a specific resistance of 10 to 15 Ω · cm is used. A resist film (not shown) is formed on the P-type semiconductor substrate 100, and an N-type buried layer 101 (As +) is formed on the P-type semiconductor substrate 100 with an acceleration energy of 30 keV and a dose of 1E15 / cm ² . 3E15 / cm ^{2 is} implanted and formed. After the heat treatment, an N-type epitaxial layer 102 is formed on the entire surface with a resistivity of 1.0 Ωcm and a thickness of about 0.5 μm. Next, a trench 103 deeper than this is formed on the side of the N-type buried layer 101 at a depth of about 3 μm, and thermal oxidation is performed to oxidize the surface of the deep trench 103. Further, for example, after depositing polycrystalline silicon, etch back is performed to fill the deep trench 103 with polycrystalline silicon.

Next, as shown in the process cross-sectional view showing the shallow trench forming process of the semiconductor device in the first embodiment of FIG. 2, a resist film 104 is formed, and the shallow trench 105 is formed by using the resist film 104 to form about 0.0. It is formed with a depth of 4 μm. Next, as shown in the process cross-sectional view showing the collector lead portion manufacturing process of the semiconductor device in the first embodiment in FIG. 3, a first silicon oxide film 106 is deposited on the entire surface, and then a chemical mechanical polishing method (CMP). The planarization is performed by, for example, filling all the shallow trenches 105 with the first silicon oxide film 106. Thereafter, an N-type impurity, for example, phosphorus ions (P +), for example, phosphorous ions (P +) with an acceleration energy of 60 keV and a dose of 1E15 / cm ^{2 to} 3E15 / cm ^{2 are} implanted into the contact portion of the collector metal electrode using a resist film (not shown) as a mask. An N-type collector lead portion 107 is formed.

  Next, as shown in the process cross-sectional view showing the base region forming process of the semiconductor device in the first embodiment of FIG. 4, a second silicon oxide film 108 is formed on the entire surface to a thickness of 40 to 50 nm, and then the first The polycrystalline silicon film 109 is deposited with a thickness of 90 to 100 nm. Thereafter, a resist film 110 is formed, and the silicon oxide film 108 and the first polycrystalline silicon film 109 are etched using the resist film 110 to define a base formation region of the capacitor element and the bipolar transistor.

Next, as shown in the process cross-sectional view showing the P-type silicon film forming process of the semiconductor device in the first embodiment in FIG. 5, after removing the resist film 110, the P-type epitaxial layer 111 is formed as a semiconductor layer by selective epitaxial growth. Are formed at a thickness of 80 to 100 nm and a boron concentration of 1E21 atoms / cm ^{3 to} 1E22 atoms / cm ³ . At this time, a P-type silicon film 112 is also formed on the first polycrystalline silicon film 109. In this way, when the P-type epitaxial layer 111 is selectively epitaxially grown, if the growth thickness of the P-type epitaxial layer 111 is increased, the selectivity is broken and the P-type silicon film 112 is also grown on the silicon oxide film by polycrystal growth. May cause particles. Therefore, it is desirable to form the first polycrystalline silicon film 109 as a seed layer for the P-type silicon film 112.

  Next, as shown in the process cross-sectional view showing the third silicon oxide film forming process of the semiconductor device in the first embodiment of FIG. 6, a third silicon oxide film 113 is formed on the entire surface with a thickness of about 15 nm. . Next, a resist film 114 is further formed thereon, and etching is performed using the resist film 114 to leave the third silicon oxide film 113 only in the central portion of the P-type epitaxial layer 111.

  Next, as shown in the process cross-sectional view showing the fourth silicon oxide film forming process of the semiconductor device in the first embodiment of FIG. 7, a P-type polycrystalline silicon film 115 is deposited on the entire surface with a thickness of about 200 nm. To do. Thereafter, a fourth silicon oxide film 116 serving as an insulating film is formed on the P-type polycrystalline silicon film 115 with a thickness of about 100 nm. Next, as shown in the process cross-sectional view showing the opening window forming process of the semiconductor device in the first embodiment of FIG. The silicon oxide film 116 is etched to form an opening window 118. As a result, the central portion of the third silicon oxide film 113 is exposed, and the P-type polycrystalline silicon film 115 is left over the P-type epitaxial layer 111 and the first silicon oxide film 106.

  Next, as shown in the process cross-sectional view showing the sidewall formation process of the semiconductor device in the first embodiment of FIG. 9, after removing the resist film 117, the fifth silicon oxide film 119 is formed to a thickness of about 15 nm. Deposits on the entire surface. As a result, a fifth silicon oxide film 119 is formed on the fourth silicon oxide film 116, on the side wall of the opening 118, and on the bottom of the opening 118 (in the drawing, the fifth silicon oxide film 119 formed on the side wall of the opening 118). 5 shows only the silicon oxide film 119). Thereafter, for example, an N-type polycrystalline silicon film is formed in the opening window 118 with a thickness of about 100 nm, and etched back to form the sidewall 120. Here, the width of the opening window 118 is formed to be larger than twice the film thickness of the N-type polycrystalline silicon film that forms the sidewall in advance. Further, it is desirable that the opening window 118 in the capacitor formation region be formed larger than the opening window 118 in the bipolar transistor formation region in order to obtain a large capacitance value. After that, as shown in the process cross-sectional view showing the electrode region forming step of the semiconductor device in the first embodiment of FIG. 10, a resist film 121 is formed and wet etching is performed so as to be surrounded by the sidewall 120 of the bipolar transistor forming region. A portion of the fifth silicon oxide film 119 and the third silicon oxide film 113 are etched. As a result, the central portion of the P-type epitaxial layer 111 is exposed.

Next, as shown in the process cross-sectional view showing the N-type electrode processing step of the semiconductor device in the first embodiment in FIG. 11, the N-type polycrystalline silicon film 122 which is a semiconductor film is made to have a phosphorus concentration of 3E20 atoms / cm ³ . It is formed at a concentration of 7E20 atoms / cm ³ , and heat treatment is performed, for example, at 900 ° C. for 10 seconds by a rapid heat treatment method. Thereby, in the bipolar transistor formation region, the N-type impurity in the N-type polycrystalline silicon film 122 is diffused into the P-type epitaxial layer 111, and the emitter layer 123 is formed. Next, a resist film 124 is formed, and using the resist film 124 as a mask, an N-type polycrystalline silicon film 122, a fifth silicon oxide film 119, and a fourth silicon oxide film formed outside the N-type electrode region. 116 is selectively etched to process an N-type electrode. Thereafter, the resist film 124 is removed.

  Next, a resist film 125 is formed as shown in the process cross-sectional view showing the collector region forming process of the semiconductor device in the first embodiment of FIG. 12, and a P-type polycrystalline silicon film 115, a P-type silicon film 112, and Three layers with the first polycrystalline silicon film 109 are simultaneously processed by dry etching. Next, the second silicon oxide film 108 is removed by wet etching.

  Next, as shown in the process cross-sectional view showing the sputtering process of the semiconductor device in the first embodiment in FIG. 13, for example, titanium is sputtered and the silicide layer 126 is formed by heat treatment. Next, as shown in the process cross-sectional view showing the contact window forming process of the semiconductor device in the first embodiment of FIG. 14, a sixth silicon oxide film 127 is formed as an interlayer insulating film, and chemical mechanical polishing (CMP) is performed. Etc.) is used to planarize the surface of the sixth silicon oxide film 127. Further, using the resist film (not shown) as a mask, a part of the sixth silicon oxide film 127 is etched to form a contact window. Finally, as shown in the process cross-sectional view showing the wiring forming process of the semiconductor device in the first embodiment of FIG. 15, for example, a titanium nitride adhesion layer 128 is formed by sputtering or the like as a metal wiring, and then the Al film Then, the Al film is etched using a resist film (not shown) as a mask to form an Al wiring 129, whereby the semiconductor device of the present invention is completed.

  The capacitance element shown in “capacitance” in FIG. 15 has a capacitance of about 1150 pF when the relative dielectric constant of the silicon oxide film is 3.9, for example, when the bottom area of the opening window 118 (see FIG. 8) is 1000 μm square. Can be formed. Although a silicon oxide film is used as the dielectric film, a dielectric film having a higher relative dielectric constant than a silicon oxide film such as a silicon nitride film may be used.

  As described above, according to the present embodiment, as shown in FIG. 15, unlike the conventional example, a process for adding a capacitor forming mask and a salicide technology are adopted, and in addition, a P-type that is a lead electrode is used. In the vicinity of the polycrystalline silicon film 115, a first silicon oxide film 106 as element isolation is formed. As a result, most of the upper surface of the P-type polycrystalline silicon film 115 serving as the capacitor extraction electrode is the silicide layer 126 with reduced resistance, and the capacitor film (the third silicon oxide film 113 and the fifth silicon oxide film). 119). For this reason, it is possible to reduce the parasitic resistance of the extraction electrode. At the same time, since the P-type polycrystalline silicon film 115 serving as a capacitor extraction electrode is formed on the first silicon oxide film 106 as element isolation, the parasitic capacitance between the silicon substrates can be reduced.

Further, as shown in the first embodiment, by adding a mask process for protecting the capacitor formation region, a capacitor element having an arbitrary opening width can be formed, and one mask is added to the bipolar transistor formation flow. The semiconductor device can be easily adapted to a process that requires a bipolar transistor simply by adding a semiconductor device, while reducing the influence of parasitic resistance generated in the semiconductor film itself as an electrode and using a semiconductor. It is possible to provide a semiconductor device in which a contact portion is not formed with the substrate, that is, parasitic capacitance is suppressed.
(Embodiment 2)
Embodiment 2 of the present invention will be described below with reference to the drawings. 16 to 29 are process cross-sectional views illustrating the manufacturing process of the semiconductor device according to the second embodiment. Note that a description of the resist film removal step is omitted.

First, as shown in the process cross-sectional view showing the deep trench formation process of the semiconductor device in the second embodiment of FIG. 16, the silicon nitride is formed from a silicon single crystal whose principal surface is a (100) plane having a specific resistance of 10 to 15 Ω · cm, for example. A resist film (not shown) is formed on the P-type semiconductor substrate 200, and an N-type buried layer 201 (As +) is formed on the P-type semiconductor substrate 200 with an acceleration energy of 30 keV and a dose of 1E15 / cm ² . 3E15 / cm ^{2 is} implanted and formed. After the heat treatment, an N-type epitaxial layer 202 is formed on the entire surface with a resistivity of 1.0 Ωcm and a thickness of about 0.5 μm. Next, a trench 203 deeper than this is formed on the side of the N-type buried layer 201 at a depth of about 3 μm, and then the surface of the deep trench 203 is oxidized by thermal oxidation. Further, for example, after depositing polycrystalline silicon, etch back is performed to fill the deep trench 203 with polycrystalline silicon.

Next, as shown in the process cross-sectional view showing the shallow trench forming process of the semiconductor device in the second embodiment in FIG. 17, a resist film 204 is formed, and the shallow trench 205 is formed to a depth of about 0.4 μm using this. It will be formed. Next, as shown in the process cross-sectional view showing the collector lead portion manufacturing process of the semiconductor device in the second embodiment in FIG. 18, a first silicon oxide film 206 is deposited on the entire surface, and then chemical mechanical polishing (CMP). Etc., and all shallow trenches 205 are filled with the first silicon oxide film 206. Thereafter, the resist film in the contact portions of the collector metal electrode (not shown) of the N-type impurity such as a mask, phosphorus ions (P +) of an acceleration energy of 60keV dose of 1E15 atoms ^/ cm 2 ～3E15 pieces / cm ² injected into the N-type The collector lead-out portion 207 is formed.

  Next, as shown in the process cross-sectional view showing the base region forming step of the semiconductor device in the second embodiment in FIG. 19, the second silicon oxide film 208 is formed on the entire surface to a thickness of 40 to 50 nm, and then the first The polycrystalline silicon film 209 is deposited with a thickness of 90 to 100 nm. Thereafter, a resist film 210 is formed, and the silicon oxide film 208 and the first polycrystalline silicon film 209 are etched using the resist film 210, thereby defining the capacitor and bipolar transistor base formation regions.

Next, as shown in the process cross-sectional view showing the P-type silicon film forming step of the semiconductor device in the second embodiment in FIG. 20, the P-type epitaxial layer 211 is formed as a semiconductor layer by selective epitaxial growth to a thickness of 80 to 100 nm. A boron concentration is 1E21 atoms / cm ^{3 to} 1E22 atoms / cm ³ . At this time, a P-type silicon film 212 is also formed on the first polycrystalline silicon film 209. As described above, when the P-type epitaxial layer 211 is selectively epitaxially grown, if the growth thickness of the P-type epitaxial layer 211 is increased, the selectivity is broken and the P-type silicon film 212 is also grown on the silicon oxide film by the polycrystalline growth. May cause particles. Therefore, it is desirable to form the first polycrystalline silicon film 209 as a seed layer for the P-type silicon film 212.

  Next, as shown in the process cross-sectional view showing the third silicon oxide film forming process of the semiconductor device in the second embodiment in FIG. 21, a third silicon oxide film 213 is formed with a thickness of about 15 nm. Next, a resist film 214 is formed and etched using this to leave the third silicon oxide film 213 only in the central portion of the P-type epitaxial layer 211.

  Next, as shown in the process cross-sectional view showing the fourth silicon oxide film forming process of the semiconductor device in the second embodiment in FIG. 22, a P-type polycrystalline silicon film 215 is deposited on the entire surface with a thickness of about 200 nm. To do. Thereafter, a fourth silicon oxide film 216 serving as an insulating film is formed on the P-type polycrystalline silicon film 215 with a thickness of about 100 nm. Next, as shown in the process cross-sectional view showing the opening window forming process of the semiconductor device in the second embodiment in FIG. 23, a resist film 217 is formed, and this is used to form the P-type polycrystalline silicon film 215 and the fourth. The silicon oxide film 216 is etched to form an opening window 218. As a result, the central portion of the third silicon oxide film 213 is exposed, and the P-type polycrystalline silicon film 215 is left over the P-type epitaxial layer 211 and the first silicon oxide film 206.

  Next, a fifth silicon oxide film 219 is deposited on the entire surface to a thickness of about 15 nm, as shown in the process cross-sectional view showing the sidewall formation process of the semiconductor device in the second embodiment in FIG. As a result, a fifth silicon oxide film 219 is formed on the fourth silicon oxide film 216 and on the side wall of the opening 218 and the bottom of the opening 218 (in the drawing, the fifth silicon oxide film 219 formed on the side wall of the opening 218 is formed. 5 shows only the silicon oxide film 219). For example, an N-type polycrystalline silicon film having a thickness of about 100 nm is formed and etched back to form sidewalls 220. At this time, the width of the opening window 218 in the element formation region is smaller than twice the thickness of the N-type polycrystalline silicon film forming the sidewall. Thus, the sidewalls 220 on both sides are formed in contact with each other in the capacitor element formation region. Therefore, the width of the opening window 218 in the element formation region is smaller than that of the opening window 218 in the bipolar transistor formation region. Thereafter, wet etching is performed to etch the fifth silicon oxide film 219 and the third silicon oxide film 213 in the portion surrounded by the sidewall 220 in the bipolar transistor formation region. As a result, the central portion of the P-type epitaxial layer 211 in the bipolar transistor formation region is exposed.

Next, as shown in the process cross-sectional view showing the electrode region forming process of the semiconductor device in the second embodiment in FIG. 25, the N-type polycrystalline silicon film 221 which is a semiconductor film is formed with a phosphorus concentration of 3E20 atoms / cm ^{3 to} 7E20 atoms / The film is formed at a concentration of cm ³ , and heat treatment is performed by a rapid heat treatment method, for example, at 900 ° C. for 10 seconds. As a result, the N-type impurity in the N-type polycrystalline silicon film 221 diffuses into the P-type epitaxial layer 211 in the bipolar transistor formation region, and the emitter layer 222 is formed. Next, a resist film 223 is formed, and using the resist film 223 as a mask, an N-type polycrystalline silicon film 221, a fifth silicon oxide film 219, and a fourth silicon oxide film formed outside the N-type electrode region 216 is selectively etched to process an N-type electrode.

  Next, as shown in the process cross-sectional view showing the silicon film removal process of the semiconductor device in the second embodiment in FIG. 26, a resist film 224 is formed, and a P-type polycrystalline silicon film 215 and a P-type silicon film 212 are formed. And the first polycrystalline silicon film 209 are simultaneously processed by dry etching. Next, the second silicon oxide film 208 is removed by wet etching.

  Next, as shown in the process cross-sectional view showing the sputtering process of the semiconductor device in the second embodiment in FIG. 27, for example, titanium is sputtered, and the silicide layer 225 is formed by heat treatment. Next, as shown in the process cross-sectional view showing the contact window process of the semiconductor device in the second embodiment in FIG. 28, a sixth silicon oxide film 226 is formed as an interlayer insulating film, and chemical mechanical polishing (CMP) is performed. Etc. is used to planarize the surface of the sixth silicon oxide film 226. Further, a part of the sixth silicon oxide film 226 is etched using a resist film (not shown) as a mask to form a contact window. Finally, as shown in the process cross-sectional view showing the wiring formation process of the semiconductor device in the second embodiment in FIG. 29, for example, a titanium nitride adhesion layer 227 is formed as a metal wiring by sputtering or the like, and then the Al film Then, the Al film is etched using a resist film (not shown) as a mask to form an Al wiring 228, whereby the semiconductor device of the present invention is completed. 29, for example, when the bottom area of the opening window 218 is 1000 μm × 0.2 μm, a capacitance of about 1 pF can be formed if the relative dielectric constant of the silicon oxide film is 3.9. A desired capacitance value can be obtained by arranging the capacitive elements side by side.

  As described above, according to the present embodiment, as shown in FIG. 29, unlike the conventional example, a self-aligned formation method and a salicide technique are employed, and in addition, a P-type multi-electrode that is a lead electrode is used. A first silicon oxide film 206 as element isolation is formed in the vicinity under the crystalline silicon film 215. As a result, most of the upper surface of the P-type polycrystalline silicon film 215 serving as a capacity extraction electrode is a silicide layer 225 with reduced resistance, and the capacity films (the third silicon oxide film 213 and the fifth silicon oxide film). 219). For this reason, it is possible to reduce the parasitic resistance of the extraction electrode. At the same time, since the P-type polycrystalline silicon film 215 serving as a capacitor extraction electrode is formed on the first silicon oxide film 206 as element isolation, the parasitic capacitance between the silicon substrates can be reduced.

  Further, as shown in the second embodiment, since the opening width of the capacitor formation region is narrower than that in the first embodiment, a bipolar transistor is required without adding a mask process for protecting the capacitor formation region. While using a method for manufacturing a semiconductor device that can be easily adapted to the process, the effect of parasitic resistance generated in the semiconductor film itself that serves as an electrode is reduced, and no contact portion is formed with the semiconductor substrate, that is, parasitic capacitance is suppressed. A semiconductor device can be provided.

  In the first embodiment and the second embodiment described above, the NPN transistor has been described as an example among the bipolar transistors. However, this may be a PNP transistor.

Further, although a silicon oxide film is used as the dielectric film, any dielectric film such as a silicon nitride film may be used.
Further, although the N-type epitaxial layer is formed after the N-type buried layer is formed, these may be formed by high energy implantation. In this case, it is possible to reduce the relatively expensive epitaxial growth process.

The deep trench is filled with a silicon oxide film and polycrystalline silicon, but this may be only a silicon oxide film.
The P-type epitaxial layer may be Si or a mixed crystal semiconductor such as SiGe (silicon germanium), SiGeC (silicon germanium carbon), or SiC (silicon carbide).

Further, the P-type epitaxial layer in the capacitive element region may be made N-type like the upper electrode by implantation.
In addition, CMP was used to planarize the interlayer insulating film, but this may be planarized by using a resist etch back method, or the interlayer insulating film is made fluid and reflowed by heat treatment to be planarized. May be used. Further, it is not always necessary to perform planarization.

Moreover, although AL was used for the wiring, this may be a metal such as W, Ti, or Cu, or a metal alloy.
Further, the process has been described in a limited manner. For example, any process may be used as long as it is compatible, such as thermal oxidation and CVD when forming an oxide film, and dry etching and wet etching when etching.

  The present invention reduces the influence of parasitic resistance generated in the semiconductor film itself as an electrode, and can suppress parasitic capacitance by not forming a contact portion with a semiconductor substrate, and a semiconductor device having a capacitive element and a bipolar transistor It is useful for a method of manufacturing a semiconductor device.

Process sectional drawing which shows the deep trench formation process of the semiconductor device in Embodiment 1 Process sectional drawing which shows the shallow trench formation process of the semiconductor device in Embodiment 1 Process sectional drawing which shows the collector drawer part manufacturing process of the semiconductor device in Embodiment 1 Process sectional drawing which shows the base region formation process of the semiconductor device in Embodiment 1 Process sectional drawing which shows the P-type silicon film formation process of the semiconductor device in Embodiment 1 Process sectional drawing which shows the 3rd silicon oxide film formation process of the semiconductor device in Embodiment 1 Process sectional drawing which shows the 4th silicon oxide film formation process of the semiconductor device in Embodiment 1 Process sectional drawing which shows the opening window formation process of the semiconductor device in Embodiment 1 Process sectional drawing which shows the sidewall formation process of the semiconductor device in Embodiment 1 Process sectional drawing which shows the electrode area | region formation process of the semiconductor device in Embodiment 1 Process sectional drawing which shows the N type electrode processing process of the semiconductor device in Embodiment 1 Process sectional drawing which shows the collector region formation process of the semiconductor device in Embodiment 1 Process sectional drawing which shows the sputtering process of the semiconductor device in Embodiment 1 Process sectional drawing which shows the contact window formation process of the semiconductor device in Embodiment 1 Process sectional drawing which shows the wiring formation process of the semiconductor device in Embodiment 1 Process sectional drawing which shows the deep trench formation process of the semiconductor device in Embodiment 2 Process sectional drawing which shows the shallow trench formation process of the semiconductor device in Embodiment 2 Process sectional drawing which shows the collector drawer part manufacturing process of the semiconductor device in Embodiment 2 Process sectional drawing which shows the base region formation process of the semiconductor device in Embodiment 2 Process sectional drawing which shows the P-type silicon film formation process of the semiconductor device in Embodiment 2 Process sectional drawing which shows the 3rd silicon oxide film formation process of the semiconductor device in Embodiment 2 Process sectional drawing which shows the 4th silicon oxide film formation process of the semiconductor device in Embodiment 2 Process sectional drawing which shows the opening window formation process of the semiconductor device in Embodiment 2 Process sectional drawing which shows the side wall formation process of the semiconductor device in Embodiment 2 Process sectional drawing which shows the electrode area | region formation process of the semiconductor device in Embodiment 2 Process sectional drawing which shows the silicon film removal process of the semiconductor device in Embodiment 2 Process sectional drawing which shows the sputtering process of the semiconductor device in Embodiment 2 Process sectional drawing which shows the contact window process of the semiconductor device in Embodiment 2 Process sectional drawing which shows the wiring formation process of the semiconductor device in Embodiment 2 Schematic structure diagram of conventional capacitive element

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation | separation 3 1st insulating film 4 1st polysilicon film 5 2nd insulating film 6 2nd polysilicon film 7 Protective film 8 1st electrode film 9 2nd electrode film 100 P type Semiconductor substrate 101 N-type buried layer 102 N-type epitaxial layer 103 Deep trench 104 Resist film 105 Shallow trench 106 First silicon oxide film 107 N-type collector lead portion 108 Second silicon oxide film 109 First polycrystalline silicon film DESCRIPTION OF SYMBOLS 110 Resist film 111 P type epitaxial layer 112 P type silicon film 113 Third silicon oxide film 114 Resist film 115 P type polycrystalline silicon film 116 Fourth silicon oxide film 117 Resist film 118 Opening window 119 Fifth Silicon oxide film 120 Side wall 121 Resist film 122 N-type Crystalline silicon film 123 Emitter layer 124 Resist film 125 Resist film 126 Silicide layer 127 Sixth silicon oxide film 128 Titanium nitride adhesion layer 129 AL wiring 200 P-type semiconductor substrate 201 N-type buried layer 202 N-type epitaxial layer 203 Deep trench 204 Resist film 205 Shallow trench 206 First silicon oxide film 207 N-type collector lead portion 208 Second silicon oxide film 209 First polycrystalline silicon film 210 Resist film 211 P-type epitaxial layer 212 P-type silicon film 213 Third silicon oxide film 214 Resist film 215 P type polycrystalline silicon film 216 Fourth silicon oxide film 217 Resist film 218 Open window 219 Fifth silicon oxide film 220 Side wall 221 N type poly Crystal silicon film 222 emitter layer 223 resist film 224 resist film 225 silicide layer 226 sixth silicon oxide film 227 of titanium nitride adhesion layer 228 AL wiring

Claims (10)

A semiconductor device in which a capacitive element and a bipolar transistor coexist,
The capacitive element is
An isolation insulator layer formed around the element formation region of the semiconductor substrate;
A semiconductor layer formed on the semiconductor substrate;
An extraction electrode of a capacitive element formed over the semiconductor layer and the insulator layer leaving an opening window on the center of the semiconductor layer;
An insulating film formed on the extraction electrode of the capacitive element along the periphery of the opening window;
A capacitive film formed on the bottom and side walls of the opening window;
A sidewall formed on the side wall of the opening window through the capacitive film;
A semiconductor film formed on the sidewall, the capacitor film, and the insulating film;
And a silicide layer formed on a surface of the extraction electrode of the capacitor element, wherein the silicide layer and the capacitor film are close to each other.   2. The semiconductor device according to claim 1, wherein the width of the opening window is larger than twice the film thickness of the sidewall. A semiconductor device in which a capacitive element and a bipolar transistor coexist,
The capacitive element is
An isolation insulator layer formed around the element formation region of the semiconductor substrate;
A semiconductor layer formed on the semiconductor substrate;
An extraction electrode of a capacitive element formed over the semiconductor layer and the insulator layer leaving an opening window on the center of the semiconductor layer;
An insulating film formed on the extraction electrode of the capacitive element along the periphery of the opening window;
A capacitive film formed on the bottom and side walls of the opening window;
A sidewall formed on the side wall of the opening window through the capacitive film;
A semiconductor film formed on the sidewall and the insulating film;
And a silicide layer formed on a surface of the extraction electrode of the capacitor element, wherein the silicide layer and the capacitor film are close to each other.   4. The semiconductor device according to claim 3, wherein the width of the opening window is smaller than twice the film thickness of the sidewall. A method of manufacturing a semiconductor device having a capacitive element and a bipolar transistor,
Forming an isolation insulator layer around a semiconductor substrate to be a collector region and a capacitor element region;
Forming a semiconductor layer to be a base region and a lower electrode on the semiconductor substrate;
Forming a first capacitive film on the semiconductor layer;
Forming an external base and an extraction electrode of the capacitor over the first capacitor film, the semiconductor layer, and the isolation insulator layer;
Forming an insulating film on the extraction electrode of the capacitive element;
Etching the insulating film on the center of the semiconductor layer and the extraction electrode of the capacitive element to form an opening window that becomes an emitter region and a capacitive region;
Forming a second capacitive film in the opening window;
Forming a sidewall on the side wall of the opening window through the second capacitive film;
Etching the first capacitive film and the second capacitive film in the emitter region;
Covering the semiconductor layer in the emitter region and the first capacitor film in the capacitor region, and forming a semiconductor film on the insulating film;
Forming an emitter layer in the semiconductor layer;
And a step of forming a silicide layer on the surface of the semiconductor film and selectively using a resist mask in the etching process of the first capacitor film and the second capacitor film. Etching is a method for manufacturing a semiconductor device.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the opening window of the capacitance region is wider than the opening window of the emitter region. A method of manufacturing a semiconductor device having a capacitive element and a bipolar transistor,
Forming an isolation insulator layer around a semiconductor substrate to be a collector region and a capacitor element region;
Forming a semiconductor layer to be a base region and a lower electrode on the semiconductor substrate;
Forming a first capacitive film on the semiconductor layer;
Forming an external base and an extraction electrode of the capacitor over the first capacitor film, the semiconductor layer, and the isolation insulator layer;
Forming an insulating film on the extraction electrode of the capacitive element;
Etching the insulating film on the center of the semiconductor layer and the extraction electrode of the capacitive element to form an opening window that becomes an emitter region and a capacitive region;
Forming a second capacitive film in the opening window;
Forming a sidewall on the side wall of the opening window through the second capacitive film;
Etching the first capacitive film and the second capacitive film in the emitter region;
Covering the semiconductor layer in the emitter region, the first capacitor film and the second capacitor film in the capacitor region, and forming a semiconductor film on the insulating film;
Forming an emitter layer in the semiconductor layer;
And a step of forming a silicide layer on the surface of the semiconductor film, and in the etching process of the first capacitor film and the second capacitor film, the inside of the opening window of the capacitor region is the A method of manufacturing a semiconductor device, wherein the method is embedded with a sidewall.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the opening window of the capacitor region has a smaller width than the opening window of the emitter region.   9. The semiconductor device according to claim 5, wherein the lead electrode, the sidewall, and the semiconductor film of the capacitor element are polycrystalline silicon films. 10. Production method.   9. The semiconductor layer according to claim 5, wherein the semiconductor layer is an alloy of silicon and germanium or a mixed semiconductor layer of an alloy of silicon and germanium containing carbon. A method for manufacturing a semiconductor device.

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