JP2006165358A - Manufacturing method of ceramic sintered substrate - Google Patents

Manufacturing method of ceramic sintered substrate Download PDF

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JP2006165358A
JP2006165358A JP2004356156A JP2004356156A JP2006165358A JP 2006165358 A JP2006165358 A JP 2006165358A JP 2004356156 A JP2004356156 A JP 2004356156A JP 2004356156 A JP2004356156 A JP 2004356156A JP 2006165358 A JP2006165358 A JP 2006165358A
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substrate
polyimide sheet
ceramic
thin film
pad
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Yoshifumi Yuuki
芳文 遊喜
Tsutomu Sakamoto
努 阪本
Hironori Shigezumi
宏典 茂澄
Shuichi Minagawa
修一 皆川
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Hitachi Ltd
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Hitachi Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology capable of decreasing damages caused to a substrate itself with a reduced number of steps at a low cost when the surface of a ceramic multilayer sintered substrate with a conductor is made flat and a thin film pad is formed on the surface. <P>SOLUTION: The ceramic substrate is manufactured by adhering a polyimide sheet to the ceramic sintered substrate, forming a via to a through-hole of the polyimide sheet, applying electric plating to the via, and polishing both the polyimide sheet and the thin film via pad at the same time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、導体を有するセラミック多層焼結基板の平坦化および薄膜パッド形成に関するものである。   The present invention relates to planarization and thin film pad formation of a ceramic multilayer sintered substrate having conductors.

従来の導体を有するセラミック多層焼結基板表面の平坦化および薄膜パッド形成方法の一例を図1を用いて説明する。従来例では、セラミック多層焼結基板1表面を直接研磨し平坦化(工程2)した後薄膜パッド3を形成する(工程3)。図2は従来例の他の例を示す。セラミック多層焼結基板1の表面導体パッド上にめっきガイドレジスト5を形成し(工程2)、薄膜ビア6を形成(工程4)した後、例えば日立化成工業(株)のPIQのような有機絶縁膜7をスピンコート法により重ね塗布・キュアベークし(工程5)、その表面をテープ研磨し平坦化していた(工程6)。この種の技術は例えば特開平7−235774号公報に示される。   An example of a conventional method for flattening the surface of a ceramic multilayer sintered substrate having a conductor and forming a thin film pad will be described with reference to FIG. In the conventional example, the surface of the ceramic multilayer sintered substrate 1 is directly polished and flattened (step 2), and then a thin film pad 3 is formed (step 3). FIG. 2 shows another example of the conventional example. After forming the plating guide resist 5 on the surface conductor pad of the ceramic multilayer sintered substrate 1 (step 2) and forming the thin film via 6 (step 4), for example, organic insulation such as PIQ of Hitachi Chemical Co., Ltd. The film 7 was repeatedly applied and cured and baked by spin coating (step 5), and the surface thereof was polished by tape and flattened (step 6). This type of technique is disclosed in, for example, Japanese Patent Application Laid-Open No. 7-235774.

特開平7−235774号公報JP-A-7-235774

上記従来技術のうち、前者の方法は、基板表面を直接研磨するため、セラミック表面にマイクロクラックが発生するという問題が有った。一方後者は、スピンコート法により塗布するため1回の塗布膜厚は10μm程度が限界であり、重ね塗りするために、工程が長くなりコストも高くなるという問題が有った。本発明は、導体を有するセラミック多層焼結基板表面を製造するにあたり、基板を平坦化し薄膜パッドを形成する際に基板に与えるダメージを軽減できる技術を提供することを目的とする。さらに基板に与えるダメージを少なくしかつ工程を短くする技術を提供することを目的とする。   Among the above prior arts, the former method has a problem that microcracks are generated on the ceramic surface because the substrate surface is directly polished. On the other hand, the latter has a problem that the coating film thickness is limited to about 10 μm because it is applied by the spin coating method, and the process becomes longer and the cost becomes higher because of repeated coating. An object of the present invention is to provide a technique capable of reducing damage to a substrate when the surface of a ceramic multilayer sintered substrate having conductors is manufactured and a thin film pad is formed by flattening the substrate. Furthermore, it aims at providing the technique which reduces the damage given to a board | substrate and shortens a process.

上記目的を達成するために、本発明では、導体を有するセラミック多層焼結基板表面の平坦化および薄膜パッド形成を、基板表面に貼りつけたポリイミドシートおよび電気めっきにより形成された薄膜ビアパッドを同時に研磨することにより行う。   In order to achieve the above object, in the present invention, the surface of a ceramic multilayer sintered substrate having conductors and the formation of a thin film pad are simultaneously polished on a polyimide sheet affixed to the substrate surface and a thin film via pad formed by electroplating. To do.

基板表面に貼りつけたポリイミドシート及び薄膜ビアパッドを研磨するので、基板自体にダメージを与えずに平坦化が可能となる。また、ポリイミドシートの厚さは基板反り量に合わせて一括で貼りつけするため、工程短縮およびコスト低減が可能である。   Since the polyimide sheet and thin film via pad attached to the substrate surface are polished, planarization is possible without damaging the substrate itself. Further, since the thickness of the polyimide sheet is affixed at a time in accordance with the amount of warpage of the substrate, the process can be shortened and the cost can be reduced.

導体を有するセラミック多層焼結基板の表面平坦化および薄膜パッド形成を短工程、低コストで実現した例を以下に示す。   An example in which surface flattening and thin film pad formation of a ceramic multilayer sintered substrate having conductors is realized in a short process and at low cost is shown below.

まず、導体を有するセラミック多層焼結基板表面の平坦化および薄膜パッド形成を、基板表面に貼りつけたポリイミドシートを研磨することで得るセラミック多層焼結基板の製造方法を説明する。図3はこの製造方法を実行したときに得られる基板の断面図を工程順に示す。図3中、1はセラミック多層焼結基板、2は導体、4は導体パッド、9はポリイミドシート、10はバリアメタル、6はめっきビア、13はビア用電極膜を示す。   First, a method for manufacturing a ceramic multilayer sintered substrate obtained by polishing a polyimide sheet attached to the substrate surface for flattening the surface of the ceramic multilayer sintered substrate having conductors and forming a thin film pad will be described. FIG. 3 shows sectional views of the substrate obtained when this manufacturing method is executed in the order of steps. In FIG. 3, 1 is a ceramic multilayer sintered substrate, 2 is a conductor, 4 is a conductor pad, 9 is a polyimide sheet, 10 is a barrier metal, 6 is a plating via, and 13 is an electrode film for via.

本実施例のセラミック多層焼結基板の製造方法では、まずセラミック多層焼結基板表面に基板表面の反り量以上の厚みがあるポリイミドシート9を貼りつける(工程2)。ポリイミドシートとしては例えば宇部興産(株)のユーピレックスSを用いることができる。   In the method for producing a ceramic multilayer sintered substrate of this embodiment, first, a polyimide sheet 9 having a thickness equal to or greater than the warpage amount of the substrate surface is attached to the surface of the ceramic multilayer sintered substrate (step 2). As the polyimide sheet, for example, Upilex S manufactured by Ube Industries, Ltd. can be used.

次に、ポリイミドシート9にスルーホール12をレーザにより形成するためのスルーホール加工用バリアメタル10を形成する(工程3)。ここでスルーホール加工用バリアメタルにはスパッタリングによるCu膜を用いる。また、スルーホール加工用バリアメタルはフォトリソ技術を用いてパターン加工する。このスルーホール加工用バリアメタルは、後工程の平坦化時に研磨にて除去するためエッチングなどの処理は行わない。   Next, a barrier metal 10 for through-hole processing for forming the through-hole 12 with a laser is formed in the polyimide sheet 9 (step 3). Here, a Cu film formed by sputtering is used as the barrier metal for through-hole processing. Also, the barrier metal for through-hole processing is patterned using photolithography technology. This through-hole processing barrier metal is removed by polishing at the time of flattening in a subsequent process, and thus is not subjected to processing such as etching.

次に、バリアメタル10を形成した基板にレーザ照射を施しスルーホール12を形成する(工程4)。この時のレーザの種類にはエキシマ、YAG、CO2レーザを用いる。レーザ光11はポリイミドシート9のうちスルーホール加工用バリアメタル10が無い面のみに当たることでスルーホール12が形成される。スルーホール加工用バリアメタル10は上述したようにフォトリソ技術でパターン加工しているためスルーホール12の寸法・位置精度を高精度とできる。   Next, the substrate on which the barrier metal 10 is formed is irradiated with laser to form the through hole 12 (step 4). At this time, excimer, YAG, or CO2 laser is used as the type of laser. The laser beam 11 strikes only the surface of the polyimide sheet 9 where the through-hole processing barrier metal 10 is not provided, whereby the through-hole 12 is formed. Since the barrier metal 10 for through-hole processing is patterned by the photolithographic technique as described above, the size and position accuracy of the through-hole 12 can be made high.

次に、めっきビア用電極膜13を基板裏面に形成し、めっきビア用6を電気めっきで成長させて形成する(工程5)。この時めっき膜厚を基板表面反り量より多くなるように形成する。後工程で研磨されるため基板表面反り量以上形成されれば問題なくそれほど精度を必要としない。   Next, a plating via electrode film 13 is formed on the back surface of the substrate, and a plating via 6 is grown by electroplating (step 5). At this time, the plating film thickness is formed to be larger than the substrate surface warpage amount. Since it is polished in a subsequent process, if it is formed more than the amount of warpage of the substrate surface, it does not require much accuracy without problems.

次に、めっきビア用電極膜13を除去し、最後に、ポリイミドシート9、スルーホール加工用バリアメタル10、めっきビア6を平坦になるまで同時にラップ研磨する(工程6)。この研磨により、平坦化と薄膜ビアパッド形成が同時に完了する。   Next, the plating via electrode film 13 is removed, and finally, the polyimide sheet 9, the through-hole processing barrier metal 10, and the plating via 6 are simultaneously lapped until flat (step 6). By this polishing, planarization and thin film via pad formation are completed simultaneously.

更に上記手法により製造されたセラミック基板のビアパッド上ににICなどのチップ部品をマウントすることでマルチチップモジュールが製造される。   Furthermore, a multi-chip module is manufactured by mounting a chip component such as an IC on a via pad of a ceramic substrate manufactured by the above method.

実施例1では基板裏面に形成しためっきビア用電極膜を基板表面(上面)に形成するセラミック基板の製造方法の例を示す。この方法は、薄膜ビアパッドを形成する導体が基板裏面と導通が無い場合有効である。図4はこの製造方法を実行したときに得られる基板の断面図を工程順に示す。工程1から工程4までは、実施例1と同プロセスで形成される。
工程5において、めっきビア用電極膜13を基板表面(上面)に形成し、電機めっき処理にて基板表面(上面)全面にめっきビア6を成長させる。この時のめっき膜厚も実施例1同様、基板表面反り量以上になるように形成する。後工程で研磨するため高い精度で形成する必要はない。またスルーホール加工用バリアメタル10上のめっきビア用電極膜13は、平坦化時の研磨にて除去するためエッチングなどの処理は不要である。最後に、めっきビア6、めっきビア用電極膜13、スルーホール加工用バリアメタル10、ポリイミドシート9を一緒に、平坦になるまでラップ研磨する。この研磨により、平坦化と薄膜ビアパッド形成が同時に完了する。
Example 1 shows an example of a method for manufacturing a ceramic substrate in which a plating via electrode film formed on the back surface of the substrate is formed on the substrate surface (upper surface). This method is effective when the conductor forming the thin film via pad is not electrically connected to the back surface of the substrate. FIG. 4 shows a cross-sectional view of a substrate obtained when this manufacturing method is executed in the order of steps. Steps 1 to 4 are formed by the same process as in the first embodiment.
In step 5, a plating via electrode film 13 is formed on the substrate surface (upper surface), and a plating via 6 is grown on the entire surface of the substrate (upper surface) by electroplating. The plating film thickness at this time is also formed so as to be equal to or greater than the substrate surface warpage amount as in the first embodiment. Since it is polished in a later process, it is not necessary to form it with high accuracy. Further, the plating via electrode film 13 on the through-hole processing barrier metal 10 is removed by polishing at the time of flattening, so that a treatment such as etching is unnecessary. Finally, the plating via 6, the plating via electrode film 13, the through-hole processing barrier metal 10, and the polyimide sheet 9 are lapped together until flat. By this polishing, planarization and thin film via pad formation are completed simultaneously.

セラミック多層焼結基板の反りを、基板表面を直接研磨し平坦化した後薄膜パッドを形成する従来例を説明する図。The figure explaining the prior art example which forms the thin film pad, after grind | polishing and planarizing the board | substrate surface directly for the curvature of a ceramic multilayer sintered board. セラミック多層焼結基板の反りを、導体パッド上に薄膜ビアを形成した後、反り量以上の有機絶縁膜を重ね塗布・キュアベークし、その表面を研磨して平坦化する従来例を説明する図。The figure explaining the prior art example which forms the thin film via on the conductor pad, and coats and cures the organic insulating film more than the amount of warp, and polishes and flattens the warp of the ceramic multilayer sintered substrate. セラミック多層焼結基板の反りを、基板表面に貼りつけたポリイミドシートおよび、薄膜ビアパッドを研磨することにより平坦化する例を説明する図。The figure explaining the example which planarizes the curvature of a ceramic multilayer sintered board by grind | polishing the polyimide sheet and thin film via pad which were affixed on the board | substrate surface. セラミック多層焼結基板の反りを、基板表面に貼りつけたポリイミドシートおよび、薄膜ビアパッドを研磨することにより平坦化する例であって、めっきビア用電極膜を基板上面に形成する例を説明する図。The figure explaining the example which planarizes the curvature of the ceramic multilayer sintered substrate by polishing the polyimide sheet affixed to the substrate surface and the thin film via pad, and forms the electrode film for the plating via on the upper surface of the substrate .

符号の説明Explanation of symbols

1…セラミック多層焼結基板、2…導体、3…薄膜パッド、4…導体パッド、5…めっきガイドレジスト、6…めっきビア、7…有機絶縁膜、8…薄膜ビアパッド、9…ポリイミドシート、10…スルーホール加工用バリアメタル、11…レーザ光、12…スルーホール、13…めっき電極膜。
DESCRIPTION OF SYMBOLS 1 ... Ceramic multilayer sintered board, 2 ... Conductor, 3 ... Thin film pad, 4 ... Conductor pad, 5 ... Plating guide resist, 6 ... Plating via, 7 ... Organic insulating film, 8 ... Thin film via pad, 9 ... Polyimide sheet, 10 ... barrier metal for through-hole processing, 11 ... laser light, 12 ... through-hole, 13 ... plating electrode film.

Claims (4)

セラミック基板の製造方法において、
導体を施したセラミック焼結基板にポリイミドシートを貼り付け、
該ポリイミドシートの貫通穴にめっきビアを形成し、
前記ポリイミドシート及びめっきビアをともに研磨することにより平坦化処理を行うことを特徴とするセラミック基板の製造方法。
In the method of manufacturing a ceramic substrate,
A polyimide sheet is attached to a ceramic sintered substrate with conductors applied.
Forming a plating via in the through hole of the polyimide sheet;
A method for producing a ceramic substrate, comprising performing planarization by polishing both the polyimide sheet and the plating via.
請求項1において、前記ポリイミドシートは前記セラミック焼結基板の反り幅より厚い厚さのシートを貼り付けることを特徴とするセラミック基板の製造方法。   The method for manufacturing a ceramic substrate according to claim 1, wherein the polyimide sheet is affixed with a sheet thicker than a warp width of the ceramic sintered substrate. 請求項1において、前記貫通穴は、前記ポリイミドシートに銅膜のスパッタリング及びフォトリソ技術を用いたパターン加工によりバリアメタルを形成した後にレーザ光照射することいより形成することを特徴とするセラミック基板の製造方法。   2. The ceramic substrate according to claim 1, wherein the through hole is formed by irradiating a laser beam after forming a barrier metal on the polyimide sheet by sputtering a copper film and patterning using a photolithographic technique. Production method. 導体を施したセラミック焼結基板にポリイミドシートを貼り付け、
該ポリイミドシートの貫通穴にめっきビアを形成し、
前記ポリイミドシート及びめっきビアをともに研磨することにより平坦化処理を行うことにより製造されるセラミック基板に、集積回路を搭載することにより製造されたマルチチップモジュール。
A polyimide sheet is attached to a ceramic sintered substrate with conductors applied.
Forming a plating via in the through hole of the polyimide sheet;
A multi-chip module manufactured by mounting an integrated circuit on a ceramic substrate manufactured by performing a planarization process by polishing both the polyimide sheet and the plating via.
JP2004356156A 2004-12-09 2004-12-09 Manufacturing method of ceramic sintered substrate Withdrawn JP2006165358A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009302089A (en) * 2008-06-10 2009-12-24 Ngk Spark Plug Co Ltd Ceramic parts and manufacturing method thereof, and wiring board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009302089A (en) * 2008-06-10 2009-12-24 Ngk Spark Plug Co Ltd Ceramic parts and manufacturing method thereof, and wiring board

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