JP2006165290A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that, when a configuration employing an enhancement MOS transistor as a driving MOS transistor for a first stage is adopted, the driving MOS transistor becomes a dominant circuit configuration of 1/f noise since the enhancement MOS transistor is a transistor utilizing a surface channel and the transistor size thereof is also small. <P>SOLUTION: In an output circuit 17 for a CCD solid-state imaging apparatus, the output circuit 17 is constituted of a two-stage source follower circuit configuration, and a depletion MOS transistor is employed as a driving MOS transistor 21 for the first stage while the enhancement MOS transistor is employed as the driving MOS transistor 22 for a second stage. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device, and more particularly to a charge transfer type solid-state imaging device represented by a CCD (Charge Coupled Device) solid-state imaging device.

  A charge transfer type solid-state imaging device, such as a CCD solid-state imaging device, has a plurality of pixels including photoelectric conversion elements arranged in a two-dimensional array, for example, and reads out signal charges photoelectrically converted by these pixels to a vertical transfer unit. In addition, the vertical transfer unit performs vertical transfer and the horizontal transfer unit performs horizontal transfer, and then the charge detection unit converts the signal into an electric signal, for example, a voltage signal, and outputs it as a CCD output via an output circuit including a source follower circuit. It is the structure to derive.

  Conventionally, as an output circuit of a CCD solid-state imaging device, as shown in FIG. 3, a first-stage source follower circuit composed of a drive MOS transistor 101 and a load MOS transistor 111 in which a source electrode and a drain electrode are connected, and a source electrode A second-stage source follower circuit composed of a drive MOS transistor 102 and a load MOS transistor 112 connected to the drain electrode, and a third-stage composed of a drive MOS transistor 103 and a load MOS transistor 113 connected to the source electrode and the drain electrode. A three-stage source follower circuit configuration having a source follower circuit is known (see, for example, Patent Document 1).

  In FIG. 3, the drain electrodes of the driving MOS transistors 101, 102, and 103 are commonly connected to the power supply terminal 131. A power supply voltage VDD is applied to the power supply terminal 131. The source electrodes of the load MOS transistors 111, 112, and 113 are grounded via resistors 121, 122, and 123.

  In the three-stage source follower circuit, the gate electrode of the first-stage driving MOS transistor 101 is connected to a floating diffusion (FD) terminal (hereinafter referred to as FD terminal) 132. In the FD terminal 132, a signal charge horizontally transferred by the horizontal transfer unit is injected into the floating diffusion, so that a voltage corresponding to the charge amount is generated.

  The gate electrode of the second stage driving MOS transistor 102 is connected to the source electrode of the first stage driving MOS transistor 101. The gate electrode of the third stage driving MOS transistor 103 is connected to the source electrode of the second stage driving MOS transistor 102. An output terminal 133 is connected to the source electrode of the third-stage driving MOS transistor 103. Each gate electrode of the load MOS transistors 111, 112, 113 is connected to the bias terminal 134. A constant bias gate voltage VG is applied to the bias terminal 134.

  A reset MOS transistor 141 is connected between the FD terminal 132 and the reset drain terminal 135. A reset drain voltage VRD is applied to the reset drain terminal 135. The reset drain voltage VRD is set to a voltage value substantially equal to the power supply voltage VDD (VRD≈VDD). The gate electrode of the reset MOS transistor 141 is connected to the reset gate terminal 136. A reset gate pulse φRG is appropriately applied to the reset gate terminal 136.

  In the output circuit having the above configuration, since the reset drain voltage VRD is set to a voltage value substantially equal to the power supply voltage VDD, in order to operate the first-stage driving MOS transistor 101 in the saturation region, the driving MOS transistor 101 An enhancement MOS transistor is used. The reason is as follows.

  In driving the transistor, the source follower circuit needs to use the transistor in a saturation region. In order to use in the saturation region, it is generally necessary to satisfy the condition of Vgs> Vds−Vth. Here, Vgs is a gate-source potential difference, Vds is a source-drain potential difference, and Vth is a threshold voltage of the transistor. The enhancement has a positive (+) value and a depletion has a negative (-) value.

  Since the gate voltage Vg of the first-stage driving MOS transistor 101 is Vg≈VRD, Vg≈Vd (drain voltage) when used at VRD≈VDD. Therefore, in order to satisfy the condition of Vgs> Vds−Vth, the first-stage driving MOS transistor 101 must be Vth> 0, that is, an enhancement MOS transistor.

  On the other hand, the second-stage and third-stage driving MOS transistors 102 and 103 are buried channel type in contrast to the surface channel type enhancement MOS transistor in consideration of noise and operating point, and noise from the substrate surface. A depletion MOS transistor having a structure that is not easily affected by this is used.

  If the driving MOS transistors 102 and 103 are enhancement MOS transistors, the source voltage is lowered, so that the gate voltage entering the driving MOS transistors 102 and 103 gradually decreases. This is a problem related to the reliability of the transistor, and if the drain-gate voltage Vdg becomes high, there is a possibility that it becomes a problem in reliability. Therefore, a depletion MOS transistor is used as the drive MOS transistors 102 and 103. .

JP 2003-283929 A

  However, when the enhancement MOS transistor is used as the first-stage driving MOS transistor 101 as in the above-described prior art, the enhancement MOS transistor is a transistor using a surface channel, and the transistor size is small. The driving MOS transistor 101 at the stage has a so-called 1 / f noise dominant circuit configuration in which the noise power spectrum is proportional to the frequency f.

  Here, if the process-dependent coefficient (coefficient related to electron capture / emission at the gate insulating film interface) is K, the gate insulating film capacitance is Cox, the transistor channel length is L, and the channel width is W, 1 / f noise The power spectrum (root mean square of the noise voltage Vn) is given by the following equation.

Vn ² = K / (Cox × L × W) · 1 / f
∝1 / (L × W)

  Further, since the source follower circuit has a three-stage configuration in the above-described prior art, the structure is disadvantageous from the viewpoint of power consumption. In addition, the area of the output circuit is reduced while the chip area (size) is required to be reduced. It is tough.

  In order to solve the above problems, in the present invention, a charge transfer unit that transfers a signal charge photoelectrically converted by a photosensitive unit, a charge detection unit that converts a signal charge transferred by the charge transfer unit into an electrical signal, In the solid-state imaging device including an output circuit that outputs the electrical signal converted by the charge detection unit, the output circuit is configured as a source follower circuit configuration of at least two stages, and is used as a driving transistor of the first stage source follower circuit. A configuration using a depletion MOS transistor is employed.

  In the solid-state imaging device having the above configuration, by using a depletion MOS transistor as the driving transistor of the first-stage source follower circuit, the driving transistor has a buried channel structure, so that the carrier is slightly away from the oxide film-silicon interface. Move. As a result, 1 / f noise can be reduced.

  According to the present invention, the output circuit has a source follower circuit configuration of at least two stages, and the depletion MOS transistor is used as the drive transistor of the first stage source follower circuit. Since carriers move in a portion slightly away from the film-silicon interface, 1 / f noise can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic configuration diagram showing a charge transfer type solid-state imaging device, for example, a CCD solid-state imaging device according to an embodiment of the present invention.

  The CCD solid-state imaging device 10 according to the present embodiment receives signal charges photoelectrically converted by photosensitive portions (pixels) 12 arranged two-dimensionally in a matrix, for example, on a semiconductor substrate (chip) 11 via a read gate portion 13. Then, the data is read out to the vertical CCD (vertical transfer unit) 14, transferred in the vertical direction by the vertical CCD 14, further transferred in the horizontal direction by the horizontal CCD (horizontal transfer unit) 15, and a charge detection unit provided at the subsequent stage of the horizontal CCD 15. 16 is converted into an electric signal, for example, a voltage signal, and is output via an output circuit 17.

  In FIG. 1, a photosensitive portion (pixel) 12 has a photoelectric conversion element such as a photodiode, photoelectrically converts received light over an exposure period, and accumulates signal charges generated by the photoelectric conversion. The vertical CCD 14 is arranged for each vertical pixel column of the photosensitive unit 12, and transfers signal charges read from each of the photosensitive units 12 via the readout gate unit 13 in the vertical direction (downward in the drawing). Signal charges are transferred from each of the vertical CCDs 14 to the horizontal CCD 15 in units of one row (one line).

  The horizontal CCD 15 transfers the signal charge for one line transferred from each of the vertical CCDs 14 in the horizontal direction (left direction in the figure). The charge detector 16 is arranged at the end of the horizontal CCD 15 on the transfer destination side and is transferred by the horizontal CCD 15 and converts the injected signal charge into a voltage signal. As the charge detection unit 16, for example, a floating diffusion configuration having a floating diffusion unit (FD unit) 161, a reset drain unit (RD unit) 162, and a reset gate unit (RG unit) 163 is used.

  In the charge detection unit 16 having the floating diffusion configuration, the potential of the RD unit 162 is a potential corresponding to the potential of the final transfer stage of the horizontal CCD 15, specifically, the potential when the final transfer stage is deep. A reset drain voltage VRD having a predetermined voltage value is applied so as to have a deeper potential. The reset gate pulse φRG is applied to the gate electrode of the RG portion 163 at a predetermined timing. As a result, the potential of the FD portion 161 is reset to the reset drain voltage VRD at the cycle of the reset gate pulse φRG.

  A voltage signal obtained by voltage conversion by the charge detection unit 16 is output to the outside of the semiconductor substrate 11 through the output circuit 17 as a CCD imaging signal Vout. The output circuit 17 is one of the peripheral circuits mounted on the same semiconductor substrate 11 as the photosensitive unit 12, the vertical CCD 14, the horizontal CCD 15, and the charge detection unit 15, and has a source follower circuit configuration.

  FIG. 2 is a circuit diagram showing an example of the configuration of the output circuit 17. As shown in FIG. 2, the output circuit 17 according to this example includes a first-stage source follower circuit including a driving MOS transistor 211 and a load MOS transistor 31 in which a source electrode and a drain electrode are connected, a source electrode and a drain electrode. Is a two-stage source follower circuit configuration having a second-stage source follower circuit composed of a drive MOS transistor 22 and a load MOS transistor 32 connected to each other.

  In FIG. 2, the drain electrodes of the drive MOS transistors 21 and 22 are commonly connected to the power supply terminal 51. A power supply voltage VDD is applied to the power supply terminal 51. The source electrodes of the load MOS transistors 31 and 32 are grounded via resistors 41 and 42.

  In the two-stage source follower circuit, the gate electrode of the first-stage driving MOS transistor 21 is connected to the FD terminal (terminal of the FD unit 161). In the FD terminal 52, a signal charge horizontally transferred by the horizontal CCD 15 in FIG. 1 is injected into the FD unit 161, and a voltage corresponding to the charge amount is generated.

  The gate electrode of the second stage driving MOS transistor 22 is connected to the source electrode of the first stage driving MOS transistor 21. An output terminal 53 is connected to the source electrode of the second-stage driving MOS transistor 22. Each gate electrode of the load MOS transistors 31 and 32 is connected to the bias terminal 54. A constant bias gate voltage VG is applied to the bias terminal 54.

  1 can be equivalently shown as a reset MOS transistor 61. In other words, the drain region of the reset transistor 61 corresponds to the reset drain portion 162, the source region corresponds to the FD portion 161, and the gate electrode corresponds to the reset gate portion 163. A reset drain voltage VRD is applied to the reset drain portion 162 via the reset drain terminal 55, and a reset gate pulse φRG is appropriately applied to the reset gate portion 163 via the reset gate terminal 56.

  In the output circuit 17 having the two-stage source follower circuit configuration, the present invention uses a depletion MOS transistor as the first-stage driving MOS transistor 21 and an enhancement MOS transistor as the second-stage driving MOS transistor 22. It is said.

  Since a depletion MOS transistor is used as the first-stage driving MOS transistor 21, the voltage value of the reset drain voltage VRD is set lower than the voltage value of the power supply voltage VDD, preferably 1V by optimizing the potential of the CCD solid-state imaging device 10. It is set low.

  Here, the optimization of the potential of the CCD solid-state imaging device 10 means that even if the voltage value of the reset drain voltage VRD is set lower than the voltage value of the power supply voltage VDD, for example, about 1 V, the photosensitive portion 12 → the vertical CCD 14 → In the charge transfer route of horizontal CCD 15 → FD unit 161 → reset drain unit 162, the potential of the reset drain unit 162 determined by the voltage value of the reset drain voltage VRD can be efficiently transferred in the transfer route. Say to set in a relationship.

  The basis for setting the voltage value of the reset drain voltage VRD to be, for example, about 1 V lower than the voltage value of the power supply voltage VDD is as follows. That is, as described above, in the source follower circuit, it is necessary to use the transistor in the saturation region, and in general, it is necessary to satisfy the condition of Vgs> Vds−Vth in order to use the transistor in the saturation region. Thus, the values are derived in consideration of transistor characteristic variations and operation margins.

  By reducing the potential of the reset drain voltage VRD, the source voltage Vs1 of the drive MOS transistor 21 is lowered as compared with the case where an enhancement MOS transistor is used as the first-stage drive MOS transistor 21.

As a result, when the gate voltage of the driving MOS transistor 21 is Vg1,
Vgs [Vg1-Vs1] -Vth <Vds [VDD-Vs1]
Therefore, even if a depletion MOS transistor is used as the first-stage driving MOS transistor 21, the driving MOS transistor 21 can be operated in the saturation region.

  In this way, by using a depletion MOS transistor for the first-stage driving MOS transistor 21, the driving MOS transistor 21 has a buried channel structure, and carriers move in a portion slightly away from the oxide film-silicon interface. 1 / f noise can be reduced.

  In the output circuit 17 having the two-stage source follower circuit configuration, one of the points is that an enhancement MOS transistor is used for the second-stage driving MOS transistor 22.

  In the prior art using a depletion MOS transistor as the driving MOS transistor in the second and subsequent stages, it was difficult to shorten the channel length L due to the short channel effect, but using an enhancement MOS transistor is advantageous for a short channel. Therefore, the channel length L can be made shorter than before.

  Here, assuming that the drain-source current of the MOS transistor is Ids and the gate capacitance is Cg, Ids∝W / L and Cg∝W × L. Therefore, the fact that the channel length L can be shortened means that the channel width W can be made smaller than in the conventional case when the same drain-source current Ids as in the conventional case is to flow. As a result, since the gate capacitance Cg can be reduced, the load capacitance that must be driven by the first-stage driving MOS transistor 21 can be reduced.

  This means that the driving capability of the second-stage driving MOS transistor 22 having the same load capacity as that of the prior art is increased. Specifically, by optimizing the circuit, specifically, the driving frequency band and the load capacity By designing the circuit optimally, etc., it is possible to drive the second-stage driving MOS transistor 22 having the driving capability equivalent to the conventional third-stage driving MOS transistor with the first-stage driving MOS transistor 21. Therefore, the second-stage source follower circuit conventionally provided for driving the third-stage source follower circuit is not necessary.

  As a result, it is possible to reduce the amount of power consumed by the second-stage source follower circuit, so that it is possible to operate with low power consumption, and the source follower circuit has been changed from three to two stages. Since the circuit block size can be reduced by that amount, the chip area of the CCD solid-state imaging device 10 can be reduced as compared with the conventional case.

  In the above embodiment, the case where the source follower circuit has a two-stage configuration has been described as an example. However, the source follower circuit is not limited to the two-stage configuration. By using a depletion MOS transistor as the MOS transistor 21, it is possible to obtain the effect of reducing 1 / f noise, although the effects of low power consumption and chip size reduction cannot be obtained.

  Further, in the above-described embodiment, the case where the photosensitive portion (pixel) 12 is applied to an area sensor that is two-dimensionally arranged in a matrix has been described as an example. However, the present invention is not limited to this application example. A CCD line sensor in which (pixels) 12 are linearly arranged one-dimensionally is not limited to a CCD solid-state imaging device, and can be applied to a charge transfer type solid-state imaging device in general.

It is a schematic block diagram which shows the CCD solid-state imaging device concerning one Embodiment of this invention. It is a circuit diagram which shows an example of a structure of an output circuit. It is a circuit diagram which shows the prior art example of an output circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... CCD solid-state imaging device, 11 ... Semiconductor substrate (chip), 12 ... Photosensitive part (pixel), 13 ... Reading gate part, 14 ... Vertical CCD (vertical transfer part), 15 ... Horizontal CCD (horizontal transfer part), 16 ... Charge detection unit, 17 ... Output circuit, 21,22 ... Drive MOS transistor, 31,32 ... Load MOS transistor

Claims (3)

A charge transfer unit that transfers signal charges photoelectrically converted by the photosensitive unit;
A charge detection unit that converts the signal charge transferred by the charge transfer unit into an electrical signal;
An output circuit that outputs the electrical signal converted by the charge detection unit;
The output circuit includes at least a two-stage source follower circuit, and a depletion MOS transistor is used as a drive transistor of the first-stage source follower circuit. The charge detection unit selectively discharges the charge of the floating diffusion unit to which a signal charge is injected from the charge transfer unit, a reset drain unit to which a reset drain voltage is applied, and the floating diffusion unit to the reset drain unit. And a reset gate portion to
The solid-state imaging device according to claim 1, wherein a voltage value of the reset drain voltage is set lower than a voltage value of a power supply voltage of the output circuit. The solid-state imaging device according to claim 1, wherein the output circuit uses an enhancement MOS transistor as a drive transistor of a source follower circuit in the second and subsequent stages.

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