JPH1041494A - Output circuit for charge/voltage converting part and charge transfer device provided with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent increase of 1/f noises even when a drive MOS transistor is small and to prevent a shutter step from being produced by restricting the lower limit of substrate voltage regulation even when its output signal is applied to the back gate of the drive MOS transistor. SOLUTION: A drive MOS transistor Q31 is connected between the drain side of a first-stage drive MOS transistor Q11 of a source follower circuit 12 and a power source VDD. Then, the output signal of the first-stage drive MOS transistor Q11 is applied through a feedback circuit 13 to the gate electrode of the feedback MOS transistor Q31 as a feedback signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an output circuit of a charge-to-voltage converter for converting a signal charge into a voltage signal, and a charge transfer device having the same.

[0002]

2. Description of the Related Art In a CCD solid-state imaging device or a CCD delay device, a charge-to-voltage converter for converting a signal charge into a voltage signal is indispensable. As the charge-voltage converter, for example, a CCD
FIG. 6 shows a configuration of a floating diffusion amplifier (FDA) used for a solid-state imaging device. In FIG. 6, a signal charge transferred by a horizontal CCD (not shown) is injected into a floating diffusion FD via an output gate OG, where it is converted into a voltage signal.

The reset MOS transistor Qr
t resets the floating diffusion FD for each packet in response to a reset pulse φRG applied to the reset gate, and resets the reset drain voltage VRD (= V
DD). The voltage signal obtained by the floating diffusion FD is subjected to impedance conversion by, for example, a three-stage source follower circuit 61 as an output circuit, and is derived as an output signal VOUT.

In the charge-to-voltage converter having the above-described structure, the floating diffusion FD includes Cpw, Co
Parasitic capacitances such as g, Crg, Cds, and Cgs are added. Here, if the connection point between the gate electrode of the first-stage drive MOS transistor Q61 of the source follower circuit 61 and the floating diffusion FD is a node N, Cpw
Is the parasitic capacitance between the node N and the ground, Cog is the parasitic capacitance between the node N and the gate electrode of the output gate OG,
Crg is the node N and the reset MOS transistor Qrt
And Cds and Cgs are parasitic capacitances between the node N and the drain and source electrodes of the drive MOS transistor Q61. These parasitic capacitances cause a reduction in conversion efficiency.

In order to increase the conversion efficiency of the charge-voltage converter, the following method has conventionally been employed.
In one of the methods, as shown in FIG. 7, by shrinking the size of the floating diffusion FD or the first-stage drive MOS transistor Q61 of the source follower circuit 61, the parasitic capacitance added to the floating diffusion FD is reduced. It was intended to reduce and improve the conversion efficiency.

[0006] In another method, as shown in FIG. 8, a first stage drive MOS of a source follower circuit 61 is provided.
By providing the output signal of the drive MOS transistor Q61 to the back gate (P well) of the transistor Q61, the gain of the source follower circuit 61 is increased, and the conversion efficiency is improved.

[0007]

However, in the former method described above, processing becomes difficult, and the first-stage drive MOS transistor Q of the source follower circuit 61 becomes difficult.
Shrinking the size of 61 causes problems such as an increase in low frequency noise inversely proportional to the frequency, so-called 1 / f noise. On the other hand, in the latter method, since the potential of the back gate (P well) of the first-stage drive MOS transistor Q61 of the source follower circuit 61 becomes a positive high voltage, the lower limit of the substrate voltage adjustment is restricted, and When a shutter pulse is applied, there is a problem that a shutter step is generated.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an output circuit of a charge-to-voltage conversion unit capable of greatly improving conversion efficiency by changing a simple circuit configuration. To provide.

[0009]

According to the present invention, there is provided an output circuit of a charge-to-voltage converter, comprising at least one source follower circuit connected to the charge-to-voltage converter and a drive transistor and a power supply of the source follower circuit. And a feedback circuit for providing a feedback signal corresponding to the output signal of the drive transistor to a control electrode of the feedback transistor.

In the output circuit having the above configuration, when a feedback signal corresponding to the output signal of the drive transistor is given to the control electrode of the feedback transistor via the feedback circuit, the power supply voltage corresponding to the output signal is applied to the drive transistor. Supplied. Thereby, the voltage difference between the electrode to which the power supply voltage of the drive transistor is applied and the electrode from which the output signal is derived becomes constant. As a result, the decrease in gain due to the short channel effect is less likely to occur, and the circuit gain increases.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows, for example, CC
FIG. 2 is a circuit diagram illustrating a first embodiment of the present invention applied to a charge-voltage converter of a D solid-state imaging device. In FIG. 1, a charge-to-voltage converter 11 for converting signal charges transferred by a horizontal CCD (not shown) into a voltage signal has, for example, a floating diffusion amplifier (FDA) configuration. That is, the floating diffusion FD and the floating diffusion FD
And a reset MOS transistor Qrt for resetting.

In the charge-voltage converter 11, the horizontally transferred signal charges are injected into the floating diffusion FD via the output gate OG of the horizontal CCD, where they are converted into voltage signals. And reset M
The OS transistor Qrt resets the floating diffusion FD for each packet in response to the reset pulse φRG applied to the reset gate, and clamps the reset to the reset drain voltage VRD applied to the reset drain.

The voltage signal obtained by the floating diffusion FD is subjected to impedance conversion by a source follower circuit 12 constituting an output circuit, and is derived as an output signal VOUT. Source follower circuit 12
Are drive MOS transistors Q11, Q12, Q1
3 and load MOS transistors Q21, Q22, Q2
For example, it has a three-stage circuit configuration of three stages.

In the source follower circuit 12, the source electrodes of the load MOS transistors Q21, Q22, Q23 are connected to ground via a resistor R1, and a predetermined bias voltage VGG is applied to each gate electrode. The first-stage drive MOS transistor Q11 is
The gate area is reduced to sufficiently reduce the parasitic capacitance of the floating diffusion FD, and the oxide film under the gate electrode is reduced in thickness to reduce 1 / f noise depending on the gate area.

This first stage drive MOS transistor Q1
1 is provided with a feedback MOS transistor Q31 cascode-connected between the drain side and the power supply VDD. Feedback MOS transistor Q
As 31, a surface channel type MOS transistor having a high gain is used. The gate electrode of this feedback MOS transistor Q31 has a first-stage drive MOS
The output signal of the transistor Q11 is the feedback circuit 1
3 as a feedback signal.

The feedback circuit 13 includes a capacitor C connected between the source electrode of the first-stage drive MOS transistor Q11 and the gate electrode of the feedback MOS transistor Q31, and a capacitor C connected between the gate electrode of the feedback MOS transistor Q31 and the power supply VDD. And the resistor R2. Then, the DC component of the output signal of the first-stage drive MOS transistor Q11 is cut by the capacitor C, and only the AC component of the output signal is superimposed on the high voltage supplied from the power supply VDD and applied to the gate electrode of the feedback MOS transistor Q31.

As described above, the feedback MOS transistor Q31 is provided between the drain of the first-stage drive MOS transistor Q11 and the power supply VDD, and the output signal of the first-stage drive MOS transistor Q11 is applied to the gate electrode via the feedback circuit 13. Thereby, the drain voltage of the drive MOS transistor Q11 changes according to the signal output. Then, the voltage difference Vsd between the drain and the source of the drive MOS transistor Q11 becomes constant, and the decrease in gain due to the short channel effect is less likely to occur, so that the circuit gain increases, and the conversion efficiency can be improved.

In particular, the first stage drive MOS transistor Q
No. 11 has a very large effect because the transistor size is made small and the short channel effect is easily generated for the purpose of reducing the parasitic capacitance of the floating diffusion FD. Since the parasitic capacitance seen from the gate electrode of the first stage drive MOS transistor Q11 is (1-G) times when the gain is G, an improvement in circuit gain leads to a reduction in the parasitic capacitance seen from the floating diffusion FD. Can further contribute to the improvement of conversion efficiency.

On the other hand, the first stage drive MOS transistor Q
Since the size of 11 has to ensure the frequency characteristics, it must be larger than the size of the reset MOS transistor Qrt and the like. Therefore, of the parasitic capacitances viewed from the floating diffusion FD, the parasitic capacitances Cdg and Cgs attached to the first-stage drive MOS transistor Q11 are largely controlled.

If the source side of the first-stage drive MOS transistor Q11 is, for example, G = 0.9, the apparent capacitance is very small as Cgs × (1-0.9) = 0.1Cgs, but the drain side is In the conventional method, the constant voltage G =
Since it is 0, Cdg × (1−0) = Cdg, and the gate-drain capacitance Cdg hinders the improvement of the conversion efficiency.

On the other hand, in the present embodiment, since the drain voltage of the drive MOS transistor Q11 changes according to the output signal of the first stage drive MOS transistor Q11, the gate voltage is Vg and the drain voltage is Vd.
Then, since Vg∝Vd, the apparent parasitic capacitance Cd seen from the floating diffusion FD side is obtained.
g is, for example, the feedback MOS transistor Q3
Assuming that the gain of 1 is 0.9, Cdg × (1−0.9 ×
0.9) = 0.19 Cdg, and a large reduction in parasitic capacitance can be realized. As a result, the conversion efficiency can be greatly improved.

In the feedback circuit 13,
The DC component of the output signal of the first-stage drive MOS transistor Q11 is cut by the capacitor C, and only the AC component of the output signal is superimposed on the high voltage supplied from the power supply VDD and applied to the gate electrode of the feedback MOS transistor Q31. Accordingly, even if the level of the output signal of the first-stage drive MOS transistor Q11 is low, DC
By the offset, a sufficiently high signal voltage can be applied to the gate electrode of the feedback MOS transistor Q31. Therefore, since a surface channel type MOS transistor having a high gain can be used as the feedback MOS transistor Q31, the conversion efficiency can be further improved.

Further, by adopting the configuration of the present embodiment,
Even if the conversion efficiency is not increased, the size of the first-stage drive MOS transistor Q11 can be set large. Among the MOS transistors of the source follower circuit 12, the size of the first-stage drive MOS transistor Q11 is the smallest and is a source of 1 / f noise and the like. Therefore, it is possible to reduce the noise by setting this size large. Also.

In the above configuration, the reset drain voltage VR of the reset MOS transistor Qrt
When D is set to the power supply voltage VDD, the first-stage drive M
Since the potential relationship of the OS transistor Q11 satisfies Vg> Vd, if a channel-drain electric field is severe and breakdown occurs, hot electrons are generated and flow into the gate electrode having a higher potential than the drain electrode. Then, there is a concern that the noise may be generated and the gate oxide film may be deteriorated by passing through the gate oxide film, thereby lowering the reliability.

Therefore, the reset MOS transistor Qr
t is set lower than the power supply voltage VDD, and the first-stage drive MOS transistor Q11
Is set so that Vd ≧ Vg. Thus, generation of noise and deterioration of the gate oxide film due to the flow of hot electrons into the gate electrode can be prevented.

The configuration according to the first embodiment described above
When applied to the first-stage source follower, a great effect is obtained, but when applied to the second and subsequent source followers, a corresponding effect can be obtained. FIG.
Next, a circuit configuration in a case where the configuration according to the first embodiment is applied to the source followers of all stages in the three-stage source follower circuit 12 is shown.

In FIG. 2, a feedback MOS transistor Q31 is provided between the drain side of the first-stage drive MOS transistor Q11 and the power supply VDD, and a feedback MOS transistor Q31 is provided between the drain side and the power supply VDD of the second-stage drive MOS transistor Q12. The feedback MOS transistor Q32 is connected to the third-stage drive MOS transistor Q1.
3 is provided with a feedback MOS transistor Q33 cascode-connected between the drain side and the power supply VDD.

Feedback MOS transistor Q3
A surface channel type MOS transistor having a high gain is used as 1, Q32 and Q33. The gate electrode of the feedback MOS transistor Q31 has
The output signal of the first-stage drive MOS transistor Q11 is provided via a feedback circuit 13, and the output signal of the second-stage drive MOS transistor Q12 is provided via a feedback circuit 14 to the gate electrode of the feedback MOS transistor Q32. The output signal of the third-stage drive MOS transistor Q13 is supplied to the gate electrode of the MOS transistor Q33 via the feedback circuit 15.

As the feedback circuits 13, 14, and 15, those having the same circuit configuration as the feedback circuit 13 of the first embodiment are used. As described above, even when the feedback circuits 13, 14, and 15 are provided in the source followers of all stages in the source follower circuit 12,
The same effect as in the first embodiment can be obtained.

It is most efficient to apply a feedback signal based on the output signal of the first-stage drive MOS transistor Q11 to the gate electrode of the feedback MOS transistor Q31. The signal may be used as a feedback signal. In short, a feedback signal proportional to the input signal of the source follower circuit 12 may be used.

FIG. 3 shows a circuit configuration when the output signal of the second-stage drive MOS transistor Q12 is used as a feedback signal. In the figure, the same parts as those in FIG. 1 are denoted by the same reference numerals. In FIG. 3, a feedback MOS transistor Q31 'is provided in cascode connection between the drain side and the power supply VDD of the first stage drive MOS transistor Q11 of the source follower circuit 12. As the feedback MOS transistor Q31 ', a depression type MOS transistor is used.

Then, the output signal of the first-stage drive MOS transistor Q11 is applied to the gate electrode of the second-stage drive MOS transistor Q12,
The output signal of the transistor Q12 is the third-stage drive MOS
The voltage is applied to the gate electrode of the transistor Q13 and to the gate electrode of the feedback MOS transistor Q31 ', and the output signal of the third-stage drive MOS transistor Q13 becomes the output signal VOUT as it is.

In the source follower circuit 12 having the above configuration, the second-stage drive MOS transistor Q12 and the load MOS transistor Q22 have a function as the second-stage source follower of the source follower circuit 12, and are proportional to the input signal. It also has a function as a feedback circuit for providing a feedback signal to the gate electrode of the feedback MOS transistor Q31 '. When a surface channel type MOS transistor is used as the feedback MOS transistor, the second-stage drive MO
The output signal of the S transistor Q12 may be supplied to the gate electrode of the feedback MOS transistor through the RC feedback circuit.

FIG. 4 is a diagram showing a CCD to which the present invention is applied.
It is a schematic block diagram which shows an area sensor. In FIG.
A plurality of sensor units 21 arranged in a matrix to convert incident light into signal charges having a charge amount corresponding to the amount of light, and a plurality of sensor units 21 provided for each vertical column of these sensor units 21
An image pickup area 23 is constituted by a plurality of vertical CCDs 22 for vertically transferring signal charges read from the CCD. A horizontal CCD 24 is arranged below the image pickup area 23 in the figure.

The horizontal CCD 24 includes a plurality of vertical CCDs 2.
The signal charges transferred in line units from 2 are sequentially horizontally transferred. A charge-voltage converter 25 is provided at an end on the transfer destination side of the horizontal CCD 22 via an output gate (OG). As the charge-voltage converter 25, for example, one having a floating diffusion amplifier (FDA) configuration is used. The charge-voltage converter 25 having the FDA configuration
, A voltage lower than the power supply voltage VDD is applied as the reset drain voltage VDD.

The voltage signal obtained by the charge-voltage conversion in the charge-voltage converter 25 is impedance-converted in the source follower circuit 26, and is derived as an output signal VOUT. The source follower circuit 26 has the circuit configuration shown in FIG. 1, FIG. 2 or FIG.
A feedback MOS transistor is provided between the drain side of the S transistor and the power supply VDD, and a circuit configuration that provides a feedback signal proportional to an input signal (an output signal of the charge-voltage converter 25) to the gate electrode of the feedback MOS transistor. Used.

As described above, in the CCD area sensor having the source follower circuit 26 to which the present invention is applied as an output circuit, the circuit gain is improved in the source follower circuit 26 and the capacitance seen from the input side is reduced. Therefore, high conversion efficiency can be realized, so that the sensitivity as an area sensor can be greatly improved. Conversely, if the conversion efficiency is almost the same as that of the conventional one, it is possible to reduce noise such as 1 / f noise and to improve S / N.

In this embodiment, an example in which the present invention is applied to an output circuit of a charge-voltage converter in a CCD area sensor has been described. However, the present invention can be similarly applied to an output circuit of a charge-voltage converter in a CCD linear sensor or a CCD delay element. . In addition, not only the charge-voltage converter in these charge transfer devices,
The present invention can also be applied to a charge-voltage conversion unit of a sensor unit in an XY address type solid-state imaging device such as an amplification type solid-state imaging device.

In the embodiment described above, the case where the conversion efficiency is improved by improving the source follower circuit itself, which is the output circuit, has been described. Similar functions and effects can be obtained by adding a simple circuit. FIG. 5 shows an outline of the configuration when applied to a CCD area sensor.

In FIG. 5, a plurality of sensor units 31 arranged in a matrix and converting incident light into signal charges having a charge amount corresponding to the amount of light are provided. An imaging area 33 is constituted by a plurality of vertical CCDs 32 for vertically transferring signal charges read from the sensor unit 31. A horizontal CCD 34 is arranged below the imaging area 33 in the figure.

The horizontal CCD 34 includes a plurality of vertical CCDs 3.
The signal charges transferred in line units from 2 are sequentially horizontally transferred. At the end of the horizontal CCD 32 on the transfer destination side, a charge-voltage converter 35 is provided via an output gate (OG). The charge-voltage converter 35 has, for example, a configuration of a floating diffusion amplifier (FDA). The charge-voltage converter 35 having the FDA configuration
, A voltage lower than the power supply voltage VDD is applied as the reset drain voltage VDD.

The voltage signal obtained by the charge-to-voltage conversion in the charge-to-voltage converter 35 is impedance-converted in the source follower circuit 36, and the output signal V
Derived as OUT. The above components are the same CCD
It is mounted on a chip 40 and constitutes a CCD area sensor. The CCD chip 40 is provided with various terminals such as an output terminal 37 and a power terminal 38. Power supply terminal 38
A feedback MOS transistor Q41 is connected between the power supply VDD and the power supply VDD. This feedback M
The output signal VOUT of the source follower circuit 36 is supplied to the gate electrode of the OS transistor Q41 as a feedback signal via the feedback circuit 39. In this example, MO is used as the feedback transistor.
Although the S type was used, the present invention is not limited to this.
Any type, such as T and bipolar, is possible.

The feedback circuit 39 has an output terminal 37
The feedback MOS transistor Q4
It comprises a Zener diode D whose cathode is connected to one gate electrode, respectively, and a resistor R connected between the gate electrode of the feedback MOS transistor Q41 and the power supply VDD. And the output signal VOUT
Is offset by the Zener diode D and applied to the gate electrode of the feedback MOS transistor Q41.

As described above, the feedback MOS transistor Q41 is provided between the power supply terminal 38 for supplying the power supply voltage to the source follower circuit 36 and the power supply VDD.
By applying a feedback signal corresponding to the output signal VOUT to the gate electrode of the feedback MOS transistor Q41, an existing C
Also in the CD area sensor, since the conversion efficiency can be increased, the sensitivity can be greatly improved.

In this example, the existing CC that has been commercialized
The case where the present invention is applied to the D area sensor has been described. However, the present invention is not limited to this.
The present invention can be similarly applied to a D linear sensor, a CCD delay element, and the like.

The output signal VOUT is given as a feedback signal to the gate electrode of the feedback MOS transistor Q41 through the feedback circuit 39. However, if the threshold voltage Vth of the feedback MOS transistor Q41 is a desired one from the beginning, DC The feedback circuit 39 for offset may be omitted, and the output signal VOUT may be directly supplied to the gate electrode of the feedback MOS transistor Q41 as a feedback signal.

[0047]

As described above, according to the output circuit of the charge-voltage converter according to the present invention, the feedback transistor is connected between the drive transistor of the source follower circuit and the power supply, and the feedback transistor is connected to the output signal of the drive transistor. By applying the feedback signal to the gate electrode of the feedback transistor, the decrease in gain due to the short channel effect in the drive transistor is less likely to occur, and the circuit gain increases.
If the conversion efficiency can be greatly improved and the conversion efficiency can be maintained as it is, noise such as 1 / f noise can be reduced and S / N can be improved.

Further, by applying the output circuit according to the present invention to a charge-voltage converter of a charge transfer device such as a CCD area sensor, the conversion efficiency can be greatly increased, so that the sensitivity is greatly improved. You can do it.

Further, in a commercialized charge transfer device such as an existing CCD area sensor, a feedback transistor is connected between a power supply terminal for supplying a power supply voltage to the output circuit from the outside and a power supply, By providing a feedback signal corresponding to the output signal to the control electrode, conversion efficiency and, consequently, sensitivity of existing products can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a modification of the first embodiment.

FIG. 3 is a circuit diagram showing another modification of the first embodiment.

FIG. 4 is a schematic configuration diagram of a CCD area sensor to which the present invention is applied.

FIG. 5 is a schematic configuration diagram showing a second embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating an example of a configuration of a charge-voltage converter and an output circuit.

FIG. 7 is a plan pattern diagram showing a conventional example.

FIG. 8 is a circuit diagram showing another conventional example.

[Explanation of symbols]

11, 25, 35 Charge-voltage conversion unit 12, 26, 36 Source follower circuit 13, 39 Feedback circuit 21, 31 Sensor unit 22, 32 Vertical CCD 24, 34 Horizontal CCD Q11 First stage drive MOS transistor Q31, Q31 ', Q41 Feedback MOS Transistor

Claims (7)

[Claims] A source follower circuit connected to the charge-voltage converter, a feedback transistor connected between a drive transistor of the source follower circuit and a power supply, and an output signal of the drive transistor. And a feedback circuit for providing the feedback signal to the control electrode of the feedback transistor. 2. The method according to claim 1, wherein the feedback transistor is a surface channel MOS transistor, and the feedback circuit superimposes an AC component of an output signal of the drive transistor on a predetermined bias voltage to generate the feedback signal. The output circuit of the charge-voltage converter according to claim 1. 3. The feedback transistor is connected between a drive transistor of each source follower stage and a power supply, and the feedback circuit is provided for each feedback transistor of each source follower stage. Item 3. An output circuit of the charge-voltage converter according to Item 2. 4. The feedback circuit according to claim 1, wherein the feedback circuit comprises a source follower stage next to the source follower stage to which the feedback transistor is connected, and an output signal of the stage is used as the feedback signal. Output circuit of the charge-voltage converter. 5. The output circuit according to claim 1, wherein a reset voltage of the charge-voltage converter is set lower than a power supply voltage. 6. A charge transfer section for transferring a signal charge, a charge-voltage conversion section for converting a signal charge transferred by the charge transfer section into a voltage, and an output circuit connected to the charge-voltage conversion section. A charge transfer device, wherein the output circuit includes at least one source follower circuit connected to the charge-voltage converter, a feedback transistor connected between a drive transistor and a power supply of the source follower circuit, A charge transfer device for providing a feedback signal corresponding to an output signal of the drive transistor to a control electrode of the feedback transistor. 7. A charge transfer section for transferring a signal charge, a charge-voltage conversion section for converting a signal charge transferred by the charge transfer section into a voltage, and an output circuit connected to the charge-voltage conversion section on the same chip. A charge transfer device having a power supply terminal mounted thereon for externally supplying a power supply voltage to the output circuit, and an output terminal for outputting an output signal of the output circuit to the outside; A charge transfer device comprising: a feedback transistor connected therebetween; and a feedback circuit for providing a feedback signal corresponding to an output signal of the drive transistor to a control electrode of the feedback transistor.