JP3658267B2

JP3658267B2 - SIGNAL TRANSFER METHOD, SIGNAL TRANSFER METHOD FOR SOLID-STATE IMAGING DEVICE USING THE SIGNAL TRANSFER METHOD, SIGNAL TRANSFER DEVICE, AND SOLID-STATE IMAGING DEVICE USING THE SIGNAL TRANSFER DEVICE

Info

Publication number: JP3658267B2
Application number: JP2000059210A
Authority: JP
Inventors: 孝正桜木
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 2000-03-03
Filing date: 2000-03-03
Publication date: 2005-06-08
Anticipated expiration: 2020-03-03
Also published as: JP2001251562A

Description

【０００１】
【発明の属する技術分野】
本発明は信号転送方法と該信号転送方法を用いた固体撮像装置の信号転送方法、信号転送装置及び該信号転送装置を用いた固体撮像装置に係わり、特に、複数の信号源から、各複数の信号源ごとに設けられたスイッチ手段を介して順次信号を共通線に転送し、入力端子が該共通線に接続され且つ入出力端子が容量を介して接続された増幅手段を通して、該信号を転送する信号転送方法と該信号転送方法を用いた固体撮像装置の信号転送方法、信号転送装置及び該信号転送装置を用いた固体撮像装置に関する。
【０００２】
【従来の技術】
複数の信号源からの信号を信号転送用スイッチを介して共通線に転送する信号転送装置は、例えば固体撮像装置に用いられている。
【０００３】
図５は従来のＭＯＳ型固体撮像装置の模式的構成図である。図５に示すように、センサーセル１は行列に２次元的に配置されており、垂直シフトレジスタ１１からの信号２（２−１，２−２，…）によってセンサーセル１を活性化させたり、リセット状態にしたりする制御が行われる。
【０００４】
各センサーセル１の出力端子は垂直信号線５（５−１，５−２，…，５−ｎ）に接続され、センサーセル１で発生した信号電圧はこの垂直信号線５に現われ、クランプ容量３（３−１，３−２，…，３−ｎ）に電荷として保存される。図示されないスイッチ、容量などで各センサーセル１で発生するバラツキをキャンセルする場合が多い。クランプ容量３に保存されている信号電荷は、水平シフトレジスタ１２からの水平選択信号７（７−１，７−２，…，７−ｎ）によって水平選択スイッチ４（４−１，４−２，…，４−ｎ）が順次導通することにより、水平信号線６を介して負帰還容量８を有する差動増幅器９の反転入力端子へ転送され、出力端子１３から電圧として出力される。差動増幅器９の非反転入力端子は基準電圧源１０に接続される。
【０００５】
【発明が解決しようとする課題】
上記固体撮像装置において、水平選択スイッチ４は通常ＭＯＳトランジスタで構成され、例えば水平選択スイッチ４として図６に示すようなＮＭＯＳトランジスタが用いられる。図６において、２１はゲート、２２はｎ型半導体で形成されたソースまたはドレイン拡散領域、２３はｐ型のウェル拡散領域、２５はゲート酸化膜である。図６から分かるように、ソース／ドレイン領域２２とＰウェル領域２３との間にはＰＮ接合容量が形成され、Ｐウェル領域２３は通常半導体集積回路内での最低電位であるＧＮＤへ接続されるため、ソース／ドレイン領域２２はＧＮＤを対極に、ある値のＰＮ接合容量を有することになる（以降、これをＣ_jとする）。また図６で示した２４は、ソース／ドレイン領域２２の拡散がある程度横方向にも行われることによる、ゲート２１との重なり部分を示しており、ゲート酸化膜２５を誘電体にした、いわゆる重なり容量がゲート２１とソース／ドレイン領域２２との間に形成される（以降、これをＣ_ovとする）。
【０００６】
したがって、図５における水平信号線６には、接続された水平選択スイッチ４が上記寄生容量Ｃ_j，Ｃ_ovを有するために、図７に示すような等価回路での容量１５，１６が付随することになる。図７は従来例である図５の垂直信号線５から出力端子１３までの信号転送経路の等価回路を示している。
【０００７】
図７において、５（５−１，５−２，…，５−ｎ）は垂直信号線、３（３−１，３−２，…，３−ｎ）はクランプ容量、４（４−１，４−２，…，４−ｎ）は水平転送スイッチ、６は水平信号線、７（７−１，７−２，…，７−ｎ）は水平シフトレジスタ１２から出力される水平選択線、８は出力アンプ９によって、信号電荷を信号電圧に変換するための負帰還容量、１４（１４−１，１４−２，…，１４−ｎ）は水平選択線７を駆動する水平シフトレジスタ１２内の駆動ゲートの出力インピーダンスを表し、図７では例として水平転送スイッチ４をＮＭＯＳトランジスタで構成し、その水平転送スイッチがＯＦＦとなる水平選択線７が“Ｌ”レベルである時に、ＧＮＤに対して形成される前記駆動ゲートの出力インピーダンスを出力インピーダンス１４としている。１５（１５−１，１５−２，…，１５−ｎ）は水平転送スイッチ４であるＮＭＯＳトランジスタのソース−ウェル間のＰＮ接合寄生容量を表し、１６（１６−１，１６−２，…，１６−ｎ）は、このＮＭＯＳトランジスタのゲート−ソース間の重なり容量を表している。図７から明かなように水平信号線６には上記の寄生容量の総和として、
Ｃ_tot＝ｎ×（Ｃ_j＋Ｃ_ov）
（ｎは固体撮像装置の垂直信号線数）
の容量が付随し、固体撮像装置の総画素数が数十万〜数百万画素のような多画素になると、上記寄生容量Ｃ_totは数ｐＦ〜数十ｐＦの大きさになってしまい、この寄生容量Ｃ_totの容量は出力アンプ９によって駆動されることになり、出力アンプ９から見た容量Ｃ_totを含めた等価回路は図８のようになる。
【０００８】
図８において、９は出力アンプ、８は負帰還容量、ｒ₀は出力アンプ９の等価出力インピーダンス、Ｖ_Nは出力アンプの入力換算ランダムノイズ源である。したがって、図８での出力アンプ９は出力インピーダンス０、ランダムノイズ０の理想アンプとしている。出力アンプ９の出力から負極入力端子（−）に至る伝達関数は次式のように表せる。
【０００９】
【数１】

ここで、Ｓはラプラス演算子、Ｃ_Nは負帰還容量８の容量値である。
【００１０】
上式（数１）から明らかなように、伝達関数はローパスフィルターの形であり、寄生容量Ｃ_totの値によってそのカットオフ周波数が影響される。したがって寄生容量Ｃ_totの存在によって出力アンプ９はその帯域が狭くなり、出力駆動速度が低下してしまうという課題が生じることになる。
【００１１】
また、出力アンプ９のもつランダムノイズ（Ｖ_N）が寄生容量Ｃ_totによって増幅されてしまうことになる（Ｖ_N×（Ｃ_tot／Ｃ_N））。
【００１２】
本発明の目的は、出力アンプにつながる寄生容量を低減することができる信号転送方法と該信号転送方法を用いた固体撮像装置の信号転送方法、信号転送装置及び該信号転送装置を用いた固体撮像装置を提供することにある。
【００１３】
【課題を解決するための手段】
本発明の信号転送方法は、複数の信号源から、各複数の信号源ごとに設けられたスイッチ手段を介して順次信号電荷を共通線に転送し、該共通線に転送された信号電荷を電圧に変換して出力する電荷電圧変換手段を通して信号を転送する信号転送方法において、
前記電荷電圧変換手段は、非反転入力端子に基準電圧源が接続され、反転入力端子に前記共通線に接続される、差動増幅器であり、
前記信号源は、光電変換素子と該光電変換素子からの信号を蓄積する容量とを含み、又は複数の光電変換素子と該複数の光電変換素子から順次転送される信号を蓄積する容量とを含み、
信号電荷を前記共通線に転送する場合に、前記共通線の信号レベルに基づいて、前記共通線につながる寄生容量の両端子間の電圧の変動をなくす又は減少されるように制御することを特徴とするものである。
【００１５】
本発明の固体撮像装置の信号転送方法は、上記本発明の信号転送方法を用いたものである。
【００１６】
本発明の信号転送装置は、複数の信号源と、各複数の信号源ごとに設けられた絶縁ゲート型トランジスタからなるスイッチ手段と、各スイッチ手段を介して順次、前記複数の信号源からの信号電荷が転送される共通線と、該共通線に転送された信号電荷を電圧に変換して出力する、前記共通線に接続された電荷電圧変換手段と、該共通線の転送信号電圧に直流オフセット電圧を加えた電圧を前記絶縁ゲート型トランジスタのバックゲートに入力する入力手段とを有し、
前記電荷電圧変換手段は、非反転入力端子に基準電圧源が接続され、反転入力端子に前記共通線に接続される、差動増幅器であり、
前記信号源は、光電変換素子と該光電変換素子からの信号を蓄積する容量とを含む、又は複数の光電変換素子と該複数の光電変換素子から順次転送される信号を蓄積する容量とを含むことを特徴とするものである。
【００１７】
本発明の信号転送装置は、複数の信号源と、
各複数の信号源ごとに設けられたスイッチ手段と、
各スイッチ手段を介して順次、前記複数の信号源からの信号電荷が転送される共通線と、
前記共通線に転送された信号電荷を電圧に変換して出力する、前記共通線に接続された電荷電圧変換手段と、
信号を前記共通線に転送する場合に、前記共通線の信号レベルに基づいて、前記共通線につながる寄生容量の両端子間の電圧の変動をなくす又は減少されるように制御する寄生容量制御手段とを有し、
前記電荷電圧変換手段は、非反転入力端子に基準電圧源が接続され、反転入力端子に前記共通線に接続される、差動増幅器であり、
前記信号源は、光電変換素子と該光電変換素子からの信号を蓄積する容量とを含む、又は複数の光電変換素子と該複数の光電変換素子から順次転送される信号を蓄積する容量とを含むことを特徴とするものである。
【００１８】
本発明の固体撮像装置は、上記本発明の信号転送装置を用いたものである。
【００１９】
本発明の好適な態様は、入出力端子が容量を介して接続された出力アンプの入力端子に付随する寄生容量、例えば共通線に接続される水平転送スイッチに付随する２つの寄生容量（ソース−ウェル間ＰＮ接合容量Ｃ_jとゲート−ソース間重なり容量Ｃ_ov）を低減するものであり、寄生容量そのものの値を小さくするのではなく、寄生容量の端子間電圧を一定又は一定に近い状態にすることで、寄生容量への電荷の流入出をなくし、見かけ上容量として機能しないようにする。上記２つの寄生容量Ｃ_j，Ｃ_ovの一方の端子は共通線となる水平信号線に接続されているので、その水平信号線の電圧に等しい電圧が上記２つの寄生容量のもう一方の端子に印加されるようにすれば、上記２つの容量の端子間電圧は一定（この場合は０）になる。
【００２０】
ただし、ソースとバックゲート（基板側の電極）との間にあるソース−ウェル間のＰＮ接合が常に０Ｖもしくは逆バイアスになり、スイッチとしての機能を損なわないようにしたり、水平シフトレジスタ内の駆動ゲート出力によって水平転送スイッチがＯＦＦする場合にはＯＦＦが維持されるよう、２つの寄生容量のもう一方の端子へ印加する電圧は、水平信号線の電圧にある値のＤＣ（直流）電圧を足すことが望ましい。
【００２１】
なお、本発明における寄生容量としてはスイッチ手段の寄生容量が挙げられるが、特にスイッチ手段に限定されず、共通線につながる他の素子により生ずる寄生容量も含まれ、かかる寄生容量の制御もスイッチ手段の寄生容量の制御と同様に行うことができる。さらに、本発明のスイッチ手段の寄生容量の制御は共通線からの信号に基づいて行う場合に限定されず、共通線の信号電圧と同様の電圧変動を行う信号発生手段等により（すなわち、スイッチ手段を介して出力される信号に対応する信号により）寄生容量の制御を行ってもよい。
【００２２】
本発明は固体撮像装置に好適に用いられるものであるが、特に固体撮像装置に限定されず、半導体メモリ、フラットディスプレイ等の表示装置等における信号転送装置に用いることができる。
【００２３】
信号源からの信号を転送するスイッチ手段としては、バイポーラトランジスタ，ＣＭＯＳトランジスタ，ＭＯＳトランジスタ等で構成されるトランジスタスイッチ、マイクロスイッチ等を用いることができる。
【００２４】
【実施例】
以下、本発明の実施例について図面を用いて詳細に説明する。
【００２５】
図１は本発明の固体撮像装置における一実施例を示す回路構成図であり、センサーセルを行列に２次元的に配置したＭＯＳ固体撮像装置を示している。
【００２６】
図１において、１はセンサーセルであり、垂直シフトレジスタ１１からの信号２（２−１，２−２，…，２−ｎ）によって活性化したり、リセット状態になる。各センサーセル１の出力は垂直信号線５（５−１，５−２，…，５−ｎ）に接続され、センサーセル１で発生する信号電圧はこの垂直信号線５に現われ、クランプ容量３（３−１，３−２，…，３−ｎ）に信号電荷として蓄えられ、その後水平シフトレジスタ１２からの水平選択信号７（７−１，７−２，…，７−ｎ）によって水平選択スイッチ４（４−１，４−２，…，４−ｎ）が順次ＯＮし、クランプ容量３に蓄えられていた信号電荷が、水平信号線６を介して負帰還容量８を有する差動増幅器９の反転入力端子へ転送され、出力端子１３から電圧として出力される。差動増幅器９の非反転入力端子は基準電圧源１０に接続される。２０は信号転送装置となる回路部分を示す。
【００２７】
ここで例として、１列目の垂直信号線の信号電荷をクランプ容量を介して水平信号線へ伝達する場合について説明する。この場合、水平シフトレジスタ１２内の第１列目の水平転送スイッチ４−１を駆動するＣＭＯＳインバーター（１５−１，１６−１）の入力端子１７−１は“Ｌ”レベルになり、同水平シフトレジスター内の他のＣＭＯＳインバーター（１５−２，１６−２，…，１５−ｎ，１６−ｎ）の入力端子（１７−２，…，１７−ｎ）は“Ｈ”レベルになっているとする。ＣＭＯＳインバーターの構成において、ＰＭＯＳトランジスタ１５（１５−１，１５−２，…，１５−ｎ）のソースは電源へ、ドレインは出力端子に接続されており、ＮＭＯＳトランジスタ１６（１６−１，１６−２，…，１６−ｎ）のドレインは出力端子に接続され、ソースはバッファーアンプ１８の出力端子に接続された配線１９に接続されている。図１に示すＣＭＯＳインバーターが通常のＣＭＯＳインバーターと異なるのは、ＮＭＯＳトランジスタ１６のソースが、バッファーアンプ１８の出力端子に接続された配線１９に接続されていることである。
【００２８】
入力端子１７−１は“Ｌ”レベルであるので、ＰＭＯＳトランジスタ１５−１はＯＮ、ＮＭＯＳトランジスタ１６−１はＯＦＦとなり、第１列目の水平選択信号線７−１は“Ｈ”レベルである。他の入力端子１７−２，…，１７−ｎは“Ｈ”レベルであるので、ＰＭＯＳトランジスタ１５−２，…，１５−ｎはＯＦＦ、ＮＭＯＳトランジスタ１６−２，…，１６−ｎはＯＮになり、第２列目以降の水平選択信号線７−２，…，７−ｎの電位はバッファーアンプ１８の出力電位に等しい値になる。バッファーアンプ１８は、その入力端子に接続された水平信号線６の電位に、ある値のＤＣ電圧を加えた電圧を出力するように設定されているものとすると、第２列目以降の水平選択信号線７−２，…，７−ｎの電位も（水平信号線６の電位＋ある値のＤＣ電圧）に等しくなる。
【００２９】
したがって、第２列目以降の水平選択スイッチ４−２，…，４−ｎのゲート−ソース間電圧は（あるＤＣ電圧）になり、一定になる。
【００３０】
また配線１９は各水平選択スイッチ４のウェルにも接続されており、上記ゲートの場合と同様にソース−ウェル間電圧も一定になる。
【００３１】
以上の説明から２つの寄生容量（ゲート−ソース間重なり容量Ｃ_ov、ソース−ウェル間重なり容量Ｃ_j）の端子間電圧は一定になり、電荷の移動がなくなるため見かけ上容量としては機能しなくなる。
【００３２】
図２は図１におけるバッファーアンプ１８の一例であって、ＮＭＯＳソースフォロワーとなっており、３１は入力端子、３２は出力端子、３３はバイアス電流源である。
【００３３】
この場合の入力端子と出力端子の端子間電圧はＮＭＯＳトランジスタのゲート−ソース間電圧に等しく、ＮＭＯＳトランジスタのゲート幅、ゲート長の大きさや電流源３３の電流値でほぼ任意に設定でき、その値は図１における水平転送スイッチ４でのソース／ドレイン−ウェル間のＰＮ接合が、あるゆる駆動条件下で順バイアスにならないように設定すれば良い。
【００３４】
なお、図１における水平シフトレジスタ１２での水平選択線７を駆動するゲートはインバーターに限らず、水平転送スイッチ４がＯＦＦのときに水平選択線７の電位が図１のバッファーアンプ１８の出力電位に等しくなり、水平転送スイッチ４がＯＮになる時には“Ｈ”レベルが出力されるよう構成すれば良い。さらに増幅器９は差動型である必要性はなく、ＣＭＯＳインバーターのような単極入力端子の増幅器でも全く同様の動作となる。また図１では垂直信号線の信号電荷をクランプ容量を介して水平信号線へ伝達する場合について説明したが、サンプル−ホールド容量を介して水平信号線へ信号電荷を伝達する場合も全く同様の効果が得られる。
【００３５】
図３は本実施例に用いることのできる固体撮像装置における画素の等価回路図である。なお、ここではエリアセンサに用いる画素構成を示しているが、画素を一列に配列する場合は選択スイッチＱ１４は設けなくて良い。
【００３６】
図３において、５０５が光電変換部にあたるホトダイオードである。Ｑ１３が増幅手段にあたるソースフォロワアンプの入力ＭＯＳトランジスタであり、Ｑ１４は読み出す行を選択するための選択スイッチである。ソースフォロワの定電流負荷は図示していないが、信号出力線５０４に接続されている。Ｑ１２はソースフォロワの入力端子をリセットするためのリセットスイッチであり、増幅手段の入力部のリセット手段にあたる。Ｑ１１は、ホトダイオード５０５の光信号を信号増幅手段であるソースフォロワの入力部に転送するための転送スイッチであり、電荷転送手段にあたる。５０１は電源線、５０２はリセットスイッチ線、５０３は選択スイッチ線、５０６は転送スイッチ線である。
【００３７】
図４は画素を一列に配列する場合の本発明の固体撮像装置における実施例を示す回路構成図である。かかる固体撮像装置においても図１の固体撮像装置と同様な本発明の効果を得ることができる。本実施例において、寄生容量制御手段は、バッファーアンプ１８と、バッファーアンプ１８と水平選択スイッチのバックゲート及びＮＭＯＳトランジスタ１６とを接続する配線１９とで構成されている。
【００３８】
【発明の効果】
以上説明したように、本発明によれば、共通線につながる寄生容量を見かけ上なくすることによって、出力アンプの入力端子、すなわち水平信号線に付随する寄生容量を大幅に削減し、出力アンプの高速動作を可能にし、かつ出力アンプのもつランダムノイズの増大を防ぐことができる。
【図面の簡単な説明】
【図１】本発明の固体撮像装置における一実施例を示す回路構成図である。
【図２】上記本発明の実施例の中のバッファーアンプの一例を示す図である。
【図３】本実施例に用いることのできる固体撮像装置における画素の等価回路図である。
【図４】画素を一列に配列する場合の本発明の固体撮像装置における実施例を示す回路構成図である。
【図５】従来のＭＯＳ型固体撮像装置の模式的構成図である。
【図６】ＭＯＳトランジスタの有する寄生容量を説明する断面図である。
【図７】従来例における問題を説明する等価回路図である。
【図８】従来例における問題を説明する等価回路図である。
【符号の説明】
１センサーセル
２制御信号
３クランプ容量
４水平選択スイッチ
５垂直信号線
６垂直信号線
７水平選択信号
８負帰還容量
９出力アンプ
１０基準電圧源
１１垂直シフトレジスタ
１２水平シフトレジスタ
１３出力端子
１４出力インピーダンス
１５ＰＭＯＳトランジスタ
１６ＮＭＯＳトランジスタ
１７入力端子
１８バッファーアンプ
１９配線[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal transfer method, a signal transfer method of a solid-state image pickup device using the signal transfer method, a signal transfer device, and a solid-state image pickup device using the signal transfer device, and in particular, from a plurality of signal sources, The signal is sequentially transferred to the common line through the switch means provided for each signal source, and the signal is transferred through the amplification means having the input terminal connected to the common line and the input / output terminal connected via the capacitor. The present invention relates to a signal transfer method, a signal transfer method of a solid-state imaging device using the signal transfer method, a signal transfer device, and a solid-state imaging device using the signal transfer device.
[0002]
[Prior art]
A signal transfer device that transfers signals from a plurality of signal sources to a common line via a signal transfer switch is used in, for example, a solid-state imaging device.
[0003]
FIG. 5 is a schematic configuration diagram of a conventional MOS solid-state imaging device. As shown in FIG. 5, the sensor cells 1 are two-dimensionally arranged in a matrix, and the sensor cells 1 are activated by signals 2 (2-1, 2-2,...) From the vertical shift register 11. Then, control for resetting is performed.
[0004]
The output terminal of each sensor cell 1 is connected to the vertical signal line 5 (5-1, 5-2,..., 5-n), and the signal voltage generated in the sensor cell 1 appears on the vertical signal line 5, and the clamp capacitance 3 (3-1, 3-2,..., 3-n) as a charge. In many cases, a variation occurring in each sensor cell 1 is canceled by a switch, a capacity, etc., not shown. The signal charges stored in the clamp capacitor 3 are converted into horizontal selection switches 4 (4-1, 4-2) by horizontal selection signals 7 (7-1, 7-2,..., 7-n) from the horizontal shift register 12. ,..., 4-n) are sequentially conducted to be transferred to the inverting input terminal of the differential amplifier 9 having the negative feedback capacitor 8 through the horizontal signal line 6 and output as a voltage from the output terminal 13. The non-inverting input terminal of the differential amplifier 9 is connected to the reference voltage source 10.
[0005]
[Problems to be solved by the invention]
In the solid-state imaging device, the horizontal selection switch 4 is usually composed of a MOS transistor. For example, an NMOS transistor as shown in FIG. 6 is used as the horizontal selection switch 4. In FIG. 6, 21 is a gate, 22 is a source or drain diffusion region formed of an n-type semiconductor, 23 is a p-type well diffusion region, and 25 is a gate oxide film. As can be seen from FIG. 6, a PN junction capacitance is formed between the source / drain region 22 and the P well region 23, and the P well region 23 is normally connected to GND, which is the lowest potential in the semiconductor integrated circuit. Therefore, the source / drain region 22 has a certain value of PN junction capacitance with GND as the counter electrode (hereinafter referred to as C _j ). Reference numeral 24 shown in FIG. 6 indicates an overlapping portion with the gate 21 due to the diffusion of the source / drain region 22 to some extent in the lateral direction, and the so-called overlapping with the gate oxide film 25 as a dielectric. A capacitance is formed between the gate 21 and the source / drain region 22 (hereinafter referred to as _Cov ).
[0006]
Accordingly, the horizontal signal line 6 in FIG. 5 is accompanied by the

capacitors

15 and 16 in the equivalent circuit as shown in FIG. 7 because the connected horizontal selection switch 4 has the parasitic capacitances C _j and C _ov . It will be. FIG. 7 shows an equivalent circuit of a signal transfer path from the vertical signal line 5 to the output terminal 13 of FIG.
[0007]
In FIG. 7, 5 (5-1, 5-2,..., 5-n) are vertical signal lines, 3 (3-1, 3-2,..., 3-n) are clamp capacitors, 4 (4-1). , 4-2,..., 4-n) are horizontal transfer switches, 6 is a horizontal signal line, and 7 (7-1, 7-2,..., 7-n) are horizontal selection lines output from the horizontal shift register 12. , 8 are negative feedback capacitors for converting signal charges into signal voltages by the output amplifier 9, and 14 (14-1, 14-2,..., 14-n) are horizontal shift registers 12 for driving the horizontal selection line 7. In FIG. 7, the horizontal transfer switch 4 is composed of an NMOS transistor as an example, and when the horizontal selection line 7 at which the horizontal transfer switch is turned off is at “L” level, The output impedance of the drive gate formed by It is a dance 14. 15 (15-1, 15-2,..., 15-n) represents the PN junction parasitic capacitance between the source and well of the NMOS transistor which is the horizontal transfer switch 4, and 16 (16-1, 16-2,. 16-n) represents the overlap capacitance between the gate and source of this NMOS transistor. As is clear from FIG. 7, the horizontal signal line 6 has the total parasitic capacitance as described above.
C _tot = n × (C _j + C _ov )
(N is the number of vertical signal lines of the solid-state imaging device)
When the total number of pixels of the solid-state imaging device is several hundred thousand to several million pixels, the parasitic capacitance C _tot becomes several pF to several tens pF. The parasitic capacitance C _tot is driven by the output amplifier 9, and an equivalent circuit including the capacitance C _tot viewed from the output amplifier 9 is as shown in FIG.
[0008]
In FIG. 8, 9 is an output amplifier, 8 is a negative feedback capacitor, r ₀ is an equivalent output impedance of the output amplifier 9, and V _N is an input conversion random noise source of the output amplifier. Therefore, the output amplifier 9 in FIG. 8 is an ideal amplifier having an output impedance of 0 and a random noise of 0. A transfer function from the output of the output amplifier 9 to the negative input terminal (−) can be expressed by the following equation.
[0009]
[Expression 1]

Here, S is a Laplace operator, and C _N is a capacitance value of the negative feedback capacitor 8.
[0010]
As is clear from the above equation (Equation 1), the transfer function is in the form of a low-pass filter, and its cutoff frequency is affected by the value of the parasitic capacitance C _tot . Accordingly, the presence of the parasitic capacitance C _tot causes a problem that the output amplifier 9 has a narrow band and the output driving speed is reduced.
[0011]
Further, the random noise (V _N ) of the output amplifier 9 is amplified by the parasitic capacitance C _tot (V _N × (C _tot / C _N )).
[0012]
An object of the present invention is to provide a signal transfer method capable of reducing parasitic capacitance connected to an output amplifier, a signal transfer method of a solid-state imaging device using the signal transfer method, a signal transfer device, and a solid-state imaging using the signal transfer device To provide an apparatus.
[0013]
[Means for Solving the Problems]
In the signal transfer method of the present invention, signal charges are sequentially transferred from a plurality of signal sources to a common line via switch means provided for each of the plurality of signal sources, and the signal charges transferred to the common line are converted into voltages. In a signal transfer method for transferring a signal through charge-voltage conversion means for converting into
The charge voltage conversion means is a differential amplifier in which a reference voltage source is connected to a non-inverting input terminal and the inverting input terminal is connected to the common line,
The signal source includes a photoelectric conversion element and a capacitor for storing signals from the photoelectric conversion element, or includes a plurality of photoelectric conversion elements and a capacitor for storing signals sequentially transferred from the plurality of photoelectric conversion elements. ,
When transferring signal charges to the common line, control is performed so as to eliminate or reduce voltage fluctuation between both terminals of the parasitic capacitance connected to the common line based on the signal level of the common line. It is what.
[0015]
The signal transfer method of the solid-state imaging device of the present invention uses the signal transfer method of the present invention.
[0016]
The signal transfer device according to the present invention includes a plurality of signal sources, switch means including insulated gate transistors provided for each of the plurality of signal sources, and signals from the plurality of signal sources sequentially through the switch means. A common line to which charges are transferred, a charge voltage converting means connected to the common line for converting the signal charge transferred to the common line to output voltage, and a DC offset to the transfer signal voltage of the common line Input means for inputting a voltage to which the voltage is applied to the back gate of the insulated gate transistor;
The charge voltage conversion means is a differential amplifier in which a reference voltage source is connected to a non-inverting input terminal and the inverting input terminal is connected to the common line,
The signal source includes a photoelectric conversion element and a capacitor for storing signals from the photoelectric conversion element, or includes a plurality of photoelectric conversion elements and a capacitor for storing signals sequentially transferred from the plurality of photoelectric conversion elements. It is characterized by this.
[0017]
The signal transfer device of the present invention includes a plurality of signal sources,
Switch means provided for each of the plurality of signal sources;
A common line to which signal charges from the plurality of signal sources are sequentially transferred through the switch means ;
Charge voltage conversion means connected to the common line, which converts the signal charge transferred to the common line into a voltage and outputs the voltage.
When transferring a signal to the common line, parasitic capacitance control means for controlling fluctuations in voltage between both terminals of the parasitic capacitance connected to the common line to be eliminated or reduced based on the signal level of the common line And
The charge voltage conversion means is a differential amplifier in which a reference voltage source is connected to a non-inverting input terminal and the inverting input terminal is connected to the common line,
The signal source includes a photoelectric conversion element and a capacitor for storing signals from the photoelectric conversion element, or includes a plurality of photoelectric conversion elements and a capacitor for storing signals sequentially transferred from the plurality of photoelectric conversion elements. It is characterized by this.
[0018]
The solid-state imaging device of the present invention uses the signal transfer device of the present invention.
[0019]
According to a preferred aspect of the present invention, a parasitic capacitance associated with an input terminal of an output amplifier having an input / output terminal connected via a capacitor, for example, two parasitic capacitances associated with a horizontal transfer switch connected to a common line (source − The inter-well PN junction capacitance C _j and the gate-source overlap capacitance C _ov ) are reduced, and instead of reducing the value of the parasitic capacitance itself, the voltage between the terminals of the parasitic capacitance is made constant or nearly constant. By doing so, the inflow and outflow of electric charge to and from the parasitic capacitance is eliminated, so that it does not function as a capacitance apparently. Since one terminal of the two parasitic capacitors C _j and C _ov is connected to a horizontal signal line that is a common line, a voltage equal to the voltage of the horizontal signal line is applied to the other terminal of the two parasitic capacitors. If applied, the voltage between the terminals of the two capacitors becomes constant (in this case, 0).
[0020]
However, the PN junction between the source and the well between the source and the back gate (substrate side electrode) is always 0 V or reverse bias, so that the function as a switch is not impaired, or driving in the horizontal shift register When the horizontal transfer switch is turned off by the gate output, the voltage applied to the other terminal of the two parasitic capacitors is added with a DC (direct current) voltage of a certain value in the voltage of the horizontal signal line so that the OFF is maintained. It is desirable.
[0021]
The parasitic capacitance in the present invention includes the parasitic capacitance of the switch means. However, the parasitic capacitance is not particularly limited to the switch means, and includes parasitic capacitance generated by other elements connected to the common line. This can be performed in the same manner as the parasitic capacitance control. Furthermore, the parasitic capacitance control of the switch means of the present invention is not limited to the case where it is performed based on the signal from the common line, but by signal generating means or the like that performs the same voltage fluctuation as the signal voltage of the common line (that is, the switch means) The parasitic capacitance may be controlled (by a signal corresponding to the signal output via).
[0022]
The present invention is preferably used for a solid-state imaging device, but is not particularly limited to a solid-state imaging device, and can be used for a signal transfer device in a display device such as a semiconductor memory or a flat display.
[0023]
As a switch means for transferring a signal from a signal source, a transistor switch, a micro switch, or the like composed of a bipolar transistor, a CMOS transistor, a MOS transistor, or the like can be used.
[0024]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0025]
FIG. 1 is a circuit configuration diagram showing an embodiment of the solid-state imaging device of the present invention, and shows a MOS solid-state imaging device in which sensor cells are two-dimensionally arranged in a matrix.
[0026]
In FIG. 1, reference numeral 1 denotes a sensor cell which is activated or reset by a signal 2 (2-1, 2-2,..., 2-n) from the vertical shift register 11. The output of each sensor cell 1 is connected to a vertical signal line 5 (5-1, 5-2,..., 5-n), and the signal voltage generated in the sensor cell 1 appears on this vertical signal line 5, and the clamp capacitor 3 (3-1, 3-2,..., 3-n) are stored as signal charges, and then are horizontal by horizontal selection signals 7 (7-1, 7-2,..., 7-n) from the horizontal shift register 12. The selection switches 4 (4-1, 4-2,..., 4-n) are sequentially turned ON, and the signal charge stored in the clamp capacitor 3 has a negative feedback capacitor 8 via the horizontal signal line 6. It is transferred to the inverting input terminal of the amplifier 9 and output as a voltage from the output terminal 13. The non-inverting input terminal of the differential amplifier 9 is connected to the reference voltage source 10. Reference numeral 20 denotes a circuit portion serving as a signal transfer device.
[0027]
Here, as an example, a case will be described in which the signal charge of the vertical signal line in the first column is transmitted to the horizontal signal line through the clamp capacitor. In this case, the input terminal 17-1 of the CMOS inverter (15-1, 16-1) that drives the horizontal transfer switch 4-1 in the first column in the horizontal shift register 12 becomes “L” level. The input terminals (17-2,..., 17-n) of other CMOS inverters (15-2, 16-2,..., 15-n, 16-n) in the shift register are at the “H” level. And In the configuration of the CMOS inverter, the source of the PMOS transistor 15 (15-1, 15-2,..., 15-n) is connected to the power supply, the drain is connected to the output terminal, and the NMOS transistor 16 (16-1, 16-). 2,..., 16-n) are connected to the output terminal, and the source is connected to the wiring 19 connected to the output terminal of the buffer amplifier 18. The CMOS inverter shown in FIG. 1 is different from a normal CMOS inverter in that the source of the NMOS transistor 16 is connected to the wiring 19 connected to the output terminal of the buffer amplifier 18.
[0028]
Since the input terminal 17-1 is at "L" level, the PMOS transistor 15-1 is ON, the NMOS transistor 16-1 is OFF, and the horizontal selection signal line 7-1 in the first column is at "H" level. . Since the other input terminals 17-2, ..., 17-n are at "H" level, the PMOS transistors 15-2, ..., 15-n are OFF, and the NMOS transistors 16-2, ..., 16-n are ON. Thus, the potentials of the horizontal selection signal lines 7-2,..., 7-n in the second column and thereafter are equal to the output potential of the buffer amplifier 18. Assuming that the buffer amplifier 18 is set to output a voltage obtained by adding a DC voltage of a certain value to the potential of the horizontal signal line 6 connected to its input terminal, the horizontal selection in the second column and thereafter The potentials of the signal lines 7-2,..., 7-n are also equal to (the potential of the horizontal signal line 6 + a certain value of DC voltage).
[0029]
Therefore, the gate-source voltages of the horizontal selection switches 4-2,..., 4-n in the second column and thereafter become (a certain DC voltage) and are constant.
[0030]
The wiring 19 is also connected to the well of each horizontal selection switch 4, and the source-well voltage becomes constant as in the case of the gate.
[0031]
From the above description, the voltage between the terminals of the two parasitic capacitances (gate-source overlap capacitance C _ov and source-well overlap capacitance C _j ) is constant, and the charge does not move, so that it does not function as a capacitance apparently. .
[0032]
FIG. 2 shows an example of the buffer amplifier 18 in FIG. 1, which is an NMOS source follower, 31 is an input terminal, 32 is an output terminal, and 33 is a bias current source.
[0033]
In this case, the voltage between the input terminal and the output terminal is equal to the gate-source voltage of the NMOS transistor, and can be set almost arbitrarily according to the gate width and gate length of the NMOS transistor and the current value of the current source 33. 1 may be set so that the PN junction between the source / drain and well in the horizontal transfer switch 4 in FIG. 1 does not become forward biased under any driving conditions.
[0034]
The gate for driving the horizontal selection line 7 in the horizontal shift register 12 in FIG. 1 is not limited to an inverter, and the potential of the horizontal selection line 7 when the horizontal transfer switch 4 is OFF is the output potential of the buffer amplifier 18 in FIG. And when the horizontal transfer switch 4 is turned on, the "H" level may be output. Further, the amplifier 9 does not have to be a differential type, and a single-pole input terminal amplifier such as a CMOS inverter performs the same operation. In FIG. 1, the case where the signal charge of the vertical signal line is transmitted to the horizontal signal line via the clamp capacitor has been described. However, the same effect can be obtained when the signal charge is transmitted to the horizontal signal line via the sample-hold capacitor. Is obtained.
[0035]
FIG. 3 is an equivalent circuit diagram of a pixel in a solid-state imaging device that can be used in this embodiment. Although the pixel configuration used for the area sensor is shown here, the selection switch Q14 may not be provided when the pixels are arranged in a line.
[0036]
In FIG. 3, reference numeral 505 denotes a photodiode corresponding to the photoelectric conversion unit. Q13 is an input MOS transistor of a source follower amplifier which is an amplifying means, and Q14 is a selection switch for selecting a row to be read. The constant current load of the source follower is not shown, but is connected to the signal output line 504. Q12 is a reset switch for resetting the input terminal of the source follower, and corresponds to reset means of the input section of the amplification means. Q11 is a transfer switch for transferring the optical signal of the photodiode 505 to the input part of the source follower which is signal amplification means, and corresponds to charge transfer means. Reference numeral 501 denotes a power supply line, 502 denotes a reset switch line, 503 denotes a selection switch line, and 506 denotes a transfer switch line.
[0037]
FIG. 4 is a circuit configuration diagram showing an embodiment of the solid-state imaging device of the present invention when pixels are arranged in a line. Even in such a solid-state imaging device, the same effects of the present invention as in the solid-state imaging device of FIG. 1 can be obtained. In this embodiment, the parasitic capacitance control means includes a buffer amplifier 18 and a wiring 19 that connects the buffer amplifier 18 to the back gate of the horizontal selection switch and the NMOS transistor 16.
[0038]
【The invention's effect】
As described above, according to the present invention, the parasitic capacitance connected to the common line is not apparent, thereby greatly reducing the parasitic capacitance associated with the input terminal of the output amplifier, that is, the horizontal signal line, and the output amplifier. High-speed operation is possible, and an increase in random noise of the output amplifier can be prevented.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram showing an embodiment of a solid-state imaging device of the present invention.
FIG. 2 is a diagram showing an example of a buffer amplifier in the embodiment of the present invention.
FIG. 3 is an equivalent circuit diagram of a pixel in a solid-state imaging device that can be used in this embodiment.
FIG. 4 is a circuit configuration diagram showing an embodiment of the solid-state imaging device of the present invention when pixels are arranged in a line.
FIG. 5 is a schematic configuration diagram of a conventional MOS type solid-state imaging device.
FIG. 6 is a cross-sectional view illustrating parasitic capacitance of a MOS transistor.
FIG. 7 is an equivalent circuit diagram for explaining a problem in the conventional example.
FIG. 8 is an equivalent circuit diagram for explaining a problem in the conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Sensor cell 2 Control signal 3 Clamp capacity | capacitance 4 Horizontal selection switch 5 Vertical signal line 6 Vertical signal line 7 Horizontal selection signal 8 Negative feedback capacity 9 Output amplifier 10 Reference voltage source 11 Vertical shift register 12 Horizontal shift register 13 Output terminal 14 Output impedance 15 PMOS transistor 16 NMOS transistor 17 Input terminal 18 Buffer amplifier 19 Wiring

Claims

A charge voltage that sequentially transfers signal charges from a plurality of signal sources to a common line via switch means provided for each of the plurality of signal sources, converts the signal charges transferred to the common line into a voltage, and outputs the voltage In a signal transfer method for transferring a signal through a conversion means,
The charge voltage conversion means is a differential amplifier in which a reference voltage source is connected to a non-inverting input terminal and the inverting input terminal is connected to the common line,
The signal source includes a photoelectric conversion element and a capacitor for storing signals from the photoelectric conversion element, or includes a plurality of photoelectric conversion elements and a capacitor for storing signals sequentially transferred from the plurality of photoelectric conversion elements. ,
When transferring signal charges to the common line, control is performed so as to eliminate or reduce voltage fluctuation between both terminals of the parasitic capacitance connected to the common line based on the signal level of the common line. Signal transfer method.

2. The signal transfer method according to claim 1 , wherein the switch means is an insulated gate transistor, and the insulated gate transistor is controlled by controlling a potential of a back gate of the insulated gate transistor based on the signal level. A signal transfer method characterized in that control is performed so as to eliminate or reduce fluctuations in voltage between both terminals of the parasitic capacitance.

2. The signal transfer method according to claim 1 , wherein the switch means is an insulated gate transistor, and the potential of the gate electrode of the insulated gate transistor other than the signal transferred to the common line is set to the signal level. A signal transfer method comprising: controlling based on the control so as to eliminate or reduce voltage fluctuation between both terminals of the parasitic capacitance of the insulated gate transistor.

2. The signal transfer method according to claim 1 , wherein the switch means is an insulated gate transistor, and the insulated gate transistor other than the signal transferred to the common line and the potential of the back gate of the insulated gate transistor. By controlling the potential of the gate electrode of the transistor based on the signal level, control is performed so as to eliminate or reduce the fluctuation of the voltage between both terminals of the parasitic capacitance of the insulated gate transistor. Signal transfer method.

A plurality of signal sources, switch means comprising insulated gate transistors provided for each of the plurality of signal sources, and a common line to which signal charges from the plurality of signal sources are sequentially transferred via the switch means, , converts the signal charges transferred to the common line voltages, the connection charges voltage converting means to the common line, the voltage obtained by adding a DC offset voltage to the transfer signal voltage of the common line insulating Input means for inputting to the back gate of the gate type transistor,
The charge voltage conversion means is a differential amplifier in which a reference voltage source is connected to a non-inverting input terminal and the inverting input terminal is connected to the common line,
The signal source includes a photoelectric conversion element and a capacitor for storing signals from the photoelectric conversion element, or includes a plurality of photoelectric conversion elements and a capacitor for storing signals sequentially transferred from the plurality of photoelectric conversion elements. A signal transfer device.

6. The signal transfer device according to claim 5 , wherein the DC offset voltage is set to 0V between the PN junction between the source, drain and back gate of the insulated gate transistor or a value in which a reverse bias state is maintained. A characteristic signal transfer device.

6. The signal transfer device according to claim 5 , wherein the switch means is a first switch means.
The gate of the first switch means is connected to the output side of the input means via the second switch means made of an insulated gate transistor, and the second switch means is turned off when the first switch means is OFF. A signal transfer device characterized by turning on the switch means.

8. The signal transfer device according to claim 7 , wherein when the first switch means is to be turned off, the voltage of the gate of the first switch means is the first switch means. A signal transfer device characterized in that a value that falls below a voltage that becomes a threshold for determining ON / OFF of the signal is set.

5. The signal transfer method of the solid-state imaging device using the signal transfer method according to claim 1, wherein the photoelectric conversion element includes a photoelectric conversion unit and a signal charge formed by the photoelectric conversion unit. A signal transfer method for a solid-state imaging device, comprising: an amplifying unit that converts the signal voltage into an amplified signal.

The solid-state imaging device using the signal transfer device according to claim 5 , wherein the photoelectric conversion element converts a photoelectric conversion unit and a signal charge formed by the photoelectric conversion unit into a signal voltage. And amplifying means for amplifying the solid-state imaging device.

Multiple signal sources;
Switch means provided for each of the plurality of signal sources;
A common line to which signal charges from the plurality of signal sources are sequentially transferred through the switch means ;
Charge voltage conversion means connected to the common line, which converts the signal charge transferred to the common line into a voltage and outputs the voltage.
When transferring a signal to the common line, parasitic capacitance control means for controlling fluctuations in voltage between both terminals of the parasitic capacitance connected to the common line to be eliminated or reduced based on the signal level of the common line And
The charge voltage conversion means is a differential amplifier in which a reference voltage source is connected to a non-inverting input terminal and the inverting input terminal is connected to the common line,
The signal source includes a photoelectric conversion element and a capacitor for storing signals from the photoelectric conversion element, or includes a plurality of photoelectric conversion elements and a capacitor for storing signals sequentially transferred from the plurality of photoelectric conversion elements. A signal transfer device.

12. The signal transfer apparatus according to claim 11 , wherein the parasitic capacitance control unit controls a parasitic capacitance of the switch unit.

13. The signal transfer device according to claim 12 , wherein the switch unit is formed of an insulated gate transistor, and the parasitic capacitance control unit is configured to input a signal from the common line to a back gate of the insulated gate transistor. A signal transfer apparatus comprising the input means .