JP2006128169A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a wire connected to a semiconductor chip by the side of a lower stage is hard to be deformed, and which can be constituted in a thin shape in relation to the semiconductor device in which a plurality of semiconductor chips are laminated and arranged, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device includes a first semiconductor chip 14 carried on a substrate 12, a second semiconductor chip 16 laminated and arranged on the first semiconductor chip 14, and wires 26 and 28 for electrically connecting the first and second semiconductor chips to the substrate 12. The second semiconductor chip 16 includes a first adhesive layer 38 and a second adhesive layer 40. A fine concave-convex structure 42 is fixed to the first semiconductor chip 14 by an insulating adhesive layer 36 formed uniformly in the interface, and at least the part of the first wire 26 is intruded into the first adhesive layer 38 of the insulating adhesive layer 36. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a structure in which a plurality of wire-bonded semiconductor chips are stacked and sealed, and a method for manufacturing the semiconductor device. More specifically, the semiconductor chip is arranged on a loop of bonded wires. The present invention relates to a semiconductor device configured as described above and a method for manufacturing the semiconductor device.

  With the recent development of electronic devices, semiconductor devices used in electronic devices are increasingly required to be smaller, thinner, multifunctional, higher performance, higher density, and lower cost. In order to cope with such a demand, a semiconductor device having a three-dimensional structure in which a plurality of semiconductor chips are stacked is put into practical use. Such a semiconductor device is called a stacked package.

  A semiconductor device is configured by mounting a semiconductor chip on a chip mounting member (for example, a substrate or a lead frame). In order to electrically connect the semiconductor chip and the chip mounting member, the wire bonding method is widely used as a low-cost connection method, and the wire bonding method is also adopted in the stacked package. For example, in a stacked package in which a substrate is used as a chip mounting member, the first semiconductor chip is bonded and fixed to the substrate with an insulating adhesive layer (adhesive), and the first semiconductor chip is bonded to the substrate with the first wire. After the second semiconductor chip is electrically connected to the first semiconductor chip, the second semiconductor chip is stacked on the previously mounted first semiconductor chip, and the second semiconductor chip is placed on the first semiconductor chip by an insulating adhesive layer (adhesive). Glue and fix to. Then, the second semiconductor chip is electrically connected to the substrate with a second wire, and the first and second semiconductor chips and the first and second wires are sealed with a sealing resin.

  The insulating adhesive layer that fixes the second semiconductor chip to the first semiconductor chip is generally an adhesive made of an epoxy resin or the like, and this adhesive is a liquid insulating adhesive layer or a film-like insulating property. Used as an adhesive layer. A film-like insulating adhesive layer is often used because it is often advantageous in terms of workability and productivity. For example, if a film-like insulating adhesive layer is bonded to the non-circuit surface of a semiconductor wafer in advance, the film-like insulating adhesive layer can be processed at the wafer level in a batch, and dicing is thereby performed. A uniform amount of adhesive is applied to each individual semiconductor chip.

  In the stacked package using such wire bonding connection, the first semiconductor chip on the lower stage side is larger than the second semiconductor chip on the upper stage side, and the electrode pad of the first semiconductor chip is the second semiconductor chip. If it is provided in the outer region, wire bonding can be performed so that the first wire does not contact the second semiconductor chip. However, depending on the combination of stacked semiconductor chips, there is a possibility that the first semiconductor chip and the second semiconductor chip having the same size are stacked and the first wire comes into contact with the bottom surface of the second semiconductor chip. There is. Therefore, in order to prevent the first wire from coming into contact with the bottom surface of the second semiconductor chip, the first wire is allowed to enter the insulating adhesive layer that fixes the second semiconductor chip to the first semiconductor chip. There is a proposal of (embedding) (see, for example, Patent Documents 1, 2, and 3).

  In Patent Document 1, when the back surface of the upper second semiconductor chip is fixed to the surface of the lower first semiconductor chip using the insulating adhesive layer, the thickness of the insulating adhesive layer is set to the first semiconductor chip. The thickness is set to be higher than the loop top (top) of the connected first wire. In this method, after supplying the insulating adhesive layer onto the first semiconductor chip, the second semiconductor chip is placed, and the insulating adhesive layer is heated and cured. The insulating adhesive layer may be liquid or film.

  The problem in this case is that the distance between the first and second semiconductor chips is maintained by the insulating adhesive layer so as not to deform the loop of the first wire, so that the thickness of the insulating adhesive layer is large. Thus, the position of the second semiconductor chip to be stacked is increased, and it is difficult to reduce the thickness of the entire semiconductor device. In addition, it is difficult to control the thickness of the insulating adhesive layer, and it is also difficult to control the parallelism between the first semiconductor chip and the second semiconductor chip.

  In Patent Document 2, a polyimide-based insulating resin layer is interposed between a second semiconductor chip and a first wire connected to the first semiconductor chip. Specifically, a resin layer having a low plastic deformation at 100 ° C. to 200 ° C., such as a polyimide-based insulating resin film for the purpose of separating, is provided on the back surface of the second semiconductor chip in advance, and an adhesive action is intended. A film-like die-bonding material having a two-layer structure consisting of a resin layer whose fluidity is increased by heating, such as an epoxy-based resin, is attached, whereby the second semiconductor chip is mounted on the first semiconductor chip. In doing so, the first wire enters the resin layer with high fluidity and comes into contact with the resin layer with less plastic deformation, thereby preventing the back surface of the second semiconductor chip from coming into contact with the first wire.

  The problem in this case is that when the second semiconductor chip is stacked and mounted on the first semiconductor chip, the loop of the first wire connected to the first semiconductor chip is a die bond material having the above two-layer structure. It is to be pressed against. In addition, in order to embed the loop of the first wire in the resin layer having high fluidity, the stacked mounting is performed while heating. Therefore, when the fluidity of the resin layer having high fluidity is sufficiently increased by heating, even if the loop of the first wire is pressed against the resin layer, the deformation of the loop of the first wire is slight. is there. However, when the loop of the first wire reaches the resin layer with less plastic deformation that is the separation layer beyond the resin layer, the resin layer with less plastic deformation is hard and the first wire loop is deformed. It's easy to do.

  Further, when the fluidity of the resin layer having high fluidity is not sufficient, the first wire loop is pressed against the resin layer, and stress enters the first wire when entering the resin layer. The wire is easily deformed. When the deformation of the first wire occurs, a short circuit occurs between the adjacent first wires. In particular, when the pitch of the electrode pads of the first semiconductor chip becomes fine or when the position of the electrode pads is arranged at the center of the first semiconductor chip, the first wire is short-circuited. The problem is likely to occur.

  Also in Patent Document 3, the first wire connected to the first semiconductor chip enters a part of the die bond material when the second semiconductor chip and the first semiconductor chip are bonded by the die bond material. Has been. A step of reducing the viscosity of the die bond material so that the first wire can be sufficiently embedded in the die bond material when the second semiconductor chip is stacked and mounted on the first semiconductor chip.

  The die bond material used for stacking the second semiconductor chip is a film-like adhesive composed of a plurality of adhesive layers having different viscosities during heating, and the adhesive layer on the side in contact with the first semiconductor chip is low. Arranged to be viscosity. The die bond material is attached in advance to the back side of the second semiconductor chip.

  As in the case of Patent Document 2, the problem in this case is that when the second semiconductor chip is stacked and mounted on the first semiconductor chip, the first wire is deformed, and the adjacent first wire It is easy to generate a short circuit.

JP 2001-60657 A JP 2002-222913 A Japanese Patent Laid-Open No. 2004-72009

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, in which a plurality of semiconductor chips are stacked and a wire connected to a lower semiconductor chip is less likely to be deformed and can be configured to be thin. It is to be.

  A semiconductor device according to the present invention is a semiconductor device including a first semiconductor chip mounted on a chip mounting member and a second semiconductor chip stacked on the first semiconductor chip. An insulating adhesive layer composed of a first adhesive layer and a second adhesive layer, which are superposed on each other, is disposed between the semiconductor chip and the second semiconductor chip, and the first adhesive A fine concavo-convex structure is uniformly formed at the interface between the layer and the second adhesive layer.

  According to the present invention, the insulating adhesive layer is composed of the first adhesive layer and the second adhesive layer which are superposed on each other and have different physical properties. Therefore, the second semiconductor chip is stacked and mounted on the first semiconductor chip. In this case, the first wire connected to the first semiconductor chip enters the first adhesive layer and is difficult to enter the second adhesive layer. Further, since the fine uneven structure is uniformly formed at the interface between the first adhesive layer and the second adhesive layer, the second semiconductor chip is stacked when mounted on the first semiconductor chip. Even if the wire connected to one semiconductor chip is pressed and deformed so that the loop is lowered, this fine concavo-convex structure prevents the wire from shifting laterally by engaging with the wire. No short circuit occurs with the wire. Therefore, the thickness of the first adhesive layer need not be so large, and the entire semiconductor device can be thinned. In addition, a stacked semiconductor device having a high degree of freedom in combination of the first semiconductor chip and the second semiconductor chip can be obtained.

A method for manufacturing a semiconductor device according to the present invention includes:
The first semiconductor chip is mounted on a chip mounting member, the electrode pads of the first semiconductor chip and the terminals of the chip mounting member are electrically connected by a first wire, and the physical properties stacked on each other are different. The second adhesion of the insulating adhesive layer comprising a first adhesive layer and a second adhesive layer, wherein a fine uneven structure is formed at the interface between the first adhesive layer and the second adhesive layer. A second semiconductor chip to which a layer is fixed is stacked on the first semiconductor chip, and a part of the first wire enters the first adhesive layer of the insulating adhesive layer. The first adhesive layer of the insulating adhesive layer is fixed to the first semiconductor chip, and the electrode pad of the second semiconductor chip and the terminal of the chip mounting member are electrically connected by the second wire. It is characterized by.

  According to this method for manufacturing a semiconductor device, a semiconductor device having the above characteristics can be manufactured.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention. The semiconductor device 10 includes a substrate 12 as a chip mounting member, a first semiconductor chip 14 mounted on the substrate 12, and a second semiconductor chip 16 stacked on the first semiconductor chip 14. .

  The substrate 12 has bonding terminals 18 and 20, the first semiconductor chip 14 has electrode pads 22, and the second semiconductor chip 16 has electrode pads 24. The electrode pad 22 of the first semiconductor chip 14 and the bonding terminal 18 of the substrate 12 are bonded by a first wire 26 and are electrically connected. The electrode pad 24 of the second semiconductor chip 16 and the bonding terminal 20 of the substrate 20 are bonded by a second wire 28 and are electrically connected.

  Further, the semiconductor device 10 includes a sealing resin 30 that seals the first and second semiconductor chips 14 and 16 and the first and second wires 26 and 28. Solder balls 32 as external connection terminals are provided on the back side of the substrate 12. The substrate 12 includes a circuit with a conductor (not shown), and the solder ball 32 is connected to the bonding terminals 18 and 20 by the circuit.

  The first semiconductor chip 14 is bonded and fixed to the substrate 12 by an insulating adhesive layer 34 mainly made of an epoxy resin adhesive, for example. The second semiconductor chip 16 is bonded and fixed to the first semiconductor chip 14 with an insulating adhesive layer 36. The insulating adhesive layer 36 has a two-layer structure composed of a first adhesive layer 38 and a second adhesive layer 40 having different physical properties. The first adhesive layer 38 is on the first semiconductor chip 14 side, and the second adhesive layer 40 is on the second semiconductor chip 16 side.

  A fine concavo-convex structure 42 is uniformly formed at the interface between the first adhesive layer 38 and the second adhesive layer 40. The fine concavo-convex structure 42 is such that convex portions and concave portions are alternately formed at a constant pitch, and the pitch between the convex portions and the convex portions or the pitch between the concave portions and the concave portions is the first semiconductor. The pitch is equal to or smaller than the pitch of the electrode pads 22 of the chip 14.

  FIG. 16 is a cross-sectional view showing an example in which the first wire 26 is fitted into the concave portion of the concave-convex structure 42. In this example, the pitch between the convex portions of the fine concavo-convex structure 42 or the pitch between the concave portions and the concave portions is equal to the pitch of the electrode pads 22 of the first semiconductor chip 14 (the first wire 26). Pitch).

  FIG. 17 is a cross-sectional view showing another example in which the first wire 26 is fitted in the concave portion of the concave-convex structure 42. In this example, the pitch between the convex portions of the fine concavo-convex structure 42 or the pitch between the concave portions and the concave portions is the pitch of the electrode pads 22 of the first semiconductor chip 14 (that is, the first wires 26). Smaller than the pitch). The number of convex portions or concave portions of the fine concavo-convex structure 42 is an integral multiple (twice in FIG. 17) of the number of electrode pads 22 (the number of first wires 26) of the first semiconductor chip 14.

  In FIG. 1, the first wire 26 enters (embeds) the first adhesive layer 38. The first wire 26 is in contact with the surface of the second adhesive layer 40 and is fitted to the concavo-convex structure 42. The first wire 26 is substantially received by the second adhesive layer 40 so as not to contact the bottom surface of the second semiconductor chip 16. The first adhesive layer 38 is formed of a material that is relatively soft or has a low viscosity, and the second adhesive layer 40 is formed of a material that is harder or higher in viscosity than the first adhesive layer 38.

  That is, when the second semiconductor chip 16 is heated and bonded to the first semiconductor chip 14 with the insulating adhesive layer 36, the first adhesive layer 38 is formed of the first wire 26 by the first adhesive layer. The second adhesive layer 40 has a hardness or viscosity that allows the first wire 26 to not enter the second adhesive layer 40 and maintain the concavo-convex structure 42. However, the material is less plastically deformed.

  Each of the first and second adhesive layers 38 and 40 is preferably made of a film-like resin adhesive layer. In this case, the second semiconductor chip 16 to which the insulating adhesive layer 36 composed of the first adhesive layer 38 and the second adhesive layer 40 adhered to each other is attached is directed to the first semiconductor chip 14. It is preferable from the viewpoint of work efficiency that both are bonded and fixed by pressing. In this case, if the first adhesive layer 38 is made of a thermosetting adhesive, it is convenient for handling. The first adhesive layer 38 is preferably made of a resin having a sufficient adhesive force.

  For example, the first adhesive layer 38 is mainly made of an epoxy resin or a mixture of an epoxy resin and a polyimide resin. The second adhesive layer 40 is made of polyimide resin or a mixture of polyimide resin and epoxy resin. When the first and second adhesive layers 38 and 40 are both made of a mixture of an epoxy resin and a polyimide resin, the physical properties of both can be made different by changing the mixing ratio of the epoxy resin and the polyimide resin. When the mixing ratio of the epoxy resin and the epoxy resin is low (for example, about several percent) in the mixture of the epoxy resin and the polyimide resin, the viscosity of the mixed resin at room temperature is about 100 Pa · s, and the mixing ratio is high (for example, several tens). %), The viscosity of the mixed resin at room temperature is about 10,000 Pa · s.

  The first adhesive layer 38 has a viscosity reduced to about 10 to 50 Pa · s under the condition that the second semiconductor chip 16 is heated to about 70 to 200 ° C. when the second semiconductor chip 16 is mounted on the first semiconductor chip 14. A material having high fluidity is used so that one wire 26 can easily enter the first adhesive layer 38. The second adhesive layer 40 has a viscosity of about 1000 Pa · s or more under the heated condition, and the plastic deformation is small so that the first wire 26 cannot enter the second adhesive layer 40 and the uneven structure 42 can be maintained. Use as material.

  The first and second adhesive layers 38 and 40 can be adjusted in physical properties by mixing other substances or by adding a filler. The second adhesive layer 40 can contain an inorganic filler at a high concentration so as to have a high hardness.

  The first adhesive layer 38 is made of an insulating film-like resin adhesive layer having low viscosity thermoplasticity, and the second adhesive layer 40 is made of an insulating film-like resin adhesive layer having high viscosity thermoplasticity. preferable. The first adhesive layer 38 is made of an insulating film-like resin adhesive layer having thermosetting properties, and the second adhesive layer 40 is made of an insulating film-like resin adhesive layer having high viscosity thermoplasticity. Good. By using a thermosetting resin, it is easy to design a resin that increases the adhesive strength.

  As described above, the insulating adhesive layer 36 includes the first adhesive layer 38 and the second adhesive layer 40 having different physical properties. Therefore, when the second semiconductor chip 16 is stacked and mounted on the first semiconductor chip 14. When the second semiconductor chip 16 is pressed toward the first semiconductor chip 14, the first wire 26 connected to the first semiconductor chip 14 enters the first adhesive layer 38, and the second The adhesive layer 40 is reached and pressed by the second adhesive layer 40, and the loop is deformed so as to be lowered. However, the fine concavo-convex structure 42 guides or restricts the first wire 26 from being laterally displaced. The Therefore, it is possible to prevent a short circuit from occurring between the adjacent first wires 26.

  FIG. 24 is a diagram illustrating an example in which the first wire 26 is deformed when the first wire 26 is pressed when the uneven structure 42 is not provided. FIG. 24A shows the second semiconductor chip 16 moving toward the first semiconductor chip 14 as indicated by an arrow A, and is a view seen from one side of the first semiconductor chip 14. It corresponds to. In FIG. 24A, a plurality of first wires 26 are arranged in parallel to each other. The first wire 26 rises from the bonding terminal 18 of the substrate 12, extends toward the other side of the paper surface of FIG. 24 while forming a loop, and is connected to the electrode pad 22 of the first semiconductor chip 14.

  In FIG. 24B, the second semiconductor chip 16 is pressed toward the first semiconductor chip 14, and the first adhesive layer 38 of the insulating adhesive layer 36 fixed to the second semiconductor chip 16 is the first. The first semiconductor chip 14 is reached, and the first wire 26 enters the soft first adhesive layer 38 and is in contact with the surface of the hard second adhesive layer 40. The first wire 26 is pressed against the second adhesive layer 40 and deforms so that the height of the loop is lowered. Accordingly, the thickness of the first adhesive layer 38 can be reduced, and the entire semiconductor device 10 can be reduced in thickness. However, when the first wire 26 is pressed against the second adhesive layer 40, the first wire 26 may be deformed so as to shift laterally along the second adhesive layer 40. Then, the adjacent first wires 26 are deformed so as to approach each other, and may come into contact with each other to cause a short circuit.

  FIG. 25 is a diagram illustrating an example in which the first wire 26 is deformed when the first wire 26 is pressed when the uneven structure 42 is present. FIG. 25A shows a state where the second semiconductor chip 16 is moved toward the first semiconductor chip 14 as indicated by an arrow A, and is a view seen from one side of the first semiconductor chip 14. It corresponds to. In FIG. 25A, a plurality of first wires 26 are arranged in parallel to each other. The first wire 26 rises from the bonding terminal 18 of the substrate 12, extends toward the other side of the paper surface of FIG. 25 while forming a loop, and is connected to the electrode pad 22 of the first semiconductor chip 14.

  In FIG. 25B, the second semiconductor chip 16 is pressed toward the first semiconductor chip 14, and the first adhesive layer 38 of the insulating adhesive layer 36 fixed to the second semiconductor chip 16 is the first. The first semiconductor chip 14 is reached, and the first wire 26 enters the soft first adhesive layer 38 and is in contact with the surface of the hard second adhesive layer 40. The first wire 26 is pressed against the second adhesive layer 40 and deforms so that the height of the loop is lowered. Accordingly, the thickness of the first adhesive layer 38 can be reduced, and the entire semiconductor device 10 can be reduced in thickness. In this case, when the first wire 26 is pressed against the second adhesive layer 40, the first wire 26 is uneven even if it receives a force that shifts laterally along the second adhesive layer 40. Since it is guided or regulated by the structure 42, it does not deform so as to be displaced laterally along the second adhesive layer 40.

  That is, the first wire 26 is guided or regulated by the concave portion of the concave-convex structure 42 when it reaches the concave-convex structure 42, or is fitted into the concave portion of the concave-convex structure 42, and the first wire 26 is connected to the second adhesive layer 40. Is not displaced laterally along the second adhesive layer 40. Therefore, the adjacent first wires 26 do not come into contact with each other to cause a short circuit. As described above, the bonding terminal 18 of the first semiconductor chip 14 can be arranged in a region overlapping the second semiconductor chip 16, and the degree of freedom of the combination of the first semiconductor chip 14 and the second semiconductor chip 16. It is possible to obtain a stacked semiconductor device having a high height.

  FIG. 2 is a cross-sectional view showing an example of the insulating adhesive layer 36 that fixes the second semiconductor chip 16 to the first semiconductor chip 14. The insulating adhesive layer 36 has a two-layer structure composed of a first adhesive layer 38 and a second adhesive layer 40 having different physical properties. A fine concavo-convex structure 42 is uniformly formed at the interface between the first adhesive layer 38 and the second adhesive layer 40. The fine concavo-convex structure 42 has a convex portion 42P and a concave portion 42Q when viewed from the second adhesive layer 40 side. The convex portion 42P has a trapezoidal shape, and the concave portion 42Q has an arc shape. The pitch between the convex part 42P and the convex part 42P or the pitch between the concave part 42Q and the concave part 42Q is constant.

  FIG. 3 is a cross-sectional view showing another example of the insulating adhesive layer 36. In this example, the convex part 42P and the concave part 42Q of the concavo-convex structure 42 are formed in a triangular shape or a sawtooth shape.

  4 is a perspective view of the concavo-convex structure 42 of the insulating adhesive layer 36 shown in FIG. The concavo-convex structure 42 includes a convex portion 42P and a concave portion 42Q, and extends long in parallel with each other.

  FIG. 5 is a perspective view of the uneven structure 42 of the insulating adhesive layer 36 shown in FIG. The concavo-convex structure 42 includes a convex portion 42P and a concave portion 42Q. The convex portion 42P and the concave portion 42Q are formed as a top portion and a bottom portion of a saw tooth having two slopes 42R, respectively. The convex part 42P and the concave part 42Q extend long in parallel with each other.

  FIG. 6 is a perspective view showing another example of the uneven structure 42 of the insulating adhesive layer 36. The concavo-convex structure 42 has a shape in which the top of a quadrangular pyramid having four slopes 42R is a convex portion 42P, and the concave portion 42Q extends long in two directions orthogonal to each other as the bottom of a continuous quadrangular pyramid. When the cross section passing through the top of the quadrangular pyramid is taken, the concavo-convex structure 42 of FIG. 6 corresponds to the shape of FIG.

  FIG. 7 is a plan view showing another example of the uneven structure 42 of the insulating adhesive layer 36. The uneven structure 42 is formed in a lattice shape. The convex portions 42P are quadrangular prism-shaped protrusions that are discontinuously arranged in rows and columns in the vertical and horizontal directions, and the concave portions 42Q extend continuously long in the vertical and horizontal rows around the convex portions 42P. The concavo-convex structure 42 of FIG. 7 corresponds to the shape of FIG.

  FIG. 8 shows the concavo-convex structure 42 which is formed in a lattice shape as in FIG. However, the convex part 42P in FIG. 8 is formed as an aggregate of four triangular prism-shaped protrusions 42S, and the concave part 42Q extends continuously in a vertical and horizontal row around the convex part 42P.

  FIG. 9 is a plan view showing another example of the concavo-convex structure 42 of the insulating adhesive layer 36. In the concavo-convex structure 42, the convex portion 42P is a cylindrical protrusion. The convex portions 42P are continuously arranged in a row in the vertical direction, and in the two adjacent vertical rows, the convex portions 42P are arranged so as to be shifted by a half pitch. The concave portion 42Q is formed around the convex portion 42P.

  Although examples of various concavo-convex structures 42 have been shown with reference to FIGS. 2 to 9, in the present invention, the concavo-convex structures 42 are not limited to the illustrated examples, and can be formed in various shapes. However, if the shape of the convex portion 42P is formed as the top portion of the slope as shown in FIGS. 3 and 6, the first wire 26 can be easily guided to the concave portion 42Q along the slope. The difference in height between the convex portion 42P and the concave portion 42Q is preferably about 5 to 30 μm when the diameter of the first wire 26 is 25 μm, for example.

  10 and 11 are cross-sectional views showing modifications of the semiconductor device 10 of FIG. Similar to the semiconductor device 10 in FIG. 1, the semiconductor device 10 in FIGS. 10 and 11 includes a substrate 12 as a chip mounting member, a first semiconductor chip 14 mounted on the substrate 12, and a first semiconductor chip 14. And the second semiconductor chip 16 arranged in a stacked manner. The electrode pad 22 of the first semiconductor chip 14 and the bonding terminal 18 of the substrate 12 are electrically connected by a first wire 26. The electrode pad 24 of the second semiconductor chip 16 and the bonding terminal 20 of the substrate 20 are electrically connected by a second wire 28. Further, the first and second semiconductor chips 14 and 16 and the first and second wires 26 and 28 are sealed with a sealing resin 30. Solder balls 32 as external connection terminals are provided on the back side of the substrate 12.

  The first semiconductor chip 14 is bonded and fixed to the substrate 12 by an insulating adhesive layer 34, and the second semiconductor chip 16 is an insulating adhesive composed of a first adhesive layer 38 and a second adhesive layer 40 having different physical properties. The layer 36 is adhered and fixed to the first semiconductor chip 14. A fine uneven structure 42 is formed at the interface between the first adhesive layer 38 and the second adhesive layer 40. At least a part of the first wire 26 enters the first adhesive layer 38 of the insulating adhesive layer 36 and is in contact with the concavo-convex structure 42.

  In FIG. 10, the first adhesive layer 38 and the second adhesive layer 40 are formed in the same shape as the first and second semiconductor chips 14 and 16, and the concavo-convex structure 42 has the same structure as that of the first adhesive layer 38. It is formed only in a region covering the electrode pad 22 of the first semiconductor chip 14 at a part of the interface with the second adhesive layer 40. Accordingly, the first wire 26 is guided or regulated by the concave portion of the concavo-convex structure 42 when reaching the concavo-convex structure 42 at the interface between the first adhesive layer 38 and the second adhesive layer 40, or the first wire 26 is The concave and convex structure 42 is fitted into the concave portion. Therefore, the operation of the semiconductor device 10 of FIG. 10 is the same as the operation of the semiconductor device 10 of FIG.

  In FIG. 11, the first adhesive layer 38 is formed in the same shape as the first semiconductor chip 14, and the second adhesive layer 40 is a peripheral portion of the first semiconductor chip 14, that is, the first semiconductor chip 14. The electrode pad 22 is formed in an annular shape corresponding to the region covering the electrode pad 22. The uneven structure 42 is formed at the interface between the first adhesive layer 38 and the second adhesive layer 40. Accordingly, the first wire 26 is guided or regulated by the concave portion of the concavo-convex structure 42 when reaching the concavo-convex structure 42 at the interface between the first adhesive layer 38 and the second adhesive layer 40, or the first wire 26 is The concave and convex structure 42 is fitted into the concave portion. Therefore, the operation of the semiconductor device 10 of FIG. 11 is the same as that of the semiconductor device 10 of FIG.

  FIG. 12 is a plan perspective view showing an example of superposition of the first semiconductor chip and the second semiconductor chip. FIG. 15 is a side view of the semiconductor device viewed from the arrow XV in FIG. 12 and 15, the second semiconductor chip 16 is larger than the first semiconductor chip 14. The first wire 26 is connected to the first semiconductor chip 14, and the second wire 28 is connected to the second semiconductor chip 16. Thus, according to the present invention, not only when the second semiconductor chip 16 is the same size as the first semiconductor chip 14, but also the second semiconductor chip 16 on the upper stage side is the first semiconductor on the lower stage side. Even when it is larger than the chip 14, a stacked package type semiconductor device can be formed.

  FIG. 13 is a plan perspective view showing an example of superposition of the first semiconductor chip 14 and the second semiconductor chip 16. The second semiconductor chip 16 is larger than the first semiconductor chip 14 when viewed in the vertical direction of the drawing, and the first semiconductor chip 14 is larger than the second semiconductor chip 16 when viewed in the horizontal direction of the drawing. The first wire 26 is connected to the first semiconductor chip 14, and the second wire 28 is connected to the second semiconductor chip 16. The first semiconductor chip 14 is a center pad type.

  FIG. 18 is a plan view showing an example of a first semiconductor chip 14 of the center pad type in which the electrode pads 22 are arranged in a row at the center. The first wire 26 in FIG. 13 is connected to the electrode pad 22 in FIG. In the case of the first semiconductor chip 14 of the center pad type, the length of the first wire 26 becomes long and is easily deformed by that much, so that a short circuit is likely to occur. Therefore, by adopting the concavo-convex structure 42 for the insulating adhesive layer 36 having a two-layer structure, the displacement of the first wire 26 can be suppressed and the occurrence of a short circuit can be prevented.

  FIG. 14 is a perspective plan view showing an example of superposition of the first semiconductor chip 14 and the second semiconductor chip 16. The first semiconductor chip 14 is larger than the second semiconductor chip 16 when viewed in the vertical direction of the drawing, and the second semiconductor chip 16 is larger than the first semiconductor chip 14 when viewed in the horizontal direction of the drawing. The first wire 26 is connected to the first semiconductor chip 14, and the second wire 28 is connected to the second semiconductor chip 16. The first wire 26 and the second wire 28 are arranged in a staggered pattern in a row.

  FIG. 19 is a plan view showing an example of the first semiconductor chip 14 in which the electrode pads 22 are arranged in a staggered pattern. The electrode pads 22 are arranged in two rows along each side of the semiconductor chip, and the electrode pads 22 in the first row and the electrode pads 22 in the second row are shifted from each other by a half pitch. In FIG. 19, the electrode pads 22 are provided on the four sides of the semiconductor chip. Since the first wires 26 in FIG. 14 are arranged along two sides of the first semiconductor chip 14, the first semiconductor chip 14 in FIG. 14 is the electrode pad 22 in the first semiconductor chip 14 in FIG. 19. Corresponds to those provided along two sides.

  FIG. 20 is a plan view showing an example of the first semiconductor chip 14 in which the electrode pads 22 of the semiconductor chips are arranged in a row and the first wires 26 are bonded to the electrode pads 22 so as to form a staggered arrangement. It is. That is, the electrode pads 22 are arranged in a line, but the connection positions of the first wires 26 to the electrode pads 22 are staggered. In the case of the semiconductor chip adopting the staggered arrangement of FIGS. 19 and 20, the pitch of the first wires 26 becomes fine, and a short circuit is likely to occur when the first wires 26 are deformed. Thus, it is possible to suppress the displacement of the first wire 26 and prevent the occurrence of a short circuit. The arrangements of FIGS. 18, 19, and 20 can be adopted for any semiconductor chip.

  FIG. 21 is a cross-sectional view showing a modification of the semiconductor device. In this example, the insulating adhesive layer 36 for fixing the second semiconductor chip 16 to the first semiconductor chip 14 has a two-layer structure including a first adhesive layer 38 and a second adhesive layer 40 having different physical properties. It is. A fine concavo-convex structure 42 is uniformly formed at the interface between the first adhesive layer 38 and the second adhesive layer 40. In this example, an inorganic filler 44 is mixed in the first adhesive layer 38. The inorganic filler 44 acts as a spacer that keeps the thickness of the first adhesive layer 38 constant when the second semiconductor chip 16 is pressed against the first semiconductor chip 14.

  FIG. 22 is a cross-sectional view showing a modification of the semiconductor device. The semiconductor device 10 includes a substrate 12 as a chip mounting member, a first semiconductor chip 14 mounted on the substrate 12, a second semiconductor chip 16 stacked on the first semiconductor chip 14, And a third semiconductor chip 46 which is stacked on the second semiconductor chip 16. The electrode pad 22 of the first semiconductor chip 14 and the bonding terminal 18 of the substrate 12 are electrically connected by a first wire 26. The electrode pad 24 of the second semiconductor chip 16 and the bonding terminal 20 of the substrate 20 are electrically connected by a second wire 28. The electrode pad 48 of the third semiconductor chip 46 and the bonding terminal 50 of the substrate 20 are electrically connected by a third wire 52. The first semiconductor chip 14 is a center pad type.

  The first, second, and third semiconductor chips 14, 16, 46 and the first, second, and third wires 26, 28, 52 are sealed with a sealing resin 30. Solder balls 32 as external connection terminals are provided on the back side of the substrate 12. Further, the first semiconductor chip 14 is bonded and fixed to the substrate 12 by the insulating adhesive layer 34, and the second semiconductor chip 16 is an insulating layer composed of a first adhesive layer 38 and a second adhesive layer 40 having different physical properties. The third semiconductor chip 46 is bonded and fixed to the second semiconductor chip 16 by the insulating adhesive layer 54, and is bonded and fixed to the first semiconductor chip 14 by the conductive adhesive layer 36. The insulating adhesive layer 54 has a two-layer structure composed of a first adhesive layer 38 and a second adhesive layer 40 having different physical properties like the insulating adhesive layer 36. The first adhesive layer 38 and the second adhesive layer A fine concavo-convex structure 42 is uniformly formed at the interface with the adhesive layer 40. Thus, in the present invention, not only two semiconductor chips can be stacked, but also three or more semiconductor chips can be stacked.

  Furthermore, cover films 56 and 58 made of an insulating resin are provided on the surfaces of the first and second semiconductor chips 14 and 16. FIG. 23 is a plan view showing the semiconductor chip of FIG. FIG. 23A shows a cover film 56 provided on the surface of the first semiconductor chip 14. FIG. 23B shows a cover film 58 provided on the surface of the second semiconductor chip 16. The cover films 56 and 58 are at least in the region from the electrode pads 22 and 24 to the outer peripheral edge of the semiconductor chips 14 and 16 on the surface where the electrode pads 22 and 24 of the first and second semiconductor chips 14 and 16 are provided. Is provided. The cover films 56 and 58 do not directly contact the surfaces of the first and second semiconductor chips 14 and 16 when the first and second wires 26 and 28 are pressed. It is provided to ensure that

  FIG. 26 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. 26A and 26B, the first semiconductor chip 14 is mounted on the substrate 12 as a chip mounting member. The first semiconductor chip 14 has circuits and electrode pads 22 on the upper surface, and the substrate 12 has bonding terminals 18 and 20. A film-like insulating adhesive layer 34 is fixed to the lower surface (non-circuit surface) of the first semiconductor chip 14, and the first semiconductor chip 14 is attached to the substrate 12 as indicated by an arrow while heating the substrate 12. The first semiconductor chip 14 is bonded and fixed to the substrate 12 by the insulating adhesive layer 34 by pressing toward the substrate 12. Then, the electrode pads 22 of the first semiconductor chip 14 and the bonding terminals 18 of the substrate 12 are wire bonded by the first wires 26. In the bonding, the first semiconductor chip 14 may be heated instead of heating the substrate 12.

  26C, 26D, and 26E, the second semiconductor chip 16 is stacked on the first semiconductor chip 14 and mounted. The second semiconductor chip 16 has circuits and electrode pads 24 on the upper surface, and an insulating adhesive layer 36 is fixed to the lower surface (non-circuit surface) of the second semiconductor chip 16. The insulating adhesive layer 36 includes a first adhesive layer 38 and a second adhesive layer 40 having different physical properties, and a fine concavo-convex structure 42 is formed at the interface between the first adhesive layer 38 and the second adhesive layer 40. Uniformly formed. The detailed structure of the insulating adhesive layer 36 corresponds to, for example, that shown in FIGS.

In the state shown in FIG. 26C, the second adhesive layer 40 of the insulating adhesive layer 36 is fixed to the second semiconductor chip 16, and the first adhesive layer 38 of the insulating adhesive layer 36 is the first adhesive layer 38. The second semiconductor layer 14 faces the first semiconductor chip 14 while being superposed on and fixed to the second adhesive layer 40.
The second semiconductor chip 16 is pressed by the insulating adhesive layer 36 by pressing the second semiconductor chip 16 toward the first semiconductor chip 14 as indicated by an arrow while heating the second semiconductor chip 16. Bonding and fixing to one semiconductor chip 14. The first adhesive layer 38 of the insulating adhesive layer 36 has a viscosity lower than that of the second adhesive layer 40 by heating, for example, and is heated to about 70 to 200 ° C. to have a viscosity of about 10 to 50 Pa · s. Become. Therefore, at least a part of the first wire 26 bonded to the first semiconductor chip 14 easily enters the first adhesive layer 38. At least a portion of the first wire 26 enters the first adhesive layer 38, but does not enter the second adhesive layer 40. As described above, the first adhesive layer 38 and the second adhesive layer 40 The first wire 26 is fitted into the concave portion of the concavo-convex structure 42, or is guided or regulated by the concave portion of the fine concavo-convex structure 42 at the interface. Thereby, even though the first wire 26 is pressed by the second adhesive layer 40, the positional displacement of the first wire 26 is prevented and the occurrence of a short circuit is prevented. In bonding, instead of heating the second semiconductor chip 16, the first semiconductor chip 14 and the first wire 26 may be heated by heating the substrate 12 with a hot plate or the like.

  Thereafter, as shown in FIG. 26F, the electrode pads 24 of the second semiconductor chip 16 and the bonding terminals 20 of the substrate 12 are wire-bonded by the second wires 28. Then, as shown in FIG. 26G, the first and second semiconductor chips 14 and 16 and the first and second wires 26 and 28 are molded with a sealing resin 30 to perform resin sealing. Then, as shown in FIG. 26H, solder balls 32 as external connection terminals are formed on the back surface side of the substrate 12.

  In this way, the first semiconductor chip 14 is bonded and fixed to the substrate 12 by the insulating adhesive layer 34, and the second semiconductor chip 16 has the first adhesive layer 38 and the second adhesive layer 40 having different physical properties. The semiconductor device 10 bonded and fixed to the first semiconductor chip 14 by the insulating adhesive layer 36 made of is formed.

  FIG. 27 is a diagram showing an example of obtaining the second semiconductor chip 16 to which the insulating adhesive layer 36 of FIG. In FIG. 27A, a sheet-like adhesive (insulating adhesive film) 40F that becomes the second adhesive layer 40 of the insulating adhesive layer 36 is prepared. The sheet-like adhesive 40F is larger than the area of the second semiconductor chip 16, and has an area corresponding to the semiconductor wafer 60 shown in FIG.

  In FIG. 27B, a concavo-convex pattern 42P is formed on the sheet-like adhesive 40F. The formation of the concavo-convex pattern 42P can be performed by various methods such as an embossing method, etching, and machining (laser machining or blade machining). 27C and 27D, a sheet-like adhesive (insulating adhesive film) 38F to be the first adhesive layer 38 of the insulating adhesive layer 36 is pasted on the sheet-like adhesive 40F having the uneven pattern 42P. Match. Also in this case, the sheet-like adhesive 38 </ b> F has an area corresponding to the semiconductor wafer 60. Thus, a sheet-like insulating adhesive layer 36F composed of the sheet-like adhesive 38F and the sheet-like adhesive 40F is formed. The uneven pattern 42P becomes the uneven structure 42 provided at the interface between the sheet-like adhesive 40F and the sheet-like adhesive 38F.

  In FIG. 27E, the sheet-like insulating adhesive layer 36F is bonded to the non-circuit surface of the semiconductor wafer 60 on which the semiconductor integrated circuit is formed. In this case, the sheet-like insulating adhesive layer 36F is bonded to the semiconductor wafer 60 with the sheet-like adhesive 40F facing the semiconductor wafer 60 side. 27F and 27G, the dicing sheet 62 is bonded to the sheet-like insulating adhesive layer 36F. In FIG. 27H, the semiconductor wafer 60 is diced and separated into second semiconductor chips 16. To do. The second semiconductor chip 16 is used by being peeled off from the dicing sheet 62. An insulating adhesive layer 36 is attached to the second semiconductor chip 16, and the insulating adhesive layer 36 includes a first adhesive layer 38 and a second adhesive layer 40 having different physical properties, and an interface between them. An insulating adhesive layer 36 having a concavo-convex structure 42 formed thereon is affixed.

  FIG. 28 is a view showing another example of obtaining the second semiconductor chip 16 to which the insulating adhesive layer 36 of FIG. 28A and 28B, a sheet-like adhesive (insulating adhesive film) 40F to be the second adhesive layer 40 of the insulating adhesive layer 36 is attached to the semiconductor wafer 60. In FIG. 28C, an uneven pattern 42P is formed on the sheet-like adhesive 40F. The formation of the concavo-convex pattern 42P can be performed by various methods such as an embossing method, etching, and machining (laser machining or blade machining). In FIG. 28D, a sheet-like adhesive (insulating adhesive film) 38F that becomes the first adhesive layer 38 of the insulating adhesive layer 36 is bonded to the sheet-like adhesive 40F having the uneven pattern 42P.

  28E and 28F, a sheet-like insulating adhesive layer 36F composed of the sheet-like adhesive 38F and the sheet-like adhesive 40F is thus formed. The sheet adhesive 40F of the sheet insulating adhesive layer 36F is on the semiconductor wafer 60 side. The uneven pattern 42P becomes the uneven structure 42 provided at the interface between the sheet-like adhesive 40F and the sheet-like adhesive 38F. The dicing sheet 62 is bonded to the sheet-like insulating adhesive layer 36F, and the semiconductor wafer 60 is diced and separated into second semiconductor chips 16 in FIG. The second semiconductor chip 16 is used by being peeled off from the dicing sheet 62. An insulating adhesive layer 36 is attached to the second semiconductor chip 16, and the insulating adhesive layer 36 includes a first adhesive layer 38 and a second adhesive layer 40 having different physical properties, and an interface between them. A concavo-convex structure 42 is formed on the surface.

  The second semiconductor chip 16 obtained as shown in FIGS. 27 and 28 is used in FIG. The insulating adhesive layer 36 is formed by the sheet-like adhesives 38F and 40F attached to the semiconductor wafer 60, and the sheet-like adhesives 38F and 40F are applied at the stage of the semiconductor wafer 60. Therefore, handling is easy, and the amount of adhesive per individual semiconductor chip can be made more uniform.

  FIG. 29 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. In this example, the second semiconductor chip 16 is bonded and fixed to the first semiconductor chip 14 by an insulating adhesive layer 64 having a single concavo-convex structure.

  29A and 29B, the first semiconductor chip 14 is mounted on the substrate 12 as a chip mounting member. The first semiconductor chip 14 has circuits and electrode pads 22 on the upper surface, and the substrate 12 has bonding terminals 18 and 20. An insulating adhesive layer 34 is fixed to the lower surface (non-circuit surface) of the first semiconductor chip 14, and the first semiconductor chip 14 is pressed against the substrate 12 while heating the first semiconductor chip 14. Thus, the first semiconductor chip 14 is bonded and fixed to the substrate 12 by the insulating adhesive layer 34. Then, the electrode pads 22 of the first semiconductor chip 14 and the bonding terminals 18 of the substrate 12 are wire bonded by the first wires 26.

  29C, 29D and 29E, the second semiconductor chip 16 is stacked on the first semiconductor chip 14 and mounted. The second semiconductor chip 16 has circuits and electrode pads 24 on the upper surface, and an insulating adhesive layer 64 is fixed to the lower surface (non-circuit surface) of the second semiconductor chip 16. The insulating adhesive layer 36 is made of a single sheet-like adhesive layer, and a fine uneven structure 66 is uniformly formed on the surface of the insulating adhesive layer 64 opposite to the second semiconductor chip 16.

  By pressing the second semiconductor chip 16 toward the first semiconductor chip 14 while heating the substrate 12, the second semiconductor chip 16 is bonded and fixed to the first semiconductor chip 14 by the insulating adhesive layer 64. . The viscosity of the insulating adhesive layer 64 decreases as the temperature rises, and at least a part of the first wire 26 that has already been bonded enters the insulating adhesive layer 64. For example, the insulating adhesive layer 64 has a viscosity of about 30 to 50 Pa · s when heated to about 60 to 150 ° C.

  In this case, the substrate 12 is heated by a hot plate or the like, and the second semiconductor chip 16 is directed toward the first semiconductor chip 14 with the temperature of the first wire 26 being high and the temperature of the insulating adhesive layer 64 being low. Press. The first wire 26 is pressed by the insulating adhesive layer 64 at a low temperature, and is deformed so that the loop is lowered while being guided or regulated by the concave portion of the concave-convex structure 66. The first wire 26 is deformed without being displaced, and thus occurrence of a short circuit is prevented.

  When the insulating adhesive layer 64 comes into contact with the first wire 26, the temperature thereof increases, the viscosity decreases, and at least a part of the first wire 26 enters the insulating adhesive layer 64. In this case, the first wire 26 enters the insulating adhesive layer 64 while being deformed so that the loop is lowered by being pressed by the insulating adhesive layer 64. Therefore, the first wire 26 does not come into contact with the bottom surface of the second semiconductor chip 16.

  Thereafter, as shown in FIG. 29F, the electrode pads 24 of the second semiconductor chip 16 and the bonding terminals 20 of the substrate 12 are wire-bonded by the second wires 28. Then, as shown in FIG. 29G, the first and second semiconductor chips 14 and 16 and the first and second wires 26 and 28 are molded with a sealing resin 30 to perform resin sealing. Then, solder balls 32 as external connection terminals are formed on the back side of the substrate 12.

  FIG. 30 is a diagram showing an example of obtaining the second semiconductor chip 16 to which the insulating adhesive layer 64 of FIG. 29C is attached. 30A and 30B, a sheet-like adhesive (insulating adhesive film) 64F that becomes the insulating adhesive layer 64 is bonded to the non-circuit surface of the semiconductor wafer 60 on which the semiconductor integrated circuit is formed. An uneven structure 66 is formed on the sheet-like adhesive 64F. The concavo-convex structure 66 is formed in a fine uniform pattern in the same manner as the concavo-convex structure 42 described above.

  The sheet-like adhesive 64F is bonded to the non-circuit surface of the semiconductor wafer 60 on which the semiconductor integrated circuit is formed. 30C and 30D, the dicing sheet 62 is bonded to the sheet-like adhesive 64F, and in FIG. 30E, the semiconductor wafer 60 is diced and separated into second semiconductor chips 16. An insulating adhesive layer 64 is affixed to the second semiconductor chip 16, and an uneven structure 66 is formed on the surface thereof.

  FIG. 31 is a view showing another example of obtaining the second semiconductor chip 16 to which the insulating adhesive layer 36 of FIG. 29C is attached. 31A and 31B, a sheet-like adhesive (insulating adhesive film) 64F that becomes the insulating adhesive layer 64 is bonded to the non-circuit surface of the semiconductor wafer 60 on which the semiconductor integrated circuit is formed. In FIG. 31C, a concavo-convex structure (concave / convex pattern) 66 is formed in the sheet-like adhesive 64F. The formation of the concavo-convex structure 66 can be performed by various methods such as an embossing method, etching, and machining (laser machining or blade machining). 31D and 31E, the dicing sheet 62 is bonded to the sheet-like adhesive 64F. In FIG. 31F, the semiconductor wafer 60 is diced and separated into second semiconductor chips 16. An insulating adhesive layer 64 is attached to the second semiconductor chip 16.

  The second semiconductor chip 16 obtained as shown in FIGS. 30 and 31 is used in FIG. The insulating adhesive layer 64 is formed by a sheet-like adhesive 64F attached to the semiconductor wafer 60, and the sheet-like adhesive 64F is applied at the stage of the semiconductor wafer 60. It is easy to handle and the amount of adhesive per individual semiconductor chip can be made more uniform.

  FIG. 32 is a sectional view showing a semiconductor device according to an embodiment of the present invention. FIG. 33 is a partial plan view showing a lead frame used for constituting the semiconductor device 10 shown in FIG. In this embodiment, a lead frame 68 is used as a chip mounting member. As shown in FIG. 33, the lead frame 68 has a plurality of die pads 70 and leads 72 formed around each die pad 70. The die pad 70 is supported on the peripheral frame portion 76 by support portions 74 located at the four corners. After the semiconductor chip is mounted, the lead 72 and the support portion 74 are cut from the peripheral frame portion 76.

  In FIG. 32, the semiconductor device 10 is disposed by being stacked on the lead frame 68 as a chip mounting member, the first semiconductor chip 14 mounted on the die pad 70 of the lead frame 68, and the first semiconductor chip 14. It consists of a second semiconductor chip 16. The electrode pads 22 of the first semiconductor chip 14 and the inner end portions (inner leads) 72I of the leads 72 of the lead frame 68 are electrically connected by the first wires 26. The electrode pad 24 of the second semiconductor chip 16 and the inner end portion (inner lead) 72I of the other lead 72 of the lead frame 68 are electrically connected by the second wire 28.

  In the embodiment, two sets of stacked first and second semiconductor chips 14 and 16 are provided above and below the die pad 70 of the lead frame 68. Further, the first and second semiconductor chips 14 and 16 and the first and second wires 26 and 28 are sealed with a sealing resin 30. An outer end portion (outer lead) 72O of the lead 72 of the lead frame 68 serves as an external connection terminal.

  The first semiconductor chip 14 is bonded and fixed to the die pad 70 by an insulating adhesive layer 34, and the second semiconductor chip 16 is an insulating adhesive composed of a first adhesive layer 38 and a second adhesive layer 40 having different physical properties. The layer 36 is adhered and fixed to the first semiconductor chip 14. A fine concavo-convex structure 42 is uniformly formed at the interface between the first adhesive layer 38 and the second adhesive layer 40. At least a part of the first wire 26 enters the first adhesive layer 38 of the insulating adhesive layer 36 and is in contact with the concavo-convex structure 42. Therefore, the operation of the semiconductor device 10 of FIG. 32 is the same as the operation of the semiconductor device 10 of FIG.

FIG. 34 is a diagram illustrating a method of manufacturing the semiconductor device 10 of FIG. The manufacturing method of FIG. 34 is similar to the manufacturing method of FIG. In FIGS. 34A and 34B, the first semiconductor chip 14 is mounted on a die pad 70 of a lead frame 68 as a chip mounting member. An insulating adhesive layer 34 is fixedly exposed to the non-circuit surface of the first semiconductor chip 14, and the first semiconductor chip 14 is pressed toward the die pad 70 while heating the die pad 70, thereby allowing the first semiconductor chip 14 to be pressed. The chip 14 is bonded and fixed to the die pad 70 by the insulating adhesive layer 34. In the bonding, the first semiconductor chip 14 may be heated instead of heating the die pad 70.
34C and 34D, the electrode pad 22 of the first semiconductor chip 14 and the inner end portion (inner lead) 72I of the lead 72 of the lead frame 68 are wire-bonded by the first wire 26.

  In FIGS. 34E and 34F, the second semiconductor chip 16 is stacked on the first semiconductor chip 14, and the second semiconductor chip 16 is mounted while heating. An insulating adhesive layer 36 is fixed to the non-circuit surface of the second semiconductor chip 16. The insulating adhesive layer 36 includes a first adhesive layer 38 and a second adhesive layer 40 having different physical properties, and a fine concavo-convex structure 42 is formed at the interface between the first adhesive layer 38 and the second adhesive layer 40. Uniformly formed. The detailed structure of the insulating adhesive layer 36 corresponds to, for example, that shown in FIGS. In mounting, instead of heating the second semiconductor chip 16, the first semiconductor chip 14 and the first wire 26 may be heated by heating the die pad 70.

  In FIGS. 34E and 34F, at least a part of the first wire 26 enters the first adhesive layer 38 of the insulating adhesive layer 36 in the same manner as described above. At least a part of the first wire 26 enters the first adhesive layer 38, but does not enter the second adhesive layer 40, and fine irregularities at the interface between the first adhesive layer 38 and the second adhesive layer 40. Guided or regulated by a recess in the structure 42 or the first wire 26 fits into a recess in the relief structure 42. Thereby, even though the first wire 26 is pressed by the second adhesive layer 40, the positional displacement of the first wire 26 is prevented and the occurrence of a short circuit is prevented.

  FIG. 35 is a diagram showing a step subsequent to FIG. 35A and 35B, the electrode pad 24 of the second semiconductor chip 16 and the inner end portion (inner lead) 72I of another lead 72 are wire-bonded by the second wire 28. Then, as shown in FIG. 35C, the first and second semiconductor chips 14 and 16 and the first and second wires 26 and 28 are molded with a sealing resin 30 to perform resin sealing. Then, as shown in FIG. 34D, the lead 72 and the support portion 74 are cut from the peripheral frame portion 76 of the lead frame 68, and the lead 72 is formed into a predetermined shape. The lead frame 68 may be subjected to exterior plating (Sn plating or the like) so that the lead 72 is excellent in oxidation resistance and corrosion resistance by plating.

  The second semiconductor chip 16 to which the insulating adhesive layer 36 shown in FIGS. 34E and 34F is attached is obtained by the method shown in FIGS. That is, in the method shown in FIG. 27, the sheet-like adhesive 38 </ b> F that becomes the first adhesive layer 38 is bonded to the sheet-like adhesive 40 </ b> F on which the uneven pattern 42 </ b> P that becomes the second adhesive layer 38 is formed. A sheet-like insulating adhesive layer 36F composed of an adhesive 38F and a sheet-like adhesive 40F is bonded to the semiconductor wafer 60, and the semiconductor wafer 60 is diced to be separated into second semiconductor chips 16.

  Further, in the method shown in FIG. 28, a sheet-like adhesive 40F that becomes the second adhesive layer 40 is attached to the semiconductor wafer 60, and a concavo-convex pattern 42P is formed on the sheet-like adhesive 40F. A sheet-like adhesive (insulating adhesive film) 38F to be the first adhesive layer 38 is bonded together, the semiconductor wafer 60 is diced, and separated into second semiconductor chips 16.

  FIG. 36 is a diagram showing a modification of the method for manufacturing the semiconductor device of FIGS. 36 (A) and (B) correspond to FIG. 34 (E). That is, in this example, the second semiconductor chip 16 is bonded and fixed to the first semiconductor chip 14 by the single insulating adhesive layer 64 having the concavo-convex structure 66. The processes of FIGS. 34 (A) to (D) and (F) and FIGS. 35 (A) to (D) are applied before and after FIGS. 36 (A) and 36 (B). The feature of the method for manufacturing the semiconductor device 10 shown in FIG. 36 is the same as that of the method for manufacturing the semiconductor device 10 of FIG.

  The embodiment described above includes the following features.

(Appendix 1) a first semiconductor chip mounted on a chip mounting member;
In a semiconductor device including a second semiconductor chip disposed on the first semiconductor chip,
Between the first semiconductor chip and the second semiconductor chip, an insulative adhesive layer composed of a first adhesive layer and a second adhesive layer having different physical properties is provided,
A fine uneven structure is uniformly formed at the interface between the first adhesive layer and the second adhesive layer.
A semiconductor device. (1)

  (Supplementary Note 2) A part of the first wire that electrically connects the electrode pad of the first semiconductor chip and the terminal of the chip mounting member enters the first adhesive layer of the insulating adhesive layer. 2. The semiconductor device according to appendix 1, wherein: (2)

  (Supplementary note 3) The supplementary note 2, wherein the chip mounting member is composed of one of a substrate and a lead frame, and the terminal of the chip mounting member is composed of one of a bonding terminal of the substrate and a lead of the lead frame. Semiconductor device.

  (Supplementary note 4) The semiconductor device according to supplementary note 2, wherein the uneven structure has a shape in which a part of the first wire is fitted.

  (Additional remark 5) The pitch between the recessed part of a concavo-convex structure, or a convex part and a convex part is equal to or smaller than the pitch of the electrode pad of a 1st semiconductor chip. The semiconductor device according to any one of 1 to 4. (3)

  (Supplementary note 6) The semiconductor device according to any one of supplementary notes 1 to 5, wherein the first adhesive layer contains a filler having a diameter larger than that of the first wire.

  (Supplementary note 7) The semiconductor device according to any one of Supplementary notes 1 to 6, wherein the electrode pads of the first semiconductor chip are arranged in a row at the center of the first semiconductor chip.

  (Supplementary Note 8) The electrode pads of the first semiconductor chips are arranged in a staggered row, or the electrode pads of the first semiconductor chip are arranged in a row, and the first wires are arranged in a staggered manner. The semiconductor device according to any one of appendices 1 to 6, wherein the semiconductor device is bonded to the electrode pad as described above.

  (Appendix 9) A cover film made of an insulating resin is formed in at least a region of the surface of the first semiconductor chip where the electrode pad is provided from the electrode pad to the outer peripheral edge of the semiconductor chip. The semiconductor device according to any one of appendices 1 to 8.

  (Supplementary Note 10) The first adhesive layer is made of an insulating film-like resin adhesive layer having low viscosity thermoplasticity, and the second adhesive layer is made of an insulating film-like resin adhesive layer having high viscosity thermoplasticity. The semiconductor device according to any one of appendices 1 to 9. (4)

  (Appendix 11) The first adhesive layer is composed of an insulating film-like resin adhesive layer having thermosetting properties, and the second adhesive layer is composed of an insulating film-like resin adhesive layer having high viscosity thermoplasticity. The semiconductor device according to any one of appendices 1 to 9.

  (Supplementary Note 12) When the semiconductor device is manufactured, the first adhesive layer has a hardness that allows the first wire to easily enter the first adhesive layer, and the second adhesive layer has the first wire The semiconductor device according to any one of appendices 1 to 11, which has a hardness that makes it difficult to enter the adhesive layer.

  (Supplementary note 13) The semiconductor device according to Supplementary note 12, wherein the second adhesive layer includes a polyimide resin.

  (Supplementary note 14) The semiconductor device according to supplementary note 13, wherein the second adhesive layer contains an inorganic filler in a high concentration.

(Supplementary note 15) mounting the first semiconductor chip on the chip mounting member;
Electrically connecting the electrode pads of the first semiconductor chip and the terminals of the chip mounting member by a first wire;
Insulating property comprising a first adhesive layer and a second adhesive layer that are superposed on each other and having different physical properties, and a fine uneven structure is formed at the interface between the first adhesive layer and the second adhesive layer A second semiconductor chip to which the second adhesive layer of the adhesive layer is fixed is laminated and disposed on the first semiconductor chip;
And fixing the first adhesive layer of the insulating adhesive layer to the first semiconductor chip so that a part of the first wire enters the first adhesive layer of the insulating adhesive layer,
A method for manufacturing a semiconductor device, comprising: electrically connecting an electrode pad of the second semiconductor chip and a terminal of the chip mounting member with a second wire. (5)

  (Supplementary Note 16) Before the dicing, an uneven structure is formed on the surface of the second adhesive layer, the second adhesive layer and the first adhesive layer are overlapped, and the first adhesive layer and 16. The method of manufacturing a semiconductor device according to appendix 15, wherein the insulating adhesive layer including the second adhesive layer is fixed to a semiconductor wafer.

  (Supplementary Note 17) Before the dicing, the second adhesive layer is fixed to a semiconductor wafer to form a fine concavo-convex structure on the surface of the second adhesive layer, and the second adhesive layer and the first 16. The method of manufacturing a semiconductor device according to appendix 15, wherein the insulating adhesive layer composed of the first adhesive layer and the second adhesive layer is fixed to a semiconductor wafer. .

  (Supplementary Note 18) When the first adhesive layer of the insulating adhesive layer is fixed to the first semiconductor chip, the viscosity is such that the first wire can enter the first adhesive layer by heating. The method for manufacturing a semiconductor device according to appendix 15, wherein the semiconductor device is provided.

(Supplementary note 19) mounting the first semiconductor chip on the chip mounting member;
Electrically connecting the electrode pads of the first semiconductor chip and the terminals of the chip mounting member by a first wire;
A semiconductor wafer having an insulating adhesive layer having a fine concavo-convex structure formed on the surface is fixed and diced into second semiconductor chips,
The second semiconductor chip is stacked on the first semiconductor chip, and an insulating adhesive layer is disposed on the first semiconductor chip so that at least a part of the first wire enters the insulating adhesive layer. Adheres to
Electrically connecting the electrode pads of the second semiconductor chip and the terminals of the chip mounting member by a second wire;
A method for manufacturing a semiconductor device.

  (Supplementary note 20) The method of manufacturing a semiconductor device according to supplementary note 19, wherein an uneven structure is formed on a surface of the insulating adhesive layer before the dicing, and the insulating adhesive layer is fixed to a semiconductor wafer. .

  (Appendix 21) Before the dicing, the insulating adhesive layer is fixed to the semiconductor wafer, a fine uneven structure is formed on the surface of the insulating adhesive layer, and the insulating adhesive layer is fixed to the semiconductor wafer. Item 20. The method for manufacturing a semiconductor device according to appendix 19, wherein:

  (Supplementary note 22) When the insulating adhesive layer is fixed to the first semiconductor chip, the loop shape of the first wire is deformed by pressing the second semiconductor chip. A semiconductor device according to 1.

  (Supplementary Note 23) When the insulating adhesive layer is fixed to the first semiconductor chip, at least a loop of the first wire is formed in the concavo-convex structure formed in the insulating adhesive layer or on the surface of the insulating adhesive layer. 20. A method for manufacturing a semiconductor device according to appendix 15 or 19, wherein a part of the semiconductor device is fitted.

  (Supplementary Note 24) When the second semiconductor chip is pressed to deform the loop shape of the first wire, the second semiconductor chip is moved along the direction of the electrode pad row of the first semiconductor chip. 24. The method of manufacturing a semiconductor device according to appendix 23, wherein the method is pressed while pressing.

  As described above, according to the present invention, a semiconductor device including a plurality of stacked semiconductor chips can be obtained.

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing an example of an insulating adhesive layer for fixing the second semiconductor chip to the first semiconductor chip. FIG. 3 is a cross-sectional view showing another example of the insulating adhesive layer. FIG. 4 is a perspective view showing an example of the uneven structure of the insulating adhesive layer. FIG. 5 is a perspective view showing another example of the uneven structure of the insulating adhesive layer. FIG. 6 is a perspective view showing another example of the uneven structure of the insulating adhesive layer. FIG. 7 is a plan view showing another example of the uneven structure of the insulating adhesive layer. FIG. 8 is a plan view showing another example of the uneven structure of the insulating adhesive layer. FIG. 9 is a plan view showing another example of the uneven structure of the insulating adhesive layer. FIG. 10 is a cross-sectional view showing a modification of the semiconductor device of FIG. FIG. 11 is a cross-sectional view showing a modification of the semiconductor device of FIG. FIG. 12 is a plan view showing an example of a combination of a first semiconductor chip and a second semiconductor chip. FIG. 13 is a plan view showing an example of a combination of a first semiconductor chip and a second semiconductor chip. FIG. 14 is a plan view showing an example of a combination of a first semiconductor chip and a second semiconductor chip. FIG. 15 is a side view of the semiconductor device viewed from the arrow XV in FIG. FIG. 16 is a cross-sectional view showing an example in which the first wire is fitted in the concave portion of the concave-convex structure. FIG. 17 is a cross-sectional view showing another example in which the first wire is fitted into the concave portion of the concave-convex structure. FIG. 18 is a plan view showing an example of a center pad type semiconductor chip in which electrode pads are arranged in a row at the center. FIG. 19 is a plan view showing an example of a semiconductor chip in which electrode pads are arranged in a staggered pattern. FIG. 20 is a plan view showing an example of a semiconductor chip bonded to the electrode pads so that the electrode pads of the semiconductor chip are arranged in a row and the first wires are in a staggered arrangement. FIG. 21 is a cross-sectional view showing a modification of the semiconductor device. FIG. 22 is a cross-sectional view showing a modification of the semiconductor device. FIG. 23 is a plan view showing the semiconductor chip of FIG. FIG. 24 is a diagram illustrating an example in which the first wire is deformed when the first wire is pressed when there is no uneven structure. FIG. 25 is a diagram illustrating an example in which the first wire is deformed when the first wire is pressed when there is an uneven structure. FIG. 26 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 27 is a diagram showing an example of obtaining a second semiconductor chip to which the insulating adhesive layer of FIG. 26 is attached. FIG. 28 is a diagram for obtaining a second semiconductor chip to which the insulating adhesive layer of FIG. 26 is attached. FIG. 29 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 30 is a view showing an example of obtaining a second semiconductor chip to which the insulating adhesive layer of FIG. 29 is attached. FIG. 31 is a diagram showing an example of obtaining a second semiconductor chip to which the insulating adhesive layer of FIG. 29 is attached. FIG. 32 is a sectional view showing a semiconductor device according to an embodiment of the present invention. 33 is a partial plan view showing the lead frame of FIG. FIG. 34 is a diagram showing a method of manufacturing the semiconductor device of FIG. FIG. 35 is a diagram showing a step subsequent to FIG. FIG. 36 is a diagram showing a modification of the method for manufacturing the semiconductor device of FIGS.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 Board | substrate 14 1st semiconductor chip 16 2nd semiconductor chip 26 1st wire 28 2nd wire 30 Sealing resin 34 Insulating adhesive layer 36 Insulating adhesive layer 38 1st adhesive layer 40 2nd Adhesive layer 42 Uneven structure 60 Semiconductor wafer 64 Insulating adhesive layer 66 Uneven structure 68 Lead frame 70 Die pad 72 Lead

Claims (5)

A first semiconductor chip mounted on the chip mounting member;
In a semiconductor device including a second semiconductor chip disposed on the first semiconductor chip,
Between the first semiconductor chip and the second semiconductor chip, an insulative adhesive layer composed of a first adhesive layer and a second adhesive layer having different physical properties is provided,
A fine uneven structure is uniformly formed at the interface between the first adhesive layer and the second adhesive layer.
A semiconductor device.   A part of the first wire for electrically connecting the electrode pad of the first semiconductor chip and the electrode of the chip mounting member penetrates into the first adhesive layer of the insulating adhesive layer. The semiconductor device according to claim 1.   2. The pitch between the concave and convex portions of the concavo-convex structure or between the convex portions and the convex portions is equal to or smaller than the pitch of the electrode pads of the first semiconductor chip. Semiconductor device.   The first adhesive layer is made of an insulating film-like resin adhesive layer having low viscosity thermoplasticity, and the second adhesive layer is made of an insulating film-like resin adhesive layer having high viscosity thermoplasticity. The semiconductor device according to claim 1. Mounting the first semiconductor chip on the chip mounting member;
Electrically connecting the electrode pads of the first semiconductor chip and the terminals of the chip mounting member by a first wire;
Insulating property comprising a first adhesive layer and a second adhesive layer that are superposed on each other and having different physical properties, and a fine uneven structure is formed at the interface between the first adhesive layer and the second adhesive layer A second semiconductor chip to which the second adhesive layer of the adhesive layer is fixed is laminated and disposed on the first semiconductor chip;
And fixing the first adhesive layer of the insulating adhesive layer to the first semiconductor chip so that a part of the first wire enters the first adhesive layer of the insulating adhesive layer,
A method for manufacturing a semiconductor device, comprising: electrically connecting an electrode pad of the second semiconductor chip and a terminal of the chip mounting member with a second wire.

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