JP2006093215A - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure for manufacturing a fin type NAND flash memory in a self-alignment process along with its manufacturing method. <P>SOLUTION: By employing a strip-like SOI layer, a silicon layer region 8 is formed on a BOX oxide film 13. A tunnel insulating film 9 and an insulating film region 31 are formed respectively on the side surface and upper surface of the silicon layer region 8. A floating gate region 36 is formed to contact the tunnel insulating film 9 and the insulating film region 31. An insulating film 37 is formed to contact the floating gate region 36. A floating gate region 38 is formed to contact the insulating film 37 and the insulating film region 31. In this construction, the floating gate region 36 is formed higher than the silicon region 8. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a NAND nonvolatile semiconductor memory device using a fin structure and a self-aligned manufacturing method thereof.

  In recent years, with the rapid expansion of the market for digital audio cameras and other portable audio devices such as mobile phones, the demand for NAND flash memories is rapidly expanding. Currently, the demands for smaller, lighter, and higher functionality of these devices are becoming stricter, and along with this, the miniaturization, higher integration, lower power supply voltage, and higher reliability of NAND flash memory are increasing. It is becoming required.

  However, the limits of miniaturization in the conventional planar structure (FIG. 1) have been recognized. For this reason, introduction of new materials and new structures is being studied. One of the most promising new structures is a structure using a fin structure. 2 is a plan view schematically showing a layout of a memory region constituted by this structure, FIG. 3 is a cross-sectional view taken along the line AA (cross-section perpendicular to the channel) in FIG. 2, and FIG. It is sectional drawing cut off by the BB cross section (cross section of a channel direction). In the conventional structure shown in FIG. 1, only the region sandwiched between the diffusion layer regions 5 and 6 immediately below the tunnel insulating film 4 is involved in channel electrical conduction, but the fin structure shown in FIGS. In the case of the NAND structure using the above, all of the silicon layer region 8 in FIG. 5 covered with the tunnel insulating film 9 contributes to the electrical conduction of the channel. FN (Fowler-Nordheim) current writing efficiency is improved. For this reason, the NAND flash memory using the fin structure (hereinafter referred to as the fin-type NAND flash memory) is considered to be one of the most promising structures that can meet the demands for further miniaturization and higher integration. It has been.

  However, the conventional fin-type NAND flash memory shown in FIG. 3 has a problem that it is difficult to manufacture as exemplified below. In this structure, in order to realize the operation peculiar to the NAND structure, it is necessary to form the floating gate 10 separately from other element regions as shown in FIG. As a manufacturing method therefor, two methods described below can be considered. One is a method of adding a mask as shown in FIG. First, the SOI layer of the SOI substrate is processed into a structure as shown in FIG. 5A by using a lithography technique to form a silicon region 8. Next, the tunnel insulating film 9 is formed by oxidizing the surface of the silicon region 8 or depositing an insulating film (by CVD or the like). Next, polysilicon is deposited and the upper portion is planarized by CMP or the like to form a structure as shown in FIG. Next, a resist is deposited, and a resist region 16 as shown in FIG. 5 (d) is formed by using lithography. By using this as a mask, the polysilicon region 15 is etched, so that FIG. 5 (e) is obtained. Get the structure shown. Next, an insulating film 11 is formed by oxidizing or depositing an insulating film on the surface of the polysilicon region 17 shown in FIG. 5E, and polysilicon 12 is deposited so as to cover the insulating film 11, whereby FIG. The structure shown in (f) is obtained.

  However, since the manufacturing method shown in FIG. 5 uses a mask, the increase in cost is serious. In the current situation where it is the most prominent task to avoid the use of masks as much as possible for cost reduction, a manufacturing method with an increased number of masks reduces cost efficiency in production. In addition, there is a limit to improving the accuracy of mask alignment, which is disadvantageous in the design of alignment.

  On the other hand, as a method for manufacturing a fin-type NAND flash memory in a self-aligning manner without using a mask, a method shown in FIG. 6 can be considered. In this manufacturing method, first, after the structure shown in FIG. 6B is formed, polysilicon 18 is deposited. Then, as shown in FIG. 6A, the upper surface of the polysilicon 18 is uneven due to the presence of the convex silicon region 8. Next, as shown in FIG. 6B, an insulating film such as a nitride film is deposited on the polysilicon region 18 and etched back to form a sidewall insulating film 19 using the unevenness on the polysilicon region 18. be able to. By etching the polysilicon region 18 using the sidewall insulating film 19 as a mask, the structure shown in FIG. 6C is obtained. Then, the structure shown in FIG. 6D is obtained by oxidizing the polysilicon layer 20 or depositing an insulating film and then depositing the polysilicon layer 21.

  According to this manufacturing method, a fin-type NAND flash memory can be manufactured in a self-aligning manner without using a mask. However, since it is difficult to control the size of the unevenness on the upper surface of the polysilicon 18, it is difficult to form the sidewall insulating film 19 used as a mask shown in FIG. 6B with good controllability. This causes a variation in the size of the polysilicon layer 20 used as a floating gate, resulting in a variation in device characteristics.

  As described above, it is difficult to manufacture the fin-type NAND flash memory in a self-aligned manner without causing a significant increase in cost.

As a process example of the manufacturing method using the mask, an insulating film is deposited, the insulating film is processed by using lithography, and a groove is formed using the processed insulating film as a mask (Patent Document) 1).
JP 2000-223676 A

  The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a structure capable of manufacturing a fin-type NAND flash memory in a self-aligned manner and a manufacturing method thereof. .

  In order to achieve the above object, a nonvolatile semiconductor memory device according to a first aspect of the present invention includes a first insulating film and a plurality of insulating films formed on the first insulating film and covered with the second insulating film. A first conductive type semiconductor substrate having a fin layer, and a floating gate having an upper surface formed lower than an upper surface height of the fin layer on both side surfaces perpendicular to the channel of the fin layer and covered with a third insulating film; A control gate formed on the second insulating film and the third insulating film in the previous period, and an upper surface region of the fin layer in contact with the second insulating film and higher than the upper surface of the floating gate. And an impurity diffusion layer of the first conductivity type.

  According to a second aspect of the present invention, there is provided a non-volatile semiconductor memory device including a first insulating film and a plurality of fin layers formed on the first insulating film and covered with the second insulating film. A conductive semiconductor substrate, a floating gate having an upper surface formed higher than the upper surface height of the fin layer on both side surfaces perpendicular to the channel of the fin layer, and covered with a third insulating film; and the second insulation And a control gate formed on the third insulating film, and the thickness of the second insulating film on the fin layer between the floating gates on both sides of the fin layer is the same as that of the floating gate. It is characterized by being formed thicker than the thickness of the second insulating film between the fin layers.

  According to a third aspect of the present invention, there is provided a non-volatile semiconductor memory device comprising: a first insulating film comprising a plurality of insulating film regions; and a plurality of insulating films formed between the plurality of insulating film regions and covered with a second insulating film. A first conductivity type semiconductor substrate having a fin layer, and a floating gate having a top surface formed lower than a top surface height of the fin layer on both side surfaces perpendicular to the channel of the fin layer and covered with a third insulating film And a control gate formed on the second insulating film and the third insulating film in the previous period, and an upper surface region of the fin layer in contact with the second insulating film and higher than the upper surface of the floating gate. And an impurity diffusion layer of the first conductivity type formed.

  According to a fourth aspect of the present invention, there is provided a non-volatile semiconductor memory device comprising: a first insulating film comprising a plurality of insulating film regions; and a plurality of insulating films formed between the plurality of insulating film regions and covered with a second insulating film. A first conductivity type semiconductor substrate having a fin layer, and a floating gate whose upper surface is formed higher than the upper surface height of the fin layer on both side surfaces perpendicular to the channel of the fin layer and covered with a third insulating film And a control gate formed on the second insulating film and the third insulating film, and the thickness of the second insulating film on the fin layer between the floating gates on both sides of the fin layer This is characterized in that it is formed thicker than the thickness of the second insulating film between the floating gate and the fin layer.

  According to a fifth aspect of the present invention, there is provided a method for manufacturing a nonvolatile semiconductor memory device, comprising: forming a plurality of fin layers on a first conductivity type semiconductor substrate formed on a first insulating film; Forming an impurity diffusion layer of a first conductivity type in an upper surface region facing the first insulating film region; covering the fin layer with a second insulating film; and the fin covered with an insulating film A step of depositing a semiconductor layer so as to cover the layer, a step of etching back the semiconductor layer to form a desired height, a fin layer covered with the insulating film, and the second layer on the semiconductor layer Depositing a third insulating film having a selectivity different from that of the insulating film; etching the second insulating film to form a sidewall insulating film on a side surface perpendicular to the channel of the fin layer; and The semiconductor layer is etched using the insulating film as a mask. Forming a floating gate on the side surface perpendicular to the channel through the first insulating film by coating, covering the floating gate with a fourth insulating film, and via the fourth insulating film Forming a control gate so as to cover the floating gate and the impurity diffusion layer region of the first conductivity type.

  According to a sixth aspect of the present invention, there is provided a method for manufacturing a nonvolatile semiconductor memory device, comprising: forming a plurality of fin layers on a first conductivity type semiconductor substrate formed on a first insulating film; Forming a second insulating film on a side surface perpendicular to the channel; and a third thickness thicker than the thickness of the second insulating film at a position facing the top surface of the fin layer and facing the first insulating film Forming an insulating film; depositing a semiconductor layer to cover the fin layer covered with the second and third insulating films; and etching back the semiconductor layer to form a desired height. And depositing a fourth insulating film having a selectivity different from that of the second and third insulating films on the fin layer covered with the second and third insulating films and the semiconductor layer; The fin layer channel is etched back by etching the fourth insulating film. Forming a side wall insulating film on a side surface perpendicular to the surface, and etching the semiconductor layer using the side wall insulating film as a mask to form the fin layer on the side surface perpendicular to the channel via the second and third insulating films. Forming a floating gate having a higher upper surface than the step of covering the floating gate with a fifth insulating film, and the floating gate and the third through the fifth insulating film. And a step of forming a control gate so as to cover the insulating film.

  According to a seventh aspect of the present invention, there is provided a non-volatile semiconductor memory device manufacturing method comprising: forming a plurality of fin layers by forming grooves in a first conductivity type semiconductor substrate; and forming a first insulating film in the grooves Forming a layer lower than the height of the upper surface of the fin layer, forming a first conductivity type impurity diffusion layer in the upper surface region of the fin layer, and covering the fin layer with a second insulating film A step of depositing a semiconductor layer so as to cover the fin layer covered with the insulating film, a step of etching the semiconductor layer to form a desired height, and a fin covered with the insulating film Depositing a third insulating film having a selectivity different from that of the second insulating film on the semiconductor layer and the semiconductor layer; and etching the second insulating film to form a side surface perpendicular to the channel of the fin layer. Forming a sidewall insulating film; Etching the semiconductor layer using the sidewall insulating film as a mask to form a floating gate on the side surface perpendicular to the channel via the first insulating film; and covering the floating gate with a fourth insulating film And a step of forming a control gate so as to cover the floating gate and the impurity diffusion layer region of the first conductivity type via the fourth insulating film. Device manufacturing method.

  According to another aspect of the present invention, there is provided a method for manufacturing a nonvolatile semiconductor memory device, the step of forming a plurality of fin layers by forming grooves in a first conductivity type semiconductor substrate, and the upper surface of the fin layer in the grooves. Forming a first insulating film layer formed lower than the height, forming a second insulating film on a side surface perpendicular to the channel of the fin layer, and forming the second insulating film on an upper surface of the fin layer. Forming a third insulating film thicker than the thickness of the insulating film; depositing a semiconductor layer so as to cover the fin layer covered with the first, second and third insulating films; Etching back the semiconductor layer to a desired height, the fin layer covered with the second and third insulating films, and the second and third insulating films on the semiconductor layer and the selection ratio Depositing a fourth insulating film having a different thickness and the fourth insulating film Forming a sidewall insulating film on the side surface perpendicular to the channel of the fin layer by etching, and etching the semiconductor layer using the sidewall insulating film as a mask to form the second and third surfaces on the side surface perpendicular to the channel. A step of forming a floating gate having an upper surface set higher than the fin layer via the insulating film, a step of covering the floating gate with a fifth insulating film, and the fifth insulating film And forming a control gate so as to cover the floating gate and the third insulating film.

  Since the manufacturing method of the nonvolatile semiconductor memory device using the fin structure of the present invention is a self-aligned manufacturing method that does not use a mask, the floating gate having a good shape can be manufactured without increasing the cost. As a result, a high-performance nonvolatile semiconductor memory device utilizing the characteristics of the fin structure can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 7 is a cross-sectional view in the direction perpendicular to the channel showing the element structure of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. A manufacturing method for forming this element structure will be described with reference to FIG.

  First, through the manufacturing steps shown in FIGS. 5A and 5B, the structure shown in FIG. 8A is obtained. Next, as shown in FIG. 8B, a p-type diffusion region 22 is formed by ion implantation to form a fin composed of 8,22. Next, as shown in FIG. 8C, a polysilicon layer 23 is deposited. Next, as shown in FIG. 8D, the polysilicon layer 24 is formed by etching back the polysilicon layer 23. Next, as shown in FIG. 8E, the sidewall insulating film 25 is formed by, for example, etching back after CVD. The sidewall insulating film may be an insulating film having a selectivity with respect to the gate insulating film 9. For example, when a thermal oxide film is used as the gate insulating film 9, a nitride film may be used. Next, the polysilicon layer 24 is etched using the side wall insulating film 25 as a mask to form a floating gate 26 (FIG. 8F). Next, insulating film regions 27 and 28 are formed by depositing or oxidizing the insulating film (FIG. 8G). Finally, a polysilicon layer 29 is deposited to form a control gate 29, thereby obtaining the structure shown in FIG.

  3 and FIG. 7, the remarkable difference is that in FIG. 7, the p-type diffusion layer region 22 exists, and this region is not covered by the floating gate but covered by the control gate 29. It is. That is, this region has a normal MOS structure. In order to form a fin-type NAND flash memory in a self-aligned manner, as shown in FIG. 8 (h), a MOS structure including a control gate 29, a gate insulating film 9, and a convex silicon region 22 is inevitably required. Will be formed. Since a high voltage is applied to the control gate, a leakage current flows through the convex silicon region 22 as it is, and the flash memory does not operate. In order to prevent this, in the first embodiment of the present invention, as shown in FIGS. 7 and 8, ion implantation is performed and a p-type diffusion layer is formed in the region 22 to increase the threshold value and leak. The current is prevented.

(Second embodiment)
FIG. 9 is a cross-sectional view showing the element structure of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. A manufacturing method for forming this element structure will be described with reference to FIG.

  First, as shown in FIG. 10A, an insulating film layer 30 is deposited on a silicon substrate 39 on the buried oxide film 13. Next, an insulating film is further formed through a lithography process and an etching process, whereby the structure shown in FIG. 10B (the insulating film 31 is formed on the silicon layer 8 that is a fin, and the tunnel insulating film 9 is formed on the side wall). Structure). Next, a polysilicon layer 33 is deposited (FIG. 10C), and after this polysilicon layer 33 is etched back, a sidewall insulating film 34 is formed (FIG. 10D). In this case, the height h of the polysilicon layer 35 is formed to be higher than the height l of the silicon region 8 by adjusting the deposition amount of the insulating film layer 30 and the etch back amount of the polysilicon layer 33. . Next, the polysilicon layer 35 is etched using the sidewall insulating film 34 as a mask to form the floating gate region 36, and then the insulating film region 37 is formed by oxidation or deposition. Next, a control gate region 38 is formed by depositing a polysilicon layer. In this way, the structure shown in FIGS. 9 and 10 (f) is obtained.

  A feature of this structure is that the height h of the floating gate 36 is set at a position higher than the height l of the silicon region 8. The reason for having such a structure will be described with reference to FIG. In FIG. 11, the height h of the floating gate 36 is set at a position lower than the height l of the silicon region 8. In this case, a region surrounded by a dotted line in FIG. 11 is constituted by a MOS structure including a control gate 38, a gate insulating film 9, and a silicon region 8. Since a high voltage is applied to the control gate 38, a leak current flows in the silicon layer region in the region surrounded by the dotted line in FIG. In order to avoid this problem, the height h of the floating gate 36 is set higher than the height l of the silicon region 8 in the structure shown in FIGS.

(Third embodiment)
FIG. 12 is a cross-sectional view showing an element structure of a nonvolatile semiconductor memory device according to the third embodiment of the present invention. The difference from the first embodiment of the present invention is that a silicon substrate 50 is used instead of an SOI substrate. A manufacturing method for forming this element structure will be described with reference to FIG.

  First, as shown in FIG. 13 (a), a resist is deposited on the silicon substrate 39, patterned using lithography, and then the silicon layer is etched, whereby a convex shape as shown in FIG. 13 (b) is obtained. A silicon region 41 is formed. Next, an insulating film layer 42 is deposited, and this insulating film layer is selectively etched to obtain the structure shown in FIG. Next, as shown in FIG. 13D, a p-type diffusion layer region 43 is formed on the silicon region 41 by ion implantation. Next, as shown in FIG. 13E, after an insulating film 44 is formed, a polysilicon layer is deposited and etched back to form a polysilicon layer 45 as shown in FIG. 13F. . Next, an insulating film having a selection ratio different from that of the insulating film 44 is deposited, and selective etching is performed to form the sidewall insulating film 46. Using this sidewall insulating film 46 as a mask, the polysilicon layer 45 is etched to form the floating gate 47 of FIG. 13 (h), and then the insulating film 48 is formed as shown in FIG. 13 (h). . Next, a control gate 49 shown in FIG. 13 (i) is formed by depositing a polysilicon layer. After the manufacturing process shown in FIG. 13 (i), ion implantation for forming a source / drain region is performed as shown in FIG. 13 (j). At this time, the presence of the insulating film region 42 prevents the source / drain regions of each transistor from being short-circuited, so the presence of the insulating film region 42 is essential. In this way, the structure shown in FIG. 12 is formed.

  The device operation effect expected in the third embodiment is the same as that of the first embodiment, but the first embodiment uses an expensive SOI substrate, whereas the third embodiment uses the third embodiment. Since the embodiment uses a conventional silicon substrate, it is characterized in that it is more advantageous in terms of cost than the device structure in the first embodiment.

(Fourth embodiment)
FIG. 14 is a sectional view showing an element structure of a nonvolatile semiconductor memory device according to the third embodiment of the present invention. The difference from the second embodiment of the present invention is that a silicon substrate 50 is used instead of an SOI substrate. A manufacturing method for forming this element structure will be described with reference to FIG.

  First, as shown in FIG. 15A, an insulating film layer 51 is deposited on a silicon substrate 39. Next, a resist is deposited on the insulating film layer 51, patterned by using lithography, and then the silicon layer is etched to form the convex silicon region 41 and the insulating film layer 52 as shown in FIG. Form. Next, after forming the insulating film 53, an insulating film layer having a selection ratio different from that of the insulating film 53 is deposited, and the insulating film layer is selectively etched to form the insulating film region 42 (FIG. 15C). ). Next, a polysilicon layer is deposited and etched back to obtain the structure shown in FIG. Next, as shown in FIG. 15E, an insulating film having a selection ratio different from that of the insulating film 52 is deposited and selectively etched to form a sidewall insulating film 46. Using this sidewall insulating film 46 as a mask, the polysilicon region 54 is etched, thereby forming a floating gate 55 as shown in FIG. Next, an insulating film 56 is formed by oxidation or deposition (FIG. 15G), and finally a polysilicon layer 57 is deposited to obtain the structure shown in FIG.

  The device operation effect expected in the fourth embodiment is the same as that of the second embodiment, but the second embodiment uses an expensive SOI substrate, while the fourth embodiment Since a conventional silicon substrate is used in the embodiment, it is advantageous in terms of cost over the device structure in the second embodiment.

(Fifth embodiment)
This embodiment shows an example of application to an actual chip, and FIG. 16 is a block diagram showing a media chip of a cellular phone incorporating the nonvolatile semiconductor memory device of the first and fourth embodiments of the present invention. It is. The nonvolatile semiconductor memory device of the present invention is incorporated in the memory portion in FIG. FIG. 16 shows a typical example of a memory / logic mixed circuit. When the NAND flash memory using the fin structure of the present invention is incorporated in the memory portion, it is conceivable that the transistors constituting the logic portion and the peripheral circuit also use the fin structure. However, even if the fin structure is used for all transistors constituting the circuit, the overall performance is not necessarily improved. Therefore, when the nonvolatile semiconductor memory device of the present invention is incorporated in the memory portion of FIG. 16, a method of using a conventional MOS transistor on a silicon substrate is practical for the other portions.

The element structure sectional drawing which shows the conventional non-volatile semiconductor memory device. The top view of a memory cell array. The element structure sectional drawing of the width direction of the conventional fin type NAND flash memory (cross section in AA of FIG. 2). Sectional drawing of the element structure in the channel direction of a conventional fin-type NAND flash memory (cross section taken along line BB in FIG. 2). Sectional drawing which shows the manufacturing process of the conventional fin type NAND flash memory. Sectional drawing which shows the manufacturing process of the conventional fin type NAND flash memory. Sectional drawing which shows the element structure of the non-volatile semiconductor memory device of 1st embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device of 1st embodiment. Sectional drawing which shows the element structure of the non-volatile semiconductor memory device of 2nd embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device of 2nd embodiment. FIG. 6 is a cross-sectional view showing an element structure of a nonvolatile semiconductor memory device in which the height of a silicon region 8 is formed larger than the height of a floating gate 36 in the second embodiment. Sectional drawing which shows the element structure of the non-volatile semiconductor memory device of 3rd embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device of 3rd embodiment. Sectional drawing which shows the element structure of the non-volatile semiconductor memory device of 3rd embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device of 3rd embodiment. 1 is a block diagram showing a media chip of a cellular phone incorporating a nonvolatile semiconductor memory device of the present invention.

Explanation of symbols

1, 12, 21, 29, 38, 49, 57: Control gate
2, 11, 27, 28, 30, 31, 37, 42, 48, 52, 56: Insulating film
3, 10, 17, 20, 26, 36, 47, 55: Floating gate
4, 9, 32, 44, 53: Tunnel insulating film
5: Source area
6: Drain region
7, 39: Silicon substrate
8, 41, 50: Silicon layer
9: Drain region
13: buried oxide film
14: Diffusion layer region
15, 18, 33, 35, 45, 54: Polysilicon layer
16, 40: resist
19, 25, 34, 46: Side wall insulating film
22, 43: p-type high-concentration diffusion layer region
23, 24: Polysilicon layer

Claims (8)

  A first conductive semiconductor substrate having a first insulating film, a plurality of fin layers formed on the first insulating film and covered with a second insulating film, and both side surfaces perpendicular to the channel of the fin layer; A floating gate having an upper surface formed lower than the upper surface height of the fin layer and covered with a third insulating film; a control gate formed on the second insulating film and the third insulating film in the previous period; A non-volatile semiconductor comprising: a first conductivity type impurity diffusion layer formed in a region of the upper surface of the fin layer in contact with the second insulating film and higher than the upper surface of the floating gate. Storage device.   A first conductive semiconductor substrate having a first insulating film, a plurality of fin layers formed on the first insulating film and covered with a second insulating film, and both side surfaces perpendicular to the channel of the fin layer; A floating gate having an upper surface formed higher than the upper surface height of the fin layer and covered with a third insulating film; a control gate formed on the second insulating film and the third insulating film; The thickness of the second insulating film on the fin layer between the floating gates on both sides of the fin layer is formed to be greater than the thickness of the second insulating film between the floating gate and the fin layer. A non-volatile semiconductor memory device. A first conductive semiconductor substrate having a first insulating film composed of a plurality of insulating film regions, a plurality of fin layers formed between the plurality of insulating film regions and covered with a second insulating film; and the fin layer A floating gate having an upper surface lower than the upper surface height of the fin layer and covered with a third insulating film on both side surfaces perpendicular to the channel; and on the second insulating film and the third insulating film in the previous period And a first conductivity type impurity diffusion layer formed in an upper surface region of the fin layer in contact with the second insulating film and higher than the upper surface of the floating gate. A non-volatile semiconductor memory device. A first conductive semiconductor substrate having a first insulating film composed of a plurality of insulating film regions, a plurality of fin layers formed between the plurality of insulating film regions and covered with a second insulating film; and the fin layer On both side surfaces perpendicular to the channel, the upper surface is formed higher than the upper surface height of the fin layer, and is covered with a third insulating film; on the second insulating film and the third insulating film; And a thickness of the second insulating film on the fin layer between the floating gates on both sides of the fin layer is set so that the second insulation between the floating gate and the fin layer A non-volatile semiconductor memory device, wherein the non-volatile semiconductor memory device is formed thicker than a film thickness.   Forming a plurality of fin layers on a first conductive type semiconductor substrate formed on the first insulating film; and an impurity of a first conductive type in an upper surface region of the fin layer facing the first insulating film region Forming a diffusion layer; covering the fin layer with a second insulating film; depositing a semiconductor layer so as to cover the fin layer covered with the insulating film; and etching back the semiconductor layer. Forming a desired height, depositing a fin layer covered with the insulating film and a third insulating film having a selectivity different from that of the second insulating film on the semiconductor layer, and Forming a sidewall insulating film on a side surface perpendicular to the channel of the fin layer by etching a second insulating film; and etching the semiconductor layer using the sidewall insulating film as a mask to form a side surface perpendicular to the channel. The first insulating film Forming a floating gate, covering the floating gate with a fourth insulating film, and interposing the floating gate and the impurity diffusion layer region of the first conductivity type through the fourth insulating film. Forming a control gate so as to cover the non-volatile semiconductor memory device.   Forming a plurality of fin layers on a first conductive type semiconductor substrate formed on the first insulating film; forming a second insulating film on a side surface perpendicular to the channel of the fin layer; Forming a third insulating film thicker than the second insulating film at a position in contact with the upper surface of the layer and facing the first insulating film; and covering with the second and third insulating films A step of depositing a semiconductor layer so as to cover the exposed fin layer, a step of etching back the semiconductor layer to form a desired height, and a fin layer covered with the second and third insulating films And depositing a fourth insulating film having a different selectivity from the second and third insulating films on the semiconductor layer, and etching back the fourth insulating film so as to be perpendicular to the channel of the fin layer. Forming a sidewall insulating film on the appropriate side surface, and masking the sidewall insulating film. Etching the semiconductor layer as a gate to form a floating gate having a height higher than the fin layer on the side surface perpendicular to the channel via the second and third insulating films; Covering the floating gate with a fifth insulating film, and forming a control gate so as to cover the floating gate and the third insulating film via the fifth insulating film. A method for manufacturing a nonvolatile semiconductor memory device.   Forming a plurality of fin layers by forming grooves in the first conductivity type semiconductor substrate; forming a first insulating film layer in the grooves lower than an upper surface height of the fin layers; and Forming a first conductivity type impurity diffusion layer in the upper surface region of the fin layer; covering the fin layer with a second insulating film; and covering the fin layer covered with the insulating film so as to cover the fin layer A step of etching the semiconductor layer to form a desired height, a fin layer covered with the insulating film, and a second insulating film having a different selectivity than the second insulating film. Depositing a third insulating film, etching the second insulating film to form a sidewall insulating film on a side surface perpendicular to the channel of the fin layer, and using the sidewall insulating film as a mask, the semiconductor layer To etch Forming a floating gate through the first insulating film on a side surface perpendicular to the channel, covering the floating gate with a fourth insulating film, and floating the floating gate through the fourth insulating film. And a step of forming a control gate so as to cover the gate and the impurity diffusion layer region of the first conductivity type.   Forming a plurality of fin layers by forming grooves in the first conductivity type semiconductor substrate; forming a first insulating film layer formed in the grooves lower than the height of the upper surface of the fin layers; Forming a second insulating film on a side surface perpendicular to the channel of the fin layer; forming a third insulating film thicker than the second insulating film on the upper surface of the fin layer; Depositing a semiconductor layer so as to cover the fin layer covered with the first, second and third insulating films; etching back the semiconductor layer to form a desired height; and Depositing a fourth insulating film having a selectivity different from that of the second and third insulating films on the fin layer covered with the second and third insulating films and the semiconductor layer; and the fourth insulating film Side to the side perpendicular to the channel of the fin layer by etching Forming an insulating film; and etching the semiconductor layer using the sidewall insulating film as a mask to form a height above the fin layer on the side surface perpendicular to the channel via the second and third insulating films. Forming a floating gate set to a high value, covering the floating gate with a fifth insulating film, and covering the floating gate and the third insulating film via the fifth insulating film Forming a control gate as described above, and a method for manufacturing a nonvolatile semiconductor memory device.

Images