TWI469270B - Method for fabricating nand type flash memory device - Google Patents

Description

Reverse gate type flash memory device manufacturing method

The present invention relates to a non-volatile memory device, and more particularly to a method of fabricating a NAND type flash memory device.

Flash memory has the advantages of small area, power saving, high speed and low operating voltage, so it is widely used in non-volatile memory technology. NAND type flash memory is a type of flash memory. It is a digital camera, mobile phone, printer, because of its large capacity, impact resistance, less noise, and lightness and shortness. Important components of products such as personal digital assistants (PDAs).

In the production of the current anti-gate type flash memory device, in order to integrate the high-voltage and low-voltage operating elements (ie, transistors) of the peripheral logic circuit into the fabrication of the memory cell array, the gates of the high-voltage and low-voltage operating elements are each The floating gate of the memory cell must use a doped semiconductor layer of the same conductivity type (eg, n-type) as the material. As a result, for the p-type low-voltage operating element, the electrical characteristics and performance of the component itself are reduced. Furthermore, the thickness of the gate dielectric layer of the low voltage operating element must be limited by the thickness of the tunnel oxide layer of the memory cell. As a result, the electrical characteristics and performance of the component itself cannot be improved by reducing the thickness of the gate dielectric layer of the low voltage operating element.

Therefore, it is necessary to find a manufacturing method of the anti-gate type flash memory device which can improve or solve the above problems.

An embodiment of the present invention provides a method for fabricating a reverse-gate type flash memory device, including: providing a semiconductor substrate having a first region and a second region and a third region adjacent to the first region; Forming a first gate oxide layer on the substrate, wherein the first gate oxide layer corresponding to the first and second regions has a first thickness, and the first gate oxide layer corresponding to the third region has a larger than the first a second thickness of the thickness; forming a first gate layer and a second gate layer on the first gate oxide layer of the second and third regions, respectively, and exposing the first gate oxide in the first region a layer; the exposed first gate oxide layer is oxidized to form a second gate oxide layer having a third thickness, wherein the third thickness is different from the first and second thicknesses; and the second gate is oxidized Forming a third gate layer and an inter-gate dielectric layer on the layer; and forming a fourth gate layer on the first gate layer, the second gate layer and the inter-gate dielectric layer, A fifth gate layer and a sixth gate layer.

Hereinafter, a method of manufacturing the anti-gate type flash memory device according to the embodiment of the present invention will be described. However, the present invention is to be understood as being limited to the details of the present invention.

1A to 1J are schematic cross-sectional views showing a manufacturing method of an anti-gate type flash memory device according to an embodiment of the present invention. Referring to Figures 1A and 1B, a semiconductor substrate 100, such as a germanium substrate or other semiconductor material substrate, is provided. The semiconductor substrate 100 has a first region 10 and a second region 20a and a third region 20b adjacent to the first region 10. In this embodiment, the first region can serve as a cell array region of the anti-gate type flash memory device. Furthermore, the second region 20a and the third region 20b can serve as a peripheral circuit region of the anti-gate type flash memory device. In an embodiment, the second zone 20a can be located between the first zone 10 and the third zone 20b, wherein the second zone 20a can be a low voltage operating element zone and the third zone 20b can be a high voltage operating element zone.

Next, a first gate oxide layer 102, such as a hafnium oxide layer, is formed on the semiconductor substrate 100, wherein the first gate oxide layer 102 corresponding to the first region 10 and the second region 20a has a first thickness T1. Furthermore, the first gate oxide layer 102 corresponding to the third region 20b has a second thickness T2 greater than the first thickness T1, as shown in FIG. 1A. For example, the first thickness T1 can be between 30 and 50 angstroms ( The range of the second thickness T2 may be in the range of 300 to 500 angstroms.

Next, a semiconductor layer 104, such as an undoped polysilicon layer or other suitable layer of semiconductor material, is formed over the first gate oxide layer 102 for subsequent fabrication of high voltage and low voltage operating elements in the peripheral circuit region. The purpose of the gate. A mask layer (not shown) such as a tantalum nitride layer is formed on the semiconductor layer 104. Next, the mask layer is patterned by conventional lithography and etching techniques to form a mask pattern layer 106 on the semiconductor layer 104 of the second region 20a and the third region 20b, thereby exposing the semiconductor located in the first region 10. Layer 104.

Next, referring to FIG. 1B, the mask pattern layer 106 can be used as an etching mask to further remove the exposed semiconductor layer 104 to expose the first gate oxide layer 102 in the first region 10, and in the second A first gate layer 104a and a second gate layer 104b are formed on the first gate oxide layer 102 of the region 20a and the third region 20b, respectively.

Referring to FIG. 1C, a mask layer (not shown) such as a tantalum nitride layer is formed conformally to the structure of FIG. 1B. An anisotropic etch is performed on the mask layer to form a mask spacer 108 on the sidewall of the semiconductor layer of the second region 20a (i.e., the first gate layer 104a). Thereafter, the exposed first gate oxide layer 102 is subjected to an oxidation treatment, such as thermal oxidation treatment, to form a second gate oxide layer 110 having a third thickness T3 in the first region 10, wherein the third thickness T3 is different. The first thickness T1 and the second thickness T2 (indicated in FIG. 1A). In the embodiment, the third thickness T3 is greater than the first thickness T1 and smaller than the second thickness T2. For example, the third thickness T3 may range from 70 to 80 angstroms. The second gate oxide layer 110 serves as a tunnel oxide layer material for each memory cell in the cell array region. As such, the thickness of the first gate oxide layer 102 of the second region 20a (ie, the first thickness T1) may not be limited to the thickness of the second gate oxide layer 110 (ie, the third thickness T3).

Next, referring to FIG. 1D, after removing the mask pattern layer 106 and the mask spacer 108 in FIG. 1C, a third gate is formed on the second gate oxide layer 110 (ie, the tantalum oxide layer). The pole layer 112 is for subsequent use of a floating gate (FG) for fabricating a memory cell in the cell array region. The third gate layer 112 can be a single layer or a multilayer structure. In an embodiment, an undoped semiconductor layer 112a (eg, an undoped polysilicon layer) may be sequentially formed on the first gate layer 104a, the second gate layer 104b, and the second gate oxide layer 110. And a doped semiconductor layer 112b (eg, an n-doped polysilicon layer). Thereafter, the undoped semiconductor layer 112a and the doped semiconductor layer 112b may be patterned by conventional lithography and etching techniques to remove undoped layers on the first gate layer 104a and the second gate layer 104b. The semiconductor layer 112a and a doped semiconductor layer 112b form a third gate layer 112 having a multilayer structure in the second gate oxide layer 110.

Referring to FIG. 1E, a hard mask layer 114 and a photoresist layer are sequentially formed on the first gate layer 104a, the second gate layer 104b, and the third gate oxide layer 112. Show). Thereafter, an opening 116 defining an isolation region can be formed in the hard mask layer 114 by conventional lithography and etching processes. Next, the gate layer (eg, the first gate layer 104a, the second gate layer 104b, and the third gate oxide layer 112) under the opening 116 is sequentially etched, and the gate oxide layer (eg, the first gate oxide) The layer 102 and the second gate oxide layer 110) and the semiconductor substrate 100 are formed with a plurality of openings 117 in the semiconductor substrate 100. The opening 117 is for subsequent formation of an isolation structure. The area between the openings 117 serves as an active area (AA). It should be noted that the section shown in Fig. 1E is the direction of the bit line of each memory cell (or the direction of the word line parallel to each memory cell).

Referring to FIG. 1F, after removing the hard mask layer 114, a dielectric material can be formed in and over each opening 117 by a conventional deposition technique, such as chemical vapor deposition (CVD). For example, yttrium oxide is formed to form isolation structures 118 (eg, shallow trench isolation (STI)). Next, a dielectric layer 120 is formed in compliance with the upper surface and sidewalls of the floating gate (ie, the third gate layer 112) of the first region 10 and the upper surface of the isolation structure 118 of the first region 10. As an inter-gate dielectric layer. In an embodiment, the dielectric layer 120 may include an oxide-nitride-oxide (ONO) structure.

Next, referring to FIGS. 1G and 1G-1, a semiconductor layer 122 is formed on the structure shown in FIG. 1F, such as an undoped polysilicon layer or other suitable semiconductor material layer for subsequent periphery. A gate of a high voltage and low voltage operating element is fabricated in the circuit region and a control gate (CG) is fabricated in the cell array region. It should be noted here that the section shown in Fig. 1G-1 is parallel to the bit line direction of each memory cell (or perpendicular to the word line direction of each memory cell).

Next, please refer to FIG. 1H, in which the cross section is parallel to the bit line direction of each memory cell (or perpendicular to the word line direction of each memory cell). The semiconductor layer 122 and its underlying gate layers (eg, the first gate layer 104a, the second gate layer 104b, and the third gate oxide layer 112) and the gate can be patterned by conventional lithography and etching processes The dielectric layer 120 is formed with a fourth gate layer 122a, a fifth gate layer 122b and a first layer on the first gate layer 104a, the second gate layer 104b and the inter-gate dielectric layer 120. Six gate layers 122c. In the present embodiment, the sixth gate layer 122c serves as a control gate, and the third gate oxide layer 112 under the control gate serves as a floating gate.

Thereafter, a portion of the dielectric material on the isolation structure 118 and a gate oxide layer on the outside of the gate layer (eg, the first gate layer 104a, the second gate layer 104b, and the third gate oxide layer 112) may be removed ( For example, the first gate oxide layer 102 and the second gate oxide layer 110) expose the surface of the semiconductor substrate 100. In this embodiment, the first gate layer 104a and the fourth gate layer 122a are used as gates of the low voltage operating element, and the first gate layer 102a under the first gate layer 104a is used as the low voltage operating element. Gate oxide layer. Furthermore, the second gate layer 104b and the fifth gate layer 122b serve as gates of the high voltage operation element, and the first gate layer 102b under the second gate layer 104b is oxidized as the gate of the high voltage operation element. Floor.

Next, referring to FIG. 1I, a dielectric layer (not shown) such as a hafnium oxide layer is formed conformally in the structure of FIG. 1H. Next, the dielectric layer is anisotropically etched to form gate spacers 124, 126, and 128 in the first region 10, the second region 20a, and the third region 20b, respectively.

Next, referring to FIG. 1J, an n-type and/or p-type ion cloth value may be performed on the structure of FIG. 1I to form a desired one in the first region 10, the second region 20a, and the third region 20b, respectively. Conductive gates and source/drain regions corresponding to these gates (not shown). In this way, the fabrication of the anti-gate type flash memory device of the embodiment is completed. In other embodiments, a metal germanide layer 130 is formed on the fourth gate layer 122a, the fifth gate layer 122, and the sixth gate layer 122c through a conventional metal germanium process, and the insulating spacers are formed. Metal telluride layers 140 and 142 are formed on the semiconductor substrate 100 on the outer sides of 126 and 128, respectively. The metal telluride layer can effectively reduce the contact resistance between the component and the interconnect. In an embodiment, the metal telluride layers 130, 140, and 142 may include cobalt telluride (CoSi _x ).

According to the above embodiment, since the doped semiconductor layer for fabricating the gate of the low voltage operating element is different from the doped semiconductor layer of the floating gate of the memory cell, the gate of the low voltage operating element and the floating of the memory cell The gates can have different conductivity types, thereby avoiding reducing the electrical characteristics and performance of the low voltage operating elements. Furthermore, since the thickness of the gate oxide layer of the low voltage operating element is not limited to the thickness of the tunneling oxide layer of the memory cell, the electrical characteristics of the low voltage operating element can be improved by reducing the thickness of the gate layer of the low voltage operating element. And performance.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . First district

20a. . . Second district

20b. . . Third district

T1. . . First thickness

T2. . . Second thickness

T3. . . Third thickness

100. . . Semiconductor substrate

102, 102a, 102b. . . First gate oxide

104, 122. . . Semiconductor layer

104a. . . First gate layer

104b. . . Second gate layer

106. . . Mask pattern layer

108. . . Curtain spacer

110. . . Second gate oxide

112. . . Third gate layer

112a. . . Undoped semiconductor layer

112b. . . Doped semiconductor layer

114. . . Hard mask layer

116, 117. . . Opening

118. . . Isolation structure

120. . . Dielectric layer

122a. . . Fourth gate layer

122b. . . Fifth gate layer

122c. . . Sixth gate layer

124, 126, 128. . . Gate spacer

130, 140, 142. . . Metal telluride layer

1A to 1J are schematic cross-sectional views showing a manufacturing method of an anti-gate type flash memory device according to an embodiment of the present invention.

10. . . First district

20a. . . Second district

20b. . . Third district

100. . . Semiconductor substrate

102. . . First gate oxide

104a. . . First gate layer

104b. . . Second gate layer

110. . . Second gate oxide

112. . . Third gate layer

112a. . . Undoped semiconductor layer

112b. . . Doped semiconductor layer

Claims (10)

A manufacturing method of a gate-type flash memory device, comprising: providing a semiconductor substrate having a first region and a second region and a third region adjacent to the first region; forming a semiconductor substrate a first gate oxide layer, wherein the first gate oxide layer corresponding to the first and second regions has a first thickness, and the first gate oxide layer corresponding to the third region has a larger a second thickness of the first thickness; a first gate layer and a second gate layer respectively formed on the first gate oxide layer of the second and third regions, and the exposed region is located in the first region The first gate oxide layer; the exposed first gate oxide layer is oxidized to form a second gate oxide layer having a third thickness, wherein the third thickness is different from the first And the second thickness; a third gate layer and an inter-gate dielectric layer are sequentially formed on the second gate oxide layer; and the first gate layer, the second gate layer, and the A fourth gate layer, a fifth gate layer and a sixth gate layer are respectively formed on the inter-gate dielectric layer. The manufacturing method of the anti-gate type flash memory device according to claim 1, further comprising forming a metal germanide layer on the fourth, the fifth and the sixth gate layer. The manufacturing method of the anti-gate type flash memory device according to claim 1, wherein the first area is a cell array area of the anti-gate type flash memory device, and the second and the third The zone is a peripheral circuit area of the gate flash memory device. The method of manufacturing the anti-gate type flash memory device of claim 1, wherein the forming the first and the second gate layer further comprises: forming a first oxide layer on the first gate oxide layer a semiconductor layer; a mask pattern layer is formed on the semiconductor layer of the second and third regions to expose the semiconductor layer located in the first region; and the exposed semiconductor layer is removed. The manufacturing method of the anti-gate type flash memory device according to claim 4, wherein before the oxidizing treatment, a mask spacer is further formed on a sidewall of the semiconductor layer of the second region. The manufacturing method of the anti-gate type flash memory device according to claim 5, wherein the mask layer and the mask spacer are made of tantalum nitride. The manufacturing method of the anti-gate type flash memory device according to claim 1, wherein the third thickness is greater than the first thickness and smaller than the second thickness. The method of manufacturing the anti-gate type flash memory device of claim 1, wherein the third gate layer comprises an undoped semiconductor layer and a doped semiconductor layer. The manufacturing method of the anti-gate type flash memory device according to claim 1, wherein the inter-gate dielectric layer comprises an oxide layer-nitride layer-oxide layer structure. The method of manufacturing a reverse-gate type flash memory device according to claim 1, wherein the fourth, fifth, and sixth gate layers are formed by patterning a semiconductor layer.