JP2006085900A - Controller for magnetic tape unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a controller for a magnetic tape unit which can process data in units of a plurality of bytes, and expand a data bus width to be processed without complicating a circuit or leading to an increase in circuit scale, thereby performing data transfer at high speed. <P>SOLUTION: Data can be processed in units of a plurality of bytes using a residual byte creating circuit 1 for creating a residual byte required to cause data from a host 10 to match a tape format, an error correction encoding circuit 3 for creating an error correction code for error correction, a deskew circuit 5 for correcting a skew between data read from an MTU 12, a syndrome creating circuit 6 for creating a syndrome for determining whether there is an error in read data, and a frame buffer 8 for holding (delaying) data. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a control device for a magnetic tape device, and more particularly, to a control device for realizing an increase in capacity, function, and transfer speed of a magnetic tape device.

  With the recent increase in speed of computer systems, higher speed is also required in magnetic tape devices that are peripheral devices. For this reason, it is necessary to expand the data bus width and improve the control method.

  FIG. 2 is a configuration diagram of the tape subsystem. The tape subsystem is interposed between the host 10 as a host device, a magnetic tape unit (MTU: Magnetic Tape Unit) 12 for recording data, and the host 10 and the MTU 12. And a magnetic tape controller (MTC: Magnetic Tape Controller) 11 that converts the format of the data. At the time of data writing, data from the host 10 is input to the MTC 11, and after format conversion is performed here, the data is transferred to the MTU 12. When reading data, read data from the MTU 12 is transferred to the MTC 11, where error correction is performed and format conversion is performed, and then the data is sent to the host 10. The MTC 11 includes an interface unit 11a for transmitting / receiving data to / from the host 10, a data format unit 11b for processing such as format conversion and error correction, and data for D / A conversion / A / D conversion. And a converter 11c.

  FIG. 1 is a block diagram showing an internal configuration of the data formatting unit 11b of the MTC 11. The data formatting unit 11b includes a write formatting unit 11d that performs formatting for recording on the magnetic tape in the MTU 12, and a magnetic tape. It is divided into a read format section 11e that corrects track deviation of read data and detects and corrects data errors.

  The write format unit 11 d includes a remaining byte creation circuit 1, multiplexers 2 and 4, and an error correction coding circuit 3. The remaining byte creating circuit 1 creates a remaining byte (RESIDUAL-BYTE) necessary for matching the data from the host 10 with the tape format. The multiplexer 2 combines custom (CUSTOM) data from the host 10, remaining bytes from the remaining byte creation circuit 1, block (BLOCK) ID, pad (PAD) bytes that are redundant bytes, and the like. The error correction coding circuit 3 creates an error correction code (ECC) that is a check character for error correction. As the error correction code, an AXP (Adaptive Cross Parity) code or a Reed-Solomon code is often used. The multiplexer 4 combines the outputs of the multiplexer 2 and the error correction coding circuit 3.

  On the other hand, the read format unit 11 e includes a deskew circuit 5, a syndrome generation circuit 6, an error correction circuit 7, and a frame buffer 8. The deskew circuit 5 corrects a deviation between data read from the MTU 12. When the data recorded on the magnetic tape is read, the magnetic tape and the magnetic head are generally not perpendicular to each other, and a certain degree of error occurs, and accordingly, a deviation (skew) between the data occurs. The deskew circuit 5 corrects the deviation between the data. The syndrome creation circuit 6 creates information called a syndrome for determining whether there is an error in the read data. The error correction circuit 7 corrects an error in the read data. The frame buffer 8 rearranges data according to the data reading direction of the magnetic tape, and holds (delays) data while the error correction circuit 7 calculates the error coefficient.

  In the tape subsystem, one frame is generally composed of 18 bytes (14-byte data and the like and 4-byte error correction code (ECC)). In the conventional example, 8 bits or 9 bits are defined as 1 byte. Data is transferred in byte units. The conventional configuration and operation of each circuit in the data format unit 11b will be described below.

(Residual byte creation circuit 1)
FIG. 55 is a diagram showing an example of a data block format recorded on a magnetic tape. The data block starts with an “IBG” frame and an “ALL1” frame, followed by a “SYNC” frame for synchronization, and a “PREFIX0” and “PREFIX1” frame indicating the start of the data area. A data group every 72 frames starting with a “SYNC” frame or a “RESYNC” frame is repeated.

  69 frames of data (DATA) are recorded in the first data group, and 71 frames of data (DATA) are recorded in the second and subsequent data groups. In the final data group, the remaining (n-1) frame data (DATA) is recorded. Thereafter, each frame of “RESID1,” “RESID2,” “COMP1,” “COMP2,” and “SYNC” is recorded, and finally, each frame of “SYNC” and “ALL1” is recorded.

  The same 9-bit special code (100010001) is recorded in both the “SYNC” frame and the “RESYNC” frame, and both frames are the same code. A synchronization signal or resynchronization signal is detected based on the “SYNC” frame or the “RESYNC” frame. The synchronization signal or resynchronization signal is a signal that informs the start of the data group and triggers skew correction in the deskew circuit 5.

  The block ID (BLOCK ID: BID) is composed of 4 bytes and is a serial number of the block. Since one frame has 14 bytes as a unit, depending on the number of bytes of custom data from the host 10, a byte (0 to 13 bytes) is required for configuring the 14 bytes. It is called a pad tool (PAD BYTE). One byte of the remaining byte count (RESIDUAL BYTE COUNT) indicates how many pad bytes are clogged with the lower 4 bits, and the upper 4 bits contain other information.

  Specifically, FIGS. 56 and 57 show data formats when the custom data from the host 10 is 12 bytes and when it is 7 bytes, respectively. In the case of 12 bytes shown in FIG. 56, the pad byte is 9 bytes, and 9 is entered in the remaining byte count. In the case of 7 bytes shown in FIG. 57, since there is no need for pad bytes, 0 is entered in the remaining byte count. As described above, a value of 0 to 13 enters the remaining byte count according to the length of the custom data.

  The configuration of the conventional example of the remaining byte creating circuit 1 is shown in FIG. The remaining byte creation circuit 1 includes an AND (logical product) circuit 13, a NOR circuit 14, and a MOD 14 counter 15. CK is a clock for operating the counter 15. -RSYNC is a RESYNC control signal generated every 72 frames, and the operation of the counter 15 stops when this signal is low. WRBK is a signal set from the register, and is set only when the write block is started. The SMDC indicates the end of the selection of the block ID at the time of creating the frame data. When this signal is low, it indicates that the block ID has ended and the operation of the counter 15 stops. CUSTBLK goes high when it is custom data or block ID. -CLR is a signal set from the register to clear the counter value, and is set at device initialization and during the "IBG" frame. -MOD1 to -MOD8 are signals representing the number of pad bytes, and the values represented by these signals are reflected in the lower 4 bits of one byte of the remaining byte count.

  One byte of the remaining byte count is realized by the mod 14 counter 15, and the output value of the counter 15 represents the number of pad bytes. The counter 15 counts up the number of custom data and block IDs, and stops its operation during the “RESYNC” frame and when the ECC is 4 bytes.

  The operation when the custom data is 8 bytes will be described. FIG. 59 shows a timing chart in that case, and FIG. 60 shows an output of the mod 14 counter 15.

  The counter 15 is initialized at the time of device initialization and during the “IBG” frame. The counter value at this time is “0000”. The firmware sets the WRBK signal from the register only at the start of the write block. The counter value at this time is “0010”. When it is time to process custom data, the CUSTBLK signal is set and the counter 15 starts counting. When the block ID ends, the SMDC signal is reset and the counting operation is stopped. The values of -MOD1 to -MOD8 ("1101" = 13), which are the inverted signals of the counter value ("0010") when the count operation is stopped, enter the lower 4 bits of the remaining byte count.

(Error correction coding circuit 3)
In the error correction method using the AXP code, one frame of data is written to 14 tracks out of 18 tracks, and the error correction code for the data of these 14 tracks is written to the remaining 4 tracks. . The error correction code is composed of a DRC (Diagonal Redundancy Check) character and a VRC (Vertical Redundancy Check) character. The total 18 tracks are divided into 9 tracks, odd tracks are set A and even tracks are set B.

  The DRC is recorded on the 0A track and the 0B track in the error correction code track. The 2 bytes of this DRC are calculated from other than VRC (15 bits) recorded in other tracks, and the m-th value is as follows.

A0 _m = (A1 _m-1 + A2 _m-2 + A3 _m-3 + ... + A7 _m-7 +
B7 _m-8 + B6 _m-9 + B5 _m-10 + ... + B0 _m-15 ) _MOD2
B0 _m = (B1 _m-1 + B2 _m-2 + B3 _m-3 + ... + B7 _m-7 +
A7 _m-8 + A6 _m-9 + A5 _m-10 + ... + A0 _m-15 ) _MOD2

  61 is a diagram for explaining the principle of a conventional DRC creation method, FIG. 62 is a chart showing the results of actual calculation of DRCA and DRCB of user data, and FIG. 63 is a diagram showing the configuration of a conventional DRC creation circuit. It is. The DRC creation circuit uses a circuit system consisting of one bit matrix array 81 that takes in data obliquely by adjusting the timing of the clock and three FF arrays 82 corresponding to each frame for set A and set B. The output from each circuit system is coupled by the multiplexer 84 together with VRCA and VRCB from the VRC creation circuit 83.

  Since DRC is a redundancy check in an oblique direction, the data is checked by adding redundant data in the oblique direction. At this time, since data is taken in diagonally, a DRC is created across three adjacent frames of data, and even parity is taken bit by bit for data in the diagonal direction excluding VRC. To create a DRC.

  VRC is recorded on 8A track and 8B track in the track for error correction code. Two bytes of VRC are calculated for each of set A (7-bit data + DRCA) and set B (7-bit data + DRCB), and the m-th value is as follows.

_{A8 m = (A0 m + A1} m + A2 m + ··· + A7 m) MOD2
However, A0 _m: DRCA
A1 _m , A2 _m ,. A7 _m: data _{B8 m = (B0 m + B1} m + B2 m + ··· + B7 m) MOD2
However, B0 _m: DRCB
B1 _m , B2 _m ,. B7 _m: data

  FIG. 64 is a diagram for explaining the principle of a conventional VRC creation method, FIG. 65 is a chart showing the results of actually calculating VRCA and VRCB of user data, and FIG. 66 is a diagram showing the configuration of a conventional VRC creation circuit. It is. The VRC creation circuit 85 is divided into a VRCA creation circuit 86 for VRCA creation and a VRCB creation circuit 87 for creation of VRCB, each having 8 toggle JK flip-flops.

  Since VRC is a vertical redundancy check, data is checked by adding redundant data in the vertical direction. At this time, since data is taken in in the vertical direction, the VRC is created within one frame. As a whole, it is composed of two creation circuits 86 and 87 (8 bits) for VRCA and VRCB. When one byte is input in set A, it is input to the circuit corresponding to each bit of VRCA, and one byte in set B When input, it is input to the circuit corresponding to each bit of VRCB. VRCA bit 1 is input with bit 1, byte 2, 1, 3, 4, 5, 6, 7 and bit 1 of DRCA. VRCA bit 2 is input with bit 2 of bytes 1, 2, 3, 4, 5, 6, 7 and DRCA. Others are the same.

  Since data is input byte by byte, only one bit is input to the 1-bit VRC creation circuit at one timing. Each bit of set A and set B is the same as having even parity for 7 bits of vertical data and 1 bit of DRC. That is, VRCA is the same as taking even parity of data bytes 1 to 7 and DRCA, and VRCB is the same as taking even parity of data bytes 8 to 14 and DRCB.

In the circuit configuration shown in FIG. 66, the data capture timing is controlled by CK and the timing signal. By inputting data to the JK flip-flop of toggle operation, even parity is taken. The data input sequence in one frame is as follows, and 18 timings are required to operate in one frame.
Data input order Timing (1) (2) (3) (4) (5) (6)
Byte 1 2 3 4 5 6
Timing (7) (8) (9) (10) (11) (12)
Byte 7 DRCA VRCA 8 9 10
Timing (13) (14) (15) (16) (17) (18)
Byte 11 12 13 14 DRCB VRCB

A Reed-Solomon code is used as an error correction code for a 36-track magnetic tape apparatus. When α is a primitive element on Galois field GF (q),
α ^h , α ^{h + 1} , α ^{h + 2} ,..., α ^{h + d-2} (0 ≦ h <q−1, 2 ≦ d ≦ q) In an apparatus for handling digital signals, the q-ary cyclic code is a Reed-Solomon code,
When q = 2 ^m and h = 0, which are important for practical use,
Code length n = 2 ^m −1
Number of information points k = 2 ^m -d
Number of inspection points n−k = d−1
Minimum distance d _min = d = n−k + 1
Becomes 2 ^m original code, generator polynomial G (x),
G (x) = (x−α ^d−2 ) (x−α ² ) (x−α) (x−1)
And α ^d-2 ,..., Α ² , α, 1 is a polynomial rooted. An arbitrary code polynomial C (x) of the Reed-Solomon code is rooted at α ^d-2 ,..., Α ² , α, 1.

In other words, the necessary condition for the polynomial C (x) on GF (2 ⁸ ) of n−1 order or less to be a sign polynomial is:
C (α ⁰ ) = 0
C (α ¹ ) = 0
・
・
・
C (α ^d-2 ) = 0
I _j (0 ≦ j ≦ k−1) is an element of GF (2 ⁸ ), and k information words i ₀ , i ₁ ,..., I _k− with k ≦ 2 ⁸ −d. _When encoding ₁ ,
I (x) = i _k-1 x ^k-1 +... + I ₂ x ² + i ₁ x + i ₀
The information polynomial I (x) is created.

Next, let D (x) be the remainder polynomial when I (x) is multiplied by ^xd-1 and divided by the generator polynomial G (x). If the quotient polynomial in this case is Q (x), the relationship between these polynomials is as follows.
I (x) × x ^d−1 = Q (x) × G (x) + D (x)
Here, since the remainder polynomial D (x) is a polynomial of x ^d−2 order or lower,
D (x) = d _d−2 × x ^d−2 +... + D ₂ × x ² + d ₁ × x + d ₀
And Since the polynomial corresponding to the code (code polynomial) needs to be divisible by G (x),
C (x) = Q (x) × G (x)
= I (x) × x ^d-1 + D (x) [subtraction and addition on GF are the same], and the n-dimensional vector on GF (2 ⁸ ) consisting of the coefficient of C (x) is
C = (c _n−1 ,..., C ₂ , c ₁ , c ₀ )
= (I _k−1 ,..., I ₂ , i ₁ , i ₀ , d _d−2 ,..., D ₁ , d ₀ ). This is the information word i _0, i _1, ···, is a code word of the Reed-Solomon code for i _k-1. Test word _{d d-2, ···, d} 1, d 0 is the information word i _0, i _1, · · ·, as described above from i _k-1, obtained by using the polynomial division. Also, check bytes d ₃ , d ₂ , d ₁ , and d ₀ can be derived using a check matrix.

If a polynomial of order n-1 or less on GF (2 ^m ) has α ^d-2 ,..., Α ² , α, 1 as roots, a check matrix H and a codeword C of the Reed-Solomon code are used. The product of this with the transpose matrix C ^t is a zero matrix.

  Here, this determinant can be rewritten as follows.

This equation is expressed as the following determinant. If d _d-2 ,..., D ₁ , d ₀ are solved using the Kramel formula, the powers of a _{0 to} a _d-2 and α are determined. A test word can be obtained by the multiplication processing and addition processing used.

  A circuit configuration for executing the encoding as described above will be described. FIG. 67 shows a circuit configuration in the case of dividing by a generator polynomial, which employs a feedback register called LFSR (linear feedback shift register), and is composed of an adder circuit 25, a register 26, and an α power multiplier circuit 27. Then, information words are sequentially input in units of 1 byte, that is, division is performed with the first input byte as the most significant byte to form an information polynomial, and a remainder at the time when the input of the least significant byte is completed is obtained.

The circuit in the case of encoding by the parity check matrix includes a circuit for calculating the sum of information words shown in FIGS. 68 and 69 and a ₀ , a ₁ ,..., A _d-2 , d ₀ , d ₁ ,. A circuit for performing multiplication and addition of α to obtain d _d−2 is required.

At this time, the circuit for calculating the sum needs to sequentially multiply each byte of the information word by the power of α, and usually multiplies α ⁰ , α ¹ , α ² ,..., Α ⁿ⁻¹ . Therefore, the summation is obtained by combining the multiplication circuit 27, the addition circuit 25, and the register 26, which have a simple configuration, and repeatedly calculating multiplication-addition-holding in units of one byte.

(Syndrome creation circuit 6)
Assume that the target code word is {D ₀ , D ₁ , D ₂ ,..., D _n−2 , D _n−1 }. This is first stored in memory. For example, when error correction processing is performed using a Reed-Solomon code, when the Hamming distance is D _min , the error correction capability is the maximum integer that does not exceed D _min / 2. Such an integer is (D _min −1), and the following syndrome calculation is performed when obtaining this integer.

When the polynomial representing the received word is R (x), the Reed-Solomon code is decoded from this R (x) to the syndrome Si = R (α ⁱ ) (i = 0, 1, 2, 3,... d-2)
Start with calculating. This is to perform constant multiplication on GF (2 ^m ) on the received word, that is, multiplication of α ⁱ .

As a method of calculating such a syndrome, a method of inputting _n data stored in a memory one by _one from D _n- 1 one by one to an α ⁱ multiplication circuit and obtaining the output as a result of the syndrome after all the data has been input. Has been done.

  According to the prior art, since data is read from the memory one by one (1 byte), there is a problem in that if a memory having a slow access is used, the processing time is greatly delayed.

(Deskew circuit 5)
70 is a diagram showing an example of a data block format recorded on an inclined track of the magnetic tape, and FIG. 71 is a partially enlarged view of FIG. 70 showing the data block format in bit units. 70 and 71, the same abbreviations as SYNC, RESYNC, etc. are attached to the same frames as in FIG. As shown in FIG. 70, it is the forward (FWD) direction (forward direction) that records or reproduces the frames in order from the beginning from the left to the right, and the opposite direction is the backward (BWD) direction (reverse). Direction).

  FIG. 72 is a block diagram showing an internal configuration of a conventional deskew circuit 5. As shown in FIG. The data (DATA) sent from the MTU 12 adopting the data block format shown in FIGS. 70 and 71 has irregularity between the tracks. These data are temporarily written in a memory called a deskewing buffer, and the data is skewed. After the correction, the data is read from the deskewing buffer and transmitted to the syndrome generation circuit 6 and the buffer memory 8 to perform error correction.

  As shown in FIG. 72, the deskewing buffer is composed of three deskewing buffers 42A, 42B, and 42C so as to reduce the memory capacity used therefor. Each deskewing buffer 42A, 42B, 42C is responsible for 6 tracks of 18 track data. The deskew control circuits 41A, 41B, and 41C and the multiplexers 43A, 43B, and 43C associated with the deskew buffers 42A, 42B, and 42C are also configured in three systems for every six tracks. Reference numeral 44 denotes a 9-8 conversion circuit that converts the 9-bit output of each of the multiplexers 43A, 43B, and 43C into 8 bits.

  Each deskewing buffer 42A, 42B, 42C divides its internal memory area into six parts (A, B, C, D, E, F) according to the address, and a synchronization signal (resynchronization signal) for one track is divided into each divided area. ) To 72 frames of data from the synchronization signal (resynchronization signal).

  73 to 76 are diagrams showing write / read control in the FWD direction in each of the deskew buffers 42A, 42B, and 42C, and FIGS. 77 to 80 are diagrams similarly showing write / read control in the BWD direction. .

  As an example, the operation of the deskew control circuit 41A and the deskewing buffer 42A in the FWD direction will be described. In each inclined track on the magnetic tape, a track having 1 byte data (9-bit data) is sequentially written into each divided memory area. First, the 1A-track data is written in the memory area (position A) assigned to the 1A-track of the deskewing buffer 42A. Similarly, 4A-track data is B position, 7A-track data is C position, 7B-track data is D position, 4B-track data is E position, and 1B-track data is 1B-track data. Write to the position F (see FIG. 73).

  Similarly, in the deskewing buffers 42B and 42C, the data of each track is written in the corresponding memory area assigned (see FIGS. 74 and 75). As described above, writing of data for 18 tracks is completed.

  When the data writing is completed, reading for each byte of data (1 byte data transfer) starts. In accordance with the reading order shown in FIGS. 73 to 75, the read data from the deskewing buffers 42A, 42B, and 42C are selected by the multiplexers 43A, 43B, and 43C in the order shown in FIG. 76 that matches the error correction method. It is output to the 9-8 conversion circuit 44. Since the data on the magnetic tape is 9-bit data, it is converted into 8-bit data by the 9-8 conversion circuit 44 and sent to the error correction processing system at the subsequent stage.

  In the BWD direction, the data write position of each track is different from that in the FWD direction, but the basic processing procedure is the same, and the description thereof is omitted.

  Data sent from the MTU 12 is temporarily written in the deskewing buffer, and then read out to perform skew correction and data transfer. At this time, since the conventional one-byte data transfer is required to read from the deskewing buffer 18 times to transfer one frame of data. Therefore, there is a problem that it is not suitable for high-speed processing. Also, depending on the FWD direction and BWD direction, the data sent from the MTU 12 has a difference in the bit definition, the track order in which 1-byte data (9-bit data) is aligned is different, and so on. It was necessary to transfer 1-byte data in the order appropriate for the error correction method. As described above, in the conventional example, the allocation of the memory areas divided into six in each deskewing buffer is different in the FWD direction and the BWD direction, and different write / read control is required in the FWD direction and the BWD direction. There is a problem.

(Data transfer control in the read format unit 11e)
Conventionally, when data is transferred, as a method for temporarily storing the data and switching the transfer timing, a method of controlling the transfer method using an element such as a multiplexer (selector) or a flip-flop is generally used. It has been broken. However, in order to perform error correction corresponding to high-density, high-speed data transfer, and to support data write / read operations in the FWD direction and BWD direction, simply add a memory element or handle each case with a selector. However, the method of performing the switching control has a problem that the circuit becomes complicated and the scale of the circuit is increased.

  As described above, in the control device of the conventional magnetic tape device, the processing is slow because the write format unit 11d and the read format unit 11e in the data format unit 11b perform processing in units of 1 byte. There is. In order to increase the processing speed, it is conceivable to increase the speed of data transfer by adding elements constituting each circuit in the data format unit 11b. In this case, however, the circuit scale is increased and complicated. There is a problem of inviting.

The data from the host device is compressed and output to the magnetic tape device, and the compressed data from the magnetic tape device is decompressed and output to the host device. The format of the input data is converted. Thus, a magnetic tape control device is known that outputs data to a magnetic tape device in parallel by 18 bits (see, for example, Patent Document 1). Also known is a magnetic tape control device that determines whether the number of bytes of data read from a connected magnetic tape is an even number or an odd number, and switches processing based on the determination result (for example, a patent) Reference 2).
JP-A-5-204552 JP 63-2111169 A

  The present invention has been made in view of such circumstances, and can perform processing in units of a plurality of bytes, and does not complicate the circuit and increases the data bus width to be processed without increasing the circuit scale. An object of the present invention is to provide a control device for a magnetic tape device that can increase the speed of data transfer.

  The control device of the magnetic tape device according to claim 1 converts the format by adding an error correction code to the data input from the host device, transfers the format-converted data to the magnetic tape unit, and reads from the magnetic tape unit In the control device of the magnetic tape device that performs error conversion on the received data and converts the format, and transfers the format-converted data to the host device, error correction coding processing in units of a plurality of bytes for the input data from the host device, And / or an error correction code configured to perform error correction processing in units of a plurality of bytes on the read data from the magnetic tape unit, and to create a Reed-Solomon error correction code for the data from the host device The error correction coding means includes a plurality of information words. Characterized by being configured to parallel process the sum calculation.

  In the present invention, the configuration of each circuit in the control device of the magnetic tape device is devised so that the data from the host device and the read data from the magnetic tape unit can be processed in units of a plurality of bytes. Compared to the conventional example in which processing is performed in units of bytes, the data processing speed is increased. When a Reed-Solomon error correction code is created, a plurality of summation calculations of information words are processed in parallel, so that the encoding processing time can be shortened and data input in units of multiple bytes can be handled.

  According to a second aspect of the present invention, when the control device of the magnetic tape device according to the first aspect configures the data from the host device in one frame of a predetermined number of bytes, the number of bytes in each frame becomes a predetermined number. Counting means for counting the remaining bytes as described above, and the counting means determines whether the number of bytes of data from the host device is an odd number or an even number, and according to the determination result, And a means for switching the counting method.

  The data input from the host device in units of 2 bytes by changing the counting method according to whether the counting means for counting the remaining bytes is an odd number or an even number of bytes from the host device It can correspond to.

  According to a third aspect of the present invention, there is provided a control device for a magnetic tape device according to the first aspect, further comprising syndrome generation means for generating a syndrome necessary for correcting an error in data read from the magnetic tape unit according to a Reed-Solomon method, The syndrome creation means is configured to have a plurality of circuits for multiplying a received word by a check matrix and to create a syndrome in parallel for a plurality of bytes of data.

  When creating the syndrome, the syndrome can be created in parallel for multiple bytes of data by operating multiple circuits that multiply the received words by the check matrix in parallel. It can handle read data in units of multiple bytes.

  According to the present invention, the function of each circuit in the data format section of the magnetic tape control device can be increased, the data bus can be expanded without complicating the circuit, and the data transfer speed can be increased. It is possible to improve the performance of the magnetic tape device.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.

  FIG. 2 is a configuration diagram of the tape subsystem, and FIG. 1 is a block diagram showing an internal configuration of the data format unit 11b of the MTC 11 shown in FIG. The tape subsystem includes a host 10 as a host device, an MTU 12 that records data, and an MTC 11 that is interposed between the host 10 and the MTU 12 and performs format conversion of data. At the time of data writing, data from the host 10 is input to the MTC 11, and after format conversion is performed here, the data is transferred to the MTU 12. When reading data, read data from the MTU 12 is transferred to the MTC 11, where error correction is performed and format conversion is performed, and then the data is sent to the host 10.

  The MTC 11 includes an interface unit 11a for transmitting / receiving data to / from the host 10, a data format unit 11b for performing processing such as format conversion and error correction, and a data conversion unit for D / A conversion / A / D conversion of data. 11c. The data format unit 11b includes a write format unit 11d that performs formatting for recording on the magnetic tape, and a read format unit 11e that corrects track deviation of data read from the magnetic tape and detects and corrects data errors. And divided.

  The write format unit 11 d includes a remaining byte creation circuit 1, multiplexers 2 and 4, and an error correction coding circuit 3. The remaining byte creating circuit 1 creates the remaining bytes necessary for matching the data from the host 10 with the tape format. The multiplexer 2 combines the custom data from the host 10, the remaining bytes from the remaining byte creation circuit 1, the block ID, the pad bytes that are redundant bytes, and the like. The error correction coding circuit 3 creates an error correction code that is a check character for error correction. As an error correction code, an AXP code or a Reed-Solomon code is often used. The multiplexer 4 combines the outputs of the multiplexer 2 and the error correction coding circuit 3.

  On the other hand, the read format unit 11 e includes a deskew circuit 5, a syndrome generation circuit 6, an error correction circuit 7, and a frame buffer 8. The deskew circuit 5 corrects a deviation between data read from the MTU 12. When the data recorded on the magnetic tape is read, the magnetic tape and the magnetic head are generally not perpendicular to each other, and a certain degree of error occurs, so that a deviation between the data occurs accordingly. The deskew circuit 5 corrects the deviation between the data. The syndrome creation circuit 6 creates information called a syndrome for determining whether there is an error in the read data. The error correction circuit 7 corrects an error in the read data. The frame buffer 8 rearranges data according to the data reading direction of the magnetic tape, and holds (delays) data while the error correction circuit 7 calculates the error coefficient.

  As described above, the basic configuration of the tape subsystem and the MTC 11 in the present invention is the same as the conventional example, but the internal configuration and processing operation of each circuit constituting the data format unit 11b in the MTC 11 are different. In other words, in the conventional example, processing is performed with a width of 1 byte. However, in the present invention, processing can be performed with a width of a plurality of bytes so as to speed up data processing. Therefore, in the present invention, the data bus in FIG. 1 is enlarged N (N is an integer of 2 or more) times as compared with the conventional example.

  Hereinafter, the configuration and operation of each circuit in the data format unit 11b according to the present invention will be described in detail. In the following embodiment, a case will be described in which processing can be performed with a width of 2 bytes in the write format unit 11d and processing can be performed with a width of 3 bytes in the read format unit 11d.

(Residual byte creation circuit 1)
In the present invention, the write format unit 11d performs processing by doubling the data width from the conventional 1-byte width to the 2-byte width, and can perform high-speed (twice conventional) data processing. Therefore, the remaining byte creating circuit 1 of the present invention can cope with the 2-byte processing from the conventional 1-byte processing. In the present invention, the operation of the mod 14 counter used in the conventional example is made to correspond to 2-byte processing.

  The configuration of the present invention of the remaining byte creating circuit 1 is shown in FIG. The remaining byte creation circuit 1 includes two AND circuits 13a and 13b, a NOR circuit 14, and a MOD 14 counter 15. CK is a clock for operating the counter 15. -RSYNC is a RESYNC control signal generated every 72 frames, and the operation of the counter 15 stops when this signal is low. WRBK is a signal set from the register, and is set only when the write block is started. The SMDC indicates the end of the selection of the block ID at the time of creating the frame data. When this signal is low, it indicates that the block ID has ended and the operation of the counter 15 stops. CUSTBLK goes high when it is custom data or block ID. -CLR is a signal set from the register to clear the counter value, and is set at device initialization and during the "IBG" frame. BID3 is a signal generated in the write format unit 11d and is set when the third byte of the block ID is processed. The ODD is a signal generated in the write format unit 11d. When custom data is transferred from the host 10, it is determined whether it is an odd byte or an even byte, and is set if it is an odd byte. -MOD1 to -MOD8 are signals representing the number of pad bytes, and the values represented by these signals are reflected in the lower 4 bits of one byte of the remaining byte count.

  4 and 5 are timing charts when the custom data is 8 bytes and 9 bytes, and FIG. 6 shows the output of the MOD 14 counter 15, respectively. The byte of the remaining byte count is realized by a mod 14 counter 15 corresponding to 2-byte processing, and the output value of the counter 15 represents the number of pad bytes. The counter 15 counts up the number of custom data and block IDs, and stops its operation in the “RESYNC” frame and when the error correction code (ECC) is 4 bytes. Also, depending on the number of bytes of custom data, there are cases of even bytes and odd bytes, and it is necessary to satisfy two types of operations, even and odd.

  Next, the operation when the custom data is 9 bytes will be described. The counter 15 is initialized at the time of device initialization and during the “IBG” frame. The counter value at this time is “0000”. The firmware sets the WRBK signal from the register only at the start of the write block. The counter value at this time is “0010”. When it is time to process custom data, the CUSTBLK signal is set and the counter 15 starts counting. The counter operation counts up by +2. When the BID3 signal is set and the ODD signal is set, the operation of the counter 15 transitions to the right table of FIG. When the block ID ends, the SMDC signal is reset and the counting operation is stopped. The values of -MOD1 to -MOD8 ("1100" = 12), which are inverted signals of the counter value ("0011") when the count operation is stopped, enter the lower 4 bits of the remaining byte count.

(Error correction coding circuit 3)
[AXP encoding method]
7 and 8 show the configuration of the DRC creation circuit of the present invention, and FIG. 9 shows the configuration of the VRC creation circuit of the present invention. This configuration example is an example when a plurality of bytes (2 bytes) are input. The DRC creation circuit is divided into two systems, one for set A (FIG. 7) and one for set B (FIG. 8). The DRC creation circuit for set A (for set B) is a data selection unit 21A (21B). And a data parity creation unit 22A (22B), a frame control unit 23A (23B), a data mask unit 24A (24B), and a timing control circuit (not shown).

  The DRC and VRC basically take parity between bits in the diagonal direction and the vertical direction, respectively. In the conventional DRC creation circuit and VRC creation circuit in which one byte is inputted, each bit takes parity in each circuit, but in the DRC creation circuit and VRC creation circuit of the present invention in which multiple bytes are inputted, each circuit In this case, it is sufficient to take a plurality of bits at the same time. This can be realized by selecting a plurality of bits necessary for creating the DRC and VRC, respectively, and obtaining the parity with the selected plurality of bits.

  Next, the operation will be described. The formula for calculating DRC and VRC of the AXP code is the same when inputting one byte at a time and when inputting multiple bytes, so the mth value calculated for each of the set A and set B of DRC and VRC. Is as follows.

DRC
A0 _m = (A1 _m-1 + A2 _m-2 + A3 _m-3 + ... + A7 _m-7 +
B7 _m-8 + B6 _m-9 + B5 _m-10 + ... + B0 _m-15 ) _MOD2
B0 _m = (B1 _m-1 + B2 _m-2 + B3 _m-3 + ... + B7 _m-7 +
A7 _m-8 + A6 _m-9 + A5 _m-10 + ... + A0 _m-15 ) _MOD2

VRC
_{A8 m = (A0 m + A1} m + A2 m + ··· + A7 m) MOD2
However, A0 _m: DRCA
A1 _m , A2 _m ,. A7 _m: data _{B8 m = (B0 m + B1} m + B2 m + ··· + B7 m) MOD2
However, B0 _m: DRCB
B1 _m , B2 _m ,. B7 _m: data

  Since the input data is 2 bytes each, the timing of one frame is 9 timings. FIG. 10 is a chart showing the relationship between the input data and timing, and FIG. 11 is a diagram for explaining the principle of the DRC creation method of the present invention. When creating the DRC, if data is input as shown in FIG. 10, the input data is 2 bytes (in the case of BS1, 2, 3, 4, 6, 7, ECC1) or 1 byte (in the case of BS5, ECC2). However, 1 bit of DRC is created by selecting data for 1 bit of the input even number (EVEN) byte and 1 bit of the odd number (ODD) byte. Since the data frame 3 -DRCA bit 7 is created for the data bits c1 to cF, the other data bits are not related to any value. The same applies to the data frame 4-DRCA bit 7 and the data frame 5-DRCA bit 7.

  For example, the data to be processed when creating the DRCA-bit 7 of the data frame 3 is data frame 2 -byte 8 -bit 7 (c8), byte 9 -bit 6 (c9), byte 10 -bit 5 ( cA), byte 11-bit 4 (cB), byte 12-bit 3 (cC), byte 13-bit 2 (cD), byte 14-bit 1 (cE), DRCB-bit 0 (cF), data frame 3 -Byte 1-bit 6 (c1), byte 2-bit 5 (c2), byte 3-bit 4 (c3), byte 4-bit 3 (c4), byte 5-bit 2 (c5), byte 6-bit 1 (c6), byte 7-bit 0 (c7). Similarly, the data targeted when creating the DRCA-bit 7 of the data frame 4 is data frame 3 -byte 8 -bit 7 (a8), byte 9 -bit 6 (a9), byte 10 -bit 5 (AA), byte 11-bit 4 (aB), byte 12-bit 3 (aC), byte 13-bit 2 (aD), byte 14-bit 1 (aE), DRCB-bit 0 (aF), data frame 4-byte 1-bit 6 (a1), byte 2-bit 5 (a2), byte 3-bit 4 (a3), byte 4-bit 3 (a4), byte 5-bit 2 (a5), byte 6- Bit 1 (a6), byte 7 to bit 0 (a7). Further, the data to be processed when creating the DRCA-bit 7 of the data frame 5 is data frame 4-byte 8-bit 7 (b8), byte 9-bit 6 (b9), byte 10-bit 5 ( bA), byte 11-bit 4 (bB), byte 12-bit 3 (bC), byte 13-bit 2 (bD), byte 14-bit 1 (bE), DRCB-bit 0 (bF), data frame 5 -Byte 1-bit 6 (b1), byte 2-bit 5 (b2), byte 3-bit 4 (b3), byte 4-bit 3 (b4), byte 5-bit 2 (b5), byte 6-bit 1 (b6), byte 7-bit 0 (b7).

  If even parity is taken for the data in the diagonal direction as described above, 1 bit of DRCA is created. A DRC can be created by sequentially performing the same processing for each bit.

  Considering the DRCA bit unit, as can be seen from FIG. 11, the DRC is generated for the data in the oblique direction, and therefore, it spans a plurality of frames (2 to 3 frames). Therefore, it is determined which data to select by dividing into three control frames. For example, when considering data frame 3, the data in one frame is divided into three as data for creating DRCA of control frames 0, 1, and 2, and the selected data does not overlap.

  Comparing the data frames 3, 4, and 5, it can be seen that what number of bytes and what number of bits are always selected depending on how the data is selected. Although the control frame to be selected is different, it can be seen which bit of the DRC is selected. For example, bit 6 of byte 1 is selected as DRCA bit 7 in data frame 3 (c1), DRCA bit 7 in data frame 4 (a1), and DRCA bit 7 in data frame 5 (b1). Bit 0 of byte 1 is selected as DRCA bit 1 in data frame 3, DRCA bit 1 in data frame 4, and DRCA bit 1 in data frame 5.

  Therefore, bit 1 of byte 1 is always selected as bit 2 of DRCA, and bit 2 of byte 2 is selected as bit 2 of DRCA. Therefore, it is only necessary to control whether or not the data is taken in by the DRC creation circuits of the control frames 0, 1, and 2. One more point to consider is that DRC creation is performed over 3 frames. For example, in the case of data frame 3 that is actually handled, DRC output at the time of data frames 3, 4 and 5 is created at the same time. It is a point that must be done. Therefore, it is understood that it is necessary to have a DRC creation circuit for at least 3 frames.

  Explain in more detail how to select data. When data of data frame 3 (control frame 2) is input, it will be described which bit should be selected as a DRCA and a bit generation circuit.

  Bit 0 of byte 1 is DRCA-bit 1 of control frame 2, bit 1 is DRCA-bit 2, bit 2 is DRCA-bit 3, bit 3 is DRCA-bit 4, bit 4 is DRCA-bit 5, bit 5 is DRCA-bit 6, bit 6 (c1) is DRCA-bit 7, bit 7 is DRCA-bit 0 of control frame 0, bit 0 of byte 2 is DRCA-bit 2 of control frame 2, bit 1 is DRCA-bit 3 , Bit 2 is DRCA-bit 4, bit 3 is DRCA-bit 5, bit 4 is DRCA-bit 6, bit 5 (c2) is DRCA-bit 7, bit 6 is DRCA-bit 0 of control frame 0, bit 7 Is DRCA-bit 1, bit 0 of byte 3 is DRCA-bit 3 of control frame 2, bit 1 is DRCA-bit 4, Bit 2 is DRCA-bit 5, bit 3 is DRCA-bit 6, bit 4 (c3) is DRCA-bit 7, bit 5 is DRCA-bit 0 of control frame 0, bit 6 is DRCA-bit 1, bit 7 Is DRCA-bit 2, bit 0 of byte 4 is DRCA-bit 4 of control frame 2, bit 1 is DRCA-bit 3, bit 2 is DRCA-bit 2, bit 3 (c4) is DRCA-bit 1, bit 4 Is DRCA-bit 0 of control frame 0, bit 5 is DRCA-bit 1, bit 6 is DRCA-bit 2, bit 7 is DRCA-bit 3, bit 0 of byte 5 is DRCA-bit 5, bit of control frame 2 1 is DRCA-bit 6, bit 2 is DRCA-bit 7, bit 3 is DRCA-bit 0 of control frame 0, bit 4 is RCA-bit 1, bit 5 is DRCA-bit 2, bit 6 is DRCA-bit 3, bit 7 is DRCA-bit 4, bit 0 of byte 6 is DRCA-bit 6 of control frame 2, bit 1 (c6) is DRCA-bit 7, bit 2 is DRCA-bit 0 of control frame 0, bit 3 is DRCA-bit 1, bit 4 is DRCA-bit 2, bit 5 is DRCA-bit 3, bit 6 is DRCA-bit 4, bit 7 is DRCA-bit 5, bit 0 of byte 7 is DRCA-bit 7 of control frame 2, bit 1 is DRCA-bit 0 of control frame 0, bit 2 is DRCA-bit 1, bit 3 is DRCA-bit 2, Bit 4 is DRCA-bit 3, bit 5 is DRCA-bit 4, bit 6 is DRCA-bit 5, bit 7 is DRC A-bit 6, bit 0 of byte 8 is DRCA-bit 0 of control frame 0, bit 1 is DRCA-bit 1, bit 2 is DRCA-bit 2, bit 3 is DRCA-bit 3, bit 4 is DRCA-bit 4, bit 5 is DRCA-bit 5, bit 6 is DRCA-bit 6, bit 7 (a8) is DRCA-bit 7, bit 0 of byte 9 is DRCA-bit 1 of control frame 0, bit 1 is DRCA-bit 2, bit 2 is DRCA-bit 3, bit 3 is DRCA-bit 4, bit 4 is DRCA-bit 5, bit 5 is DRCA-bit 6, bit 6 (a9) is DRCA-bit 7, bit 7 is a control frame 1 DRCA-bit 0, byte 10 bit 0 is control frame 0 DRCA-bit 2, bit 1 is DRCA-bit 3, Bit 2 is DRCA-bit 4, bit 3 is DRCA-bit 5, bit 4 is DRCA-bit 6, bit 5 (aA) is DRCA-bit 7, bit 6 is DRCA-bit 0 of control frame 1, bit 7 Is DRCA-bit 1, bit 0 of byte 11 is DRCA-bit 3 of control frame 0, bit 1 is DRCA-bit 4, bit 2 is DRCA-bit 5, bit 3 is DRCA-bit 6, bit 4 (aB) Is DRCA-bit 7, bit 5 is DRCA-bit 0 of control frame 1, bit 6 is DRCA-bit 1, bit 7 is DRCA-bit 2, bit 12 of byte 12 is DRCA-bit 4, bit of control frame 0 1 is DRCA-bit 5, bit 2 is DRCA-bit 6, bit 3 (aC) is DRCA-bit 7, bit 4 is control DRCA-bit 0 of bit 1, bit 5 is DRCA-bit 1, bit 6 is DRCA-bit 2, bit 7 is DRCA-bit 3, bit 0 of byte 13 is DRCA-bit 5 of control frame 0, bit 1 is DRCA-bit 6, bit 2 (aD) is DRCA-bit 7, bit 3 is DRCA-bit 0 of control frame 1, bit 4 is DRCA-bit 1, bit 5 is DRCA-bit 2, bit 6 is DRCA-bit 3, bit 7 is DRCA-bit 4, bit 14 of bit 14 is DRCA-bit 6 of control frame 0, bit 1 (cE) is DRCA-bit 7, bit 2 is DRCA-bit 0 of control frame 1, bit 3 Is DRCA-bit 1, bit 4 is DRCA-bit 2, bit 5 is DRCA-bit 3, and bit 6 is DRCA-bit. Bit 4, bit 7 is DRCA-bit 5, bit 0 (aF) of DRCB is DRCA-bit 7 of control frame 0, bit 1 is DRCA-bit 0 of control frame 1, bit 2 is DRCA-bit 1, bit 3 is DRCA-bit 2, bit 4 is DRCA-bit 3, bit 5 is DRCA-bit 4, bit 6 is DRCA-bit 5, bit 7 is DRCA-bit 6.

  The selection relationships as described above are summarized in tables as shown in FIGS. If this is tabulated at the timing of FIG. 10 with 2-byte input, it will be as shown in FIGS. Examples of circuit configurations for realizing such table relationships are shown in FIGS.

  Since data is input by 2 bytes at a time, it is necessary not to input data unnecessary for data creation when creating DRC. Since the DRC is created in units of bits, when only one bit is required for one bit of the first byte and one bit of the second byte, the data that is not captured becomes unnecessary data.

  With reference to the DRC creation format of FIG. 11, unnecessary data is illustrated. Consider a case in which DRCA bit 1 of control frame 0 is obtained. When byte 1 and byte 2 of control frame 0 are input, only bit 0 of byte 1 is used for DRCA creation, and byte 2 is not used. When creating DRCA bit 1, bit 0 of byte 1 and bit 2 of byte 2 are selected, but only the data to be used (bit 0 of byte 1) may be selected. In order to make this selection, the input unnecessary data (bit 2 of byte 2) is masked. As another example, when the DRCA bit 3 of the control frame 0 is obtained, the timing BS2, the bit 0 of the byte 3, and the bit 7 of the byte 4 are input, but the unnecessary bit 7 of the byte 4 is masked. To do.

  Thus, when the data input is 1 bit, the data masking sections 24A and 24B in FIGS. 7 and 8 perform data masking. Details of the data mask are shown in FIGS. The signals input to the data mask units 24A and 24B in FIGS. 7 and 8 are MAO-0? , MAE-0? , MAO-1? , MAE-1? , MAO-2? , MAE-2? And MBO-0? , MBE-0? , MBO-1? , MBE-1? , MBO-2? , MBE-2? It is. This signal is generated by the control frame and timing signal used when generating the DRC. Details of the internal circuits of the data mask sections 24A and 24B are shown in FIG. 22, FIG. 23, FIG. 24 and FIG.

  Since the data to be input is determined by the data selection units 21A and 21B and the data mask units 24A and 24B, the timing for capturing the data will be described. Each of the DRCA creation circuit and the DRCB creation circuit has a circuit for three frames, but the timing for fetching each data is different, so timing control is necessary. The timing table for taking in data is shown in FIGS. This indicates which data is captured for each of output frames 0, 1, and 2 when creating a DRC.

  The control frames 0, 1, and 2 indicating which frame is currently processed and the output frame that outputs DRC at three frame timings indicate which data bits are captured. ○ indicates that the bit at the place with the mark is taken in. X indicates that a DRC has been created. If a table is made as the timing of taking in the circles, it will be as shown in FIGS. Based on this table, the signal CE0FA for controlling the flip-flop set conditions of the data parity creation units 22A and 22B in FIGS. , CE1FA? , CE2FA? , CE0FB? , CE1FB? , CE2FB? Create

  As described above, the data selection units 21A and 21B select data, the data mask units 24A and 24B mask unnecessary data, and the data parity creation units 22A and 22B set the parity in the diagonal direction of the data. By taking this, a DRC is created.

  Next, VRC will be described. The theory of creating VRC is the same when inputting 1 byte at a time and when inputting 2 bytes at a time. That is, even parity for each bit of set A and set B may be taken. If a circuit configuration as shown in FIG. 9 is used, creation of VRC can be realized.

  First, the JK flip-flop is cleared before data is input. In the set A, each bit of the first byte and the second byte is EORed (exclusive OR) and input to the JK flip-flop of the toggle circuit. If the 3rd, 4th, 5th, 6th and 7th bytes + DRCA are input in the same way, a VRCA is created on the flip-flop. In Set B, the 8th byte is input and input to the JK flip-flop of the toggle circuit. Each bit of the ninth and tenth bytes is EORed and input to the JK flip-flop of the toggle circuit. Similarly, the 11th, 12th and 13th and 14th bytes are input. Then, when the DRCB and the output of the JK flip-flop are EORed, a VRCB is created.

  In the configuration of the above-described DRC creation circuit, the data selection unit of 3 frames is common as shown in FIGS. 7 and 8, and data is selected by the set control of the data mask unit and the flip-flop. However, there is another method for performing data selection. There are three types of data selection as shown by the shaded area in FIG. Data can be selected by selecting these three types in order. The circuit configuration in such an example is as shown in FIG.

  In the above example, the AXP correction code is created by inputting 2 bytes at a time. However, by inputting multiple bytes other than 2 bytes, the diagonal parity of DRC and the vertical parity of VRC are set. It is also possible to take.

[Reed-Solomon code]
Next, speeding up of the Reed-Solomon code of the present invention will be described. An encoding calculation using a parity check matrix is specifically shown using the following codes.
Code length n = 18
Information score k = 14
Number of inspection points n−k = 4
Minimum distance d _min = 5
Primitive polynomial g (x) = x ⁸ + x ⁴ + x ³ + x ² +1
Generator polynomial G (x) = (x−α ³ ) (x−α ² ) (x−α) (x−1)
= X ⁴ + α ⁷⁵ x ³ + α ²⁴⁹ x ² + α ⁷⁸ x + α ⁶
And can be expanded.
d _{0 to} d ₃ are represented by the following matrix.

  Where the sum shown below,

That is, if a _{0 to} a ₃ are expanded,
a ₀ = i ₁₃ + i ₁₂ + i ₁₁ + i ₁₀ + i ₉ + i ₈ + i ₇ + i ₆ + i ₅ + i ₄ + i ₃ + i ₂ + i ₁ + i ₀
a ₁ = i ₁₃ × α ¹⁷ + i ₁₂ × α ¹⁶ + i ₁₁ × α ¹⁵ + i ₁₀ × α ¹⁴ + i ₉ × α ¹³
+ I ₈ × α ¹² + i ₇ × α ¹¹ + i ₆ × α ¹⁰ + i ₅ × α ⁹ + i ₄ × α ⁸
+ I ₃ × α ⁷ + i ₂ × α ⁶ + i ₁ × α ⁵ + i ₀ × α ⁴
a ₂ = i ₁₃ × α ³⁴ + i ₁₂ × α ³² + i ₁₁ × α ³⁰ + i ₁₀ × α ²⁸ + i ₉ × α ²⁶
+ I ₈ × α ²⁴ + i ₇ × α ²² + i ₆ × α ²⁰ + i ₅ × α ¹⁸ + i ₄ × α ¹⁶
+ I ₃ × α ¹⁴ + i ₂ × α ¹² + i ₁ × α ¹⁰ + i ₀ × α ⁸
a ₃ = i ₁₃ × α ⁵¹ + i ₁₂ × α ⁴⁸ + i ₁₁ × α ⁴⁵ + i ₁₀ × α ⁴² + i ₉ × α ³⁹
+ I ₈ × α ³⁶ + i ₇ × α ³³ + i ₆ × α ³⁰ + i ₅ × α ²⁷ + i ₄ × α ²⁴
+ I ₃ × α ²¹ + i ₂ × α ¹⁸ + i ₁ × α ¹⁵ + i ₀ × α ¹²
It becomes.

Here, the information words i _{13 to} i ₀ are expressed in 2-byte units (i ₁₃ and i ₁₂ , i ₁₁ and i ₁₀ , i ₉ and i ₈ , i ₇ and i ₆ , i ₅ and i ₄ , i ₃ and i ₂ , i ₁ and i ₀ ), considering that they are input to the circuit for obtaining the sum, a _{1 to} a ₃ are changed to the formulas summarized in the following common terms.
a ₁ = α ⁵ (i ₁₃ × α ¹² ++ i ₁₁ × α ¹⁰ + i ₉ × α ⁸ + i ₇ × α ⁶
+ I ₅ × α ⁴ + i ₃ × α ² + i ₁ × α ⁰ ) +
α ⁴ (i ₁₂ × α ¹² ++ i ₁₀ × α ¹⁰ + i ₈ × α ⁸ + i ₆ × α ⁶
+ I ₄ × α ⁴ + i ₂ × α ² + i ₀ × α ⁰ )
a ₂ = α ¹⁰ (i ₁₃ × α ²⁴ ++ i ₁₁ × α ²⁰ + i ₉ × α ¹⁶ + i ₇ × α ¹²
+ I ₅ × α ⁸ + i ₃ × α ⁴ + i ₁ × α ⁰ ) +
α ⁸ (i ₁₂ × α ²⁴ ++ i ₁₀ × α ²⁰ + i ₈ × α ¹⁶ + i ₆ × α ¹²
+ I ₄ × α ⁸ + i ₂ × α ⁴ + i ₀ × α ⁰ )
a ₃ = α ¹⁵ (i ₁₃ × α ³⁶ ++ i ₁₁ × α ³⁰ + i ₉ × α ²⁴ + i ₇ × α ¹⁸
+ I ₅ × α ¹² + i ₃ × α ⁶ + i ₁ × α ⁰ ) +
α ¹² (i ₁₂ × α ³⁶ ++ i ₁₀ × α ³⁰ + i ₈ × α ²⁴ + i ₆ × α ¹⁸
+ I ₄ × α ¹² + i ₂ × α ⁶ + i ₀ × α ⁰ )

This equation indicates that when the input is performed in units of 2 bytes, the circuit for obtaining the sum can be simplified by multiplying each of the even and odd bytes by a constant. The multiplication constant in the multiplication circuit for obtaining a ₁ from this equation is α ² for both even and odd bytes, and the multiplication constant for a ₂ is α ⁴ and the multiplication constant for a ₃ is α ⁶ is the same value common to even and odd bytes. Therefore, the values in parentheses of each expression can be obtained by sequentially repeating multiplication-addition-holding. That is, it is possible to obtain the sum of information words at a speed twice that of the conventional circuit.

Then, a ₀ to obtain the test word d ₀ to d ₃ from ~a ₃ may be a circuit to solve the above matrix equation, conventional and multiplication circuit that sets a predetermined multiplicative constant similarly adder circuit And can be realized in accordance with an arithmetic expression as shown below.
d ₀ = α ²¹⁸ × a ₀ + α ¹⁵⁸ × a ₁ + α ¹⁵⁶ × a ₂ + α ²¹² × a ₃
d ₁ = α ¹⁵⁸ × a ₀ + α ¹³⁸ × a ₁ + α ² × a ₂ + α ¹⁵³ × a ₃
d ₂ = α ¹⁵⁶ × a ₀ + α ² × a ₁ + α ¹³⁵ × a ₂ + α ¹⁵² × a ₃
d ₃ = α ²¹² × a ₀ + α ¹⁵³ × a ₁ + α ¹⁵² × a ₂ + α ²⁰⁹ × a ₃

FIG. 40 and FIG. 41 are circuit configuration diagrams for obtaining a _{0 to} a ₃ and d _{0 to} d ₃ as described above. An adder circuit 25 on the Galois field composed of EOR, a multiplier circuit 27 of a constant term on the Galois field composed of EOR and AND, and a register 26 for holding data (information word) multiplied and added And have. When performing encoding, enter the information word two bytes, it is a ₀ ~a ₃ when all the data has been entered is calculated in the circuit of Figure 40, is calculated a ₀ ~a ₃ There is obtained test word d ₀ to d ₃ at the same time is input to the circuit of Figure 41. That is, the time required for encoding is information word length / 2, and the error correction encoding processing time is reduced by half compared to the conventional example.

  In the above description, in order to simplify the description, the input data is in units of 2 bytes. For example, if the input data is 4 bytes, 6 bytes,. A circuit can be constructed.

(Syndrome creation circuit 6 for Reed-Solomon code)
FIG. 42 is a block diagram showing the configuration of the syndrome generation circuit 6 of the present invention. The syndrome generation circuit 6 includes a memory 31, a bit weight conversion unit 32, a parallel syndrome calculation unit 33, a syndrome result storage unit 34, And a controller unit 35.

  Before the syndrome calculation, the data read from the memory 31 may have different Galois fields GF depending on the traveling direction, and bit weights may need to be replaced. In this case, the bit weight conversion unit 32 replaces the bit weights of the data and outputs the data to the parallel syndrome calculation unit 33. The parallel syndrome calculation unit 33 obtains a syndrome of data after bit weight conversion. The syndrome result storage unit 34 stores the calculation result of the syndrome. The controller unit 35 controls arithmetic processing in the parallel syndrome arithmetic unit 33.

  FIG. 43 shows the internal configuration of the parallel syndrome calculation unit 33 and the controller unit 35 of FIG. The parallel syndrome calculation unit 33 includes an EOR unit 36, a multiplier 37, an multiplexer 38, and a register 39, and the controller unit 35 includes a byte switch 35a and a pulse generator 35b.

An operation according to the following conditions will be described.
Field in which code exists: GF (2) The total number of elements is 256 Primitive polynomials constituting field: g (x) = x ⁸ + x ⁴ + x ³ + x ² +1
RS code generator polynomial: G (x) = x ⁴ + α ⁷⁵ x ³ + α ²⁴⁹ x ² + α ⁷⁸ x
+ Α ⁶
= (X + α ⁰ ) (x + α ¹ ) (x + α ² ) (x + α ³ )
Code length n = 18 bytes Number of information points k = 14 bytes Number of inspection points m = 4 bytes Minimum distance d _min = 5
Correction capability Up to 2 error corrections or 4 error detections

  First, the 18-byte codeword stored in the memory 31 is collected every 3 bytes, and the 3-byte data is simultaneously taken into the bit weight converter 32. The Galois field differs depending on the traveling direction, and the bit weight needs to be replaced. Replace bit weight with. The data after the bit weight conversion is input to the parallel syndrome calculation unit 33 to calculate the syndrome. The syndrome is obtained by multiplying each EOR result by the power table of the multiplier 37. The multiplexer 38 is necessary for switching the number of bytes at the time of data transfer, and the number of bytes is switched by information from the outside by a byte switch 35 a for syndrome calculation of the controller unit 35. The register 39 is necessary for temporarily storing the computed syndrome result and outputting it accurately. After the 18-byte data is input, the calculated syndrome result is stored in the syndrome result storage unit 34 in accordance with the timing pulse generated from the pulse generator 35b after the 18-byte data is input.

  As described above, since the processing is performed in units of 3 bytes, the syndrome calculation can be performed at high speed.

(Deskew circuit 5)
In the present invention, the process of transferring three bytes of data at a time by reading three deskewing buffers simultaneously is performed six times, thereby increasing the transfer rate of one frame of data to three times that of the conventional example. In addition, by changing the allocation of each track in the deskewing buffer and changing the control method, data transfer can be performed by the same control method in the FWD direction and the BWD direction.

  FIG. 44 is a block diagram showing the internal configuration of the deskew circuit 5 of the present invention. Three systems comprising a deskew control circuit 41A (41B, 41C), a deskewing buffer 42A (42B, 42C), a multiplexer 43A (43B, 43C), and a 9-8 conversion circuit 44A (44B, 44C) A circuit is provided so that 3 bytes of data can be transferred at a time.

  45 to 48 are diagrams showing data write / read control in each of the deskewing buffers 42A, 42B, and 42C. In the present invention, unlike the conventional example, the writing / reading control is common in the FWD direction and the BWD direction.

  As an example, the control operation of the deskew control circuit 41A and the deskewing buffer 42A will be described. In each inclined track on the magnetic tape, a track having 1 byte data (9-bit data) is sequentially written into each divided memory area. First, the 1A-track data is written in the memory area (position A) assigned to the 1A-track of the deskewing buffer 42A. Similarly, 4A-track data is B position, 7A-track data is C position, 5B-track data is D position, 2B-track data is E position, and 0A-track data is 0A-track data. Write to position F (see FIG. 45).

  Similarly, in the deskewing buffers 42B and 42C, the data of each track is written in the corresponding memory area assigned (see FIGS. 46 and 47). As described above, writing of data for 18 tracks is completed.

  When the data writing is completed, transfer of 3-byte data is started. The data of the block (position A) in the reading order No. 1 of each of the deskewing buffers 42A, 42B, and 42C shown in FIGS. 45 to 47 is simultaneously read to realize 3-byte transfer at one timing. The read 3-byte data is transferred to 9-8 conversion circuits 44A, 44B, 44C independent of the three systems, and converted into 8-bit data. Next, the data of one frame for 18 tracks is read at a total of six times, such as the block with the second reading order (position B) of each deskewing buffer 42A, 42B, 42C and then the third reading order. Transmit (see FIG. 48).

  By the method as described above, it is possible to transfer data at one frame at a triple speed as compared with the conventional example, and the processing speed can be improved. Further, it is possible to perform the deskew process using the same control method regardless of the FWD direction and the BWD direction.

(Data transfer control in the read format unit 11e)
When error correction processing is performed on data transferred with a 3-byte width, which is three times that of the prior art, until the data is transferred to the next-stage circuit (host 10), a means for temporarily storing the data is required. . In order to minimize the use of elements such as memories, flip-flops, and selectors as storage means, and to cope with read operations in the FWD direction and BWD direction, it is necessary to devise a memory address control method. .

  When data read from a medium such as a magnetic tape is stored in a memory, an address counter is controlled by a counter control circuit that controls a memory address to be stored. The output value of the counter is input to an address line of the memory, and address control is performed so that data is stored in a predetermined area of the memory. In the counter control circuit, the address order can be switched according to the magnetic tape reading direction (FWD direction or BWD direction). When performing error correction processing, the input data order is opposite in the BWD direction and the FWD direction, but it is necessary to provide separate error correction circuits in the BWD direction and the FWD direction by switching the address order in the counter control circuit. There is no.

  FIG. 49 is a block diagram showing the configuration of the data transfer control system of the present invention. The data transfer control system shown in FIG. 49 switches the order of transfer data in the SRAM 51 having a memory area for storing data, the address load value setting circuit 52 for setting a specific address value, and the FWD direction and the BWD direction, respectively. FWD / BWD switching circuit 53 for controlling, address counter circuit 54 for controlling each address of writing and reading, medium 55 such as a magnetic tape, error correction processing circuit 56 for performing error correction, FWD direction and BWD direction A traveling direction determination circuit 57 for determining, and a BWD byte data conversion circuit 58 that rearranges the data order of 3 bytes in the same address in the BWD direction. The address counter circuit 54 includes a write counter 54a and a read counter 54b.

  FIG. 50 is a diagram showing a memory map in the SRAM 51, and shows a memory storage area for each group. In FIG. 50, (1), (2), and 3) are group numbers of data in frame units, and 00, 05, 06, 0B, 0C, 11, and 12 are initial addresses indicating areas for storing data of each group. Value (load value).

  FIG. 51 is a diagram showing a format of one frame of data transferred from the medium 55 in units of 3 bytes. FIG. 51A is a read in the FWD direction, and FIG. 51B is a BWD direction. The data format at the time of reading is shown respectively. FIG. 52 is a timing chart for writing and reading data in units of frames, FIG. 53 is a detailed timing chart for writing and reading at a certain frame data during FWD, and FIG. 54 is a timing at a BWD for certain frame data. It is a detailed timing chart of writing and reading.

  When the data read in the FWD direction from the medium 55 is sent in parallel in the format (3 byte width: 1A, 2A, 3A) as shown in FIG. 51A, the address load value setting circuit 52 For each set group of frames (18 bytes from 1A to 8B), 3 bytes of data are stored in the storage address (load value) determined in the SRAM 51. In this case, 00 is first loaded, and 3 bytes of 1A, 2A, and 3A are stored at address 00.

  Thereafter, the address is incremented by the address counter circuit 54, and data is stored in units of 3 bytes each according to the incremented address. When data is stored at the address incremented to 05, storage of one frame of data, that is, group (1) is completed. Similarly, the data storage processing is performed for each group, such that the group (2) has addresses 06 to 0B and the group (3) has 0C to 11.

  Next, a description will be given of reading out the same address stored (written) in the SRAM 51 for each group. At this time, as shown in FIG. 52, a delay of 2 frames occurs at the timing of writing and reading. This is because it takes one frame to complete the writing of frame data (18 bytes) and one frame to perform error correction processing for the written data. The reason why the group is divided into three when data is stored and the start address and end address of each group are set as load values is to cope with the difference between the two frames.

  Since two frames are delayed in reading the same address written in the SRAM 1, as shown in FIG. 52, when writing the group (3), reading the group (1) and writing the group (1) Controls the address counters 54a and 54b for writing and reading so that the group (2) is read and the group (3) is read when the group (2) is written. FIG. 53 shows the detailed timing of this address counter control. In FIG. 53, 0 is written when 0C is written, and 0C is read when 08 is written.

  In the above example, the writing in the FWD direction is described. However, in the case of writing in the BWD direction, the read data read from the medium 55 is converted in the order of the data in the FWD direction at the previous stage for the convenience of error correction processing. In order to output to the next stage, it must be converted back to the BWD direction. The traveling direction is determined by a traveling direction determination circuit 57 that determines the traveling direction of each FWD / BWD, and is switched by an FWD / BWD switching circuit 53 that controls the reading / writing order. That is, in the FWD direction, the group start address is loaded and the counter value is increased, but in the BWD direction, the last address of the group is set as the load value and the counter value is decreased.

  For example, in FIG. 54, when reading the group (1) in the BWD direction, the read address counter is configured to count down using the final address of the group (1) as the load value, such as reading 05 when 0C is written. To control. In BWD, as shown in FIG. 51B, in addition to the output data order, the arrangement of 3 bytes in the same address also changes. Therefore, in BWD, byte conversion control is performed by the BWD byte data conversion circuit 58.

  According to the above method, when data transfer speed is increased (3-byte transfer), the reading order of data from the tape medium is changed in the FWD direction or the BWD direction, or when high-performance error correction processing is performed. Even when a data shift occurs as a frame unit, the above-described factors can be comprehensively addressed in the data transfer control method that is becoming more sophisticated and complicated. By switching and controlling the address counter in the FWD direction and the BWD direction, it is possible to cope with read operations in the FWD direction and the BWD direction by setting a counter load value and setting the counter to up-count or down-count. By dividing the data into three groups, the write operation and the read operation can be performed at the same timing even in the above-described phenomenon of two frames being shifted at the time of writing and at the time of reading. Can do.

  In contrast to the conventional method of improving the data transfer control method, which is a conventional means of adding data in a large amount of elements such as flip-flops and selectors for performing data storage or buffer control, the present invention adopts the above method. Data transfer control, minimizing the absolute number of elements used for data storage and buffer control, preventing an increase in circuit scale and complexity, shortening the development period, reducing development costs, Furthermore, it is possible to simplify test items, and it is possible to improve efficiency in many ways.

It is a block diagram which shows the internal structural example of the data format part of a magnetic tape control apparatus. It is a block diagram which shows the structural example of a tape subsystem. It is a figure which shows the structural example of the remaining byte preparation circuit of this invention. It is a timing chart (custom data is 8 bytes) of the remaining byte creation circuit of this invention. It is a timing chart (custom data is 9 bytes) of the remaining byte creation circuit of this invention. It is a graph which shows the mod14 counter output of the remaining byte preparation circuit of this invention. It is a figure which shows the structural example of the DRC preparation circuit of this invention. It is a figure which shows the structural example of the DRC preparation circuit of this invention. It is a figure which shows the structural example of the VRC preparation circuit of this invention. It is a graph which shows the relationship between the input data at the time of DRC preparation in this invention, and a data timing. It is a figure which shows an example of DRC preparation in this invention. It is a chart which shows the data selection in the DRC preparation circuit of a prior art example. It is a chart which shows the data selection in the DRC preparation circuit of a prior art example. It is a chart which shows the data selection in the DRC preparation circuit of this invention. It is a chart which shows the data selection in the DRC preparation circuit of this invention. It is a figure which shows the structural example of the data selection part in the DRC preparation circuit of this invention. It is a figure which shows the structural example of the data selection part in the DRC preparation circuit of this invention. It is a figure which shows the structural example of the data selection part in the DRC preparation circuit of this invention. It is a figure which shows the structural example of the data selection part in the DRC preparation circuit of this invention. It is a graph which shows the data mask timing in the data mask part of the DRC preparation circuit of this invention. It is a graph which shows the data mask timing in the data mask part of the DRC preparation circuit of this invention. It is a figure which shows the structural example of the data mask part of the DRC preparation circuit of this invention. It is a figure which shows the structural example of the data mask part in the DRC preparation circuit of this invention. It is a figure which shows the structural example of the data mask part of the DRC preparation circuit of this invention. It is a figure which shows the structural example of the data mask part in the DRC preparation circuit of this invention. It is a figure which shows the data acquisition timing in the DRC preparation circuit of this invention. It is a figure which shows the data acquisition timing in the DRC preparation circuit of this invention. It is a figure which shows the data acquisition timing in the DRC preparation circuit of this invention. It is a figure which shows the data acquisition timing in the DRC preparation circuit of this invention. It is a figure which shows the data acquisition timing in the DRC preparation circuit of this invention. It is a figure which shows the data acquisition timing in the DRC preparation circuit of this invention. It is a figure which shows the data set timing in the DRC preparation circuit of this invention. It is a figure which shows the data set timing in the DRC preparation circuit of this invention. It is a figure which shows the data set timing in the DRC preparation circuit of this invention. It is a figure which shows the data set timing in the DRC preparation circuit of this invention. It is a figure which shows the data set timing in the DRC preparation circuit of this invention. It is a figure which shows the data set timing in the DRC preparation circuit of this invention. It is a figure which shows the data selection in the DRC preparation circuit of this invention. It is a figure which shows the structural example of the data selection part of the DRC preparation circuit of this invention. It is a figure which shows the structural example of the encoding circuit of this invention. It is a figure which shows the structural example of the encoding circuit of this invention. It is a block diagram which shows the structural example of the syndrome production circuit of this invention. FIG. 43 is a diagram illustrating an internal configuration example of a parallel syndrome calculation unit and a controller unit illustrated in FIG. 42. It is a block diagram which shows the structural example of the deskew circuit of this invention. It is a figure which shows the operation | movement of the deskewing buffer in the deskew circuit of this invention. It is a figure which shows the operation | movement of the deskewing buffer in the deskew circuit of this invention. It is a figure which shows the operation | movement of the deskewing buffer in the deskew circuit of this invention. It is a figure which shows the operation | movement of the deskewing buffer in the deskew circuit of this invention. It is a block diagram which shows the structural example of the data transfer control system of this invention. It is a figure which shows the memory map in the data transfer control system of this invention. It is a figure which shows the frame data format in the data transfer control system of this invention. It is a figure which shows the frame data transfer timing in the data transfer control system of this invention. 6 is a timing chart of writing / reading (during FWD) in the data transfer control system of the present invention. 4 is a timing chart of writing / reading (during BWD) in the data transfer control system of the present invention. It is a figure which shows the data format recorded on the magnetic tape. It is a figure which shows the data format when custom data is 12 bytes. It is a figure which shows the data format when custom data is 7 bytes. It is a figure which shows the structural example of the remaining byte preparation circuit of a prior art example. It is a timing chart of the remaining byte creation circuit of a prior art example. It is a graph which shows the mod14 counter output of the remaining byte preparation circuit of a prior art example. It is a figure which shows the DRC preparation format of a prior art example. It is a graph which shows the example of calculation of DRC in a prior art example. It is a figure which shows the structural example of the DRC preparation circuit of a prior art example. It is a figure which shows the preparation method of VRC in a prior art example. It is a chart which shows the example of calculation of VRC in a conventional example. It is a figure which shows the structural example of the VRC preparation circuit of a prior art example. It is a figure which shows the structural example of the encoding circuit using LFSR of a prior art example. It is a figure which shows the structural example of the encoding circuit using the check matrix of a prior art example. It is a figure which shows the structural example of the encoding circuit using the check matrix of a prior art example. It is a figure which shows the data format on a magnetic tape. It is the elements on larger scale of the data format shown in FIG. It is a block diagram which shows the structural example of the deskew circuit of a prior art example. It is a figure which shows the motion (at the time of FWD) of the deskewing buffer in the deskew circuit of a prior art example. It is a figure which shows the motion (at the time of FWD) of the deskewing buffer in the deskew circuit of a prior art example. It is a figure which shows the motion (at the time of FWD) of the deskewing buffer in the deskew circuit of a prior art example. It is a figure which shows the motion (at the time of FWD) of the deskewing buffer in the deskew circuit of a prior art example. It is a figure which shows the motion (at the time of BWD) of the deskewing buffer in the deskew circuit of a prior art example. It is a figure which shows the motion (at the time of BWD) of the deskewing buffer in the deskew circuit of a prior art example. It is a figure which shows the motion (at the time of BWD) of the deskewing buffer in the deskew circuit of a prior art example. It is a figure which shows the motion (at the time of BWD) of the deskewing buffer in the deskew circuit of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Residual byte creation circuit 2, 4 Multiplexer 3 Error correction coding circuit 5 Deskew circuit 6 Syndrome creation circuit 7 Error correction circuit 8 Frame buffer 10 Host 11 Magnetic tape controller (MTC)
12 Magnetic tape unit (MTU)
11b Data format part 11d Write format part 11e Read format part 21A, 21B Data selection part 22A, 22B Data parity creation part 23A, 23B Frame control part 24A, 24B Data mask part 25 Adder circuit 26 Register 27 Multiplier circuit 33 Parallel syndrome arithmetic part 41A, 41B, 41C Deskew control circuit 42A, 42B, 42C Deskewing buffer 51 SRAM
52 Address load value setting circuit 53 FWD / BWD switching circuit 54 Address counter circuit

Claims (3)

An error correction code is added to the data input from the host device, the format is converted, the format-converted data is transferred to the magnetic tape unit, and the data read from the magnetic tape unit is error-corrected and the format is converted to the format. In the control device of the magnetic tape device that transfers the converted data to the host device,
It is configured to perform error correction encoding processing in units of a plurality of bytes for input data from the host device and / or to perform error correction processing in units of a plurality of bytes for read data from the magnetic tape unit, It comprises an error correction coding means for creating a Reed-Solomon error correction code for data from a host device, and the error correction coding means is configured to process a plurality of summation calculations of information words in parallel. Control device for magnetic tape device.   When the data from the higher-level device is configured in one frame of a predetermined number of bytes, the counter includes a counting unit that counts the remaining bytes so that the number of bytes in each frame is a predetermined number, 2. The apparatus according to claim 1, further comprising means for determining whether the number of bytes of data from the host device is an odd number or an even number, and a means for switching a remaining byte counting method according to the determination result. Control unit for magnetic tape unit.   Syndrome creation means for creating a syndrome necessary for correcting an error in data read from the magnetic tape unit according to a Reed-Solomon method, the syndrome creation means having a plurality of circuits for multiplying a received word by a check matrix 2. The control device for a magnetic tape device according to claim 1, wherein syndromes are created in parallel for a plurality of bytes of data.

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