JP2006084681A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which extends a ghost margin to be able to prevent a vertical stripe pattern in a display picture of a display panel. <P>SOLUTION: Resistance elements R31 and R32 for adjusting phases of clock pulses DCK and DCKX for sampling a video signal supplied from a clock generation circuit 40 provided on the outside of a LCD panel 30, and a video signal VDO are connected between input pads PD31 and PD32 of clock pulses DCK and DCKX and an input terminal of a clock buffer circuit 34 which has a level shifter and shifts levels of input clocks DCK1 and DCK2 and then supplies them to a horizontal scanner 33. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device, and more particularly to a dot sequential drive type active matrix display device employing a so-called clock drive method for a horizontal drive circuit (horizontal scanner).

  In a display device, for example, an active matrix type liquid crystal display device using a liquid crystal cell as a pixel display element (electro-optical element), a dot sequential driving method is adopted for a horizontal driving circuit (horizontal scanner unit).

FIG. 1 is a block diagram illustrating a configuration of an active matrix liquid crystal display device.
FIG. 2 is a circuit diagram showing a configuration of an active matrix liquid crystal display device adopting a general dot sequential driving method (see, for example, Patent Document 1).

The liquid crystal display device 1 includes a liquid crystal display panel (LCD panel) 10 and a clock generation circuit (GEN: timing generator) 20 as shown in FIGS.
As shown in FIG. 2, the LCD panel 10 includes an effective pixel portion (PXLP) 11, a vertical scanner (VSCN) 12 (-1, -2), a horizontal scanner (HSCN) 13, a level shift and clock buffer circuit ( LVL + BUF) 14 (-1, -2, -3, -4) and a signal line precharge circuit (PRCG) 15 are provided as main components.
As shown in FIG. 1, the vertical scanner may be arranged not only on one side of the pixel unit 11 but also on both sides, but in FIG. 2, for simplification of the drawing and description. The example which provided only in the one side part of the pixel part 11 is shown.
Further, not only the pulse signals DCK1 and DCK2, but also all the driving pulses pass through the level shift and clock buffer circuits (LVL + BUF) 14-1 to 14-4 to the vertical scanner 12, the horizontal scanner 13, and the precharge circuit 15. In FIG. 2, for convenience of explanation, only the pulse signals DCK1 and DCK2 are shown to be input via the level shift and clock buffer circuit (LVL + BUF) 14-1.

The pixel unit 11 includes a plurality of pixels PXL arranged in a matrix of m rows and n columns. Here, in order to simplify the drawing, a case of a pixel array of 4 rows and 4 columns is shown as an example.
Each of the pixels PXL arranged in a matrix form a thin film transistor (TFT) 11 that is a pixel transistor, a liquid crystal cell LC in which the pixel electrode is connected to the drain electrode of the TFT 11, and one side to the drain electrode of the TFT 11. And a storage capacitor Cs to which the electrodes are connected.
For each of these pixels PXL, signal lines SGNL1 to SGNL4 are wired along the pixel arrangement direction for each column, and gate lines GTL1 to GTL4 are wired along the pixel arrangement direction for each row.

The vertical scanner 12 performs a process of sequentially selecting each pixel PXL connected to the gate lines GTL1 to GTL4 in units of rows by scanning in the vertical direction (row direction) every field period.
That is, when the scanning pulse SP1 is applied from the vertical scanner 12 to the gate line GTL1, the pixels in each column of the first row are selected, and when the scanning pulse SP2 is applied to the gate line GTL2, the second row. A pixel in each column is selected. Similarly, scan pulses SP3 and SP4 are sequentially applied to the gate lines GTL3 and GTL4.

For example, a horizontal scanner 13 is disposed above the pixel unit 11 in the drawing.
The horizontal scanner 13 sequentially samples the input video signal VDO every 1H (H is a horizontal scanning period), and performs processing of writing to each pixel PXL selected in units of rows by the vertical scanner 12.
As shown in FIG. 2, the horizontal scanner 13 employs a clock drive system, and includes a shift register 131, a clock extraction switch group 132, a phase adjustment circuit (PAC; Phase).
Adjust Cirsuit) group 133 and sampling switch group 134.

  The shift register 131 includes four shift stages (S / R stages) 131-1 to 131-4 corresponding to the pixel columns (four columns in this example) of the pixel unit 11. When the start pulse HST is given, the shift operation is performed in synchronization with the horizontal clocks HCK and HCKX having opposite phases, and the shift pulses SFTP1 to SFTP4 are sequentially output.

The clock extraction switch group 132 includes four switches 132-1 to 132-4 corresponding to the pixel columns of the pixel unit 11, and one end of each of the switches 132-1 to 132-4 is formed by the clock generation circuit 20. The clock lines DKL2 and DKL1 are alternately connected to the clock lines DCK2 and DCK1.
The shift pulses SFTP1 to SFTP4 sequentially output from the shift stages 131-1 to 131-4 of the shift register 131 are given to the switches 132-1 to 132-4 of the clock extraction switch group 132, and these shift pulses SFTP1. The second clocks DCK2 and DCK1 are alternately extracted by sequentially turning on in response to .about.SFTP4.

  The phase adjustment circuit group 133 includes four phase adjustment circuits 133-1 to 133-4 corresponding to the pixel columns of the pixel unit 11, and each of the phase adjustment circuits 133-1 to 133-4 has a clock extraction switch group 132. After the phases of the second clocks DCKX and DCK extracted by the respective switches 132-1 to 132-4 are adjusted, they are supplied to the sampling switches of the corresponding sampling switch group 134.

  The sampling switch group 134 includes four sampling switches 134-1 to 134-4 corresponding to the pixel columns of the pixel unit 11, and one end of each of the sampling switches 134-1 to 134-4 receives the video signal VDO. It is connected to the input video line VDL1. In each sampling switch 134-1 to 134-4, clock pulses DCK2 and DCK1 extracted by the respective switches 132-1 to 132-4 of the clock extraction switch group 132 and phase-adjusted by the phase adjustment circuit group 133 are sampled and held. Given as pulses SHP1 to SHP4 and sequentially turned on in response to the sample hold pulses SHP1 to SHP4, the video signal VDO inputted through the video line VDL1 is sequentially sampled, and the signal lines SGNL1 to SGNL1 of the pixel unit 11 Supply to SGNL4.

The clock generation circuit 20 includes a vertical start pulse VST for instructing the start of vertical scanning, vertical clocks VCK and VCKX having opposite phases as a reference for vertical scanning, a vertical start pulse VST for instructing the start of horizontal scanning, and a reference for horizontal scanning. The horizontal clocks HCK and HCKX having opposite phases to each other are generated, the vertical start pulse VST and the vertical clocks VCK and VCKX are supplied to the vertical scanner 12, and the horizontal clocks HCK and HCKX are supplied to the horizontal scanner 13.
The clock generation circuit 20 generates second clocks DCK1 and DCK2 having the same period (T1 = T2) as the generated horizontal clocks (first clocks) HCK and HCKX and having a low duty ratio and opposite phases. And supplied to the horizontal scanner 13. Here, the duty ratio is a ratio between the pulse width t and the pulse repetition period T in the pulse waveform.
For example, as shown in FIGS. 3A to 3D, the duty ratio (t1 / T1) of the horizontal clocks HCK and HCKX is 50%, and the duty ratio (t2 / T2) of the clock pulses DCK1 and DCK2 is more than this. ) Is small, that is, the pulse width t2 of the clock pulses DCK1 and DCK2 is set narrower than the pulse width t1 of the horizontal clocks HCK and HCKX.

  In the horizontal scanner 13 described above, the shift pulses SFTP1 to SFTP4 sequentially output from the shift register 131 are not used as sample hold pulses, but the clocks DCK2 and DCK1 having opposite phases are alternately synchronized with the shift pulses SFTP1 to SFTP4. These clocks DCK2 and DCK1 are used as sample and hold pulses SHP1 to SHP via a phase adjustment circuit. Thereby, the dispersion | variation in the sample hold pulses SHP1-SHP can be suppressed. As a result, it is possible to remove ghosts caused by variations in the sample hold pulses SHP1 to SHP.

  In addition, the horizontal scanner 13 does not extract the horizontal clocks HCKX and HCK, which are the reference for the shift operation of the shift register 131, and use them as sample-and-hold pulses. Since small clocks DCK2 and DCK1 are separately generated, and these clock pulses DCK2 and DCK1 are extracted and used as sample hold pulses SHP1 to SHP, complete non-overlapping sampling between sampling pulses is performed during horizontal driving. Therefore, it is possible to suppress the occurrence of vertical stripes due to overlap sampling.

Here, for example, as shown in FIG. 4, the operation when the video signal VDO is written to the corresponding pixel at the Nth and N + 1th stages adjacent to each other will be described with reference to FIGS. To do.
In this case, for example, the video signal VDO, the drive signal DRVP-N of the Nth stage signal line SGNL-N, and the drive pulse DRVP-N + 1 of the N + 1 stage signal line SGNL-N + 1 are shown in FIGS. In the case of the timing relationship shown in FIG. 5C, ideally, a white signal is written in the Nth stage and a black signal is written in the N + 1th stage, and there is no ghost as shown in FIG. An image is obtained.

However, in LCDs using TFTs, transistor characteristics generally change due to panel aging. Due to this characteristic change, a pulse delay occurs in each transistor, and eventually the sample hold pulse SHP drifts with respect to its initial state.
Due to this drift, the optimum sample hold position with respect to the ghost shifts, and if the sample hold position set value at the time of initial shipment is maintained, the video signal at the adjacent stage is sampled and held, and a ghost is generated.
Specifically, as shown in FIGS. 6A to 6C, the drive signal DRVP-N of the Nth signal line SGNL-N and the drive pulse DRVP− of the N + 1th signal line SGNL-N + 1. N + 1 is delayed as indicated by the solid line after aging from the initial state indicated by the broken line. As a result, as shown in FIG. 6D, a black signal is written in the Nth stage, and a ghost GST occurs.

Thus, in the dot sequential active matrix LCD, the drive pulse is delayed to the rear side as the drive time elapses. This is because Vth increases due to hot carriers of the TFT. Generally, the delay amount of the pulse generated by the elapse of the driving time is about 30 nsec, and the LCD panel 10 needs a ghost margin larger than this delay amount.
Conventionally, as the ghost margin expansion, as shown in FIGS. 7A and 7B, the non-overlap time is increased and the pulse is sharpened.
JP 2002-72987 A

By the way, although the steepening of the pulse has been performed by reducing the load related to the sampling pulse and increasing the buffer size, the present LCD panel is approaching the limit value due to the limitation of the layout area.
The increase in the non-overlap time means narrowing of the sampling pulse width. In the XGA (Extended Graphics Array) display standard panel, which is the mainstream at present, the sampling pulse width is narrow due to the 6-dot simultaneous sampling method. There is a disadvantage that unit period band streaks are likely to occur due to the duty difference between the clock pulses DCK1 and DCK2.

  The present invention has been made in view of such circumstances, and an object of the present invention is to realize an enlargement of a ghost margin in addition to an increase in non-overlap time and a sharpening of a sampling pulse, and consequently a display screen on a display panel. It is an object of the present invention to provide a display device capable of preventing vertical stripe patterns.

  In order to achieve the above object, according to an aspect of the present invention, there is provided a clock generation circuit that generates a clock pulse, and a pixel unit in which a plurality of pixels are arranged in a matrix and a signal line is wired for each pixel column A driving circuit that sequentially samples the video signal in response to the clock pulse and supplies the video signal to each corresponding signal line of the pixel unit; and the clock pulse generated by the clock generation circuit is waveform-shaped and supplied to the driving circuit. And a resistance element connected between the clock generation circuit and the clock buffer circuit and having a resistance value set to match the phase of the video signal and the phase of the clock pulse.

  Preferably, the phase adjustment is performed by adjusting a delay amount by adjusting a resistance value of the resistance element.

  Preferably, the clock buffer circuit includes a level shifter, shapes a clock pulse level-shifted by the level shifter, and the resistance element is arranged at a stage prior to the level shifter.

  Preferably, the pixel portion, the driving circuit, the clock buffer circuit, and the resistance element are formed on the same panel.

  Preferably, the pixel portion, the drive circuit, and the clock buffer circuit are formed on the same panel, and the resistance element is formed outside the panel.

According to the present invention, the ghost margin is expanded by matching the phases of the clock pulse as the sampling pulse and the video signal.
Specifically, in the phase matching, the delay amount is adjusted by adjusting the resistance value of the resistance element with respect to the phase of the clock pulse serving as the sampling pulse.
Thus, since the phase adjustment is determined by the resistance value, it is not governed by the phase change in units of master clock MCK (= several nsec units) for driving the panel.
Then, by inserting a phase adjusting resistor element before the level shifter, even if a pulse with a rising / falling τ of the panel input waveform is input, the input pulse is shaped by the buffer after the level shifter. For this reason, as the sampling pulse, it is possible to use, as the sampling pulse, a waveform that maintains the same transient as that before the phase adjusting resistance element is inserted.

  According to the present invention, in addition to an increase in the non-overlap time and a sharpening of the sampling pulse, it is possible to realize an increase in the ghost margin and, in turn, to prevent a vertical stripe pattern on the display screen in the display panel. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 8 is a block diagram showing a configuration of an active matrix liquid crystal display device according to the first embodiment of the present invention using, for example, a liquid crystal cell as a pixel display element (electro-optical element).
FIG. 9 is a circuit diagram showing a configuration of an active matrix liquid crystal display device adopting the dot sequential driving method according to the first embodiment.

As shown in FIGS. 8 and 9, the liquid crystal display device 2 includes a liquid crystal display panel (LCD panel) 30 and a clock generation circuit (GEN: timing generator) 40.
As shown in FIG. 8, the LCD panel 30 includes DCK input pads PD31 and PD32, phase adjusting resistor elements R31 and R32, an effective pixel portion (PXLP) 31, and a vertical scanner (VSCN) 32 (−1, − 2), a horizontal scanner (HSCN) 33, a level shift and clock buffer circuit (LVL + BUF) 34 (-1, -2, -3, -4), and a signal line precharge circuit (PRCG) 35 as main components Have.
As shown in FIG. 8, the vertical scanner may be arranged not only on one side of the pixel unit 11 but also on both sides, but in FIG. 9, for simplification of the drawing and description. The example provided in only one side of the pixel unit 31 is shown.
Further, not only the pulse signals DCK1 and DCK2, but also all the driving pulses pass through the level shift and clock buffer circuits (LVL + BUF) 14-1 to 14-4 to the vertical scanner 12, the horizontal scanner 13, and the precharge circuit 15. In FIG. 9, for convenience of explanation, only the pulse signals DCK1 and DCK2 are shown to be input via the level shift and clock buffer circuit (LVL + BUF) 14-1.

  In the first embodiment, input pads PD31 and PD32 for clock pulses DCK and DCKX for sampling a video signal supplied by a clock generation circuit 40 provided outside the LCD panel 30, and as will be described later. The phase of the clock pulses DCK and DCKX as sampling pulses and the video signal VDO between the input terminal of the clock buffer circuit 34 which has a level shifter and shifts the input clock shift clocks DCK1 and DCK2 to the horizontal scanner 33 after level shift. Phase adjustment resistance elements R31 and R32 for adjusting the frequency are connected.

In this embodiment, in an active matrix liquid crystal display device adopting a dot sequential driving method, the ghost margin is increased by matching the phases of the sampling pulse and the video signal VDO.
In the phase matching, the delay amount is adjusted by adjusting the phase of the input pulses DCK1 and DCK2 serving as sampling pulses and the resistance values of the resistance elements R31 and R32.
Thus, in the present embodiment, since the phase adjustment is determined by the resistance value, it is not governed by the phase change in units of the master clock MCK (= several nsec units) for driving the LCD panel 30.
Further, since the phase adjustment is performed by adjusting the resistance value of the resistance element, the phase adjustment in units of 1 nsec is realized.
Then, by inserting the phase adjusting resistor elements R31 and R32 before the level shifter inside the panel, even if a pulse whose rising / falling time τ of the panel input waveform is input is input, the input pulse is input by the buffer after the level shifter. Since the waveform is shaped, it is possible to use, as the sampling pulse, a waveform that maintains a transient equivalent to that before inserting the phase adjusting resistance elements R31 and R32.

In the pixel unit 31, a plurality of pixels PXL are arranged in a matrix of m rows and n columns. Here, in order to simplify the drawing, a case of a pixel array of 4 rows and 4 columns is shown as an example.
Each of the pixels PXL arranged in a matrix includes a thin film transistor (TFT) 31 that is a pixel transistor, a liquid crystal cell LC in which the pixel electrode is connected to the drain electrode of the TFT 31, and a drain electrode of the TFT 31. And a storage capacitor Cs to which the electrodes are connected.
For each of these pixels PXL, signal lines SGNL31 to SGNL34 are wired along the pixel arrangement direction for each column, and gate lines GTL31 to GTL34 are wired along the pixel arrangement direction for each row.
In each pixel PXL, the source electrode (or drain electrode) of the TFT 31 is connected to the corresponding signal lines SGNL31 to SGNL34. The gate electrode of the TFT 31 is connected to the gate lines GTL31 to GTL34, respectively. The counter electrode of the liquid crystal cell LC and the other electrode of the storage capacitor Cs are connected to the Cs line CsL31 in common between the pixels. A predetermined DC voltage is applied as a common voltage Vcom to the Cs line Cs L31.
In the pixel unit 31, one end of each of the gate lines GTL <b> 31 to GTL <b> 34 is connected to the output end of each row of the vertical scanner 32 (−1) disposed on the left side of the pixel unit 31 in the drawing, for example.

The vertical scanner 32 performs a process of scanning in the vertical direction (row direction) for each field period and sequentially selecting each pixel PXL connected to the gate lines GTL1 to GTL4 in units of rows.
That is, when the scanning pulse SP31 is applied from the vertical scanner 32 to the gate line GTL31, the pixels in each column of the first row are selected, and when the scanning pulse SP32 is applied to the gate line GTL32, the second row. A pixel in each column is selected. Similarly, scanning pulses SP33 and SP34 are sequentially applied to the gate lines GTL33 and GTL34.

For example, a horizontal scanner 33 is disposed above the pixel unit 31 in the drawing.
The horizontal scanner 33 sequentially samples the input video signal VDO every 1H (H is a horizontal scanning period), and performs processing of writing to each pixel PXL selected in units of rows by the vertical scanner 32.
As shown in FIG. 9, the horizontal scanner 33 employs a clock drive system, and includes a shift register 331, a clock extraction switch group 332, a phase adjustment circuit (PAC; Phase
Adjust Cirsuit) group 333 and sampling switch group 334.

  The shift register 331 includes four shift stages (S / R stages) 331-1 to 331-4 corresponding to the pixel columns (four columns in this example) of the pixel unit 31. When the start pulse HST is given, a shift operation is performed in synchronization with the horizontal clocks HCK and HCKX having opposite phases. Accordingly, shift pulses SFTP31 to SFTP34 having the same pulse width as the cycles of the horizontal clocks HCK and HCKX are sequentially output from the shift stages 331-1 to 331-4 of the shift register 331.

The clock extraction switch group 332 includes four switches 332-1 to 332-4 corresponding to the pixel columns of the pixel unit 31, and one end of each of the switches 332-1 to 332-4 is formed by the clock generation circuit 40. They are alternately connected to clock lines DKL32 and DKL31 that transmit clock pulses DCK2 and DCK1.
That is, one end of each of the switches 332-1 and 332-3 is connected to the clock line DKL 32, and each end of each of the switches 332-2 and 332-4 is connected to the clock line DKL 31.
Shift pulses SFTP31 to SFTP34 sequentially output from the shift stages 331-1 to 331-4 of the shift register 331 are applied to the switches 332-1 to 332-4 of the clock extraction switch group 332. When the shift pulses SFTP31 to SFTP34 are given from the shift stages 331 to 331-4 of the shift register 331, the switches 332-1 to 332-4 of the clock extraction switch group 332 respond to these shift pulses SFTP31 to SFTP34. The clocks DCK2 and DCK1 are alternately extracted by sequentially turning on.

  The phase adjustment circuit group 333 includes four phase adjustment circuits 333-1 to 333-4 corresponding to the pixel columns of the pixel unit 31, and each phase adjustment circuit 333-1 to 333-4 has a clock extraction switch group 332. The second clocks DCKX and DCK extracted by the respective switches 332-1 to 332-4 are adjusted in phase, and then supplied to the sampling switches of the corresponding sampling switch group 334.

The sampling switch group 334 includes four sampling switches 334-1 to 334-4 corresponding to the pixel columns of the pixel unit 31, and one end of each of the sampling switches 334-1 to 334-4 receives the video signal VDO. It is connected to the input video line VDL31. In each sampling switch 334-1 to 334-4, clocks DCK 2 and DCK 1 extracted by the respective switches 332-1 to 332-4 of the clock extraction switch group 332 and phase-adjusted by the phase adjustment circuit group 333 are sample hold pulses. Given as SHP31-SHP34.
When the sample hold pulses SHP31 to SHP34 are applied, the sampling switches 334-1 to 334-4 of the sampling switch group 334 are sequentially turned on in response to the sample hold pulses SHP31 to SHP34, whereby the video line VDL31. Are sequentially sampled and supplied to the signal lines SGNL31 to SGNL34 of the pixel unit 31.

  The clock buffer circuit 34 is supplied by a clock generation circuit 40 provided outside the LCD panel 30, is input into the LCD panel 30 through the input pads PD31 and PD32, and is input through the phase adjusting resistance elements R31 and R32. The clock pulses DCK1 and DCK2 for sampling are level-shifted and supplied to the horizontal scanner 33.

FIG. 10 is a circuit diagram showing a configuration example of the clock buffer circuit 34.
The clock buffer circuit 34 in FIG. 10 is a circuit mainly for performing level shift, and can be provided separately from the horizontal scanner 33 as shown in FIG. 8, or provided in the clock input section in the horizontal scanner 33. You can also.
The clock buffer circuit 34 includes a level shifter 341-1 in a system for generating the drive clock DCK1, and an even number (four in the example of FIG. 10) of inverters 342-1 to 342-1 connected in series to the output side of the level shifter 341-1. 345-1. Similarly, a level shifter 341-2 is connected to a system for generating the drive clock DCK2, and an even number (four in the example of FIG. 10) of inverters 342-2 to 345-2 connected in series on the output side of the level shifter 341-2. Have The level shifters 341-1 and 341-2 have the same function.
Then, the level-converted clock pulses DCK1, DCK2 are output from the final stage inverters 345-1, 345-2 in each system.

The clock generation circuit 30 includes a vertical start pulse VST for instructing the start of vertical scanning, vertical clocks VCK and VCKX having opposite phases as a reference for vertical scanning, a vertical start pulse VST for instructing the start of horizontal scanning, and a reference for horizontal scanning. The horizontal clocks HCK and HCKX having opposite phases to each other are generated, the vertical start pulse VST and the vertical clocks VCK and VCKX are supplied to the vertical scanner 32, and the horizontal clocks HCK and HCKX are supplied to the horizontal scanner 33.
The clock generation circuit 30 generates second clocks DCK1 and DCK2 having the same period (T1 = T2) as the generated horizontal clocks (first clocks) HCK and HCKX and having a low duty ratio and opposite phases. And supplied to the horizontal scanner 13. Here, the duty ratio is a ratio between the pulse width t and the pulse repetition period T in the pulse waveform.

  Hereinafter, an advantage of providing the resistance elements R31 and R32 on the input side of the clock pulses DCK1 and DCK2 of the clock buffer circuit 34 having the level shifter will be described.

In an active matrix liquid crystal display device adopting a dot sequential driving method, a ghost is determined by the phase relationship between clock pulses DCL1 and DCK2 serving as sampling pulses and a video signal VDO.
Therefore, as a set, the initial ghost margin is adjusted by adjusting the phase of the clock pulse DCK or the video signal VDO input to the LCD panel.
This phase adjustment can be performed only in units of the master clock MCK when the resistance elements R31 and R32 are not provided on the input side of the clocks DCK1 and DCK2 of the clock buffer circuit 34 as in the present embodiment, and it is assumed that the MCK is 65 MHz. In the set using, it can be varied only in units of 1/65 MHz = 15.4 nsec.

  FIG. 11A is a diagram showing the phase relationship between the clock pulse DCK as a sampling pulse and the video signal VDO when the initial phase alignment by the resistance element is not performed. FIG. 11B is a diagram showing the phase relationship between the clock yield DCK as the sampling pulse and the video signal VDO when the initial phase matching is performed by the resistance element.

As shown in FIG. 11A, when the initial phase alignment by the resistance element is not performed, the video signal VDO is covered with the clock pulse DCK as the sampling pulse of the subsequent stage (N + 1) in the initial state.
Therefore, the phase of the clock pulse DCK as the sampling pulse is moved by one master clock MCK, and the state shown by the vertical line in the figure is obtained. For this reason, when the two-scale pulse is delayed, the video signal VDO generates a clock pulse DCK as a sampling pulse of the previous stage (N-1 stage) and a covering ghost.

On the other hand, as shown in FIG. 11B, in the case of performing the initial phase alignment by the resistance element, the phase of the rising edge of the subsequent stage (N + 1 stage) of the clock pulse DCK as the sampling pulse and the falling edge of the video signal VDO are set. Synchronize completely.
As a result, if the 5-scale pulse is not delayed, the video signal VDO is not covered with the clock pulse DCK as the sampling pulse of the previous stage (N-1 stage), and the ghost margin is expanded by matching the initial phase.

FIG. 12 is a diagram showing transients of the clock pulse DCK in the DCK line DKL31 (DKL32) and the horizontal scanner 33 before the level shifter (LVL) and after the level shifter of the clock buffer circuit 34 according to the present embodiment.
FIG. 13 is a diagram showing the delay amount of the clock pulse DCK in the DCK line DKL31 (DKL32) and the horizontal scanner 33 before and after the level shifter of the clock buffer circuit 34 according to the present embodiment.
12 and 13, the curve indicated by A indicates the characteristic before the level shifter, the curve indicated by B indicates the characteristic after the level shifter, the curve indicated by C indicates the characteristic in the DCK line, and the curve indicated by D indicates the characteristic in the horizontal scanner. Each is shown.

As shown in FIG. 12, by inserting the phase adjusting resistance elements R31 and R32 before the level shifter (clock buffer circuit 34) of the clock pulse DCK that becomes the sampling pulse as in the present embodiment, the transient is not detected before the level shifter. Although it becomes distorted due to the RC time constant, the waveform is shaped by passing through the DCK clock buffer circuit 34, and the sampling pulse maintains the same transient as the conventional pulse.
Further, as shown in FIG. 13, by inserting the phase adjusting resistor elements R31 and R32, the clock pulse DCK serving as a sampling pulse has a delay relationship proportional to the inserted resistance value.
The amount of delay can be adjusted with an accuracy of 1 nsec by the resistance value to be inserted, and is not a rough phase adjustment as in the master clock MCK unit.
Thereby, the ghost margin can be expanded by adjusting the phase of the clock pulse DCK using the initial ghost as the sampling pulse and the video signal VDO.

As described above, according to the first embodiment, the input pads PD31 of the clock pulses DCK and DCKX for sampling the video signal supplied by the clock generation circuit 40 provided outside the LCD panel 30 are provided. Clock pulses DCK and DCKX as sampling pulses and video signals are connected between the PD 32 and an input terminal of a clock buffer circuit 34 which has a level shifter and shifts the input clock shift clocks DCK1 and DCK2 and supplies the clocks to the horizontal scanner 33. Since the resistance elements R31 and R32 for adjusting the phase of the VDO are connected, the delay amount is adjusted by adjusting the phase of the input pulses DCK1 and DCK2 serving as sampling pulses and the resistance values of the resistance elements R31 and R32. By adjusting the dot sequential drive system In an active matrix liquid crystal display device in which use can be realized ghost margin enlarge a way to push the combined phases of the sampling pulse and the image signal VDO.
Since the phase adjustment is determined by the resistance value, the phase adjustment is not governed by a phase change in units of master clock MCK (= several nsec units) for driving the LCD panel 30. Therefore, it is possible to realize phase alignment in units of 1 nsec.
Then, by inserting the phase adjusting resistor elements R31 and R32 before the level shifter inside the panel, even if a pulse whose rising / falling time τ of the panel input waveform is input is input, the input pulse is input by the buffer after the level shifter. Since the waveform is shaped, a waveform maintaining a transient equivalent to that before inserting the phase adjusting resistance elements R31 and R32 can be used as the sampling pulse.
Therefore, the liquid crystal display prosecution according to the first embodiment has an advantage that the ghost margin can be enlarged, and the vertical stripe pattern of the display screen in the display panel can be prevented.

Second Embodiment
FIG. 14 is a block diagram showing a configuration of an active matrix liquid crystal display device according to the second embodiment of the present invention using, for example, a liquid crystal cell as a pixel display element (electro-optical element).
FIG. 15 is a circuit diagram showing a configuration of an active matrix liquid crystal display device adopting a dot sequential driving method according to the second embodiment.

The second embodiment is different from the first embodiment described above in that the phase adjusting resistor elements R31 and R32 are connected to the supply lines of the clock pulses DCK1 and DCK2 outside the panel instead of inside the LCD panel 30A. It is in.
As described above, the phase adjusting resistance elements R31 and R32 may be arranged in any position inside or outside the panel as long as they are in front of the level shifter of the clock buffer circuit 34.
Other configurations are the same as those of the first embodiment.

  According to the second embodiment, it is possible to obtain the same effect as in the first embodiment described above.

  In the above description, an analog video signal is input and applied to a liquid crystal display device equipped with an analog interface driving circuit that samples and drives each pixel in a dot sequence. However, a digital video signal is input. The present invention can be similarly applied to a liquid crystal display device equipped with a digital interface driving circuit that converts this into an analog video signal, samples the analog video signal, and drives each pixel in a dot-sequential manner.

In the above description, the case where the present invention is applied to an active matrix type liquid crystal display device using a liquid crystal cell for each pixel is described as an example. However, the present invention is not limited to application to a liquid crystal display device, and as a display element for each pixel, For example, an electroluminescence (EL) element may be used.
As other dot sequential driving methods to which the present invention can be applied, in addition to the well-known 1H inversion driving method and the dot inversion driving method, in the pixel arrangement after writing the video signal, the left and right pixels adjacent to each other are adjacent. So as to simultaneously write video signals of opposite polarities to pixels in two rows, for example, the upper and lower rows, which are separated by an odd number of rows between adjacent pixel columns so that the pixels have the same polarity and the upper and lower pixels have the opposite polarity. There is a dot line inversion driving method.
Further, the image display panel may be a direct-view type or a projection type liquid crystal panel (image display panel in a liquid crystal projector) provided for each of RGB.

1 is a block diagram illustrating a configuration of an active matrix liquid crystal display device. It is a circuit diagram which shows the structure of the active matrix type liquid crystal display device which employ | adopted the general point sequential drive system. 4 is a timing chart showing a timing relationship between horizontal clocks HCK and HCKX and clocks DCK1 and DCK2. FIG. 3 is a diagram for explaining an operation centering on the horizontal scanner of FIG. 2. FIG. 3 is a waveform diagram for explaining an operation centering on the horizontal scanner of FIG. 2. It is a figure for demonstrating the subject of the horizontal scanner of FIG. It is a figure for demonstrating the expansion method of the conventional ghost margin. 1 is a block diagram illustrating a configuration of an active matrix liquid crystal display device according to a first embodiment of the present invention in which a liquid crystal cell is used as a pixel display element (electro-optical element). 1 is a circuit diagram illustrating a configuration of an active matrix liquid crystal display device that employs a dot sequential driving method according to a first embodiment. FIG. FIG. 3 is a diagram illustrating a specific configuration example of a clock buffer circuit according to the first embodiment. It is a figure which shows the phase relationship of the clock pulse DCK as a sampling pulse, and the video signal VDO, Comprising: (A) is the clock pulse DCK as a sampling pulse and video signal VDO when not performing initial phase alignment by a resistive element. It is a figure which shows a phase relationship, (B) is a figure which shows the phase relationship of the clock pulse DCK as a sampling pulse at the time of performing initial phase alignment by a resistive element, and the video signal VDO. It is a figure which shows the transient of the clock pulse DCK in a DCK line and a horizontal scanner before the level shifter (LVL) of the clock buffer circuit based on this embodiment, after a level shifter. It is a figure which shows the delay amount of the clock pulse DCK in a DCK line and a horizontal scanner before the level shifter of the clock buffer circuit which concerns on this embodiment, after a level shifter. It is a block diagram which shows the structure of the active-matrix liquid crystal display device based on the 2nd Embodiment of this invention which used the liquid crystal cell as a display element (electro-optical element) of a pixel. It is a circuit diagram which shows the structure of the active matrix type liquid crystal display device which employ | adopted the point-sequential drive system which concerns on 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 2 ... Liquid crystal display device, 30 ... LCD panel, 31 ... Effective pixel part (PXLP), 32 ... Vertical scanner (VSCN), 33 ... Horizontal scanner (HSCN), 34 ... Clock buffer circuit (CLKBUF), 35 ... Precharge circuit (PRCG), R31, R32... Phase adjustment resistance element, 40... Clock generation circuit (GEN).

Claims (7)

A clock generation circuit for generating a clock pulse;
A pixel portion in which a plurality of pixels are arranged in a matrix and a signal line is wired for each pixel column;
A driving circuit that sequentially samples video signals in response to the clock pulses and supplies the video signals to the corresponding signal lines of the pixel unit;
A clock buffer circuit that shapes the clock pulse by the clock generation circuit and supplies the clock pulse to the drive circuit;
A display device comprising: a resistance element connected between the clock generation circuit and the clock buffer circuit and having a resistance value set to match the phase of the video signal and the phase of the clock pulse. The display device according to claim 1, wherein the phase alignment is performed by adjusting a delay amount by adjusting a resistance value of the resistance element. The clock buffer circuit has a level shifter, and shapes the clock pulse level-shifted by the level shifter,
The display device according to claim 1, wherein the resistance element is arranged in front of the level shifter. The display device according to claim 1, wherein the pixel portion, the driving circuit, the clock buffer circuit, and the resistance element are formed on the same panel. The display device according to claim 3, wherein the pixel portion, the driving circuit, the clock buffer circuit, and the resistance element are formed on the same panel. The pixel portion, the drive circuit, and the clock buffer circuit are formed on the same panel,
The display device according to claim 1, wherein the resistance element is formed outside the panel. The pixel portion, the drive circuit, and the clock buffer circuit are formed on the same panel,
The display device according to claim 3, wherein the resistance element is formed outside the panel.

Images