JP3788435B2 - Display device and projection display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device and a driving method thereof, and more particularly to a dot sequential drive type active matrix display device and a projection type display device employing a so-called clock drive method for a horizontal drive circuit (horizontal scanner).
[0002]
[Prior art]
In a display device, for example, an active matrix type liquid crystal display device using a liquid crystal cell as a pixel display element (electro-optical element), a dot sequential driving method is adopted for a horizontal driving circuit (horizontal scanner unit).
[0003]
FIG. 1 is a circuit diagram showing a configuration of an active matrix liquid crystal display device adopting a general dot sequential driving method (see, for example, Patent Document 1).
[0004]
As shown in FIG. 1, the liquid crystal display device (LCD panel) 10 includes an effective pixel unit (PXLP) 11, a vertical scanner (VSCN) 12, a horizontal scanner (HSCN) 13, and a first clock generation circuit (GEN1: timing). Generator) 14 and a second clock generation circuit (GEN2) 15 as main components.
As shown in FIG. 2, the vertical scanner may be arranged not only on one side of the pixel unit 11 but also on both sides, and a signal line precharge circuit (PRCG) 16 is provided. .
[0005]
The pixel unit 11 includes a plurality of pixels PXL arranged in a matrix of n rows and m columns. Here, in order to simplify the drawing, a case of a pixel array of 4 rows and 4 columns is shown as an example.
Each of the pixels PXL arranged in a matrix form a thin film transistor (TFT) 11 that is a pixel transistor, a liquid crystal cell LC in which the pixel electrode is connected to the drain electrode of the TFT 11, and one side to the drain electrode of the TFT 11. And a storage capacitor Cs to which the electrodes are connected.
For each of these pixels PXL, signal lines SGNL1 to SGNL4 are wired along the pixel arrangement direction for each column, and gate lines GTL1 to GTL4 are wired along the pixel arrangement direction for each row.
In each pixel PXL, the source electrode (or drain electrode) of the TFT 11 is connected to the corresponding signal line SGNL1 to SGNL4. The gate electrode of the TFT 11 is connected to each of the gate lines GTL1 to GTL4. The counter electrode of the liquid crystal cell LC and the other electrode of the storage capacitor Cs are connected to the Cs line CsL1 in common between the pixels. A predetermined DC voltage is applied as a common voltage Vcom to the Cs line Cs L1.
In the pixel unit 11, one end of each of the gate lines GTL <b> 1 to GTL <b> 4 is connected to an output end of each row of the vertical scanner 12 disposed on the left side of the pixel unit 11 in the drawing, for example.
[0006]
The vertical scanner 12 performs a process of sequentially selecting each pixel PXL connected to the gate lines GTL1 to GTL4 in units of rows by scanning in the vertical direction (row direction) every field period.
That is, when the scanning pulse SP1 is applied from the vertical scanner 12 to the gate line GTL1, the pixels in each column of the first row are selected, and when the scanning pulse SP2 is applied to the gate line GTL2, the second row. A pixel in each column is selected. Similarly, scan pulses SP3 and SP4 are sequentially applied to the gate lines GTL3 and GTL4.
[0007]
For example, a horizontal scanner 13 is disposed above the pixel unit 11 in the drawing.
The horizontal scanner 13 sequentially samples the input video signal VDO every 1H (H is a horizontal scanning period), and performs processing of writing to each pixel PXL selected in units of rows by the vertical scanner 12.
As shown in FIG. 1, the horizontal scanner 13 employs a clock drive system, and includes a shift register 131, a clock extraction switch group 132, a phase adjustment circuit (PAC) group 133, and a sampling switch group 134. Have.
[0008]
The shift register 131 includes four shift stages (S / R stages) 131-1 to 131-4 corresponding to the pixel columns (four columns in this example) of the pixel unit 11, and includes a first clock generation circuit. When the horizontal start pulse HST is given by 14, the shift operation is performed in synchronization with the horizontal clocks HCK and HCKX having opposite phases. Thus, shift pulses SFTP1 to SFTP4 having the same pulse width as the cycles of the horizontal clocks HCK and HCKX are sequentially output from the shift stages 131-1 to 131-4 of the shift register 131.
[0009]
The clock extraction switch group 132 includes four switches 132-1 to 132-4 corresponding to the pixel columns of the pixel unit 11, and one end of each of the switches 132-1 to 132-4 is a first clock generator. The circuit 15 is alternately connected to clock lines DKL1 and DKXL1 for transmitting clocks DCKX and DCK.
That is, one end of each of the switches 132-1 and 132-3 is connected to the clock line DKXL1, and one end of each of the switches 132-2 and 132-4 is connected to the clock line DKL1.
Shift pulses SFTP1 to SFTP4 sequentially output from the shift stages 131-1 to 131-4 of the shift register 131 are applied to the switches 132-1 to 132-4 of the clock extraction switch group 132, respectively. When the shift pulses SFTP1 to SFTP4 are given from the shift stages 131-1 to 131-4 of the shift register 131, the switches 132-1 to 132-4 of the clock extraction switch group 132 respond to the shift pulses SFTP1 to SFTP4. The second clocks DCKX and DCK having opposite phases are alternately extracted by sequentially turning on.
[0010]
The phase adjustment circuit group 133 includes four phase adjustment circuits 133-1 to 133-4 corresponding to the pixel columns of the pixel unit 11, and each of the phase adjustment circuits 133-1 to 133-4 has a clock extraction switch group 132. After the phases of the second clocks DCKX and DCK extracted by the respective switches 132-1 to 132-4 are adjusted, they are supplied to the sampling switches of the corresponding sampling switch group 134.
[0011]
The sampling switch group 134 includes four sampling switches 134-1 to 134-4 corresponding to the pixel columns of the pixel unit 11, and one end of each of the sampling switches 134-1 to 134-4 receives the video signal VDO. It is connected to the input video line VDL1. The sampling switches 134-1 to 134-4 receive the clocks DCKX and DCK extracted by the switches 132-1 to 132-4 of the clock extraction switch group 132 and phase-adjusted by the phase adjustment circuit group 133 as sample hold pulses. Given as SHP1 to SHP4.
When the sample hold pulses SHP1 to SHP4 are given, the sampling switches 134-1 to 134-4 of the sampling switch group 134 are sequentially turned on in response to the sample hold pulses SHP1 to SHP4, whereby the video line VDL1. The video signal VDO input through the signal is sequentially sampled and supplied to the signal lines SGNL1 to SGNL4 of the pixel unit 11.
[0012]
  The first clock generation circuit14, A vertical start pulse VST for instructing the start of vertical scanning, vertical clocks VCK and VCKX having opposite phases as a reference for vertical scanning, and a command for starting the horizontal scanningHorizontalStart pulseHST, Generating horizontal clocks HCK and HCKX having opposite phases as horizontal scanning references, supplying a vertical start pulse VST and vertical clocks VCK and VCKX to the vertical scanner 12, and supplying the horizontal clocks HCK and HCKX to the horizontal scanner 13 and 2 is supplied to the second clock generation circuit 15.
[0013]
The second clock generation circuit 15 has the same period (T1 = T2) as the horizontal clocks (first clocks) HCK and HCKX generated by the first clock generation circuit 14 and has a small duty ratio and are opposite to each other. Phase second clocks DCK and DCKX are generated and supplied to the horizontal scanner 13. Here, the duty ratio is a ratio between the pulse width t and the pulse repetition period T in the pulse waveform.
For example, as shown in FIGS. 3A to 3D, the duty ratio (t1 / T1) of the horizontal clocks HCK and HCKX is 50%, and the duty ratio of the clocks DCK and DCKX (t2 / T2) is higher than this. Is smaller, that is, the pulse width t2 of the clocks DCK and DCKX is set narrower than the pulse width t1 of the horizontal clocks HCK and HCKX.
[0014]
In the horizontal scanner 13 described above, the shift pulses SFTP1 to SFTP4 sequentially output from the shift register 131 are not used as sample hold pulses, but clocks DCKX and DCK having opposite phases are alternately synchronized with the shift pulses SFTP1 to SFTP4. These clocks DCKX and DCK are used as sample hold pulses SHP1 to SHP via a phase adjustment circuit. Thereby, the dispersion | variation in the sample hold pulses SHP1-SHP can be suppressed. As a result, it is possible to remove ghosts caused by variations in the sample hold pulses SHP1 to SHP.
[0015]
In addition, the horizontal scanner 13 does not extract the horizontal clocks HCKX and HCK, which are the reference for the shift operation of the shift register 131, and use them as sample hold pulses, but has the same cycle and duty ratio as the horizontal clocks HCKX and HCK. Since small clocks DCKX and DCK are separately generated, and these clocks DCKX and DCK are extracted and used as sample hold pulses SHP1 to SHP, complete non-overlapping sampling between sampling pulses is performed during horizontal driving. Since this can be realized, it is possible to suppress the occurrence of vertical stripes due to overlap sampling.
[0016]
Here, for example, as shown in FIG. 4, the operation when the video signal VDO is written to the corresponding pixel at the Nth and N + 1th stages adjacent to each other will be described with reference to FIGS. To do.
In this case, for example, the video signal VDO, the drive signal DRVP-N of the N-th stage signal line SGNL-N, and the drive pulse DRVP-N + 1 of the (N + 1) -th stage signal line SGNL-N + 1 are shown in FIGS. In the case of the timing relationship shown in FIG. 5C, ideally, a white signal is written in the Nth stage and a black signal is written in the N + 1th stage, and there is no ghost as shown in FIG. An image is obtained.
[0017]
However, in LCDs using TFTs, transistor characteristics generally change due to panel aging. Due to this characteristic change, a pulse delay occurs in each transistor, and eventually the sample hold pulse SHP drifts with respect to its initial state.
Due to this drift, the optimum sample hold position with respect to the ghost shifts, and if the sample hold position set value at the time of initial shipment is maintained, the video signal at the adjacent stage is sampled and held, and a ghost is generated.
Specifically, as shown in FIGS. 6A to 6C, the drive signal DRVP-N of the Nth signal line SGNL-N and the drive pulse DRVP− of the N + 1th signal line SGNL-N + 1. N + 1 is delayed as indicated by the solid line after aging from the initial state indicated by the broken line. As a result, as shown in FIG. 6D, a black signal is written in the Nth stage, and a ghost GST occurs.
[0018]
In order to prevent the occurrence of ghost due to drift, a monitor circuit (dummy scanner) is arranged, the output of the sampling switch is output to the outside of the panel, and the change in phase from the initial state of the output is monitored by an external IC However, a countermeasure for feeding back the phase change to the panel input clock has become common (see, for example, Patent Document 2 or Patent Document 3).
[0019]
FIG. 7 is a block diagram showing a configuration example of a conventional liquid crystal display device provided with a monitor circuit 17. FIG. 8 is a circuit diagram showing a specific configuration example of a part of the monitor circuit 17 and the peripheral horizontal scanner 13 of FIG.
[0020]
The monitor circuit 17 in FIG. 8 is arranged adjacent to the first stage of the horizontal scanner 13, that is, the stage where the horizontal start pulse HST is first input and the shift operation is started.
The monitor circuit 17 is ideally configured in the same manner as the configuration of each stage of the horizontal scanner 13 in order to align the delay amount of the output pulse of each stage of the horizontal scanner 13.
The monitor circuit 17 in FIG. 8 receives a horizontal start pulse HST, outputs a shift pulse SFTP17, a shift stage (S / R stage) 171, and a switch 172 that extracts the second clock DCKX by the shift pulse SFTP17 generated by the shift stage 171. A phase adjustment circuit 173 that generates a sample hold pulse SHP17 composed of two signals that take a complementary level by adjusting the phase of the clock DCLX extracted by the switch 171, and a first sample hold pulse SHP17 by the phase adjustment circuit 173. A sampling switch 174 whose conduction is controlled between the terminal and the second terminal is provided.
[0021]
The sampling switch 174 of the monitor circuit 17 has a first terminal grounded and the other end connected to one end of the monitor line MNTL1. The other end of the monitor line MNTL1 is connected to a feedback IC 18 outside the LCD panel.
The monitor line MNTL1 is pulled up outside the panel, and the external feedback IC 18 monitors the phase change from the initial state from the timing when the sampling switch 173 is turned on and the monitor line MNTL1 transitions to the ground level. The amount of phase change is fed back to the panel input clock.
In the example of FIG. 8, the horizontal clocks HCKX, HCK and the like are configured to be generated by an external feedback IC 18.
[0022]
[Patent Document 1]
Japanese Patent Application No. 2001-109460
[Patent Document 2]
Japanese Patent Laid-Open No. 11-119746
[Patent Document 3]
JP 2000-298459 A
[0023]
[Problems to be solved by the invention]
By the way, the active matrix type liquid crystal display device adopting the above-described dot sequential driving method is used as a display panel of a projection type liquid crystal display device (liquid crystal projector), that is, an LCD panel. In the case of color, three LCD panels are arranged corresponding to each of the three primary colors R (red), G (green), and B (blue).
In this case, due to the relationship between the optical system and the optical path, it is necessary to reverse one LCD panel with the other LCD panel and perform reverse scanning in the horizontal scanner.
For this reason, the LCD panel is configured to have a function of scanning from the right side in the drawing, that is, a reverse scanning function in addition to the function of scanning from the left side in the drawing of FIG.
[0024]
However, in a circuit in which one conventional monitor circuit (dummy scanner) is arranged, in a horizontal scanner in which the phase of the clock is inverted by left-right inversion, the number of shift registers provided in the horizontal scanner 13 is generally an even number. Therefore, there are the following disadvantages.
[0025]
As shown in FIGS. 9A to 9K, when scanning from left to right, for example, as shown in FIG. 9B, pulses (1), (2), (3) of the horizontal clock HCK. The first sample hold pulse SHP1 of the horizontal scanner 13 and the sample of the monitor circuit 17 at the second timing {circle over (2)} of the horizontal clock HCK and at the timing of the second clock DCKX. The hold pulse SHP17 is generated at substantially the same timing, and image display is performed without any problem.
[0026]
On the other hand, as shown in FIGS. 10A to 10K, when scanning from right to left, for example, as shown in FIG. 10B, pulses (1) and (2) of the horizontal clock HCK. When the symbols ▼ and (3) are attached, the sample hold pulse SHP17 of the monitor circuit 17 is generated at the first timing (1) of the horizontal clock HCK and at the timing of the second clock DCKX. SHP1 is generated at timing (2) and at the timing of the first clock DCK.
That is, in this case, the phase of the sample hold pulse SHP17 for feedback is changed by one pulse due to left-right inversion, and accurate feedback cannot be performed. In such a case, the image is shifted by half, and a highly accurate image table cannot be performed.
[0027]
The object of the present invention is that even in a horizontal scanner that can invert the scan direction and in which the phase of the clock is inverted in the scan direction inversion, the phase of the output potential change does not change, and the accuracy does not change even if operated in any scan direction An object of the present invention is to provide a display device and a projection display device that can realize high image display.
[0028]
[Means for Solving the Problems]
In order to achieve the above object, a display device according to a first aspect of the present invention includes a pixel portion in which a plurality of pixels are arranged in a matrix and signal lines are wired for each pixel column, and is held at a first potential. A first clock signal and a first inverted clock signal which are at least opposite to each other as a reference for horizontal scanning, and monitor the potential change of the monitor line, and the timing of the potential change A control circuit that corrects at least the generation timing of the clock signal and the inverted clock signal based on the change of the first clock signal, and the first clock signal based on the first clock signal and the first inverted clock signal generated by the control circuit. The second clock signal and the second inverted clock signal having the same period and a small duty ratio with respect to the clock signal and the first inverted clock signal A first scan operation in which a plurality of shift stages are connected in cascade, and a shift is sequentially performed from the first stage to the last stage in accordance with a switching signal. And the second scan operation that shifts in order from the last stage to the first stage can be switched. During the first scan operation or the second scan operation, the shift pulse is sequentially transmitted from each shift stage in synchronization with the clock signal and the inverted clock signal. In response to the shift pulse output from the shift register to be output and the shift stage corresponding to the shift register, the second clock signal and the second inverted clock signal are alternately extracted sequentially and output as a sample hold pulse. The sample switch by each switch of the first switch group and the first switch group of the video signal. And a second switch group that sequentially samples in response to the pulse and supplies the signal lines to the corresponding signal lines of the pixel portion. The monitor circuit receives the switching signal, and the switching signal is the first switching signal. When a scan operation is instructed, a signal having a phase different from that extracted from the first shift stage of the shift register in the horizontal scanner is extracted from the first clock signal and the first inverted clock signal. When a two-scan operation is instructed, a signal having a phase different from that of the signal extracted by the last shift stage of the shift register in the horizontal scanner is extracted from the first clock signal and the first inverted clock signal. A selector unit that outputs as a hold pulse, and the mode in response to the sample hold pulse by the selector unit. And a third switch for setting the potential of the nita line to the second potential.
[0029]
A projection display device according to a second aspect of the present invention generates a monitor line held at a first potential, a clock signal and an inverted clock signal that are at least opposite to each other as a reference for horizontal scanning, and A control circuit that monitors the potential change of the monitor line and corrects at least the generation timing of the clock signal and the inverted clock signal based on the change in timing of the potential change, and the first clock signal generated by the control circuit Based on the first inverted clock signal and the first inverted clock signal, the second clock signal and the second inverted clock signal having the same period and a small duty ratio with respect to the first clock signal and the first inverted clock signal are generated. A clock generation means, a pixel portion in which a plurality of pixels are arranged in a matrix, and a signal line is wired for each pixel column; A display panel including at least a flat scanner and a monitor circuit; irradiation means for irradiating the display panel with light; and projection means for projecting light that has passed through the display panel onto a screen. The horizontal scanner has a plurality of shift stages connected in cascade, and can switch between a first scan operation for sequentially shifting from the first stage to the last stage and a second scan operation for sequentially shifting from the last stage to the first stage according to the switching signal. The shift register that sequentially outputs shift pulses from each shift stage in synchronization with the clock signal and the inverted clock signal during the one-scan operation or the second scan operation, and the shift that is output from the corresponding shift stage of the shift register In response to the pulse, the second clock signal and the second inverted clock signal are alternately extracted sequentially. A first switch group that outputs as a field pulse; and a second switch that sequentially samples the video signal in response to a sample-and-hold pulse by each switch of the first switch group and supplies the video signal to each corresponding signal line of the pixel portion. A switch group, and the monitor circuit of the display panel receives the switching signal, and when the switching signal indicates the first scan operation, the first clock signal and the first In the inverted clock signal, when a signal having a phase different from that extracted by the first shift stage of the shift register in the horizontal scanner is extracted and the second scan operation is instructed, the first clock signal and the first clock signal are output. Signal whose phase is different from the signal extracted by the last shift stage of the shift register in the horizontal scanner And a third switch that sets the potential of the monitor line to the second potential in response to the sample-and-hold pulse from the selector unit.
[0030]
Preferably, the selector unit receives the select pulse and extracts the clock signal, and outputs the sample switch as a sample hold pulse to the third switch, and receives the select pulse and extracts the inverted clock signal. In response to the fifth switch output to the third switch as the sample hold pulse and the switching signal, and the switching signal indicates the first scan operation, the select pulse is transmitted to the third switch. And a selector for outputting the select pulse to the fifth switch when the second scan operation is instructed.
[0031]
Preferably, the first scan operation and the second scan operation are started in response to a horizontal start pulse, and the horizontal start pulse is sent to the first stage shift stage of the shift register and the monitor circuit during the first scan operation. Is supplied to the last shift stage of the shift register and the monitor circuit during the second scan operation, and the selector of the monitor circuit uses the horizontal start pulse as the select pulse in response to the switching signal. Supply switch or fifth switch.
[0032]
Preferably, the selector transfers the horizontal start pulse as the select pulse to the fourth switch, and transfers the horizontal start pulse as the select pulse to the fifth switch. A first select switch that connects the first transfer line to the horizontal start pulse supply line when the switching signal indicates the first scan operation; A second select switch for connecting the second transfer line to the horizontal start pulse supply line; and a horizontal start pulse supply line when the switching signal indicates the second scan operation. The first transfer line or the second transfer line in the disconnected state is connected to the first transfer line or the second transfer line. And a potential setting means for holding the fourth switch or the fifth switch-in is connected to a potential capable of retaining the non-conductive state.
[0033]
The number of shift stages in the shift register of the horizontal scanner is an even number.
[0034]
The display element of the pixel is a liquid crystal cell.
[0035]
According to the present invention, for example, in a control circuit, generation of a clock signal and an inverted clock signal that are opposite in phase to each other as a reference for horizontal scanning is generated and supplied to a horizontal scanner and a monitor circuit.
Further, for example, the first scan operation or the second scan operation for scanning in the direction opposite to the first scan operation is designated by the switching signal.
When the first scan operation is designated, for example, a horizontal start pulse is supplied to the first stage shift stage in the monitor circuit and the shift register of the horizontal scanner.
A switching signal is input to the monitor circuit. At this time, since the switching signal instructs the first scan operation, the supplied horizontal start pulse is output to the fourth switch as a select pulse in the selector unit. In the fourth switch, the first clock signal or the first inverted clock signal whose phase is different from that of the second clock signal or the second inverted clock signal to be extracted by the first shift stage of the horizontal scanner is extracted, and the sample hold pulse is extracted. Is output to the third switch.
In the third switch, the potential of the monitor line is set from the first potential to the second potential (for example, ground potential) in response to the sample hold pulse by the fourth switch of the selector unit.
In the horizontal scanner, a shift pulse is sequentially output from each shift stage to each corresponding switch of the first switch group in synchronization with the first clock signal and the first inverted clock signal.
In the first switch group, the second clock signal and the second inverted clock signal are alternately and sequentially extracted in response to the shift pulse output from the corresponding shift stage. Then, the extracted signal is output as a sample hold pulse to each corresponding switch of the second switch group.
In the second switch group, the input video signals are sequentially sampled in response to sample and hold pulses by the respective switches of the first switch group, and are supplied to the corresponding signal lines of the pixel portion.
In the control circuit, the potential change of the monitor line is monitored. Specifically, the control circuit monitors a change in phase from the initial state of the output of the monitor circuit, and corrects the generation timing of the clock signal and the inverted clock signal so as to cancel out the change in the phase.
Thereby, the drift of the sample hold pulse due to the change in the characteristics of the transistor due to panel aging or the like is corrected.
[0036]
When the second scan operation is designated, for example, a horizontal start pulse is supplied to the final shift stage in the monitor circuit and the shift register of the horizontal scanner.
A switching signal is input to the monitor circuit. At this time, since the switching signal instructs the second scan operation, the supplied horizontal start pulse is output to the fifth switch as a select pulse in the selector unit. In the fifth switch, the first clock signal or the first inverted clock signal whose phase is different from that of the second clock signal or the second inverted clock signal to be extracted by the final shift stage of the horizontal scanner is extracted, and the sample hold pulse is extracted. Is output to the third switch.
In the third switch, the potential of the monitor line is set from the first potential to the second potential (for example, ground potential) in response to the sample hold pulse by the fifth switch of the selector unit.
In the horizontal scanner, a shift pulse is sequentially output from each shift stage to each corresponding switch of the first switch group in synchronization with the first clock signal and the first inverted clock signal.
In the first switch group, the second clock signal and the second inverted clock signal are alternately and sequentially extracted in response to the shift pulse output from the corresponding shift stage. Then, the extracted signal is output as a sample hold pulse to each corresponding switch of the second switch group.
In the second switch group, the input video signals are sequentially sampled in response to sample and hold pulses by the respective switches of the first switch group, and are supplied to the corresponding signal lines of the pixel portion.
In the control circuit, the potential change of the monitor line is monitored. Specifically, in the control circuit, the change in phase from the initial state of the output of the monitor circuit is monitored, and the generation timing of the first clock signal and the first inverted clock signal so as to cancel the change in the phase. Is corrected.
Thereby, the drift of the sample hold pulse due to the change in the transistor characteristics due to panel aging or the like is accurately corrected.
As described above, even in a horizontal scanner in which the clock phase is inverted in the scan direction inversion, the phase of the output potential change does not change, and a high-precision image display is realized regardless of the scan direction. Further, it is possible to obtain a sample hold pulse in which the ghost margin increases with aging.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0038]
FIG. 11 is a circuit diagram showing a configuration example of a dot sequential drive type active matrix liquid crystal display device according to an embodiment of the present invention using, for example, a liquid crystal cell as a pixel display element (electro-optical element).
[0039]
As shown in FIG. 11, the liquid crystal display device 20 includes an effective pixel portion (PXLP) 21, a vertical scanner (VSCN) 22, a horizontal scanner (HSCN) 23, a monitor circuit (MNT) 24, and a clock generation circuit (GEN) 25. , And a feedback control circuit (FDBCIC) 26 including a timing generator as a main component.
As shown in FIG. 12, the vertical scanner may be arranged not only on one side (left side in the figure) of the pixel unit 21 but also on both sides (left side and right side in the figure). In addition, a signal line precharge circuit (PRCG) 28 is provided.
The effective pixel portion (PXLP) 21, vertical scanner (VSCN) 22 (22-1 and 22-2), horizontal scanner (HSCN) 23, monitor circuit 24, clock generation circuit (GEN) 25 (and precharge circuit 26). ) Is mounted on the display panel (LCD panel) 30.
[0040]
The function of the clock generation circuit 25 is also provided in the feedback control circuit 26, and a circuit having level conversion and buffer functions is provided in place of the clock generation circuit 25, and the first clock signal and the first inversion are provided via this circuit. The horizontal clocks HCK and HCKX and the second clock signal are supplied to the horizontal scanner 23 and the monitor circuit 24 as clock signals, and the horizontal clocks DCK and DCKX are supplied to the horizontal scanner 23 as the second inverted clock signal. It is also possible to configure.
[0041]
In the pixel unit 21, a plurality of pixels PXL are arranged in a matrix of n rows and m columns. Here, in order to simplify the drawing, a case of a pixel array of 4 rows and 4 columns is shown as an example.
Each of the pixels PXL arranged in a matrix form a thin film transistor (TFT) 21 that is a pixel transistor, a liquid crystal cell LC 21 having a pixel electrode connected to the drain electrode of the TFT 21, and a drain electrode of the TFT 21. And a storage capacitor Cs 21 to which the electrodes are connected.
For each of these pixels PXL, signal lines SGNL21 to SGNL24 are wired along the pixel arrangement direction for each column, and gate lines GTL21 to GTL24 are wired along the pixel arrangement direction for each row.
In each pixel PXL, the source electrode (or drain electrode) of the TFT 21 is connected to the corresponding signal lines SGNL21 to SGNL24. The gate electrode of the TFT 21 is connected to each of the gate lines GTL21 to GTL24. The counter electrode of the liquid crystal cell LC21 and the other electrode of the storage capacitor Cs21 are connected to the Cs line CsL21 in common among the pixels. A predetermined DC voltage is applied as a common voltage Vcom to the Cs line Cs L21.
In the pixel unit 21, one end of each of the gate lines GTL <b> 21 to GTL <b> 24 is connected to the output end of each row of the vertical scanner 22 disposed on the left side of the pixel unit 21 in the drawing, for example.
[0042]
The vertical scanner 22 performs a process of sequentially selecting each pixel PXL connected to the gate lines GTL21 to GTL24 in units of rows by scanning in the vertical direction (row direction) every field period.
That is, when the scanning pulse SP21 is applied from the vertical scanner 22 to the gate line GTL21, the pixel PXL in each column of the first row is selected, and when the scanning pulse SP22 is applied to the gate line GTL22, the second row. The pixels PXL in each column are selected. Similarly, scanning pulses SP23 and SP24 are sequentially applied to the gate lines GTL23 and GTL24.
[0043]
For example, a horizontal scanner 23 and a monitor circuit (dummy scanner) 24 are arranged above the pixel unit 21 in the drawing.
[0044]
The horizontal scanner 23 sequentially samples the input video signal VDO every 1H (H is a horizontal scanning period), and performs processing of writing to each pixel PXL selected in units of rows by the vertical scanner 22.
As shown in FIG. 11, the horizontal scanner 23 employs a clock drive system, and includes a shift register 231, a clock extraction switch group 232, a phase adjustment circuit (PAC) group 233, and a sampling switch group 234. Have.
[0045]
The shift register 231 includes four shift stages (S / R stages) 231-1 to 231-4 corresponding to the pixel columns (four columns in this example) of the pixel unit 21, for example, an external feedback control circuit 26, when the horizontal start pulse HST is applied to the first (first stage) shift stage 231-1 or the fourth (final) shift stage 231-4, the horizontal clock HCK and the inverted horizontal clock HCKX (hereinafter, both of which are opposite to each other). The first shift operation (normal shift operation) or the second shift operation (reverse shift operation) is performed in synchronization with the horizontal clock.
Thus, shift pulses SFTP231 to SFTP234 having the same pulse width as the cycles of the horizontal clocks HCK and HCKX are sequentially output from the shift stages 231-1 to 231-4 of the shift register 231.
[0046]
Here, the normal shift operation is from left to right in FIG. 11, that is, the first shift stage 231-1, the second shift stage 231-2, the third shift stage 231-3, and the fourth shift stage in the first stage. Scanning in the order of 231-4.
On the other hand, the reverse shift operation is the right to left direction in FIG. 11, that is, the fourth shift stage 231-4, the third shift stage 231-3, the second shift stage 231-2, and the first shift stage 231-1. Scanning in this order.
[0047]
The normal shift operation and the reverse shift operation are determined by a shift direction switching signal RGT given from the outside.
For example, the shift register 231 of the horizontal scanner 23 performs a normal shift operation when receiving the shift direction switching signal RGT at a high level, and performs a reverse shift operation when receiving it at a low level.
[0048]
The shift register 231 receives the horizontal start pulse HST and propagates the shift pulse SFTP in the normal direction from the first shift stage 231-1 to the fourth shift stage 231-4, or from the fourth shift stage 231-4 to the first. Switching circuits 2311, 2312 and 2313 for switching whether to propagate in the reverse direction toward the shift stage 231-1 are inserted between the shift stages.
Specifically, a switching circuit 2311 is inserted between the first shift stage 231-1 and the second shift stage 231-2, and a switching circuit 2312 is inserted between the second shift stage 231-2 and the third shift stage 231-3. The switching circuit 2313 is inserted between the third shift stage 231-3 and the fourth shift stage 231-4.
Each of the switching circuits 2311 to 2313 receives the shift direction switching signal RGT and switches the signal propagation direction to the normal direction or the reverse direction.
[0049]
FIG. 13 is a circuit diagram illustrating a configuration example of the switching circuit 2311 (˜2313) inserted between the shift stages of the shift register. In FIG. 13, the switching circuit 2311 inserted between the first shift stage 231-1 and the second shift stage 131-2 is shown as an example, but the other switching circuits 3212 and 2313 have the same configuration. is doing.
[0050]
As shown in FIG. 13, the switching circuit 2311 has transfer gates TM231-1, TM231-2 and an inverter INV231.
The transfer gate TMG231-1 has a first terminal T1 and a second terminal T2 that connect the sources and drains of a p-channel MOS (PMOS) transistor PT231-1 and an n-channel MOS (NMOS) transistor NT231-1. Yes.
The gate of the NMOS transistor NT231-1 is connected to the supply line of the switching signal RGT, and the gate of the PMOS transistor PT231-1 is connected to the output terminal of the inverter INV231 that outputs the signal RGTX obtained by inverting the level of the switching signal RGT. The first terminal T1 is connected to the output terminal O1 of the first shift stage (left shift stage) 231-1, and the second terminal T2 is connected to the input terminal I1 of the second shift stage (right shift stage) 231-2. Has been.
[0051]
The transfer gate TMG231-2 connects the sources and drains of the PMOS transistor PT231-2 and NMOS transistor NT231-2 to form a first terminal T1 and a second terminal T2.
The gate of the PMOS transistor PT231-2 is connected to the supply line of the switching signal RGT, and the gate of the NMOS transistor NT231-2 is connected to the output terminal of the inverter INV231 that outputs the signal RGTX obtained by inverting the level of the switching signal RGT. The first terminal T1 is connected to the input terminal I1 of the first shift stage (left shift stage) 231-1, and the second terminal T2 is connected to the output terminal O1 of the second shift stage (right shift stage) 231-2. Has been.
[0052]
In the switching circuit 2311 having such a configuration, for example, when the switching signal RGT is supplied at a high level, the output signal RGTX of the inverter INV231 becomes a low level, and the PMOS transistor PT231-1 and the NMOS transistor NT231 of the transfer gate TMG231-1 -1 conducts.
On the other hand, the PMOS transistor PT231-2 and the NMOS transistor NT231-2 of the transfer gate TMG231-2 are held in a non-conductive state.
Therefore, the signal (horizontal start pulse HST) output from the output terminal O1 of the first shift stage 231-1 is propagated to the input terminal I1 of the second shift stage 231-2 through the transfer gate TMG231-1. That is, a normal shift operation is performed.
[0053]
On the other hand, when the switching signal RGT is supplied at a low level, the output signal RGTX of the inverter INV231 becomes a high level, and the PMOS transistor PT231-1 and the NMOS transistor NT231-1 of the transfer gate TMG231-1 become non-conductive. Retained.
On the other hand, the PMOS transistor PT231-2 and the NMOS transistor NT231-2 of the transfer gate TMG231-2 become conductive.
Therefore, the signal (horizontal start pulse HST) output from the output terminal O1 of the second shift stage 231-2 is propagated to the input terminal I1 of the first shift stage 231-1 through the transfer gate TMG231-2. That is, a reverse shift operation is performed.
[0054]
In the configuration of FIG. 13, the inverter INV231 is provided in each switching circuit. However, an inverter is provided in the input stage of the switching signal RGT, and the inverted output signal RGTX is supplied to each switching circuit together with the switching signal RGT. It is also possible to configure as described above.
[0055]
The clock extraction switch group 232 includes four switches 232-1 to 232-4 corresponding to the pixel columns of the pixel unit 21, and one end of each of the switches 232-1 to 232-4 is formed by the clock generation circuit 25. The clock lines DKL1 and DKXL1 that transmit the second clock DCK and the second inverted clock DCKX are alternately connected.
That is, one end of each of the switches 232-1 and 232-3 corresponding to the odd columns of the pixel columns of the pixel unit 21 is connected to the clock line DKXL21, and the switches 232-2 and 232 corresponding to the even columns of the pixel columns of the pixel unit 21 are connected. Each end of 4 is connected to the clock line DKL21.
Shift pulses SFTP231 to SFTP234 that are sequentially output from the shift stages 231-1 to 231-4 of the shift register 231 are applied to the switches 232-1 to 232-4 of the clock extraction switch group 232, respectively.
The switches 232-1 to 232-4 of the clock extraction switch group 232 respond to the shift pulses SFT23P1 to SFTP234 when the shift pulses SFTP231 to SFTP234 are given from the shift stages 231-1 to 231-4 of the shift register 231. Then, the clocks DCKX and DCK having opposite phases are alternately extracted by sequentially turning on.
[0056]
The phase adjustment circuit group 233 includes four phase adjustment circuits 233-1 to 233-4 corresponding to the pixel columns of the pixel unit 21, and each phase adjustment circuit 233-1 to 233-4 has a clock extraction switch group 232. After the phases of the clocks DCKX and DCK extracted by the switches 232-1 to 232-4 are adjusted, they are supplied to the sampling switches of the corresponding sampling switch group 234.
[0057]
The sampling switch group 234 has four sampling switches 234-1 to 234-4 corresponding to the pixel columns of the pixel unit 21, and one end of each of these sampling switches 234-1 to 234-4 receives the video signal VDO. It is connected to an input video line VDL21.
The sampling switches 234-1 to 234-4 receive the clocks DCKX and DCK extracted by the switches 232-1 to 232-4 of the clock extraction switch group 232 and phase-adjusted by the phase adjustment circuit group 233 as sample hold pulses. It is given as SHP231 to SHP234.
When the sample hold pulses SHP231 to SHP234 are given, the sampling switches 234-1 to 234-4 of the sampling switch group 234 are sequentially turned on in response to the sample hold pulses SHP231 to SHP234, whereby the video line VDL21. Are sequentially sampled and supplied to the signal lines SGNL21 to SGNL24 of the pixel unit 21.
[0058]
The monitor circuit 24 corresponds to the first pixel column of the pixel unit 21 of the horizontal scanner 23, that is, the first shift stage 231 that starts the first shift operation (normal shift operation) when the horizontal start pulse HST is input first. -1, the extraction switch 232-1, the phase adjustment circuit 233-1, and the sampling switch 234-1 are arranged adjacent to the left side in FIG.
The monitor circuit 24 adjusts the output pulse delay amount of each stage of the horizontal scanner 23, the extraction switch 232-1 of each stage scanner section of the horizontal scanner 23, the phase adjustment circuit 233-1, and the sampling switch 234-1. It is comprised similarly to the structure containing.
[0059]
Specifically, the monitor circuit 24 receives the horizontal start pulse HST and the switching signal RGT, and when the switching signal RGT instructs the first scan operation, the monitor circuit 24 uses the horizontal start pulse HST as the select pulse and outputs the first Of the horizontal clocks HCK and HCKX as the clock signal and the first inverted clock signal, a clock HCK having a phase different from that of the clock DCKX extracted by the first stage shift stage 231-1 of the shift register 231 in the horizontal scanner 23 is extracted and the second scan operation is performed. Is selected, the horizontal clock HCKX having a phase different from that of the clock DCK signal extracted by the final shift stage 231-4 of the shift register 231 in the horizontal scanner 23 out of the clocks DCK and DCKX using the horizontal start pulse HST as a select pulse. Extract The selector unit 241 that outputs the sample hold pulse, and the phase adjustment circuit 242 that generates the sample hold pulse SHP 241 composed of two signals that take the complementary levels by adjusting the phase of the horizontal clock HCK or HCKX extracted by the selector unit 241. And a sampling switch (third switch) 243 whose conduction is controlled between the first terminal T1 and the second terminal T2 by the sample hold pulse SHP241 by the phase adjustment circuit 242.
[0060]
The sampling switch 243 of the monitor circuit 24 is an analog switch in which the sources and drains of the PMOS transistor and the NMOS transistor are connected to each other, the first terminal T1 is grounded, and the other end is connected to one end of the monitor line MNTL21.
The monitor line MNTL21 is pulled up by a pullup resistor R21 outside the LCD panel, and the other end is connected to the input terminal of the feedback control circuit 26 via the buffer BF21.
[0061]
The selector unit 241 of the monitor circuit 24 receives the select pulse SLP 241 and extracts the horizontal clock HCK and outputs it to the phase adjustment circuit 242 (fourth switch) 2411 and receives the SLP 242 and extracts the horizontal clock HCKX to adjust the phase. In response to the switch (fifth switch) 2412 output to the circuit 242 and the horizontal start pulse HST and the switching signal RGT, when the switching signal RGT instructs the first scan operation, the horizontal start pulse HST is selected. A selector 2413 that outputs the pulse SLP 241 to the switch 2411 and outputs the horizontal start pulse HST to the switch 2412 as the select pulse SLP 242 when the switching signal RGT instructs the second scan operation.
[0062]
FIG. 14 is a circuit diagram illustrating a specific configuration example of the selector unit of the monitor circuit according to the present embodiment.
[0063]
As shown in FIG. 14, the selector 2413 includes select switches SW241 and SW242, NMOS transistors NT241 and NT242, inverters INV241 to INV246, an input terminal THST for a horizontal start pulse HST, an input terminal TRGT for a switching signal RGT, and a switching signal RGT. It has an input terminal TRGTX for the inverted signal RGTX.
In the configuration of FIG. 14, the switching signal RGT and the inverted signal RGTX of the switching signal RGT are input from the outside. However, only the switching signal RGT is input from the outside, and the switching signal RGT of the switching signal RGT is input via the inverter. It is also possible to configure so that the inverted signal RGTX is generated inside the selector 2413.
[0064]
The select switch SW241 has a first terminal T1 and a second terminal T2 that connect the sources and drains of the NMOS transistor NT2411 and the PMOS transistor PT2411.
The select switch SW242 has a first terminal T1 and a second terminal T2 that connect the sources and drains of the NMOS transistor NT2412 and the PMOS transistor PT2412.
Similarly, the switch (fourth switch) 2411 connects the source and drain of the NMOS transistor NT24111 and the PMOS transistor PT24111 to form a first terminal T1 and a second terminal T2.
The switch (fifth switch) 2412 connects the source and drain of the NMOS transistor NT24121 and the PMOS transistor PT24121 to form a first terminal T1 and a second terminal T2.
[0065]
In the select switch SW241, the first terminal T1 is connected to the input terminal THST of the horizontal start pulse HST, the second terminal T2 is connected to the input terminal of the inverter INV241, the source of the NMOS transistor NT241 is connected to the connection node ND241 and the ground GND.・ Drains are connected to each other.
The gate of the NMOS transistor NT2411 of the select switch SW241 is connected to the input terminal TRGT of the switching signal RGT, and the gate of the PMOS transistor PT2411 and the gate of the NMOS transistor NT241 are connected to the input terminal TRGTX of the inverted signal RGTX of the switching signal RGT.
The inverters INV241 to INV243 are connected in series to the node ND241, the output terminal of the inverter INV242 is connected to the gate of the NMOS transistor NT24111 of the switch 2411, and the output terminal of the inverter INV243 is connected to the gate of the PMOS transistor PT24111 of the switch 2411. ing.
The first transfer line TML241 is configured by a signal propagation path from the terminal T2 of the select switch SW241 including the node ND241 to the NMOS transistor 24111 and the NMOS transistor NT24111 of the switch 2411.
Further, the NMOS transistor NT241 can maintain the potential of the first transfer line TML241 in the non-selected state during the second scan operation (reverse scan operation), that is, the potential at which the switch 2411 can stably hold the non-conductive state, that is, the present embodiment. In the embodiment, potential setting means for setting the ground potential is configured.
[0066]
In the select switch SW242, the first terminal T1 is connected to the input terminal THST of the horizontal start pulse HST, the second terminal T2 is connected to the input terminal of the inverter INV244, the source of the NMOS transistor NT242 is connected to the connection node ND242 and the ground GND.・ Drains are connected to each other.
The gate of the PMOS transistor PT2412 of the select switch SW242 is connected to the input terminal TRGT of the switching signal RGT, and the gate of the NMOS transistor PT2421 and the gate of the NMOS transistor NT242 are connected to the input terminal TRGTX of the inverted signal RGTX of the switching signal RGT.
The inverters INV244 to INV246 are connected in series to the node ND242, the output terminal of the inverter INV245 is connected to the gate of the NMOS transistor NT24121 of the switch 2412, and the output terminal of the inverter INV246 is connected to the gate of the PMOS transistor PT24121 of the switch 2412. ing.
The second transfer line TML242 is configured by a signal propagation path from the terminal T2 of the select switch SW242 including the node ND242 to the gates of the NMOS transistor 24121 and the NMOS transistor NT24121 of the switch 2412.
Further, the NMOS transistor NT242 allows the switch 2412 to stably hold the potential of the second transfer line TML242 that is in the non-selected state during the first scan operation (normal scan operation), that is, this embodiment. In the embodiment, potential setting means for setting the ground potential is configured.
[0067]
  In the selector unit 241 having such a configuration, the switching signal RGT is input at the high level and the inverted signal RGTX is input at the low level during the first scan operation. As a result, the select switch SW241 and the NMOS transistor NT242 are turned on, and the select switch SW242 and the NMOS transistor NT241 are turned off.
  Therefore, the horizontal start pulse HST that is high level for a certain period input from the input terminal THST passes through the select switch SW241, is supplied to the NMOS transistor NT24111 of the switch 2411 at high level by the inverter INV242, and is also low level by the inverter INV243. Is supplied to the PMOS transistor NT24111 of the switch 2411.
  As a result, the switch 2411 becomes conductive for a certain period, the horizontal clock HCK is extracted, and the phase is adjusted.circuitIt is output to 242.
  At this time, since the NMOS transistor NT242 is in a conductive state, the potential of the node ND242 is held at the ground level. Accordingly, the inverter INV245 supplies a low level signal to the NMOS transistor NT24121 of the switch 2412, and the inverter INV246 supplies a high level signal to the PMOS transistor NT24121 of the switch 2412. As a result, the switch 2412 is stably held in the non-conductive state.
[0068]
  On the other hand, during the second scan operation, the switching signal RGT is input at a low level and the inverted signal RGTX is input at a high level. As a result, the select switch SW241 and the NMOS transistor NT242 are turned off, and the select switch SW242 and the NMOS transistor NT241 are turned on.
  Therefore, the horizontal start pulse HST that is high level for a certain period input from the input terminal THST passes through the select switch SW242, is supplied to the NMOS transistor NT24121 of the switch 2412 at high level by the inverter INV245, and is also low level by the inverter INV246. Is supplied to the PMOS transistor NT24121 of the switch 2412.
  As a result, the switch 2412 becomes conductive for a certain period, and the horizontal clock DCKX is extracted and the phase is adjusted.circuitIt is output to 242.
  At this time, since the NMOS transistor NT241 is in a conductive state, the potential of the node ND241 is held at the ground level. Accordingly, the inverter INV242 supplies a low level signal to the NMOS transistor NT24111 of the switch 2411, and the inverter INV243 supplies a high level signal to the PMOS transistor NT24111 of the switch 2411. As a result, the switch 2411 is stably held in the non-conductive state.
[0069]
As described above, in the present embodiment, in the monitor circuit 24, the horizontal clock HCK extracted by the extraction switches 2411 and 2412 during the first scan operation (normal scan operation) and the second scan operation (reverse scan operation). , HCKX are set to different clocks. Here, the clock HCK is extracted during the first scan operation, and the horizontal clock HCKX is extracted during the second scan operation.
[0070]
The clock generation circuit 25 is a second clock having the same period (T1 = T2) as the horizontal clocks (first clocks) HCK and HCKX generated by the feedback control circuit 26 and having a low duty ratio and opposite phases. DCK and DCKX are generated and supplied only to the horizontal scanner 23 through the clock lines DKL1 and DKXL1. Here, the duty ratio is a ratio between the pulse width t and the pulse repetition period T in the pulse waveform.
For example, as shown in FIGS. 3A to 3D, the duty ratio (t1 / T1) of the horizontal clocks HCK and HCKX is 50%, and the duty ratio of the clocks DCK and DCKX (t2 / T2) is higher than this. Is smaller, that is, the pulse width t2 of the clocks DCK and DCKX is set narrower than the pulse width t1 of the horizontal clocks HCK and HCKX.
[0071]
  The feedback control circuit 26 commands a vertical start pulse VST for instructing the start of vertical scanning, vertical clocks VCK and VCKX having opposite phases as a reference for vertical scanning, and a command for starting horizontal scanning.HorizontalStart pulseHST, Generating horizontal clocks HCK and HCKX having opposite phases as horizontal scanning references, supplying a vertical start pulse VST and vertical clocks VCK and VCKX to the vertical scanner 22, and supplying the horizontal clocks HCK and HCKX to the horizontal scanner 23 and a monitor. This is supplied to the circuit 24 and the clock generation circuit 25.
  Further, the feedback control circuit 26 generates a horizontal start pulse HST and supplies it to the first shift stage 231-1 and the second shift stage 231-2 of the shift register 231 of the horizontal scanner 23 and the selector 2413 of the monitor circuit 24.
  Further, the feedback control circuit 26 monitors the change in phase from the initial state from the timing when the sampling switch 243 of the monitor circuit 24 is turned on and the monitor line MNTL21 transits to the ground level during the normal scan operation or the reverse scan operation. The phase change is fed back to the panel input horizontal clock HCK and the inverted horizontal clock HCKX, and control is performed to prevent the occurrence of a ghost due to the drift of the sample hold pulse SHP with respect to its initial state.
[0072]
As described above, in the present embodiment, the clock extracted by the monitor circuit 24 is the same in the cycle and the duty ratio of the horizontal clocks HCK and HCKX generated by the clock generation circuit 25 extracted by the horizontal scanner 23. The first clocks HCK and HCKX are used instead of the reverse-phase second clocks DCK and DCKX.
Hereinafter, the reason why the clock extracted by the monitor circuit 24 is not the second clocks DCK and DCKX but the first clocks HCK and HCKX will be described with reference to the drawings.
[0073]
FIG. 15 is a circuit diagram of an output portion of a general drift correction circuit including the monitor circuit 17 of FIG. 8 in which the second clocks DCK and DCKX are extracted.
In FIG. 15, in the monitor circuit 24, the shift stage R22 indicates the wiring resistance, and C21 indicates the wiring capacitance.
[0074]
The resistance R21 of the pull-up portion is sufficient compared to the internal resistance of the panel so that almost no through current flows through the pull-up power supply when the sampling switch (HSW) 174 is turned on and the output is set to the ground level GND. It needs to be set aside.
For this reason, as shown in FIGS. 16A and 16B, the transient at the time of pull-up becomes gentle and pull-down is fast, but pull-up takes time.
If this output potential change is not steep, a delay difference will occur due to variations in pull-up transients when the drift amount is monitored by a feedback control circuit, which is an external IC, and an accurate drift amount can be measured. Disappear. For this reason, in the conventional method, a potential change at the time of pulling down to the ground level GND when the sampling switch (HSW) 174 is ON is monitored by an external feedback control circuit to perform correction.
[0075]
  FIG. 17 is a circuit diagram showing a DCK generation circuit in the clock generation circuit 25.
  As shown in FIG. 17, the second clock DCK includes an input first clock HCK and a plurality of inverters INV251 to INV.254NAND combination with the clock pulse (HCK +) delayed through is obtained by the NAND gate NA251.
  That is, as shown in FIGS. 18A to 18C, the rise of DCK is determined by the delayed rise of HCK +.
  Here, since the amount of drift in long-time use is the sum of the individual transistor delay amounts, in the above DCK generation circuit, the rise of DCK is delayed more than the fall, and its pulse width becomes shorter due to drift. Conceivable.
  As described above, the drift delay amount needs to be monitored when the sampling switch (HSW) 174 is turned on and pull-down occurs, that is, at the rising edge of DCK, in order to prevent variation at the time of monitoring. On the other hand, the sample hold inside the panel is performed at the falling edge of DCK. That is, in the circuit that generates DCK inside the panel, the drift amount at the rise of the DCK extraction output pulse is larger than the drift amount of the sample hold pulse because of the circuit configuration, and the accurate drift amount cannot be monitored.
[0076]
This will be described in more detail with reference to the timing chart of FIG. In FIG. 19, when sampling the video signal VDO, (A) the initial state, (B) after aging drift, and (C) the waveform after drift correction are shown in parallel.
[0077]
When the DCK pulse is extracted and used as a monitor output, as described above, the rising delay amount increases with respect to the falling edge of the clock DCK.
For example, assume that the rising edge is delayed by 30 ns and the falling edge is delayed by 15 ns.
At this time, as shown in (1) to (6) of FIG. 19B, a ghost GST is generated in the forward direction. Here, since drift correction is performed on the rising edge of the clock DCK, in this case, the 30 ns input pulse is advanced. Then, the pulse timing as shown in FIG.
Here, the fall timing of the sample hold pulse after drift correction is 15 ns earlier than the initial state. As a result, the black signal written on the signal line of the (N + 1) th stage does not return to the gray level, and a potential of ΔV remains, and a rear ghost GST occurs at this position. That is, as the drift increases, the rear ghost margin decreases, and the drift correction circuit may become meaningless.
[0078]
On the other hand, in this embodiment, in order to cope with the above phenomenon, the first clocks HCK and HCKX are extracted instead of the second clocks DCK and DCKX as the sample hold pulse of the monitor circuit 24.
[0079]
FIG. 20 is a timing chart when drift correction is performed by extracting the first clocks HCK and HCKX as in the present embodiment.
In FIG. 20, when sampling the video signal VDO, (A) an initial state, (B) after aging drift, and (C) after drift correction are shown in parallel.
[0080]
The number of transistors in the path of the first clock HCK is substantially equal to the number of transistors in the path of the second clock DCK falling, and the delay amount of the first HCK rises and falls is substantially the same as the delay amount of the fall of DCK. Take no value.
In other words, performing drift correction at the rising edge of the first clock HCK is equivalent to performing drift correction at the falling timing of the second clock DCK, and can accurately correct the delay amount of the sample hold pulse. it can.
[0081]
  For example, as shown in FIGS. 20A to 20C, it is assumed that the rising edge of the second clock DCK is delayed by 30 na and the falling edge is delayed by 15 ns.
  At this time, the rising edge of the first clock HCK is delayed by 15 ns. Here, since drift correction is performed for the rising edge of the first clock HCK, in this case, the 15 ns input pulse is advanced.
  Then, the pulse timing as shown in FIG. Here, the falling timing of the sample hold pulse does not change compared to the initial state. As a result, the margin for the back ghost is the same as the initial state. Further, since the rise of the sample hold pulse is extended by 15 ns compared to the initial state, the drive pulse DRVP is also shortened.
  Here, since the ghost margin increases when the drive pulse is short, the drift correction is accurately performed by extracting the first clock HCK by the monitor circuit 24 and using it as the sample hold pulse as in this embodiment.soIn addition, the ghost margin increases.
[0082]
Next, the normal scan operation and the reverse scan operation with the above-described configuration will be described with reference to the timing charts of FIGS. 21 (A) to (K) and FIGS.
[0083]
First, the normal scanning operation will be described with reference to the timing charts of FIGS.
[0084]
In this case, the scan direction switching signal RGT is set to a high level and supplied to the shift register 231 of the horizontal scanner 23 and the selector 2413 of the monitor circuit 24 (for example, the inverted signal RGTX is also supplied to the selector 2413).
As a result, a path is formed through which the switching circuits 2311 to 2313 inserted between the shift stages in the shift register 231 of the horizontal scanner 23 propagate the signal from left to right. That is, from the first shift stage 231-1 to the second shift stage 231-2, from the second shift stage 231-2 to the third shift stage 231-3, and from the third shift stage 231-3 to the fourth shift stage 231-4. A signal propagation path in which the horizontal start pulse HST is sequentially shifted is formed.
[0085]
In this state, the feedback control circuit 26 generates a horizontal start pulse HST as shown in FIG. 21A, and the first shift stage 231-1 of the shift register 231 in the horizontal scanner 23 and the monitor circuit 24. It is supplied to the selector 2413.
In the feedback control circuit 26, as shown in FIGS. 21B and 21C, horizontal clocks HCK and HCKX having opposite phases are generated, and the first shift stage 231 of the shift register 231 in the horizontal scanner 23 is generated. −1 to the fourth shift stage 231-4, the monitor circuit 24, and the clock generation circuit 25.
In the clock generation circuit 25, as shown in FIGS. 21D and 21E, the horizontal clocks HCK and HCKX generated by the feedback control circuit 26 have the same period (T1 = T2) and the duty ratio. Small clocks DCK and DCKX having opposite phases are generated and supplied to the horizontal scanner 23 through the clock lines DKL1 and DKXL1.
[0086]
  In the feedback control circuit 26, a vertical start pulse VST for instructing the start of vertical scanning, vertical clocks VCK and VCKX having opposite phases as a reference for vertical scanning, and a command for starting the horizontal scanning are instructed.HorizontalStart pulseHSTAre generated and supplied to the vertical scanner 22.
[0087]
Then, the monitor circuit 24 receives the horizontal start pulse HST, the switching signal RGT and its inverted signal RGTX, and the switching signal RGT is at a high level instructing the first scanning operation, so that it is shown in FIG. The horizontal start pulse HST is output to the switch 2411 as the select pulse SLP241, and the first clock HCK having a phase different from that of the second clock DCKX to be extracted by the first shift stage 231-1 of the horizontal scanner 23 is extracted, and the phase After the phase adjustment by the adjustment circuit 242, as shown in FIG. 21I, the sample hold pulse SHP241 is supplied to the sampling switch 243.
As a result, the sampling switch 243 is turned on in response to the sample hold pulse SHP241, the monitor line MNTL21 pulled up by the pullup resistor R21 outside the LCD panel is pulled to the ground level, and the level change information is buffered. The feedback control circuit 26 is input via the BF21.
[0088]
In the shift register 231 of the horizontal scanner 23, the first shift stage 231-1 to which the horizontal start pulse HST is supplied by the external feedback control circuit 26 is synchronized with the reverse-phase horizontal clocks HCK and HCKX in FIG. As shown in (G), a shift pulse SFTP 231 having the same pulse width as the horizontal clocks HCK and HCKX is output to the extraction switch 232-1. Further, the shift pulse SFTP 231 is shifted in from the first shift stage 231-1 to the second shift stage 231-2.
The extraction switch 232-1 corresponding to the first shift stage 231-1 is turned on in response to the shift pulse SFTP231, and the first switch output to the clock line DKXL1 as shown in FIGS. 21 (E) and (J). The second clock DCKX is extracted, phase-adjusted by the phase adjustment circuit 233-1, and then supplied to the sampling switch 234-1 as the sample hold pulse SHP231.
Accordingly, the sampling switch 234-1 is turned on in response to the sample hold pulse SHP231, and the video signal VDO input through the video line VDL21 is sampled and supplied to the signal line SGNL21 of the pixel unit 21.
[0089]
Next, in the second shift stage 231-2 in which the shift pulse SFTP 231 is shifted in from the first shift stage 231-1, as shown in FIG. 21 (G) in synchronization with the reverse-phase horizontal clocks HCK and HCKX. A shift pulse SFTP 232 having the same pulse width as that of the horizontal clocks HCK and HCKX is output to the extraction switch 232-2. Further, the shift pulse SFTP232 is shifted in from the second shift stage 231-2 to the third shift stage 231-3.
The extraction switch 232-2 corresponding to the second shift stage 231-2 is turned on in response to the shift pulse SFTP232, and as shown in FIGS. 21D and 21K, the first output outputted to the clock line DKL1. The second clock DCK is extracted and phase-adjusted by the phase adjustment circuit 233-2, and then supplied to the sampling switch 234-2 as the sample hold pulse SHP232.
Accordingly, the sampling switch 234-2 is turned on in response to the sample hold pulse SHP232, and the video signal VDO input through the video line VDL21 is sampled and supplied to the signal line SGNL22 of the pixel unit 21.
[0090]
Next, in the third shift stage 231-3 in which the shift pulse SFTP232 is shifted in from the second shift stage 231-2, the period of the horizontal clocks HCK and HCKX is the same as that of the horizontal clocks HCK and HCKX having opposite phases. A shift pulse SFTP233 having a pulse width is output to the extraction switch 232-3. Further, the shift pulse SFTP233 is shifted in from the third shift stage 231-3 to the fourth shift stage 231-4.
The extraction switch 232-3 corresponding to the third shift stage 231-3 is turned on in response to the shift pulse SFTP233, and the second clock DCKX output to the clock line DKXL1 is extracted, and the phase adjustment circuit 233-3 is extracted. After being phase-adjusted, the sample hold pulse SHP233 is supplied to the sampling switch 234-3.
Accordingly, the sampling switch 234-3 is turned on in response to the sample hold pulse SHP233, and the video signal VDO input through the video line VDL21 is sampled and supplied to the signal line SGNL23 of the pixel unit 21.
[0091]
Next, in the fourth shift stage 231-4 to which the shift pulse SFTP233 is shifted in from the third shift stage 231-3, the period of the horizontal clocks HCK and HCKX is the same as that of the horizontal clocks HCK and HCKX having opposite phases. A shift pulse SFTP234 having a pulse width is output to the extraction switch 232-4.
The extraction switch 232-4 corresponding to the fourth shift stage 231-4 is turned on in response to the shift pulse SFTP234, the second clock DCK output to the clock line DKL1 is extracted, and the phase adjustment circuit 233-4. After being phase-adjusted, the sample hold pulse SHP234 is supplied to the sampling switch 234-4.
As a result, the sampling switch 234-4 is turned on in response to the sample hold pulse SHP 234, and the video signal VDO input through the video line VDL 21 is sampled and supplied to the signal line SGNL 24 of the pixel unit 21.
[0092]
In the feedback control circuit 26, the change in phase from the initial state is monitored from the timing when the sampling switch 243 of the monitor circuit 24 in the normal scanning operation is turned on and the monitor line MNTL21 transitions to the ground level.
In the feedback control circuit 26, the monitored phase change is fed back to the panel input clocks HCK, HCKX, etc., and an appropriate timing is set. As a result, the generation of a ghost due to the drift of the sample hold pulse SHP with respect to its initial state is prevented.
[0093]
As described above, during the normal scan operation, the monitor circuit 24 receives the horizontal start pulse HST, the switching signal RGT and its inverted signal RGTX, and the selector unit 241 extracts the first shift stage 231-1 of the horizontal scanner 23. The first clock HCK having a phase different from that of the second clock DCKX to be extracted is extracted, adjusted in phase by the phase adjustment circuit 242, and then supplied to the sampling switch 243 as the sample hold pulse SHP241, and the sampling switch 243 is turned on. Become. Further, in the horizontal scanner 23, when the switches 232-1 to 232-4 of the clock extraction switch group 232 are supplied with the shift pulses SFTP231 to SFTP234 from the shift stages 231-1 to 231-4 of the shift register 231, these are provided. By sequentially turning on in response to the shift pulses SFTP231 to SFTP234, the second clocks DCKX and DCK having opposite phases are alternately extracted, and the clocks DCKX and DCK whose phases are adjusted by the phase adjustment circuit group 233 are sample-held. It is given as pulses SHP231 to SHP234.
When the sample hold pulses SHP231 to SHP234 are given to the sampling switches 234-1 to 234-4 of the sampling switch group 234, the sampling switches 234-1 to 234-4 are sequentially turned on in response to the sample hold pulses SHP231 to SHP234, and passed through the video line VDL21. The input video signal VDO is sequentially sampled and supplied to the signal lines SGNL21 to SGNL24 of the pixel unit 21.
That is, the sample hold pulse SHP231 of the first shift stage of the horizontal scanner 23 and the sample hold pulse SHP241 of the monitor circuit 24 are generated at substantially the same timing as the relationship between the other sample hold pulses SHP231 to SHP233, and the image display is performed without any problem. Is called.
[0094]
Next, the reverse scan operation will be described with reference to the timing charts of FIGS.
[0095]
In this case, the scan direction switching signal RGT is set to a low level and supplied to the shift register 231 of the horizontal scanner 23 and the selector 2413 of the monitor circuit 24 (for example, the inverted signal RGTX is also supplied to the selector 2413).
As a result, a path is formed through which the switching circuits 2311 to 2313 inserted between the shift stages in the shift register 231 of the horizontal scanner 23 propagate the signal from right to left. That is, the fourth shift stage 231-4 to the third shift stage 231-3, the third shift stage 231-3 to the second shift stage 231-2, and the second shift stage 231-2 to the first shift stage 231-1. A signal propagation path in which the horizontal start pulse HST is sequentially shifted is formed.
[0096]
In this state, the feedback control circuit 26 generates a horizontal start pulse HST as shown in FIG. 22A, and the fourth shift stage 231-4 of the shift register 231 in the horizontal scanner 23 and the monitor circuit 24. It is supplied to the selector 2413.
In the feedback control circuit 26, as shown in FIGS. 22B and 22C, horizontal clocks HCK and HCKX having opposite phases are generated, and the first shift stage 231 of the shift register 231 in the horizontal scanner 23 is generated. −1 to the fourth shift stage 231-4, the monitor circuit 24, and the clock generation circuit 25.
In the clock generation circuit 25, as shown in FIGS. 22D and 22E, the horizontal clocks HCK and HCKX generated by the feedback control circuit 26 have the same period (T1 = T2) and the duty ratio. Small clocks DCK and DCKX having opposite phases are generated and supplied to the horizontal scanner 23 through the clock lines DKL1 and DKXL1.
[0097]
  In the feedback control circuit 26, a vertical start pulse VST for instructing the start of vertical scanning, vertical clocks VCK and VCKX having opposite phases as a reference for vertical scanning, and a command for starting the horizontal scanning are instructed.HorizontalStart pulseHSTAre generated and supplied to the vertical scanner 22.
[0098]
Then, the monitor circuit 24 receives the horizontal start pulse HST, the switching signal RGT and its inverted signal RGTX, and the switching signal RGT is at a high level instructing the first scanning operation, so that it is shown in FIG. In addition, the horizontal start pulse HST is output to the switch 2412 as the select pulse SLP242, and the first clock HCKX having a phase different from that of the second clock DCK to be extracted by the fourth shift stage 231-4 of the horizontal scanner 23 is extracted, and the phase After the phase adjustment by the adjustment circuit 242, as shown in FIG. 22I, the sample hold pulse SHP241 is supplied to the sampling switch 243.
As a result, the sampling switch 243 is turned on in response to the sample hold pulse SHP241, the monitor line MNTL21 pulled up by the pullup resistor R21 outside the LCD panel is pulled to the ground level, and the level change information is buffered. The feedback control circuit 26 is input via the BF21.
[0099]
Then, in the shift register 231 of the horizontal scanner 23, the fourth shift stage 231-4 to which the horizontal start pulse HST is supplied by the external feedback control circuit 26 is synchronized with the reverse-phase horizontal clocks HCK and HCKX in FIG. As shown in (G), a shift pulse SFTP234 having the same pulse width as the horizontal clocks HCK and HCKX is output to the extraction switch 232-4. Further, the shift pulse SFTP234 is shifted in from the fourth shift stage 231-4 to the third shift stage 231-3.
The extraction switch 232-4 corresponding to the fourth shift stage 231-4 is turned on in response to the shift pulse SFTP234, and as shown in FIGS. 22E and 22J, the extraction switch 232-4 output to the clock line DKL1. The second clock DCK is extracted and phase-adjusted by the phase adjustment circuit 233-4, and then supplied to the sampling switch 234-4 as a sample hold pulse SHP234.
As a result, the sampling switch 234-4 is turned on in response to the sample hold pulse SHP 234, and the video signal VDO input through the video line VDL 21 is sampled and supplied to the signal line SGNL 24 of the pixel unit 21.
[0100]
Next, in the third shift stage 231-3 in which the shift pulse SFTP234 is shifted in from the fourth shift stage 231-4, as shown in FIG. 22 (G) in synchronization with the reverse-phase horizontal clocks HCK and HCKX. A shift pulse SFTP233 having the same pulse width as the horizontal clocks HCK and HCKX is output to the extraction switch 232-3. Further, the shift pulse SFTP233 is shifted in from the third shift stage 231-3 to the second shift stage 231-2.
The extraction switch 232-3 corresponding to the third shift stage 231-3 is turned on in response to the shift pulse SFTP 233, and as shown in FIGS. 22D and 22K, the extraction switch 232-3 output to the clock line DKLX 1. The second clock DCKX is extracted and phase-adjusted by the phase adjustment circuit 233-3 and then supplied to the sampling switch 234-3 as a sample hold pulse SHP 233.
Accordingly, the sampling switch 234-3 is turned on in response to the sample hold pulse SHP233, and the video signal VDO input through the video line VDL21 is sampled and supplied to the signal line SGNL23 of the pixel unit 21.
[0101]
Next, in the second shift stage 231-2 in which the shift pulse SFTP 233 is shifted in from the third shift stage 231-3, the same period as the horizontal clocks HCK and HCKX is synchronized with the opposite-phase horizontal clocks HCK and HCKX. A shift pulse SFTP 232 having a pulse width is output to the extraction switch 232-2. Further, the shift pulse SFTP232 is shifted in from the second shift stage 231-2 to the first shift stage 231-1.
The extraction switch 232-2 corresponding to the second shift stage 231-2 is turned on in response to the shift pulse SFTP232, the second clock DCK output to the clock line DKL1 is extracted, and the phase adjustment circuit 233-2. After being phase-adjusted, the sample hold pulse SHP232 is supplied to the sampling switch 234-2.
Accordingly, the sampling switch 234-2 is turned on in response to the sample hold pulse SHP232, and the video signal VDO input through the video line VDL21 is sampled and supplied to the signal line SGNL22 of the pixel unit 21.
[0102]
Next, in the first shift stage 231-1 in which the shift pulse SFTP232 is shifted in from the second shift stage 231-2, the period of the horizontal clocks HCK and HCKX is the same as that of the horizontal clocks HCK and HCKX having opposite phases. A shift pulse SFTP 231 having a pulse width is output to the extraction switch 232-1.
The extraction switch 232-1 corresponding to the fourth shift stage 231-1 is turned on in response to the shift pulse SFTP231, the second clock DCKX output to the clock line DKXL1 is extracted, and the phase adjustment circuit 233-1. After being phase-adjusted, the sample hold pulse SHP231 is supplied to the sampling switch 234-1.
Accordingly, the sampling switch 234-1 is turned on in response to the sample hold pulse SHP231, and the video signal VDO input through the video line VDL21 is sampled and supplied to the signal line SGNL21 of the pixel unit 21.
[0103]
In the feedback control circuit 26, the change in phase from the initial state is monitored from the timing when the sampling switch 243 of the monitor circuit 24 in the normal scanning operation is turned on and the monitor line MNTL21 transitions to the ground level.
In the feedback control circuit 26, the monitored phase change is fed back to the panel input clocks HCK, HCKX, etc., and an appropriate timing is set. As a result, the generation of a ghost due to the drift of the sample hold pulse SHP with respect to its initial state is prevented.
[0104]
As described above, during the reverse scan operation, the monitor circuit 24 receives the horizontal start pulse HST, the switching signal RGT and its inverted signal RGTX, and the selector unit 241 extracts the fourth shift stage 231-4 of the horizontal scanner 23. The first clock HCKX having a phase different from that of the power second clock DCK is extracted, adjusted in phase by the phase adjustment circuit 242, and then supplied to the sampling switch 243 as the sample hold pulse SHP241, so that the sampling switch 243 is turned on. Become.
In the horizontal scanner 23, when the switches 232-4 to 232-1 of the clock extraction switch group 232 receive the shift pulses SFTP234 to SFTP231 from the shift stages 234-1 to 231-1 of the shift register 231, these are provided. By sequentially turning on in response to the shift pulses SFTP234 to SFTP231, the second clocks DCK and DCKX having opposite phases are alternately extracted, and the clocks DCK and DCKX whose phases are adjusted by the phase adjustment circuit group 233 are sample-held. The pulses are provided as pulses SHP234 to SHP231.
When the sample hold pulses SHP234 to SHP231 are given to the sampling switches 234-4 to 234-1 of the sampling switch group 234, the sampling switches 234-4 to 234-1 are sequentially turned on in response to the sample hold pulses SHP234 to SHP231, and pass through the video line VDL21. The input video signal VDO is sequentially sampled and supplied to the signal lines SGNL24 to SGNL21 of the pixel unit 21.
That is, the sample hold pulse SHP231 of the first shift stage of the horizontal scanner 23 and the sample hold pulse SHP241 of the monitor circuit 24 are generated at substantially the same timing as the relationship between the other sample hold pulses SHP231 to SHP233, and the image display is performed without any problem. Is called.
In other words, even if the clock phase changes during the horizontal reversal of the scan operation, pulses with the same output phase can be obtained.
[0105]
As described above, according to the present embodiment, the monitor circuit 24 is disposed close to one side of the horizontal scanner 23, and during the first scan operation (normal scan operation), the horizontal start pulse HST is sent to the first stage of the horizontal scanner. This is supplied to the shift stage 231-1 and the selector 2413 of the monitor circuit 24, and the monitor circuit 24 receives the horizontal start pulse HST, the switching signal RGT and its inverted signal RGTX, and the selector unit 241 performs the first shift of the horizontal scanner 23. The first clock HCK having a phase different from that of the second clock DCKX to be extracted by the stage 231-1 is extracted and output as the sample hold pulse SHP 241, and the monitor line pulled up in response to the sample hold pulse by the sampling switch 244 MNTL21 potential to ground potential In the second scan operation (reverse scan operation), the monitor circuit 24 receives the horizontal start pulse HST, the switching signal RGT and its inverted signal RGTX, and the selector unit 241 performs the fourth shift of the horizontal scanner 23. The second clock HCKX having a phase different from that of the second clock DCK to be extracted by the stage 231-4 is extracted and output as the sample hold pulse SHP241. The monitor line is pulled up in response to the sample hold pulse by the sampling switch 244. Since the potential of the MNTL 21 is set to the ground potential, the following effects can be obtained.
That is, it is possible to accurately correct the drift of the sample hold pulse due to the change in the transistor characteristics due to panel aging or the like.
As described above, even in a horizontal scanner (the number of shift stages is an even number) in which the phase of the clock is inverted in the scan direction inversion, the phase of the output potential change does not change, and the accuracy can be obtained regardless of the scan direction. High image display is realized. Further, it is possible to obtain a sample hold pulse in which the ghost margin increases with aging.
[0106]
In addition, a configuration in which monitor circuits are provided on both sides of the horizontal scanner 23 is possible, but in this case, the outputs of both monitor circuits are connected by wiring such as Al. Therefore, in order to prevent a resistance difference corresponding to the Al wiring in the outputs of both monitor circuits, the line width of the Al wiring needs to be set to about 100 μm, which greatly increases the layout area and reduces the frame width in the future. There are also problems above.
On the other hand, in this embodiment, the scan operation of the horizontal scanner in which the clock phase is inverted in the scan direction inversion can be monitored with high accuracy only by providing one monitor circuit. The layout space can be reduced and the layout is advantageous, and it is possible to cope with the future narrowing of the frame.
Further, by making the circuit configuration after extracting the clock in the monitor circuit 24 the same as that of other horizontal scanners, an output pulse having the same delay amount can be obtained.
[0107]
The horizontal scanner 23 does not use the shift pulses SFTP231 to SFTP234 sequentially output from the shift register 231 as sample hold pulses, but alternately uses clocks DCKX and DCK having opposite phases in synchronization with the shift pulses SFTP231 to SFTP234. These clocks DCKX and DCK are used as sample and hold pulses SHP231 to SHP234 via a phase adjustment circuit. Thereby, the dispersion | variation in the sample hold pulses SHP231-SHP234 can be suppressed. As a result, ghosts caused by variations in the sample hold pulses SHP231 to SHP234 can be removed.
[0108]
In addition, the horizontal scanner 23 does not extract the horizontal clocks HCKX and HCK that serve as a reference for the shift operation of the shift register 231 and use them as sample hold pulses, but has the same cycle and a duty ratio with respect to the horizontal clocks HCKX and HCK. Since small clocks DCKX and DCK are separately generated, and these clocks DCKX and DCK are extracted and used as sample hold pulses SHP231 to SHP234, complete non-overlapping sampling between sampling pulses is performed in horizontal driving. Since this can be realized, it is possible to suppress the occurrence of vertical stripes due to overlap sampling.
[0109]
In the present embodiment, an analog video signal is input, and this is sampled and applied to a liquid crystal display device equipped with an analog interface driving circuit that drives each pixel in a dot-sequential manner. Can be applied to a liquid crystal display device equipped with a digital interface drive circuit that takes the input and latches it, converts it into an analog video signal, samples the analog video signal, and drives each pixel in a dot sequence It is.
In the present embodiment, the case where the present invention is applied to an active matrix liquid crystal display device using a liquid crystal cell as a display element (electro-optical element) of each pixel has been described as an example. It is not limited, but an active matrix display using a dot sequential drive system that employs a clock drive system in a horizontal drive circuit, such as an active matrix EL display device using an electroluminescence (EL) element as a display element of each pixel. Applicable to all devices.
[0110]
In addition to the well-known 1H inversion driving method and the dot inversion driving method, the dot sequential driving method has the same polarity in the pixel arrangement after the video signal is written, and the left and right pixels adjacent to each other. There is a so-called dot line inversion driving method in which video signals having opposite polarities are simultaneously written in two rows separated by odd numbers between adjacent pixel columns, for example, pixels in two upper and lower rows so that the pixels have opposite polarities.
[0111]
Second embodiment
In the second embodiment, a configuration example of a projection type liquid crystal display device (liquid crystal projector) to which the dot matrix driving type active matrix liquid crystal display device of FIG. 11 can be applied as a display panel (LCD) will be described.
[0112]
The dot matrix driving type active matrix liquid crystal display device according to the above embodiment can be used as a display panel of a projection type liquid crystal display device (liquid crystal projector), that is, an LCD (liquid crystal display) panel.
[0113]
FIG. 23 is a block diagram showing a system configuration of a projection type liquid crystal display device to which the dot matrix driving type active matrix liquid crystal display device according to the present invention can be applied as a display panel (LCD).
[0114]
The projection-type liquid crystal display device 40 according to this example includes a video signal source (VSRC) 41, a system board (SYSBRD) 42, and an LCD panel (PNL) 43.
In this system configuration, the system board 42 performs signal processing such as adjustment of the sample hold position described above on the video signal output from the video signal source 41. A feedback control circuit 26 including the timing generator of FIG. 11 is also mounted on the system board 42.
As the LCD panel 43, the dot matrix driving type active matrix liquid crystal display device according to the above-described embodiment is used. In the case of color, the LCD panel 43 is provided corresponding to each of R (red), G (green), and B (blue).
[0115]
FIG. 24 is a schematic configuration diagram showing an example of the configuration of the optical system of the projection type color liquid crystal display device.
In the optical system 400 of the projection type color liquid crystal display device of FIG. 24, white light emitted from the light source 401 is only a specific color component, for example, a B (blue) light component having the shortest wavelength, by the first beam splitter 402. Are transmitted, and the light components of the remaining colors are reflected. The B light component transmitted through the first beam splitter 402 is changed in optical path by the mirror 403 and irradiated to the B LCD panel 405B through the lens 404.
For the light component reflected by the first beam splitter 402, for example, the G (green) light component is reflected by the second beam splitter 406, and the R (red) light component is transmitted. The G light component reflected by the second beam splitter 406 is applied to the G LCD panel 405G through the lens 407.
The R light component transmitted through the second beam splitter 406 has its optical path changed by mirrors 408 and 409, and is irradiated onto the R LCD panel 405 R through the lens 410.
Each of the LCD panels 405R, 405G, and 405B includes a first substrate in which a plurality of pixels are arranged in a matrix, a second substrate that is opposed to the first substrate with a predetermined interval, and these It has a liquid crystal layer held between the substrates and a filter layer corresponding to each color.
The R, G, and B lights that have passed through the LCD panels 405R, 405G, and 405B are combined by a cross prism 411. The combined light emitted from the cross prism 411 is projected onto the screen 413 by the projection prism 412.
[0116]
In the projection type liquid crystal display device configured as described above, the dot-sequential driving type active matrix liquid crystal display device according to the above-described embodiment is used as the LCD panels 405R, 405G, and 405B. The scan direction switching signal RGT is supplied to the LCD panels 405R and 405B at a high level and supplied to the LCD panel 405G at a low level so that the LCD panel 405G performs the second scan operation (reverse scan operation). Is done.
As a result, even if the phase of the clock changes during the horizontal reversal of the scanning operation, pulses with the same phase of output can be obtained from the monitor circuit 24 of any LCD panel 405R, 405G, 405B.
That is, even in a horizontal scanner where the clock phase is inverted in the scan direction inversion, the phase of the output potential change does not change, and it can be monitored with high accuracy regardless of the scan direction, and the image is halved. A highly accurate image display can be realized without being shifted.
In addition, since the liquid crystal display device according to the present embodiment realizes complete non-overlap sampling in the horizontal drive system, generation of vertical stripes due to overlap sampling can be suppressed and a ghost margin can be increased. Therefore, higher quality image display can be realized.
[0117]
There are two types of projection type liquid crystal display devices: a rear type and a front type. Generally, a rear type projection type liquid crystal display device is a projection TV for moving images, and a front type projection type liquid crystal display device is a data projector. Although being used, the dot matrix driving type active matrix liquid crystal display device according to the above-described embodiment can be applied to any type. Further, here, the case where the present invention is applied to a color projection type liquid crystal display device has been described as an example, but the present invention can be similarly applied to a monochrome projection type liquid crystal display device.
[0118]
【The invention's effect】
As described above, according to the present invention, it is possible to accurately correct the drift of the sample-and-hold pulse due to the change in transistor characteristics due to panel aging or the like.
As described above, even in a horizontal scanner (the number of shift stages is an even number) in which the phase of the clock is inverted in the scan direction inversion, the phase of the output potential change does not change, and the accuracy can be obtained regardless of the scan direction. High image display is realized. Further, it is possible to obtain a sample hold pulse in which the ghost margin increases with aging.
[0119]
In addition, it is possible to monitor the scanning operation of a horizontal scanner that reverses the clock phase in the scan direction inversion with a single monitor circuit with high accuracy, thus reducing the layout space and sufficiently supporting future narrower frames. There is an advantage that it is possible.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of an active matrix liquid crystal display device adopting a general dot sequential driving method.
FIG. 2 is a block diagram illustrating a configuration example of a display panel of an active matrix liquid crystal display device.
FIG. 3 is a timing chart showing a timing relationship between horizontal clocks HCK and HCKX and clocks DCK and DCKX.
4 is a diagram for explaining an operation centering on the horizontal scanner of FIG. 1; FIG.
5 is a waveform diagram for explaining an operation centering on the horizontal scanner of FIG. 1; FIG.
6 is a diagram for explaining a problem of the horizontal scanner in FIG. 1. FIG.
FIG. 7 is a block diagram illustrating a configuration example of a conventional liquid crystal display device provided with a monitor circuit.
8 is a circuit diagram showing a specific example of the configuration of a part of the monitor circuit of FIG. 7 and a peripheral horizontal scanner.
9 is a timing chart for explaining an operation when scanning is performed in a normal direction (from left to right in FIG. 8) of the circuit of FIG. 8;
10 is a timing chart for explaining operations and problems when scanning in the reverse direction (right to left in FIG. 8) of the circuit of FIG. 8;
FIG. 11 is a circuit diagram illustrating a configuration example of a dot-sequential driving type active matrix liquid crystal display device according to an embodiment of the present invention.
12 is a block diagram illustrating a configuration example of a display panel of the active matrix liquid crystal display device of FIG.
FIG. 13 is a circuit diagram showing a configuration example of a switching circuit inserted between shift stages of the shift register.
FIG. 14 is a circuit diagram showing a specific configuration example of a selector unit of the monitor circuit according to the present embodiment.
FIG. 15 is a circuit diagram when drift correction is performed by extracting second clocks DCK and DCKX;
FIG. 16 is an explanatory diagram when drift correction is performed by extracting the second clocks DCK and DCKX;
FIG. 17 is a diagram illustrating a configuration example of a generation circuit for a second clock DCK.
FIG. 18 is a timing chart of the generation circuit for the second clock DCK.
FIG. 19 is a timing chart in the case where drift correction is performed by extracting the second clocks DCK and DCKX.
FIG. 20 is a timing chart when drift correction is performed by extracting the first clocks HCK and HCKX as in the present embodiment.
FIG. 21 is a timing chart for explaining a normal scan operation of the circuit of FIG. 11;
22 is a timing chart for explaining the reverse scan operation of the circuit of FIG.
FIG. 23 is a block diagram showing a system configuration of a projection type liquid crystal display device to which the dot matrix drive type active matrix liquid crystal display device according to the present invention can be applied as a display panel (LCD).
FIG. 24 is a schematic configuration diagram showing an example of a configuration of an optical system of a projection type color liquid crystal display device to which the dot matrix driving type active matrix liquid crystal display device according to the present invention can be applied as a display panel (LCD).
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 20 ... Liquid crystal display device, 21 ... Effective pixel part (PXLP), 22 ... Vertical scanner (VSCN), 23 ... Horizontal scanner (HSCN), 24 ... Monitor circuit (MNT), 25 ... Clock generation circuit (GEN), 26 ... Feedback control circuit (FDCBIC), 27 ... Precharge circuit (PRCG), 30 ... Display panel, 40 ... Projection type liquid crystal display device, 41 ... Video signal source (VSRC), 42 ... System board (SYSBRD), 43 ... LCD panel (PNL) 43, 400 ... optical system, 401 ... light source, 402 ... first beam splitter, 403, 408, 409 ... mirror, 404, 407, 410 ... lens, 405R, 405G, 405B ... LCDF panel, 406 ... first 2 beam splitters, 411... Cross prism, 412... Projection prism, 413. Over emissions.

Claims (12)

A pixel portion in which a plurality of pixels are arranged in a matrix and a signal line is wired for each pixel column;
A monitor line held at a first potential;
Generating at least a first clock signal and a first inverted clock signal that are opposite in phase to be a reference for horizontal scanning, and monitoring a potential change of the monitor line, and at least based on a change in timing of the potential change. A control circuit for correcting the generation timing of the clock signal and the inverted clock signal;
Based on the first clock signal and the first inverted clock signal generated by the control circuit, the first clock signal and the first inverted clock signal have the same period and a small duty ratio. Clock generating means for generating two clock signals and a second inverted clock signal;
A horizontal scanner,
A monitor circuit;
The horizontal scanner
A plurality of shift stages are connected in cascade, and a first scan operation that sequentially shifts from the first stage to the last stage and a second scan operation that sequentially shifts from the last stage to the first stage can be switched according to a switching signal. Or a shift register that sequentially outputs shift pulses from each shift stage in synchronization with the clock signal and the inverted clock signal during the second scan operation;
A first switch group for alternately taking out the second clock signal and the second inverted clock signal in response to the shift pulse output from the corresponding shift stage of the shift register, and outputting as a sample hold pulse; ,
A second switch group that sequentially samples a video signal in response to a sample hold pulse by each switch of the first switch group and supplies the video signal to a corresponding signal line of the pixel unit,
The monitor circuit is
When the switching signal indicates the first scan operation in response to the switching signal, the first stage shift of the shift register in the horizontal scanner is selected from the first clock signal and the first inverted clock signal. When a signal having a phase different from that of the signal extracted by the stage is extracted and the second scan operation is instructed, the last of the shift registers in the horizontal scanner is selected from the first clock signal and the first inverted clock signal. A selector unit that extracts a signal whose phase is different from that of the signal extracted by the shift stage, and outputs it as a sample hold pulse;
And a third switch for setting the potential of the monitor line to a second potential in response to a sample hold pulse by the selector unit. The selector unit receives a select pulse, extracts the clock signal, and outputs a sample hold pulse to the third switch;
A fifth switch that receives the select pulse, extracts the inverted clock signal, and outputs it to the third switch as a sample hold pulse;
When the switch signal is received and the switch signal instructs the first scan operation, the select pulse is output to the fourth switch and the second scan operation is indicated. The display device according to claim 1, further comprising: a selector that outputs the select pulse to the fifth switch. The first scan operation and the second scan operation are started in response to a horizontal start pulse, and the horizontal start pulse is supplied to the first shift stage of the shift register and the monitor circuit during the first scan operation. At the time of the second scan operation, it is supplied to the final shift stage of the shift register and the monitor circuit,
3. The display device according to claim 2, wherein the selector of the monitor circuit supplies the horizontal start pulse as the select pulse to the fourth switch or the fifth switch in accordance with the switching signal. The selector includes a first transfer line for transferring the horizontal start pulse as the select pulse to the fourth switch;
A second transfer line for transferring the horizontal start pulse as the select pulse to the fifth switch;
A first select switch for connecting the first transfer line to the horizontal start pulse supply line when the switching signal indicates the first scan operation;
A second select switch for connecting the second transfer line to the horizontal start pulse supply line when the switching signal indicates the second scan operation;
The fourth switch to which the first transfer line or the second transfer line connected to the horizontal start pulse supply line is connected to the first transfer line or the second transfer line. The display device according to claim 3, further comprising: a potential setting unit that holds the fifth switch at a potential that can hold the non-conductive state. The display device according to claim 1, wherein the number of shift stages in the shift register of the horizontal scanner is an even number. The display device according to claim 1, wherein the display element of the pixel is a liquid crystal cell. A monitor line held at a first potential;
A clock signal and an inverted clock signal that are at least opposite to each other as a reference for horizontal scanning are generated, and a change in the potential of the monitor line is monitored. A control circuit for correcting the signal generation timing;
Based on the first clock signal and the first inverted clock signal generated by the control circuit, the first clock signal and the first inverted clock signal have the same period and a small duty ratio. Clock generating means for generating two clock signals and a second inverted clock signal;
A display panel including at least a pixel portion in which a plurality of pixels are arranged in a matrix and a signal line is wired for each pixel column, a horizontal scanner, and a monitor circuit;
Irradiating means for irradiating the display panel with light;
Projecting means for projecting light that has passed through the display panel onto a screen,
The horizontal scanner of the above display panel
A plurality of shift stages are connected in cascade, and a first scan operation that sequentially shifts from the first stage to the last stage and a second scan operation that sequentially shifts from the last stage to the first stage can be switched according to a switching signal. Or a shift register that sequentially outputs shift pulses from each shift stage in synchronization with the clock signal and the inverted clock signal during the second scan operation;
A first switch group for alternately taking out the second clock signal and the second inverted clock signal in response to the shift pulse output from the corresponding shift stage of the shift register, and outputting as a sample hold pulse; ,
A second switch group that sequentially samples a video signal in response to a sample hold pulse by each switch of the first switch group and supplies the video signal to a corresponding signal line of the pixel unit,
The monitor circuit of the display panel is
When the switching signal indicates the first scan operation in response to the switching signal, the first stage shift of the shift register in the horizontal scanner is selected from the first clock signal and the first inverted clock signal. When a signal having a phase different from that of the signal extracted by the stage is extracted and the second scan operation is instructed, the last of the shift registers in the horizontal scanner is selected from the first clock signal and the first inverted clock signal. A selector unit that extracts a signal whose phase is different from that of the signal extracted by the shift stage, and outputs it as a sample hold pulse;
And a third switch for setting a potential of the monitor line to a second potential in response to a sample hold pulse by the selector unit. The selector unit receives a select pulse, extracts the clock signal, and outputs a sample hold pulse to the third switch;
A fifth switch that receives the select pulse, extracts the inverted clock signal, and outputs it to the third switch as a sample hold pulse;
When the switch signal is received and the first switch operation is instructed, the select pulse is output to the fourth switch, and the second scan operation is instructed. The projection display apparatus according to claim 7, further comprising: a selector that outputs the select pulse to the fifth switch. The first scan operation and the second scan operation are started in response to a horizontal start pulse, and the horizontal start pulse is supplied to the first shift stage of the shift register and the monitor circuit during the first scan operation. At the time of the second scan operation, it is supplied to the final shift stage of the shift register and the monitor circuit,
9. The projection display device according to claim 8, wherein the selector of the monitor circuit supplies the horizontal start pulse as the select pulse to the fourth switch or the fifth switch in accordance with the switching signal. The selector includes a first transfer line for transferring the horizontal start pulse as the select pulse to the fourth switch;
A second transfer line for transferring the horizontal start pulse as the select pulse to the fifth switch;
A first select switch for connecting the first transfer line to the horizontal start pulse supply line when the switching signal indicates the first scan operation;
A second select switch for connecting the second transfer line to the horizontal start pulse supply line when the switching signal indicates the second scan operation;
The fourth switch to which the first transfer line or the second transfer line connected to the horizontal start pulse supply line is connected to the first transfer line or the second transfer line. The projection display device according to claim 9, further comprising: a potential setting unit that holds the fifth switch at a potential that can be held in a non-conductive state. 8. The projection display device according to claim 7, wherein the number of shift stages in the shift register of the horizontal scanner is an even number. The projection display device according to claim 7, wherein a display element of each pixel of the pixel portion is a liquid crystal cell.

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