JP3852418B2 - Display device and projection display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device and a driving method thereof, and more particularly to a dot sequential drive type active matrix display device and a projection type display device employing a so-called clock drive method for a horizontal drive circuit (horizontal scanner).
[0002]
[Prior art]
In a display device, for example, an active matrix type liquid crystal display device using a liquid crystal cell as a pixel display element (electro-optical element), a dot sequential driving method is adopted for a horizontal driving circuit (horizontal scanner unit).
[0003]
FIG. 1 is a circuit diagram showing a configuration of an active matrix liquid crystal display device adopting a general dot sequential driving method (see, for example, Patent Document 1).
[0004]
As shown in FIG. 1, the liquid crystal display device (LCD panel) 10 includes an effective pixel unit (PXLP) 11, a vertical scanner (VSCN) 12, a horizontal scanner (HSCN) 13, and a first clock generation circuit (GEN1: timing). Generator) 14 and a second clock generation circuit (GEN2) 15 as main components.
As shown in FIG. 2, the vertical scanner may be arranged not only on one side of the pixel unit 11 but also on both sides, and a signal line precharge circuit (PRCG) 16 is provided. .
[0005]
The pixel unit 11 includes a plurality of pixels PXL arranged in a matrix of n rows and m columns. Here, in order to simplify the drawing, a case of a pixel array of 4 rows and 4 columns is shown as an example.
Each of the pixels PXL arranged in a matrix form a thin film transistor (TFT) 11 that is a pixel transistor, a liquid crystal cell LC in which the pixel electrode is connected to the drain electrode of the TFT 11, and one side to the drain electrode of the TFT 11. And a storage capacitor Cs to which the electrodes are connected.
For each of these pixels PXL, signal lines SGNL1 to SGNL4 are wired along the pixel arrangement direction for each column, and gate lines GTL1 to GTL4 are wired along the pixel arrangement direction for each row.
In each pixel PXL, the source electrode (or drain electrode) of the TFT 11 is connected to the corresponding signal line SGNL1 to SGNL4. The gate electrode of the TFT 11 is connected to each of the gate lines GTL1 to GTL4. The counter electrode of the liquid crystal cell LC and the other electrode of the storage capacitor Cs are connected to the Cs line CsL1 in common between the pixels. A predetermined DC voltage is applied as a common voltage Vcom to the Cs line Cs L1.
In the pixel unit 11, one end of each of the gate lines GTL <b> 1 to GTL <b> 4 is connected to an output end of each row of the vertical scanner 12 disposed on the left side of the pixel unit 11 in the drawing, for example.
[0006]
The vertical scanner 12 performs a process of sequentially selecting each pixel PXL connected to the gate lines GTL1 to GTL4 in units of rows by scanning in the vertical direction (row direction) every field period.
That is, when the scanning pulse SP1 is applied from the vertical scanner 12 to the gate line GTL1, the pixels in each column of the first row are selected, and when the scanning pulse SP2 is applied to the gate line GTL2, the second row. A pixel in each column is selected. Similarly, scan pulses SP3 and SP4 are sequentially applied to the gate lines GTL3 and GTL4.
[0007]
For example, a horizontal scanner 13 is disposed above the pixel unit 11 in the drawing.
The horizontal scanner 13 sequentially samples the input video signal VDO every 1H (H is a horizontal scanning period), and performs processing of writing to each pixel PXL selected in units of rows by the vertical scanner 12.
As shown in FIG. 1, the horizontal scanner 13 employs a clock drive system, and includes a shift register 131, a clock extraction switch group 132, a phase adjustment circuit (PAC) group 133, and a sampling switch group 134. Have.
[0008]
The shift register 131 includes four shift stages (S / R stages) 131-1 to 131-4 corresponding to the pixel columns (four columns in this example) of the pixel unit 11, and includes a first clock generation circuit. When the horizontal start pulse HST is given by 14, the shift operation is performed in synchronization with the horizontal clocks HCK and HCKX having opposite phases. Thus, shift pulses SFTP1 to SFTP4 having the same pulse width as the cycles of the horizontal clocks HCK and HCKX are sequentially output from the shift stages 131-1 to 131-4 of the shift register 131.
[0009]
The clock extraction switch group 132 includes four switches 132-1 to 132-4 corresponding to the pixel columns of the pixel unit 11, and one end of each of the switches 132-1 to 132-4 is a first clock generator. The circuit 15 is alternately connected to clock lines DKL1 and DKXL1 for transmitting clocks DCKX and DCK.
That is, one end of each of the switches 132-1 and 132-3 is connected to the clock line DKXL1, and one end of each of the switches 132-2 and 132-4 is connected to the clock line DKL1.
Shift pulses SFTP1 to SFTP4 sequentially output from the shift stages 131-1 to 131-4 of the shift register 131 are applied to the switches 132-1 to 132-4 of the clock extraction switch group 132, respectively. When the shift pulses SFTP1 to SFTP4 are given from the shift stages 131-1 to 131-4 of the shift register 131, the switches 132-1 to 132-4 of the clock extraction switch group 132 respond to the shift pulses SFTP1 to SFTP4. The second clocks DCKX and DCK having opposite phases are alternately extracted by sequentially turning on.
[0010]
The phase adjustment circuit group 133 includes four phase adjustment circuits 133-1 to 133-4 corresponding to the pixel columns of the pixel unit 11, and each of the phase adjustment circuits 133-1 to 133-4 has a clock extraction switch group 132. After the phases of the second clocks DCKX and DCK extracted by the respective switches 132-1 to 132-4 are adjusted, they are supplied to the sampling switches of the corresponding sampling switch group 134.
[0011]
The sampling switch group 134 includes four sampling switches 134-1 to 134-4 corresponding to the pixel columns of the pixel unit 11, and one end of each of the sampling switches 134-1 to 134-4 receives the video signal VDO. It is connected to the input video line VDL1. The sampling switches 134-1 to 134-4 receive the clocks DCKX and DCK extracted by the switches 132-1 to 132-4 of the clock extraction switch group 132 and phase-adjusted by the phase adjustment circuit group 133 as sample hold pulses. Given as SHP1 to SHP4.
When the sample hold pulses SHP1 to SHP4 are given, the sampling switches 134-1 to 134-4 of the sampling switch group 134 are sequentially turned on in response to the sample hold pulses SHP1 to SHP4, whereby the video line VDL1. The video signal VDO input through the signal is sequentially sampled and supplied to the signal lines SGNL1 to SGNL4 of the pixel unit 11.
[0012]
  The first clock generation circuit14, A vertical start pulse VST for instructing the start of vertical scanning, vertical clocks VCK and VCKX having opposite phases as a reference for vertical scanning, and a command for starting the horizontal scanningHorizontalStart pulseHST, Generating horizontal clocks HCK and HCKX having opposite phases as horizontal scanning references, supplying a vertical start pulse VST and vertical clocks VCK and VCKX to the vertical scanner 12, and supplying the horizontal clocks HCK and HCKX to the horizontal scanner 13 and 2 is supplied to the second clock generation circuit 15.
[0013]
The second clock generation circuit 15 has the same period (T1 = T2) as the horizontal clocks (first clocks) HCK and HCKX generated by the first clock generation circuit 14 and has a small duty ratio and are opposite to each other. Phase second clocks DCK and DCKX are generated and supplied to the horizontal scanner 13. Here, the duty ratio is a ratio between the pulse width t and the pulse repetition period T in the pulse waveform.
For example, as shown in FIGS. 3A to 3D, the duty ratio (t1 / T1) of the horizontal clocks HCK and HCKX is 50%, and the duty ratio of the clocks DCK and DCKX (t2 / T2) is higher than this. Is smaller, that is, the pulse width t2 of the clocks DCK and DCKX is set narrower than the pulse width t1 of the horizontal clocks HCK and HCKX.
[0014]
In the horizontal scanner 13 described above, the shift pulses SFTP1 to SFTP4 sequentially output from the shift register 131 are not used as sample hold pulses, but clocks DCKX and DCK having opposite phases are alternately synchronized with the shift pulses SFTP1 to SFTP4. These clocks DCKX and DCK are used as sample hold pulses SHP1 to SHP via a phase adjustment circuit. Thereby, the dispersion | variation in the sample hold pulses SHP1-SHP can be suppressed. As a result, it is possible to remove ghosts caused by variations in the sample hold pulses SHP1 to SHP.
[0015]
In addition, the horizontal scanner 13 does not extract the horizontal clocks HCKX and HCK, which are the reference for the shift operation of the shift register 131, and use them as sample hold pulses, but has the same cycle and duty ratio as the horizontal clocks HCKX and HCK. Since small clocks DCKX and DCK are separately generated, and these clocks DCKX and DCK are extracted and used as sample hold pulses SHP1 to SHP, complete non-overlapping sampling between sampling pulses is performed during horizontal driving. Since this can be realized, it is possible to suppress the occurrence of vertical stripes due to overlap sampling.
[0016]
Here, for example, as shown in FIG. 4, the operation when the video signal VDO is written to the corresponding pixel at the Nth and N + 1th stages adjacent to each other will be described with reference to FIGS. To do.
In this case, for example, the video signal VDO, the drive signal DRVP-N of the N-th stage signal line SGNL-N, and the drive pulse DRVP-N + 1 of the (N + 1) -th stage signal line SGNL-N + 1 are shown in FIGS. In the case of the timing relationship shown in FIG. 5C, ideally, a white signal is written in the Nth stage and a black signal is written in the N + 1th stage, and there is no ghost as shown in FIG. An image is obtained.
[0017]
However, in LCDs using TFTs, transistor characteristics generally change due to panel aging. Due to this characteristic change, a pulse delay occurs in each transistor, and eventually the sample hold pulse SHP drifts with respect to its initial state.
Due to this drift, the optimum sample hold position with respect to the ghost shifts, and if the sample hold position set value at the time of initial shipment is maintained, the video signal at the adjacent stage is sampled and held, and a ghost is generated.
Specifically, as shown in FIGS. 6A to 6C, the drive signal DRVP-N of the Nth signal line SGNL-N and the drive pulse DRVP− of the N + 1th signal line SGNL-N + 1. N + 1 is delayed as indicated by the solid line after aging from the initial state indicated by the broken line. As a result, as shown in FIG. 6D, a black signal is written in the Nth stage, and a ghost GST occurs.
[0018]
In order to prevent the occurrence of ghost due to drift, a monitor circuit (dummy scanner) is arranged, the output of the sampling switch is output to the outside of the panel, and the change in phase from the initial state of the output is monitored by an external IC However, a countermeasure for feeding back the phase change to the panel input clock has become common (see, for example, Patent Document 2 or Patent Document 3).
[0019]
FIG. 7 is a block diagram showing a configuration example of a conventional liquid crystal display device provided with a monitor circuit 17. FIG. 8 is a circuit diagram showing a specific configuration example of a part of the monitor circuit 17 and the peripheral horizontal scanner 13 of FIG.
[0020]
The monitor circuit 17 in FIG. 8 is arranged adjacent to the first stage of the horizontal scanner 13, that is, the stage where the horizontal start pulse HST is first input and the shift operation is started.
The monitor circuit 17 is ideally configured in the same manner as the configuration of each stage of the horizontal scanner 13 in order to align the delay amount of the output pulse of each stage of the horizontal scanner 13.
The monitor circuit 17 in FIG. 8 receives a horizontal start pulse HST, outputs a shift pulse SFTP17, a shift stage (S / R stage) 171, and a switch 172 that extracts the second clock DCKX by the shift pulse SFTP17 generated by the shift stage 171. A phase adjustment circuit 173 that generates a sample hold pulse SHP17 composed of two signals that take a complementary level by adjusting the phase of the clock DCLX extracted by the switch 171, and a first sample hold pulse SHP17 by the phase adjustment circuit 173. A sampling switch 174 whose conduction is controlled between the terminal and the second terminal is provided.
[0021]
The sampling switch 174 of the monitor circuit 17 has a first terminal grounded and the other end connected to one end of the monitor line MNTL1. The other end of the monitor line MNTL1 is connected to a feedback IC 18 outside the LCD panel.
The monitor line MNTL1 is pulled up outside the panel, and the external feedback IC 18 monitors the phase change from the initial state from the timing when the sampling switch 173 is turned on and the monitor line MNTL1 transitions to the ground level. The amount of phase change is fed back to the panel input clock.
In the example of FIG. 8, the horizontal clocks HCKX, HCK and the like are configured to be generated by an external feedback IC 18.
[0022]
[Patent Document 1]
Japanese Patent Application No. 2001-109460
[Patent Document 2]
Japanese Patent Laid-Open No. 11-119746
[Patent Document 3]
JP 2000-298459 A
[0023]
[Problems to be solved by the invention]
By the way, the active matrix type liquid crystal display device adopting the above-described dot sequential driving method is used as a display panel of a projection type liquid crystal display device (liquid crystal projector), that is, an LCD panel. In the case of color, three LCD panels are arranged corresponding to each of the three primary colors R (red), G (green), and B (blue).
In this case, due to the relationship between the optical system and the optical path, it is necessary to reverse one LCD panel with the other LCD panel and perform reverse scanning in the horizontal scanner.
For this reason, the LCD panel is configured to have a function of scanning from the right side in the drawing, that is, a reverse scanning function in addition to the function of scanning from the left side in the drawing of FIG.
[0024]
However, in a circuit in which one conventional monitor circuit (dummy scanner) is arranged, in a horizontal scanner in which the phase of the clock is inverted by left-right inversion, the number of shift registers provided in the horizontal scanner 13 is generally an even number. Therefore, there are the following disadvantages.
[0025]
As shown in FIGS. 9A to 9K, when scanning from left to right, for example, as shown in FIG. 9B, pulses (1), (2), (3) of the horizontal clock HCK. The first sample hold pulse SHP1 of the horizontal scanner 13 and the sample of the monitor circuit 17 at the second timing {circle over (2)} of the horizontal clock HCK and at the timing of the second clock DCKX. The hold pulse SHP17 is generated at substantially the same timing, and image display is performed without any problem.
[0026]
On the other hand, as shown in FIGS. 10A to 10K, when scanning from right to left, for example, as shown in FIG. 10B, pulses (1) and (2) of the horizontal clock HCK. When the symbols ▼ and (3) are attached, the sample hold pulse SHP17 of the monitor circuit 17 is generated at the first timing (1) of the horizontal clock HCK and at the timing of the second clock DCKX. SHP1 is generated at timing (2) and at the timing of the first clock DCK.
That is, in this case, the phase of the sample hold pulse SHP17 for feedback is changed by one pulse due to left-right inversion, and accurate feedback cannot be performed. In such a case, the image is shifted by half, and a highly accurate image table cannot be performed.
[0027]
The object of the present invention is that even in a horizontal scanner that can invert the scan direction and in which the phase of the clock is inverted in the scan direction inversion, the phase of the output potential change does not change, and the accuracy does not change even if operated in any scan direction An object of the present invention is to provide a display device and a projection display device that can realize high image display.
[0028]
[Means for Solving the Problems]
  In order to achieve the above object, a display device according to a first aspect of the present invention includes a pixel portion in which a plurality of pixels are arranged in a matrix and signal lines are wired for each pixel column, and is held at a first potential. Generating a monitor signal and an inverted clock signal that are at least opposite to each other as a reference for horizontal scanning, and monitoring a potential change of the monitor line, and at least based on a change in timing of the potential change A control circuit for correcting the generation timing of the clock signal and the inverted clock signal; a horizontal scanner; a first monitor circuit; and a second monitor circuit. The horizontal scanner has a plurality of shift stages connected in cascade. In accordance with the switching signal, it is possible to switch between a first scan operation that sequentially shifts from the first stage to the last stage and a second scan operation that sequentially shifts from the last stage to the first stage, At the time of the first scan operation or the second scan operation, the shift register that sequentially outputs the shift pulse from each shift stage in synchronization with the clock signal and the inverted clock signal and the shift stage corresponding to the shift register output In response to the shift pulse, the clock signal and the inverted clock signal are alternately extracted sequentially and output as a sample and hold pulse, and the video signal is converted into a sample and hold pulse by each switch of the first switch group. A second switch group that sequentially samples in response and supplies the corresponding signal lines to the corresponding signal lines of the pixel unit, and the first monitor circuit includes a shift register of the horizontal scanner during the first scan operation. It is connected to the final shift stage and the signal from the final shift stage is shifted in. Then, a shift stage that outputs a shift pulse in synchronization with the clock signal and the inverted clock signal, and the final shift stage of the clock signal and the inverted clock signal in response to the shift pulse output from the shift stage. Extracts a signal different from the extracted signal and outputs it as a sample and hold pulse, and sets the potential of the monitor line to the second potential in response to the sample and hold pulse from the third switch. A second switch, and the second monitor circuit is connected to the first shift stage of the shift register in the horizontal scanner during the second scan operation, and when the signal from the first shift stage is shifted in, the second monitor circuit Shift that outputs a shift pulse in synchronization with the signal and inverted clock signal In response to the shift pulse output from the stage and the shift stage, a signal different from the signal extracted by the first stage shift stage is extracted from the clock signal and the inverted clock signal and output as a sample hold pulse. The monitor line in response to the sample hold pulse by the switch and the fifth switch.TheA sixth switch set to the second potential.
[0029]
  A projection display device according to a second aspect of the present invention generates a monitor line held at a first potential, a clock signal and an inverted clock signal that are at least opposite to each other as a reference for horizontal scanning, and A control circuit that monitors the potential change of the monitor line and corrects at least the generation timing of the clock signal and the inverted clock signal based on the change in timing of the potential change, and a plurality of pixels are arranged in a matrix, and each pixel column A display panel including a pixel portion to which a signal line is wired, a horizontal scanner, a first monitor circuit, and a second monitor circuit, irradiation means for irradiating light to the display panel, and the display panel A horizontal scanner of the display panel, wherein a plurality of shift stages are connected in cascade, and the initial scanning is performed in response to a switching signal. The first scan operation that sequentially shifts from the first stage to the second stage and the second scan operation that sequentially shifts from the last stage to the first stage can be switched, and the clock signal and the inverted clock signal can be switched during the first scan operation or the second scan operation. A shift register that sequentially outputs a shift pulse from each shift stage in synchronism, and the clock signal and the inverted clock signal are sequentially extracted in response to the shift pulse output from the corresponding shift stage of the shift register. A first switch group that outputs as a hold pulse, and a second switch that sequentially samples a video signal in response to a sample hold pulse by each switch of the first switch group and supplies it to each corresponding signal line of the pixel section. A first monitor circuit of the display panel includes: A shift stage that is connected to the last shift stage of the shift register in the horizontal scanner during one scan operation and outputs a shift pulse in synchronization with the clock signal and the inverted clock signal when a signal from the last shift stage is shifted in; A third switch for extracting a signal different from the signal extracted by the final shift stage from the clock signal and the inverted clock signal in response to the shift pulse output from the shift stage, and outputting as a sample hold pulse; A fourth switch for setting the potential of the monitor line to a second potential in response to a sample hold pulse by the third switch.the aboveThe second monitor circuit of the display panel is connected to the first shift stage of the shift register in the horizontal scanner during the second scan operation. When the signal from the first shift stage is shifted in, the second monitor circuit is synchronized with the clock signal and the inverted clock signal. In response to the shift pulse output from the shift stage and the shift pulse output from the shift stage, a signal different from the signal extracted by the first stage shift stage is extracted from the clock signal and the inverted clock signal. A fifth switch for outputting a hold pulse; and the monitor line in response to a sample hold pulse by the fifth switch for outputting a video signal.TheA sixth switch set to the second potential.
[0030]
Preferably, the first scan operation and the second scan operation are started in response to a horizontal start pulse, and the horizontal start pulse is supplied to the first shift stage of the shift register during the first scan operation. At the time of the second scan operation, it is supplied to the last shift stage of the shift register and not supplied to the first monitor circuit and the second monitor circuit.
[0031]
  Preferably, the first monitor circuit has an arrangement position of a final shift stage of the horizontal scanner.Adjacent toThe second monitor circuit is disposed at the position of the first shift stage of the horizontal scanner.AdjacentHas been placed.
[0032]
The monitor line is shared by the first monitor circuit and the second monitor circuit.
Preferably, the monitor lines are individually formed on a first monitor line connected to the first monitor circuit and a second monitor line connected to the second monitor circuit.
[0033]
The number of shift stages in the shift register of the horizontal scanner is an even number.
[0034]
  Preferably, based on the clock signal and the inverted clock signal generated by the control circuit, the second clock signal and the second inverted signal having the same period and a small duty ratio with respect to the clock signal and the inverted clock signal. Clock generating means for generating a clock signal and supplying it to the horizontal scanner, the first monitor circuit, and the second monitor circuit, each switch of the first switch group of the horizontal scanner, and a third of the first monitor circuit The switch, the fifth switch of the second monitor circuit, has two clock signals by the clock generation means.OrThe second inverted clock signal is extracted.
[0035]
The display element of the pixel is a liquid crystal cell.
[0036]
According to the present invention, for example, in a control circuit, generation of a clock signal and an inverted clock signal which are opposite in phase to each other as a reference for horizontal scanning is generated, and is generated in the horizontal scanner and the first monitor circuit (and / or the second monitor circuit). Supplied.
Further, for example, the first scan operation or the second scan operation for scanning in the direction opposite to the first scan operation is designated by the switching signal.
When the first scan operation is designated, for example, a horizontal start pulse is supplied to the first shift stage in the shift register of the horizontal scanner.
In the horizontal scanner, a shift pulse is sequentially output from each shift stage to each corresponding switch of the first switch group in synchronization with the clock signal and the inverted clock signal.
In the first switch group, the clock signal and the inverted clock signal are alternately extracted sequentially in response to the shift pulse output from the corresponding shift stage. Then, the extracted signal is output as a sample hold pulse to each corresponding switch of the second switch group.
In the second switch group, the input video signals are sequentially sampled in response to sample and hold pulses by the respective switches of the first switch group, and are supplied to the corresponding signal lines of the pixel portion.
When the above-described first scan operation in the horizontal scanner is performed up to the final shift stage, the signal from the final shift stage of the horizontal scanner is shifted into the shift stage of the first monitor circuit. As a result, the shift pulse is output to the third switch in synchronization with the clock signal and the inverted clock signal at the shift stage of the first monitor circuit.
In the third switch, a signal different from the signal extracted by the last shift stage of the horizontal scanner is extracted from the clock signal and the inverted clock signal in response to the shift pulse output from the shift stage, and the signal is output as the sample hold pulse. 4 is output to the switch.
In the fourth switch of the first monitor circuit, the potential of the monitor line is set from the first potential to the second potential (for example, ground potential) in response to the sample hold pulse by the third switch.
In the control circuit, the potential change of the monitor line is monitored. Specifically, in the control circuit, the change in the phase from the initial state of the output of the first monitor circuit is monitored, and the generation timing of the clock signal and the inverted clock signal is corrected so as to cancel the change in the phase. .
Thereby, the drift of the sample hold pulse due to the change in the characteristics of the transistor due to panel aging or the like is corrected.
[0037]
When the second scan operation is designated, for example, a horizontal start pulse is supplied to the final shift stage in the shift register of the horizontal scanner.
In the horizontal scanner, a shift pulse is sequentially output from each shift stage to each corresponding switch of the first switch group in synchronization with the clock signal and the inverted clock signal.
In the first switch group, the clock signal and the inverted clock signal are alternately extracted sequentially in response to the shift pulse output from the corresponding shift stage. Then, the extracted signal is output as a sample hold pulse to each corresponding switch of the second switch group.
In the second switch group, the input video signals are sequentially sampled in response to sample and hold pulses by the respective switches of the first switch group, and are supplied to the corresponding signal lines of the pixel portion.
When the first scan operation in the horizontal scanner is performed up to the first shift stage, the signal from the first shift stage of the horizontal scanner is shifted into the shift stage of the second monitor circuit. Thus, the shift pulse is output to the fifth switch in synchronization with the clock signal and the inverted clock signal at the shift stage of the second monitor circuit.
In the fifth switch, in response to the shift pulse output from the shift stage, a signal different from the signal extracted by the first stage shift stage of the horizontal scanner is extracted from the clock signal and the inverted clock signal. 6 is output to the switch 6.
In the sixth switch of the second monitor circuit, the potential of the monitor line is set from the first potential to the second potential (for example, ground potential) in response to the sample hold pulse by the fifth switch.
In the control circuit, the potential change of the monitor line is monitored. Specifically, in the control circuit, the change in the phase from the initial state of the output of the first monitor circuit is monitored, and the generation timing of the clock signal and the inverted clock signal is corrected so as to cancel the change in the phase. .
Thereby, the drift of the sample hold pulse due to the change in the characteristics of the transistor due to panel aging or the like is corrected.
As described above, even in a horizontal scanner in which the clock phase is inverted in the scan direction inversion, the phase of the output potential change does not change, and a high-precision image display is realized regardless of the scan direction.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0039]
First embodiment
FIG. 11 is a circuit diagram showing a configuration example of an active matrix liquid crystal display device of a dot sequential drive system according to the first embodiment of the present invention using, for example, a liquid crystal cell as a pixel display element (electro-optic element). .
[0040]
As shown in FIG. 11, the liquid crystal display device 20 includes an effective pixel portion (PXLP) 21, a vertical scanner (VSCN) 22, a horizontal scanner (HSCN) 23, a first monitor circuit (MNT1) 24, a second monitor circuit ( MNT2) 25, a clock generation circuit (GEN) 26, and a feedback control circuit (FDBCIC) 27 including a timing generator are included as main components.
As shown in FIG. 12, the vertical scanner may be arranged not only on one side (left side in the figure) of the pixel unit 21 but also on both sides (left side and right side in the figure). In addition, a signal line precharge circuit (PRCG) 28 is provided. The effective pixel unit (PXLP) 21, the vertical scanner (VSCN) 22 (22-1 and 22-2), the horizontal scanner (HSCN) 23, the first monitor circuit 24, the second monitor circuit 25, and the clock generation circuit (GEN) ) 26 (and the precharge circuit 27) are mounted on the display panel (LCD panel) 30.
[0041]
In the pixel unit 21, a plurality of pixels PXL are arranged in a matrix of n rows and m columns. Here, in order to simplify the drawing, a case of a pixel array of 4 rows and 4 columns is shown as an example.
Each of the pixels PXL arranged in a matrix form a thin film transistor (TFT) 21 that is a pixel transistor, a liquid crystal cell LC 21 having a pixel electrode connected to the drain electrode of the TFT 21, and a drain electrode of the TFT 21. And a storage capacitor Cs 21 to which the electrodes are connected.
For each of these pixels PXL, signal lines SGNL21 to SGNL24 are wired along the pixel arrangement direction for each column, and gate lines GTL21 to GTL24 are wired along the pixel arrangement direction for each row.
In each pixel PXL, the source electrode (or drain electrode) of the TFT 21 is connected to the corresponding signal lines SGNL21 to SGNL24. The gate electrode of the TFT 21 is connected to each of the gate lines GTL21 to GTL24. The counter electrode of the liquid crystal cell LC21 and the other electrode of the storage capacitor Cs21 are connected to the Cs line CsL21 in common among the pixels. A predetermined DC voltage is applied as a common voltage Vcom to the Cs line Cs L21.
In the pixel unit 21, one end of each of the gate lines GTL <b> 21 to GTL <b> 24 is connected to the output end of each row of the vertical scanner 22 disposed on the left side of the pixel unit 21 in the drawing, for example.
[0042]
The vertical scanner 22 performs a process of sequentially selecting each pixel PXL connected to the gate lines GTL21 to GTL24 in units of rows by scanning in the vertical direction (row direction) every field period.
That is, when the scanning pulse SP21 is applied from the vertical scanner 22 to the gate line GTL21, the pixel PXL in each column of the first row is selected, and when the scanning pulse SP22 is applied to the gate line GTL22, the second row. The pixels PXL in each column are selected. Similarly, scanning pulses SP23 and SP24 are sequentially applied to the gate lines GTL23 and GTL24.
[0043]
For example, a horizontal scanner 23, a first monitor circuit (first dummy scanner) 24, and a second monitor circuit (second dummy scanner) 25 are arranged above the pixel unit 21 in the drawing.
[0044]
The horizontal scanner 23 sequentially samples the input video signal VDO every 1H (H is a horizontal scanning period), and performs processing of writing to each pixel PXL selected in units of rows by the vertical scanner 22.
As shown in FIG. 11, the horizontal scanner 23 employs a clock drive system, and includes a shift register 231, a clock extraction switch group 232, a phase adjustment circuit (PAC) group 233, and a sampling switch group 234. Have.
[0045]
The shift register 231 includes four shift stages (S / R stages) 231-1 to 231-4 corresponding to the pixel columns (four columns in this example) of the pixel unit 21, for example, an external feedback control circuit 27, when the horizontal start pulse HST is applied to the first (first stage) shift stage 231-1 or the fourth (final) shift stage 231-4, the horizontal clock HCK and the inverted horizontal clock HCKX (hereinafter referred to as both) The first shift operation (normal shift operation) or the second shift operation (reverse shift operation) is performed in synchronization with the horizontal clock.
Thus, shift pulses SFTP231 to SFTP234 having the same pulse width as the cycles of the horizontal clocks HCK and HCKX are sequentially output from the shift stages 231-1 to 231-4 of the shift register 231.
[0046]
Here, the normal shift operation is from left to right in FIG. 11, that is, the first shift stage 231-1, the second shift stage 231-2, the third shift stage 231-3, and the fourth shift stage in the first stage. It means that scanning is performed in the order of 231-4 and further the second monitor circuit 25.
On the other hand, the reverse shift operation is from right to left in FIG. 11, that is, the fourth shift stage 231-4, the third shift stage 231-3, the second shift stage 231-2, and the first shift stage 231-1. Further, it means scanning in the order of the first monitor circuit 24.
[0047]
The normal shift operation and the reverse shift operation are determined by a shift direction switching signal RGT given from the outside.
For example, the shift register 231 of the horizontal scanner 23 performs a normal shift operation when receiving the shift direction switching signal RGT at a high level, and performs a reverse shift operation when receiving it at a low level.
[0048]
The shift register 231 receives the horizontal start pulse HST and propagates the shift pulse SFTP in the normal direction from the first shift stage 231-1 to the fourth shift stage 231-4 and the second monitor circuit 25, or the fourth shift stage. Switching circuits 2311, 2312, and 2313 for switching whether to propagate in the reverse direction from 231-4 to the first shift stage 231-1 and the first monitor circuit 24 are inserted between the respective shift stages.
Specifically, a switching circuit 2311 is inserted between the first shift stage 231-1 and the second shift stage 231-2, and a switching circuit 2312 is inserted between the second shift stage 231-2 and the third shift stage 231-3. The switching circuit 2313 is inserted between the third shift stage 231-3 and the fourth shift stage 231-4.
In the shift register 231, a fourth shift stage 231-4 and a shift stage 251 described later of the second monitor circuit 25 are connected, and a switching circuit 2314 is inserted in the connection path. Similarly, the first shift stage 231-1 and a shift stage 241 (to be described later) of the first monitor circuit 24 are connected, and a switching circuit 2315 is inserted in the connection path.
Each switching circuit 2311 to 2315 receives the shift direction switching signal RGT and switches the signal propagation direction to the normal direction or the reverse direction.
[0049]
However, the switching circuit 2314 between the shift stage 251 described later of the fourth shift stage 231-4 and the second monitor circuit 25 and the switching between the shift stage 241 described later of the first shift stage 231-1 and the first monitor circuit 24 are switched. The circuit 2315 is not necessarily provided.
[0050]
FIG. 13 is a circuit diagram showing a configuration example of the switching circuit 2311 (˜2315) inserted between the shift stages of the shift register. In FIG. 3, the switching circuit 2311 inserted between the first shift stage 231-1 and the second shift stage 131-2 is shown as an example, but the other switching circuits 3212 to 2315 have the same configuration. is doing.
[0051]
As shown in FIG. 13, the switching circuit 2311 has transfer gates TM231-1, TM231-2 and an inverter INV231.
The transfer gate TMG231-1 has a first terminal T1 and a second terminal T2 that connect the sources and drains of a p-channel MOS (PMOS) transistor PT231-1 and an n-channel MOS (NMOS) transistor NT231-1. Yes.
The gate of the NMOS transistor NT231-1 is connected to the supply line of the switching signal RGT, and the gate of the PMOS transistor PT231-1 is connected to the output terminal of the inverter INV231 that outputs the signal RGTX obtained by inverting the level of the switching signal RGT. The first terminal T1 is connected to the output terminal O1 of the first shift stage (left shift stage) 231-1, and the second terminal T2 is connected to the input terminal I1 of the second shift stage (right shift stage) 231-2. Has been.
[0052]
The transfer gate TMG231-2 connects the sources and drains of the PMOS transistor PT231-2 and NMOS transistor NT231-2 to form a first terminal T1 and a second terminal T2.
The gate of the PMOS transistor PT231-2 is connected to the supply line of the switching signal RGT, and the gate of the NMOS transistor NT231-2 is connected to the output terminal of the inverter INV231 that outputs the signal RGTX obtained by inverting the level of the switching signal RGT. The first terminal T1 is connected to the input terminal I1 of the first shift stage (left shift stage) 231-1, and the second terminal T2 is connected to the output terminal O1 of the second shift stage (right shift stage) 231-2. Has been.
[0053]
In the switching circuit 2311 having such a configuration, for example, when the switching signal RGT is supplied at a high level, the output signal RGTX of the inverter INV231 becomes a low level, and the PMOS transistor PT231-1 and the NMOS transistor NT231 of the transfer gate TMG231-1 -1 conducts.
On the other hand, the PMOS transistor PT231-2 and the NMOS transistor NT231-2 of the transfer gate TMG231-2 are held in a non-conductive state.
Therefore, the signal (horizontal start pulse HST) output from the output terminal O1 of the first shift stage 231-1 is propagated to the input terminal I1 of the second shift stage 231-2 through the transfer gate TMG231-1. That is, a normal shift operation is performed.
[0054]
On the other hand, when the switching signal RGT is supplied at a low level, the output signal RGTX of the inverter INV231 becomes a high level, and the PMOS transistor PT231-1 and the NMOS transistor NT231-1 of the transfer gate TMG231-1 become non-conductive. Retained.
On the other hand, the PMOS transistor PT231-2 and the NMOS transistor NT231-2 of the transfer gate TMG231-2 become conductive.
Therefore, the signal (horizontal start pulse HST) output from the output terminal O1 of the second shift stage 231-2 is propagated to the input terminal I1 of the first shift stage 231-1 through the transfer gate TMG231-2. That is, a reverse shift operation is performed.
[0055]
3, the inverter INV231 is provided in each switching circuit. However, an inverter is provided in the input stage of the switching signal RGT, and the inverted output signal RGTX is supplied to each switching circuit together with the switching signal RGT. It is also possible to configure as described above.
[0056]
The clock extraction switch group 232 includes four switches 232-1 to 232-4 corresponding to the pixel columns of the pixel unit 21, and one end of each of the switches 232-1 to 232-4 is formed by the clock generation circuit 26. The clock lines DKL1 and DKXL1 that transmit the second clock DCK and the second inverted clock DCKX are alternately connected.
That is, one end of each of the switches 232-1 and 232-3 corresponding to the odd columns of the pixel columns of the pixel unit 21 is connected to the clock line DKXL21, and the switches 232-2 and 232 corresponding to the even columns of the pixel columns of the pixel unit 21 are connected. Each end of 4 is connected to the clock line DKL21.
Shift pulses SFTP231 to SFTP234 that are sequentially output from the shift stages 231-1 to 231-4 of the shift register 231 are applied to the switches 232-1 to 232-4 of the clock extraction switch group 232, respectively.
The switches 232-1 to 232-4 of the clock extraction switch group 232 respond to the shift pulses SFT23P1 to SFTP234 when the shift pulses SFTP231 to SFTP234 are given from the shift stages 231-1 to 231-4 of the shift register 231. Then, the clocks DCKX and DCK having opposite phases are alternately extracted by sequentially turning on.
[0057]
The phase adjustment circuit group 233 includes four phase adjustment circuits 233-1 to 233-4 corresponding to the pixel columns of the pixel unit 21, and each phase adjustment circuit 233-1 to 233-4 has a clock extraction switch group 232. After the phases of the clocks DCKX and DCK extracted by the switches 232-1 to 232-4 are adjusted, they are supplied to the sampling switches of the corresponding sampling switch group 234.
[0058]
The sampling switch group 234 has four sampling switches 234-1 to 234-4 corresponding to the pixel columns of the pixel unit 21, and one end of each of these sampling switches 234-1 to 234-4 receives the video signal VDO. It is connected to an input video line VDL21.
The sampling switches 234-1 to 234-4 receive the clocks DCKX and DCK extracted by the switches 232-1 to 232-4 of the clock extraction switch group 232 and phase-adjusted by the phase adjustment circuit group 233 as sample hold pulses. It is given as SHP231 to SHP234.
When the sample hold pulses SHP231 to SHP234 are given, the sampling switches 234-1 to 234-4 of the sampling switch group 234 are sequentially turned on in response to the sample hold pulses SHP231 to SHP234, whereby the video line VDL21. Are sequentially sampled and supplied to the signal lines SGNL21 to SGNL24 of the pixel unit 21.
[0059]
The first monitor circuit 24 corresponds to the fourth pixel column of the pixel unit 21 of the horizontal scanner 23, that is, the fourth shift in which the horizontal start pulse HST is first input and the second shift operation (reverse shift operation) is started. The fourth stage scanner unit including the stage 231-4, the extraction switch 232-4, the phase adjustment circuit 233-4, and the sampling switch 234-4 is arranged adjacent to the right side in FIG.
The first monitor circuit 24 is configured similarly to the configuration of each stage scanner unit of the horizontal scanner 23 in order to equalize the delay amount of the output pulse of each stage of the horizontal scanner 23.
[0060]
Specifically, the first monitor circuit 24 is connected to the fourth shift stage 231-4 of the shift register 231 of the horizontal scanner 23 without receiving the horizontal start pulse HST. The shift stage (S / R stage) 241 that receives the shift pulse SFTP 234 shifted in from 231-4 and outputs the shift pulse SFTP 241 in synchronization with the horizontal clocks HCK and HCKX, and the shift pulse generated by the shift stage 241. A switch (third switch) 242 that is extracted by the SFTP 241; a phase adjustment circuit 243 that generates a sample hold pulse SHP241 that includes two signals that take the complementary levels by adjusting the phase of the clock DCKX extracted by the switch 242; Sample hold pulse by adjustment circuit 243 The HP241 sampling switch in which the first terminal T1 is controlled in conduction between the second terminal T2 and a (fourth switch) 244.
[0061]
The sampling switch 244 of the first monitor circuit 24 is composed of an analog switch in which the sources and drains of the PMOS transistor and the NMOS transistor are connected, the first terminal T1 is grounded, and the other end is connected to one end of the monitor line MNTL21. . The monitor line MNTL21 is generated by a low resistance wiring such as aluminum (Al).
The monitor line MNTL21 is pulled up by a pullup resistor R21 outside the LCD panel, and the other end is connected to the input terminal of the feedback control circuit 27 via the buffer BF21.
[0062]
The second monitor circuit 25 corresponds to the first pixel column (first pixel column) of the pixel unit 21 of the horizontal scanner 23, that is, the first shift operation (normal shift operation) is performed when the horizontal start pulse HST is input first. The fourth stage scanner unit including the first shift stage 231-1 to be started, the extraction switch 232-1, the phase adjustment circuit 233-1, and the sampling switch 234-1 is arranged adjacent to the left side in FIG.
The second monitor circuit 25 is configured similarly to the configuration of each stage scanner unit of the horizontal scanner 23 in order to equalize the delay amount of the output pulse of each stage of the horizontal scanner 23.
[0063]
Specifically, the second monitor circuit 25 is connected to the first shift stage 231-1 of the shift register 231 of the horizontal scanner 23 without receiving the horizontal start pulse HST, and this first shift stage during the reverse shift operation. The shift stage (S / R stage) 251 that receives the shift pulse SFTP 231 shifted in from 231-1 and outputs the O shift pulse SFTP 251 in synchronization with the horizontal clocks HCK and HCKX, and the clock DCK is shifted by the shift stage 251 A switch (fifth switch) 252 that is extracted by the pulse SFTP251, a phase adjustment circuit 253 that generates a sample hold pulse SHP251 that includes two signals that take the complementary level by adjusting the phase of the clock DCK extracted by the switch 252; Sample hold pulse SH by phase adjustment circuit 243 The 251 sampling switch in which the first terminal T1 is controlled in conduction between the second terminal T2 has the (sixth switch) 254.
[0064]
The sampling switch 254 of the second monitor circuit 25 is an analog switch in which the sources and drains of the PMOS transistor and the NMOS transistor are connected to each other, the first terminal T1 is grounded, and the other end is a monitor line shared with the first monitor circuit 24. It is connected to one end of MNTL21.
[0065]
As described above, in the present embodiment, the first monitor circuit 24 and the second monitor circuit 25 use different clocks to be extracted by the extraction switches 242 and 252. Here, the first monitor circuit 24 extracts the clock DCKX, and the second monitor circuit 25 extracts the clock DCK.
[0066]
Further, since the horizontal start pulse HST is not input to the first monitor circuit 24 and the second monitor circuit 25, an external output pulse can be obtained only from the monitor circuit at the scan end.
That is, an output pulse is obtained from the first monitor circuit 24 at the right end in the normal scan operation (scan from left to right), and from the second monitor circuit 25 at the left end in the reverse scan operation (scan from right to left). An output pulse is obtained.
[0067]
The clock generation circuit 26 is the second clock having the same period (T1 = T2) as the horizontal clocks (first clocks) HCK and HCKX generated by the feedback control circuit 27 and having a low duty ratio and opposite phases. DCK and DCKX are generated and supplied to the first monitor circuit 24, the horizontal scanner 23, and the second monitor circuit 25 through the clock lines DKL1 and DKXL1. Here, the duty ratio is a ratio between the pulse width t and the pulse repetition period T in the pulse waveform.
For example, as shown in FIGS. 3A to 3D, the duty ratio (t1 / T1) of the horizontal clocks HCK and HCKX is 50%, and the duty ratio of the clocks DCK and DCKX (t2 / T2) is higher than this. Is smaller, that is, the pulse width t2 of the clocks DCK and DCKX is set narrower than the pulse width t1 of the horizontal clocks HCK and HCKX.
[0068]
The feedback control circuit 27 includes a vertical start pulse VST for instructing the start of vertical scanning, vertical clocks VCK and VCKX having opposite phases as a reference for vertical scanning, a vertical start pulse VST for instructing the start of horizontal scanning, and a reference for horizontal scanning. The horizontal clocks HCK and HCKX having opposite phases to each other are generated, the vertical start pulse VST and the vertical clocks VCK and VCKX are supplied to the vertical scanner 22, the horizontal clocks HCK and HCKX are supplied to the horizontal scanner 23, the first monitor circuit 24, This is supplied to the second monitor circuit 25 and the clock generation circuit 26.
Further, the feedback control circuit 27 generates a horizontal start pulse HST and supplies it only to the first shift stage 231-1 and the second shift stage 231-2 of the shift register 231 of the horizontal scanner 23. The voltage is not supplied to the shift stage 241 and the shift stage 251 of the second monitor circuit 25.
Further, the feedback control circuit 27 changes the phase from the initial state or reverse scan operation from the timing when the sampling switch 244 of the first monitor circuit 24 in the normal scan operation becomes conductive and the monitor line MNTL21 changes to the ground level. The phase change from the initial state is monitored from the timing when the sampling switch 254 of the second monitor circuit 25 is turned on and the monitor line MNTL21 transits to the ground level, and the phase change is inverted to the horizontal clock HCK of the panel input. Feedback is performed to the horizontal clock HCKX, and control is performed to prevent the occurrence of a ghost caused by the sample hold pulse SHP drifting with respect to its initial state.
[0069]
Next, the normal scan operation and the reverse scan operation with the above configuration will be described with reference to the timing charts of FIGS. 14A to 14M and FIGS. 15A to 15M.
[0070]
First, the normal scan operation will be described with reference to the timing charts of FIGS.
[0071]
In this case, the scan direction switching signal RGT is set to a high level and supplied to the shift register 231 of the horizontal scanner 23. As a result, a path through which the switching circuits 2311 to 2314 inserted between the shift stages propagate signals from left to right is formed. That is, the first shift stage 231-1 to the second shift stage 231-2, the second shift stage 231-2 to the third shift stage 231-3, the third shift stage 231-3 to the fourth shift stage 231-4, Further, a signal propagation path through which the horizontal start pulse HST is sequentially shifted is formed in the shift stage 241 of the first monitor circuit 24.
[0072]
In this state, the feedback control circuit 27 generates a horizontal start pulse HST as shown in FIG. 14A and supplies it to the first shift stage 231-1 of the shift register 231 in the horizontal scanner 23. The horizontal start pulse HST is not supplied to the shift stage 241 of the first monitor circuit 24.
In the feedback control circuit 27, as shown in FIGS. 14B and 14C, horizontal clocks HCK and HCKX having opposite phases are generated, and the first shift stage 231 of the shift register 231 in the horizontal scanner 23 is generated. −1 to the fourth shift stage 231-4, the shift stage 241 of the first monitor circuit 24, and the clock generation circuit 26.
In the clock generation circuit 26, as shown in FIGS. 14D and 14E, the horizontal clocks HCK and HCKX generated by the feedback control circuit 27 have the same period (T1 = T2) and the duty ratio. Small, opposite-phase clocks DCK and DCKX are generated and supplied to the first monitor circuit 24, the horizontal scanner 23, and the second monitor circuit 25 through the clock lines DKL1 and DKXL1.
[0073]
  In the feedback control circuit 27, the vertical start pulse VST for instructing the start of vertical scanning, the vertical clocks VCK and VCKX having opposite phases as the reference for the vertical scanning, and the start of horizontal scanning are instructed.HorizontalStart pulseHSTAre generated and supplied to the vertical scanner 22.
[0074]
In the shift register 231 of the horizontal scanner 23, in the first shift stage 231-1 to which the horizontal start pulse HST is supplied by the external feedback control circuit 27, in synchronization with the reverse-phase horizontal clocks HCK and HCKX, FIG. As shown in (F), a shift pulse SFTP 231 having the same pulse width as that of the horizontal clocks HCK and HCKX is output to the extraction switch 232-1. Further, the shift pulse SFTP 231 is shifted in from the first shift stage 231-1 to the second shift stage 231-2.
The extraction switch 232-1 corresponding to the first shift stage 231-1 is turned on in response to the shift pulse SFTP231, and the clock output to the clock line DKXL1 as shown in FIGS. After DCKX is extracted and phase-adjusted by the phase adjustment circuit 233-1, it is supplied to the sampling switch 234-1 as the sample hold pulse SHP231.
Accordingly, the sampling switch 234-1 is turned on in response to the sample hold pulse SHP231, and the video signal VDO input through the video line VDL21 is sampled and supplied to the signal line SGNL21 of the pixel unit 21.
[0075]
Next, in the second shift stage 231-2 in which the shift pulse SFTP 231 is shifted in from the first shift stage 231-1, as shown in FIG. 14 (G) in synchronization with the reverse phase horizontal clocks HCK and HCKX. A shift pulse SFTP 232 having the same pulse width as that of the horizontal clocks HCK and HCKX is output to the extraction switch 232-2. Further, the shift pulse SFTP232 is shifted in from the second shift stage 231-2 to the third shift stage 231-3.
The extraction switch 232-2 corresponding to the second shift stage 231-2 is turned on in response to the shift pulse SFTP232 and, as shown in FIGS. 14D and 14K, the clock output to the clock line DKL1. After the DCK is extracted and phase-adjusted by the phase adjustment circuit 233-2, it is supplied to the sampling switch 234-2 as the sample hold pulse SHP 232.
Accordingly, the sampling switch 234-2 is turned on in response to the sample hold pulse SHP232, and the video signal VDO input through the video line VDL21 is sampled and supplied to the signal line SGNL22 of the pixel unit 21.
[0076]
Next, in the third shift stage 231-3 in which the shift pulse SFTP232 is shifted in from the second shift stage 231-2, the period of the horizontal clocks HCK and HCKX is the same as that of the horizontal clocks HCK and HCKX having opposite phases. A shift pulse SFTP233 having a pulse width is output to the extraction switch 232-3. Further, the shift pulse SFTP233 is shifted in from the third shift stage 231-3 to the fourth shift stage 231-4.
The extraction switch 232-3 corresponding to the third shift stage 231-3 is turned on in response to the shift pulse SFTP233, the clock DCKX output to the clock line DKXL1 is extracted, and the phase adjustment circuit 233-3 adjusts the phase. After that, the sample hold pulse SHP233 is supplied to the sampling switch 234-3.
Accordingly, the sampling switch 234-3 is turned on in response to the sample hold pulse SHP233, and the video signal VDO input through the video line VDL21 is sampled and supplied to the signal line SGNL23 of the pixel unit 21.
[0077]
Next, in the fourth shift stage 231-4 in which the shift pulse SFTP233 is shifted in from the third shift stage 231-3, as shown in FIG. 14 (H) in synchronization with the reverse-phase horizontal clocks HCK and HCKX. A shift pulse SFTP234 having the same pulse width as that of the horizontal clocks HCK and HCKX is output to the extraction switch 232-4. Further, the shift pulse SFTP 234 is shifted in from the fourth shift stage 231-4 to the shift stage 241 of the first monitor circuit 24.
The extraction switch 232-4 corresponding to the fourth shift stage 231-4 is turned on in response to the shift pulse SFTP234, and the clock output to the clock line DKL1 as shown in FIGS. After the DCK is extracted and phase-adjusted by the phase adjustment circuit 233-4, it is supplied to the sampling switch 234-4 as a sample hold pulse SHP234.
As a result, the sampling switch 234-4 is turned on in response to the sample hold pulse SHP 234, and the video signal VDO input through the video line VDL 21 is sampled and supplied to the signal line SGNL 24 of the pixel unit 21.
[0078]
Next, in the shift stage 241 of the first monitor circuit 24 to which the shift pulse SFTP234 has been shifted in from the fourth shift stage 231-4, it is shown in FIG. 14 (I) in synchronization with the reverse-phase horizontal clocks HCK and HCKX. As described above, the shift pulse SFTP 241 having the same pulse width as that of the horizontal clocks HCK and HCKX is output to the extraction switch 242.
The extraction switch 242 corresponding to the shift stage 241 is turned on in response to the shift pulse SFTP241, and as shown in FIGS. 14E and 14M, the clock DCKX output to the clock line DKXL1 is extracted, and the phase After the phase adjustment by the adjustment circuit 243, the sample hold pulse SHP 241 is supplied to the sampling switch 244.
As a result, the sampling switch 244 is turned on in response to the sample hold pulse SHP241, the monitor line MNTL21 pulled up by the pullup resistor R21 outside the LCD panel is pulled to the ground level, and the level change information is buffered. The feedback control circuit 27 is input via the BF21.
[0079]
In the feedback control circuit 27, the change in phase from the initial state is monitored from the timing when the sampling switch 244 of the first monitor circuit 24 in the normal scan operation is turned on and the monitor line MNTL21 transitions to the ground level.
In the feedback control circuit 27, the monitored phase change is fed back to the panel input clocks HCK, HCKX, etc., and an appropriate timing is set. As a result, the generation of a ghost due to the drift of the sample hold pulse SHP with respect to its initial state is prevented.
[0080]
As described above, during the normal scan operation, in the horizontal scanner 23, the shift pulses SFTP 231 from the shift stages 231-1 to 231-4 of the shift register 231 are switched by the switches 232-1 to 232-4 of the clock extraction switch group 232. To SFTP 234, the clocks DCKX and DCK having opposite phases are alternately extracted in response to the shift pulses SFTP 231 to SFTP 234 in order, and the clock DCKX whose phase is adjusted by the phase adjustment circuit group 233 , DCK are given as sample hold pulses SHP231 to SHP234.
When the sample hold pulses SHP231 to SHP234 are given to the sampling switches 234-1 to 234-4 of the sampling switch group 234, the sampling switches 234-1 to 234-4 are sequentially turned on in response to the sample hold pulses SHP231 to SHP234, and passed through the video line VDL21. The input video signal VDO is sequentially sampled and supplied to the signal lines SGNL21 to SGNL24 of the pixel unit 21.
Then, the clock DCKX different from that of the fourth shift stage is extracted as a continuous operation by the first monitor circuit 24 located at the final stage, phase-adjusted by the phase adjustment circuit 253, and then supplied to the sampling switch 244 as the sample hold pulse SHP241. Thus, the sampling switch 244 is turned on.
In other words, the sample hold pulse SHP234 of the fourth shift stage of the horizontal scanner 23 and the sample hold pulse SHP241 of the first monitor circuit 24 are generated at substantially the same timing as the relationship between the other sample hold pulses SHP231 to SHP233, and the image is displayed without any problem. Is done.
[0081]
Next, the reverse scan operation will be described with reference to the timing charts of FIGS.
[0082]
In this case, the scan direction switching signal RGT is set to a low level and supplied to the shift register 231 of the horizontal scanner 23. As a result, a path through which the switching circuits 2311 to 2313 and 2315 inserted between the shift stages propagate signals from left to right is formed. That is, the fourth shift stage 231-4 to the third shift stage 231-3, the third shift stage 231-3 to the second shift stage 231-2, the second shift stage 231-2 to the first shift stage 231-1, Further, a signal propagation path through which the horizontal start pulse HST is sequentially shifted is formed in the shift stage 251 of the second monitor circuit 25.
[0083]
In this state, the feedback control circuit 27 generates a horizontal start pulse HST as shown in FIG. 15A and supplies it to the fourth shift stage 231-4 of the shift register 231 in the horizontal scanner 23. This horizontal start pulse HST is not supplied to the shift stage 251 of the second monitor circuit 25.
Further, in the feedback control circuit 27, as shown in FIGS. 15B and 15C, horizontal clocks HCK and HCKX having opposite phases are generated, and the first shift stage 231 of the shift register 231 in the horizontal scanner 23 is generated. −1 to the fourth shift stage 231-4, the shift stage 251 of the second monitor circuit 25, and the clock generation circuit 26.
In the clock generation circuit 26, as shown in FIGS. 15D and 15E, the horizontal clocks HCK and HCKX generated by the feedback control circuit 27 have the same period (T1 = T2) and the duty ratio. Small clocks DCK and DCKX having opposite phases are generated and supplied to the horizontal scanner 23 and the second monitor circuit 25 through the clock lines DKL1 and DKXL1 (first monitor circuit 24).
[0084]
  In the feedback control circuit 27, the vertical start pulse VST for instructing the start of vertical scanning, the vertical clocks VCK and VCKX having opposite phases as the reference for the vertical scanning, and the start of horizontal scanning are instructed.HorizontalStart pulseHSTAre generated and supplied to the vertical scanner 22.
[0085]
In the shift register 231 of the horizontal scanner 23, the fourth shift stage 231-4 to which the horizontal start pulse HST is supplied by the external feedback control circuit 27 synchronizes with the reverse-phase horizontal clocks HCK and HCKX in FIG. As shown in (F), a shift pulse SFTP234 having the same pulse width as the horizontal clocks HCK and HCKX is output to the extraction switch 232-4. Further, the shift pulse SFTP234 is shifted in from the fourth shift stage 231-4 to the third shift stage 231-3.
The extraction switch 232-4 corresponding to the fourth shift stage 231-4 is turned on in response to the shift pulse SFTP234, and the clock output to the clock line DKL1 as shown in FIGS. After the DCK is extracted and phase-adjusted by the phase adjustment circuit 233-4, it is supplied to the sampling switch 234-4 as a sample hold pulse SHP234.
As a result, the sampling switch 234-4 is turned on in response to the sample hold pulse SHP 234, and the video signal VDO input through the video line VDL 21 is sampled and supplied to the signal line SGNL 24 of the pixel unit 21.
[0086]
Next, in the third shift stage 231-3 in which the shift pulse SFTP234 is shifted in from the fourth shift stage 231-4, as shown in FIG. 15 (H) in synchronization with the reverse-phase horizontal clocks HCK and HCKX. A shift pulse SFTP233 having the same pulse width as the horizontal clocks HCK and HCKX is output to the extraction switch 232-3. Further, the shift pulse SFTP233 is shifted in from the fourth shift stage 231-3 to the second shift stage 231-2.
The extraction switch 232-3 corresponding to the third shift stage 231-3 is turned on in response to the shift pulse SFTP233, and as shown in FIGS. 15E and 15K, the clock output to the clock line DKXL1. After DCKX is extracted and phase-adjusted by the phase adjustment circuit 233-3, it is supplied as a sample hold pulse SHP 233 to the sampling switch 234-3.
Accordingly, the sampling switch 234-3 is turned on in response to the sample hold pulse SHP233, and the video signal VDO input through the video line VDL21 is sampled and supplied to the signal line SGNL23 of the pixel unit 21.
[0087]
Next, in the second shift stage 231-2 in which the shift pulse SFTP 233 is shifted in from the third shift stage 231-3, the same period as the horizontal clocks HCK and HCKX is synchronized with the opposite-phase horizontal clocks HCK and HCKX. A shift pulse SFTP 232 having a pulse width is output to the extraction switch 232-2. Further, the shift pulse SFTP232 is shifted in from the second shift stage 231-2 to the first shift stage 231-1.
The extraction switch 232-2 corresponding to the second shift stage 231-2 is turned on in response to the shift pulse SFTP232, the clock DCK output to the clock line DKL1 is extracted, and the phase adjustment circuit 233-2 adjusts the phase. After that, the sample hold pulse SHP232 is supplied to the sampling switch 234-2.
Accordingly, the sampling switch 234-2 is turned on in response to the sample hold pulse SHP232, and the video signal VDO input through the video line VDL21 is sampled and supplied to the signal line SGNL22 of the pixel unit 21.
[0088]
Next, in the first shift stage 231-1 in which the shift pulse SFTP232 is shifted in from the second shift stage 231-2, as shown in FIG. 15 (H) in synchronization with the horizontal clocks HCK and HCKX having opposite phases. The shift pulse SFTP231 having the same pulse width as the horizontal clocks HCK and HCKX is output to the extraction switch 232-1. Further, the shift pulse SFTP 231 is shifted into the shift stage 251 of the second monitor circuit 25 from the first shift stage 231-1.
The extraction switch 232-1 corresponding to the first shift stage 231-1 is turned on in response to the shift pulse SFTP231, and the clock output to the clock line DKXL1 as shown in FIGS. After DCKX is extracted and phase-adjusted by the phase adjustment circuit 233-1, it is supplied to the sampling switch 234-1 as the sample hold pulse SHP231.
Accordingly, the sampling switch 234-1 is turned on in response to the sample hold pulse SHP231, and the video signal VDO input through the video line VDL21 is sampled and supplied to the signal line SGNL21 of the pixel unit 21.
[0089]
Next, in the shift stage 251 of the second monitor circuit 25 to which the shift pulse SFTP 231 has been shifted in from the first shift stage 231-1, it is shown in FIG. 15 (I) in synchronization with the reverse-phase horizontal clocks HCK and HCKX. As described above, the shift pulse SFTP 251 having the same pulse width as the cycle of the horizontal clocks HCK and HCKX is output to the extraction switch 252.
The extraction switch 252 corresponding to the shift stage 251 is turned on in response to the shift pulse SFTP251, and as shown in FIGS. 15D and 15M, the clock DCK output to the clock line DKL1 is extracted, and the phase After the phase adjustment by the adjustment circuit 253, the sample hold pulse SHP251 is supplied to the sampling switch 254.
As a result, the sampling switch 254 is turned on in response to the sample hold pulse SHP251, the monitor line MNTL21 pulled up by the pullup resistor R21 outside the LCD panel is pulled to the ground level, and the level change information is buffered. The feedback control circuit 27 is input via the BF21.
[0090]
In the feedback control circuit 27, the phase change from the initial state is monitored from the timing at which the sampling switch 254 of the second monitor circuit 25 is turned on during the reverse scan operation and the monitor line MNTL21 transitions to the ground level.
In the feedback control circuit 27, the monitored phase change is fed back to the panel input clocks HCK, HCKX, etc., and an appropriate timing is set. As a result, the generation of a ghost due to the drift of the sample hold pulse SHP with respect to its initial state is prevented.
[0091]
As described above, during the normal scan operation, in the horizontal scanner 23, the shift pulses SFTP 234 from the shift stages 231-4 to 231-1 of the shift register 231 by the switches 232-4 to 232-1 of the clock extraction switch group 232. To SFTP 231, the clocks DCK and DCKX having opposite phases are alternately extracted in response to these shift pulses SFTP 234 to SFTP 231, and the clock DCK whose phase is adjusted by the phase adjustment circuit group 233. , DCKX are supplied as sample hold pulses SHP234 to SHP231.
When the sample hold pulses SHP234 to SHP231 are given to the sampling switches 234-4 to 234-1 of the sampling switch group 234, the sampling switches 234-4 to 234-1 are sequentially turned on in response to the sample hold pulses SHP234 to SHP231, and pass through the video line VDL21. The input video signal VDO is sequentially sampled and supplied to the signal lines SGNL24 to SGNL21 of the pixel unit 21.
Then, the clock DCK different from that of the first shift stage is extracted as a continuous operation in the second monitor circuit 25 located at the final stage, and after the phase adjustment by the phase adjustment circuit 253, the sample hold pulse SHP251 is supplied to the sampling switch 244. Thus, the sampling switch 254 is turned on.
That is, the sample hold pulse SHP 231 of the first shift stage of the horizontal scanner 23 and the sample hold pulse SHP 251 of the second monitor circuit 25 are generated at substantially the same timing as the relationship between the other sample hold pulses SHP 234 to SHP 232, and image display can be performed without any problem. Is done.
In other words, even if the clock phase changes during the horizontal reversal of the scan operation, pulses with the same output phase can be obtained.
[0092]
As described above, according to the first embodiment, the first monitor circuit 24 and the second monitor circuit 25 are arranged in close proximity to both sides of the horizontal scanner 23, and at the time of the first scan operation (normal scan operation). When the horizontal start pulse HST is supplied to the first shift stage 231-1 of the horizontal scanner, the scanning operation from the first stage to the final stage is performed, and the signal from the final shift stage 231-4 of the horizontal scanner is shifted in, One monitor circuit 24 outputs a shift pulse SFTP 241 in synchronization with the horizontal clock signal HCK and the inverted clock signal HCKX, and a final shift stage 231-of the clock signal DCK and the inverted clock signal DCKX in response to the shift pulse at the switch 242. Sample DC hold signal DCKX, which is different from signal DCK extracted by 4 The potential of the monitor line MNTL21 output as the pulse SHP 241 and pulled up in response to the sample hold pulse by the sampling switch 244 is set to the ground potential, and the horizontal start pulse HST is set during the second scan operation (reverse scan operation). When the signal is supplied to the first shift stage 231-1 of the horizontal scanner, the scanning operation from the last stage to the first stage is performed, and the signal from the first stage shift stage 231-1 of the horizontal scanner is shifted in, the second monitor circuit 25 performs horizontal scanning. A shift pulse SFTP251 is output in synchronization with the clock signal HCK and the inverted clock signal HCKX, and the signal DCKX extracted by the first-stage shift stage 231-1 of the clock signal DCK and the inverted clock signal DCKX in response to the shift pulse by the switch 252. And different signal Since CK is extracted and output as the sample hold pulse SHP251, and the potential of the monitor line MNTL21 pulled up in response to the sample hold pulse by the sampling switch 254 is set to the ground potential, the following effects can be obtained. .
In other words, even in a horizontal scanner (the number of shift stages is an even number) whose clock phase is inverted in the scan direction inversion, the phase of the output potential change does not change, and it can be monitored with high accuracy regardless of the scan direction. Therefore, the image is not shifted by half and a highly accurate image display can be realized.
[0093]
The horizontal scanner 23 does not use the shift pulses SFTP231 to SFTP234 sequentially output from the shift register 231 as sample hold pulses, but alternately uses clocks DCKX and DCK having opposite phases in synchronization with the shift pulses SFTP231 to SFTP234. These clocks DCKX and DCK are used as sample and hold pulses SHP231 to SHP234 via a phase adjustment circuit. Thereby, the dispersion | variation in the sample hold pulses SHP231-SHP234 can be suppressed. As a result, ghosts caused by variations in the sample hold pulses SHP231 to SHP234 can be removed.
[0094]
In addition, the horizontal scanner 23 does not extract the horizontal clocks HCKX and HCK that serve as a reference for the shift operation of the shift register 231 and use them as sample hold pulses, but has the same cycle and a duty ratio with respect to the horizontal clocks HCKX and HCK. Since small clocks DCKX and DCK are separately generated, and these clocks DCKX and DCK are extracted and used as sample hold pulses SHP231 to SHP234, complete non-overlapping sampling between sampling pulses is performed in horizontal driving. Since this can be realized, it is possible to suppress the occurrence of vertical stripes due to overlap sampling.
[0095]
In the present embodiment, an analog video signal is input, and this is sampled and applied to a liquid crystal display device equipped with an analog interface driving circuit that drives each pixel in a dot-sequential manner. Can be applied to a liquid crystal display device equipped with a digital interface drive circuit that takes the input and latches it, converts it into an analog video signal, samples the analog video signal, and drives each pixel in a dot sequence It is.
In the present embodiment, the case where the present invention is applied to an active matrix liquid crystal display device using a liquid crystal cell as a display element (electro-optical element) of each pixel has been described as an example. It is not limited, but an active matrix display using a dot sequential drive system that employs a clock drive system in a horizontal drive circuit, such as an active matrix EL display device using an electroluminescence (EL) element as a display element of each pixel. Applicable to all devices.
[0096]
In addition to the well-known 1H inversion driving method and the dot inversion driving method, the dot sequential driving method has the same polarity in the pixel arrangement after the video signal is written, and the left and right pixels adjacent to each other. There is a so-called dot line inversion driving method in which video signals having opposite polarities are simultaneously written in two rows separated by odd numbers between adjacent pixel columns, for example, pixels in two upper and lower rows so that the pixels have opposite polarities.
[0097]
Second embodiment
FIG. 16 is a circuit diagram showing a configuration example of a dot sequential drive type active matrix liquid crystal display device according to the second embodiment of the present invention.
[0098]
The second embodiment is different from the first embodiment described above in that the monitor lines for transmitting the output pulses of the first monitor circuit 24 and the second monitor circuit 25 to the feedback control circuit 27 are not used in common. This is because the individual first monitor line MNTL21 and the second monitor line MNTL22 are wired.
[0099]
In this case, the output of the first monitor circuit 24 is connected to the first monitor line MNTL21, and the output of the second monitor circuit 25 is connected to the second monitor line MNTL22.
The first monitor line MNTL21 is pulled up by a pull-up resistor R21, and the other end is connected to the first input terminal of the feedback control circuit 27 via the buffer BF21.
Similarly, the second monitor line MNTL22 is pulled up by a pull-up resistor R22, and the other end is connected to the second input terminal of the feedback control circuit 27 via the buffer BF22.
[0100]
According to the second embodiment, in addition to the effects of the first embodiment described above, it is possible to form the first monitor line MNTL21 and the second monitor line MNTL22 as wirings having substantially the same length, and propagation. There is an advantage that monitoring error due to delay difference and the like can be prevented, and more accurate monitoring can be realized.
[0101]
Third embodiment
In the third embodiment, a configuration example of a projection type liquid crystal display device (liquid crystal projector) to which the dot matrix driving type active matrix liquid crystal display device of FIG. 11 or FIG. 16 can be applied as a display panel (LCD) will be described. .
[0102]
The dot matrix driving type active matrix liquid crystal display device according to the first and second embodiments described above is used as a display panel of a projection type liquid crystal display device (liquid crystal projector), that is, an LCD (liquid crystal display) panel. Is possible.
[0103]
FIG. 17 is a block diagram showing a system configuration of a projection type liquid crystal display device to which the dot matrix driving type active matrix liquid crystal display device according to the present invention can be applied as a display panel (LCD).
[0104]
The projection-type liquid crystal display device 40 according to this example includes a video signal source (VSRC) 41, a system board (SYSBRD) 42, and an LCD panel (PNL) 43.
In this system configuration, the system board 42 performs signal processing such as adjustment of the sample hold position described above on the video signal output from the video signal source 41. A feedback control circuit 27 including the timing generator of FIG. 11 is also mounted on the system board 42.
As the LCD panel 43, the dot matrix driving type active matrix liquid crystal display device according to the above-described embodiment is used. In the case of color, the LCD panel 43 is provided corresponding to each of R (red), G (green), and B (blue).
[0105]
FIG. 18 is a schematic configuration diagram showing an example of the configuration of the optical system of the projection type color liquid crystal display device.
In the optical system 400 of the projection type color liquid crystal display device shown in FIG. Are transmitted, and the light components of the remaining colors are reflected. The B light component transmitted through the first beam splitter 402 is changed in optical path by the mirror 403 and irradiated to the B LCD panel 405B through the lens 404.
For the light component reflected by the first beam splitter 402, for example, the G (green) light component is reflected by the second beam splitter 406, and the R (red) light component is transmitted. The G light component reflected by the second beam splitter 406 is applied to the G LCD panel 405G through the lens 407.
The R light component transmitted through the second beam splitter 406 has its optical path changed by mirrors 408 and 409, and is irradiated onto the R LCD panel 405 R through the lens 410.
Each of the LCD panels 405R, 405G, and 405B includes a first substrate in which a plurality of pixels are arranged in a matrix, a second substrate that is opposed to the first substrate with a predetermined interval, and these It has a liquid crystal layer held between the substrates and a filter layer corresponding to each color.
The R, G, and B lights that have passed through the LCD panels 405R, 405G, and 405B are combined by a cross prism 411. The combined light emitted from the cross prism 411 is projected onto the screen 413 by the projection prism 412.
[0106]
In the projection type liquid crystal display device configured as described above, the dot-sequential driving type active matrix liquid crystal display device according to the above-described embodiment is used as the LCD panels 405R, 405G, and 405B. The scan direction switching signal RGT is supplied to the LCD panels 405R and 405B at a high level and supplied to the LCD panel 405G at a low level so that the LCD panel 405G performs the second scan operation (reverse scan operation). Is done.
As a result, even if the phase of the clock is changed during the horizontal reversal of the scanning operation, pulses having the same output phase are obtained from the first monitor circuit 24 or the second monitor circuit 25 of any LCD panel 405R, 405G, 405B. Can do.
That is, even in a horizontal scanner where the clock phase is inverted in the scan direction inversion, the phase of the output potential change does not change, and it can be monitored with high accuracy regardless of the scan direction, and the image is halved. A highly accurate image display can be realized without being shifted.
In addition, since the liquid crystal display device according to the present embodiment realizes complete non-overlap sampling in the horizontal drive system, generation of vertical stripes due to overlap sampling can be suppressed and a ghost margin can be increased. Therefore, higher quality image display can be realized.
[0107]
There are two types of projection type liquid crystal display devices: a rear type and a front type. Generally, a rear type projection type liquid crystal display device is a projection TV for moving images, and a front type projection type liquid crystal display device is a data projector. Although being used, the dot matrix driving type active matrix liquid crystal display device according to the above-described embodiment can be applied to any type. Further, here, the case where the present invention is applied to a color projection type liquid crystal display device has been described as an example, but the present invention can be similarly applied to a monochrome projection type liquid crystal display device.
[0108]
【The invention's effect】
As described above, according to the present invention, even in a horizontal scanner in which the phase of the clock is inverted in the scan direction inversion, the phase of the output potential change does not change, and the high accuracy can be achieved regardless of the scan direction. Can be monitored. Therefore, there is an advantage that a highly accurate image display can be realized without the image being shifted by half.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of an active matrix liquid crystal display device adopting a general dot sequential driving method.
FIG. 2 is a block diagram illustrating a configuration example of a display panel of an active matrix liquid crystal display device.
FIG. 3 is a timing chart showing a timing relationship between horizontal clocks HCK and HCKX and clocks DCK and DCKX.
4 is a diagram for explaining an operation centering on the horizontal scanner of FIG. 1; FIG.
5 is a waveform diagram for explaining an operation centering on the horizontal scanner of FIG. 1; FIG.
6 is a diagram for explaining a problem of the horizontal scanner in FIG. 1. FIG.
FIG. 7 is a block diagram illustrating a configuration example of a conventional liquid crystal display device provided with a monitor circuit.
8 is a circuit diagram showing a specific example of the configuration of a part of the monitor circuit of FIG. 7 and a peripheral horizontal scanner.
9 is a timing chart for explaining an operation when scanning is performed in a normal direction (from left to right in FIG. 8) of the circuit of FIG. 8;
10 is a timing chart for explaining operations and problems when scanning in the reverse direction (right to left in FIG. 8) of the circuit of FIG. 8;
FIG. 11 is a circuit diagram illustrating a configuration example of an active matrix liquid crystal display device of a dot sequential driving method according to the first embodiment of the present invention.
12 is a block diagram illustrating a configuration example of a display panel of the active matrix liquid crystal display device of FIG.
FIG. 13 is a circuit diagram showing a configuration example of a switching circuit inserted between shift stages of the shift register.
14 is a timing chart for explaining a normal scan operation of the circuit of FIG.
15 is a timing chart for explaining a reverse scan operation of the circuit of FIG.
FIG. 16 is a circuit diagram showing a configuration example of an active matrix liquid crystal display device of a dot sequential driving method according to a second embodiment of the present invention.
FIG. 17 is a block diagram showing a system configuration of a projection type liquid crystal display device to which the dot matrix driving type active matrix liquid crystal display device according to the present invention can be applied as a display panel (LCD).
FIG. 18 is a schematic configuration diagram showing an example of the configuration of an optical system of a projection type color liquid crystal display device to which the dot matrix driving type active matrix liquid crystal display device according to the present invention can be applied as a display panel (LCD).
[Explanation of symbols]
20, 20A ... Liquid crystal display device, 21 ... Effective pixel portion (PXLP), 22 ... Vertical scanner (VSCN), 23 ... Horizontal scanner (HSCN), 24 ... First monitor circuit (MNT1), 25 ... Second monitor circuit ( MNT2), 26 ... Clock generation circuit (GEN), 27 ... Feedback control circuit (FDBCIC), 28 ... Precharge circuit (PRCG), 30 ... Display panel, 40 ... Projection type liquid crystal display device, 41 ... Video signal source (VSRC) ), 42 ... System board (SYSBRD), 43 ... LCD panel (PNL) 43, 400 ... Optical system, 401 ... Light source, 402 ... First beam splitter, 403, 408, 409 ... Mirror, 404, 407, 410 ... Lens, 405R, 405G, 405B ... LCDF panel, 406 ... Second beam splitter, 411 ... Supurizumu, 412 ... projection prism, 413 ... screen.

Claims (16)

A pixel portion in which a plurality of pixels are arranged in a matrix and a signal line is wired for each pixel column;
A monitor line held at a first potential;
A clock signal and an inverted clock signal that are at least opposite to each other as a reference for horizontal scanning are generated, and a change in the potential of the monitor line is monitored. A control circuit for correcting the signal generation timing;
A horizontal scanner,
A first monitor circuit;
A second monitor circuit;
The horizontal scanner
A plurality of shift stages are connected in cascade, and a first scan operation that sequentially shifts from the first stage to the last stage and a second scan operation that sequentially shifts from the last stage to the first stage can be switched according to a switching signal. Or a shift register that sequentially outputs shift pulses from each shift stage in synchronization with the clock signal and the inverted clock signal during the second scan operation;
A first switch group that alternately and sequentially extracts the clock signal and the inverted clock signal in response to the shift pulse output from the corresponding shift stage of the shift register, and outputs the sample signal as a sample hold pulse;
A second switch group that sequentially samples a video signal in response to a sample hold pulse by each switch of the first switch group and supplies the video signal to a corresponding signal line of the pixel unit,
The first monitor circuit includes:
During the first scan operation, a shift stage that is connected to the last shift stage of the shift register in the horizontal scanner and outputs a shift pulse in synchronization with the clock signal and the inverted clock signal when a signal from the last shift stage is shifted in. When,
A third switch for extracting a signal different from the signal extracted by the final shift stage from the clock signal and the inverted clock signal in response to the shift pulse output from the shift stage, and outputting as a sample hold pulse;
A fourth switch for setting the potential of the monitor line to a second potential in response to a sample hold pulse by the third switch,
The second monitor circuit includes:
During the second scan operation, the shift stage is connected to the first shift stage of the shift register in the horizontal scanner and outputs a shift pulse in synchronization with the clock signal and the inverted clock signal when a signal from the first shift stage is shifted in. When,
A fifth switch for extracting a signal different from the signal extracted by the first-stage shift stage from the clock signal and the inverted clock signal in response to the shift pulse output from the shift stage, and outputting as a sample hold pulse;
And a sixth switch for setting the monitor line to a second potential in response to a sample hold pulse by the fifth switch. The first scan operation and the second scan operation are started in response to a horizontal start pulse. The horizontal start pulse is supplied to the first shift stage of the shift register during the first scan operation, and the second scan operation is performed. The display device according to claim 1, wherein the display device is sometimes supplied to the last shift stage of the shift register and not supplied to the first monitor circuit and the second monitor circuit. The first monitor circuit is disposed adjacent to the final shift stage of the horizontal scanner,
The display device according to claim 1, wherein the second monitor circuit is disposed adjacent to a first shift stage of the horizontal scanner. The display device according to claim 1, wherein the monitor line is shared by the first monitor circuit and the second monitor circuit. The display device according to claim 1, wherein the monitor lines are individually formed on a first monitor line connected to the first monitor circuit and a second monitor line connected to the second monitor circuit. The display device according to claim 1, wherein the number of shift stages in the shift register of the horizontal scanner is an even number. Based on the clock signal and the inverted clock signal generated by the control circuit, a second clock signal and a second inverted clock signal having the same period and a small duty ratio with respect to the clock signal and the inverted clock signal are generated. And a clock generation means for supplying the horizontal scanner, the first monitor circuit, and the second monitor circuit,
Each switch of the first switch group of the horizontal scanner, the third switch of the first monitor circuit, and the fifth switch of the second monitor circuit receive the two clock signals or the second inverted clock signal by the clock generating means. The display device according to claim 1. The display device according to claim 1, wherein the display element of the pixel is a liquid crystal cell. A monitor line held at a first potential;
A clock signal and an inverted clock signal that are at least opposite to each other as a reference for horizontal scanning are generated, and a change in the potential of the monitor line is monitored. A control circuit for correcting the signal generation timing;
A display panel including a pixel portion in which a plurality of pixels are arranged in a matrix and a signal line is wired for each pixel column, a horizontal scanner, a first monitor circuit, and a second monitor circuit;
Irradiating means for irradiating the display panel with light;
Projecting means for projecting light that has passed through the display panel onto a screen,
The horizontal scanner of the above display panel
A plurality of shift stages are connected in cascade, and a first scan operation that sequentially shifts from the first stage to the last stage and a second scan operation that sequentially shifts from the last stage to the first stage can be switched according to a switching signal. Or a shift register that sequentially outputs shift pulses from each shift stage in synchronization with the clock signal and the inverted clock signal during the second scan operation;
A first switch group that alternately and sequentially extracts the clock signal and the inverted clock signal in response to the shift pulse output from the corresponding shift stage of the shift register, and outputs the sample signal as a sample hold pulse;
A second switch group that sequentially samples a video signal in response to a sample hold pulse by each switch of the first switch group and supplies the video signal to a corresponding signal line of the pixel unit,
The first monitor circuit of the display panel includes:
During the first scan operation, a shift stage that is connected to the last shift stage of the shift register in the horizontal scanner and outputs a shift pulse in synchronization with the clock signal and the inverted clock signal when a signal from the last shift stage is shifted in. When,
A third switch for extracting a signal different from the signal extracted by the final shift stage from the clock signal and the inverted clock signal in response to the shift pulse output from the shift stage, and outputting as a sample hold pulse;
A fourth switch for setting the potential of the monitor line to a second potential in response to a sample hold pulse by the third switch,
The second monitor circuit of the display panel,
During the second scan operation, the shift stage is connected to the first shift stage of the shift register in the horizontal scanner and outputs a shift pulse in synchronization with the clock signal and the inverted clock signal when a signal from the first shift stage is shifted in. When,
A fifth switch for extracting a signal different from the signal extracted by the first-stage shift stage from the clock signal and the inverted clock signal in response to the shift pulse output from the shift stage, and outputting as a sample hold pulse;
And a sixth switch for setting the monitor line to a second potential in response to a sample hold pulse by the fifth switch. The first scan operation and the second scan operation are started in response to a horizontal start pulse. The horizontal start pulse is supplied to the first shift stage of the shift register during the first scan operation, and the second scan operation is performed. The projection display device according to claim 9, wherein the projection type display device is sometimes supplied to the last shift stage of the shift register and not supplied to the first monitor circuit and the second monitor circuit. The first monitor circuit is disposed adjacent to the final shift stage of the horizontal scanner,
The projection display device according to claim 9, wherein the second monitor circuit is disposed adjacent to an initial shift stage of the horizontal scanner. The projection display device according to claim 9, wherein the monitor line is shared by the first monitor circuit and the second monitor circuit. The projection display device according to claim 9, wherein the monitor lines are individually formed on a first monitor line connected to the first monitor circuit and a second monitor line connected to the second monitor circuit. The projection display device according to claim 9, wherein the number of shift stages in the shift register of the horizontal scanner is an even number. Based on the clock signal and the inverted clock signal generated by the control circuit, a second clock signal and a second inverted clock signal having the same period and a small duty ratio with respect to the clock signal and the inverted clock signal are generated. And a clock generation means for supplying the horizontal scanner, the first monitor circuit, and the second monitor circuit,
Each switch of the first switch group of the horizontal scanner, the third switch of the first monitor circuit, and the fifth switch of the second monitor circuit receive the two clock signals or the second inverted clock signal by the clock generating means. The projection type display device according to claim 9. The projection display device according to claim 9, wherein a display element of each pixel of the pixel unit is a liquid crystal cell.

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