JP2006080239A - Laminated high-frequency circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low loss multilayer high-frequency circuit board which does not depend on frequency and can be manufactured by a simple method. <P>SOLUTION: The laminated high-frequency circuit board is formed by connecting a plurality of high-frequency circuit layers via a metal-coated via-hole. A ground conductor is disposed between the high-frequency circuit layers to create a capacitance between the via-hole and the ground conductor. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a high-frequency circuit module, and more particularly to a laminated high-frequency circuit board in which a plurality of high-frequency circuit layers are stacked and electrically connected by via holes covered with metal between the high-frequency circuits.

It is known that impedance matching between circuits must be performed in order to transmit a high-frequency signal without loss in a high-frequency circuit of GHz or higher that uses a plurality of high-frequency circuit layers stacked (see Patent Documents 1 and 2). ).
As represented by mobile phones, the progress of high-performance, high-frequency and miniaturization of high-frequency circuit modules in wireless devices is remarkable. The miniaturization of the high-frequency circuit has the effect of shortening the wiring length and contributes to the improvement of performance.
In particular, recently, a high-density circuit board using a multilayer wiring board called a build-up board in which wirings and insulating layers are alternately stacked in a three-dimensional manner has been used. In such a laminated substrate, electrical connection is made through via holes in which circuits are covered with metal.
In a high-frequency circuit of GHz or higher, impedance matching between circuits needs to be performed in order to transmit a high-frequency signal without loss. In a wiring that does not consider impedance matching, reflection occurs due to impedance mismatching, and loss of signal power occurs. Therefore, it is necessary to form a circuit with a transmission line having a characteristic impedance Z _o in consideration of impedance matching for signal wiring at high frequencies.
As the transmission line, a microstrip type, triplate type or coplanar type transmission line is used. However, when the high-frequency circuit constituted by the transmission line is connected by a via hole, there is a problem that impedance mismatch occurs due to inductance parasitic on the via hole and a reflection loss occurs.
As described above, in a multilayer high-frequency substrate of GHz or higher, how to reduce the influence of the inductance parasitic on the via hole portion is a major technical problem.
For example, Patent Document 1 and Patent Document 2 are known as conventional techniques for solving such technical problems.
In the past, inductance was canceled by providing a gap between the power supply unit and the patch antenna, or capacitance was created by providing a gap between the power supply unit and the patch antenna, but the structure was complicated. There were problems such as disturbing the radiation pattern.
FIG. 16 is a schematic diagram showing an example of an antenna in which a capacitance is formed by providing a gap between a power feeding unit and a patch antenna, which is one of the prior arts. In the probe feeding method in the conventional antenna, power is fed by a coaxial line up to just below the antenna substrate, but power is fed only from the bottom of the substrate to the antenna by a signal line.
Therefore, in this prior art, the capacitance that cancels the inductance is formed by providing a gap between the feeding portion on the antenna surface and the patch antenna. However, when the gap is formed in the antenna pattern in this way, there is a problem that the radiation pattern is disturbed.

FIG. 17 is a plan view showing a high-frequency multilayer circuit board disclosed in Patent Document 1. In FIG. In this prior art, impedance matching is performed by providing a matching adjustment microstrip line 15 and a rectangular stub 14 for impedance matching between the via hole 10 and the microstrip type signal line 11 on the surface 13 of the high frequency circuit board. The parasitic inductance is cancelled.
FIG. 18 is a perspective view showing the high-frequency circuit module disclosed in Patent Document 2. As shown in FIG. FIG. 19 is a plan view showing one layer of each vertical transmission line of the high-frequency circuit module of FIG. 20 is a cross-sectional view showing the high-frequency circuit module of FIG.
In this prior art, by forming a via hole group 10 connected to the ground metal layer 16 or a coaxial via hole around the signal transmission via hole 10c, the via hole portion has a transmission line structure having the same characteristic impedance as the high frequency circuit. By doing so, the influence of the parasitic inductance is canceled.
JP 2001-308547 A JP 2003-133801 A

However, since the transmission line is used in the method of Patent Document 1, the usable frequency is fixed, and at other frequencies, there is a problem of being affected by the parasitic inductance.
In addition, the method of Patent Document 2 requires the formation of a via hole group that is electrically grounded around the via hole of the signal line or the via-hole having a coaxial structure, and the manufacturing process is complicated, so that the manufacturing cost is high. there were.
Accordingly, an object of the present invention is to provide a multilayer high-frequency circuit board that has a low-loss multilayer structure that does not depend on frequency and that is easy to manufacture in consideration of the above-described circumstances.

In order to solve the above-mentioned problem, the invention according to claim 1 is directed to a stacked high-frequency circuit board in which a plurality of high-frequency circuit layers are connected via a metal-coated via hole, and the via hole is interposed between the high-frequency circuit layers. And a laminated high-frequency circuit board on which a ground conductor for forming a capacitance is arranged.
According to a second aspect of the present invention, there is provided the multilayer high-frequency circuit board according to the first aspect, wherein the ground conductor is disposed at the center between the high-frequency circuit layers disposed above and below.
A third aspect of the present invention is characterized in that a plurality of the ground conductors are disposed between the high-frequency circuit layers disposed above and below, and the distance between them is equal.
According to a fourth aspect of the present invention, the ground conductors are arranged so as to be displaced from the center between the upper and lower high-frequency circuit layers, and the diameters of the via holes are different with respect to the position of the ground conductor. It is characterized by the laminated high frequency circuit board described.
The invention according to claim 5 is characterized in that the high-frequency circuit formed in the high-frequency circuit layer is constituted by a microstrip-type transmission line, and the laminated high-frequency circuit board according to claim 1.
The invention according to claim 6 is characterized in that the high-frequency circuit formed in the high-frequency circuit layer comprises a triplate type transmission line, and the laminated high-frequency circuit board according to claim 1.
The invention described in claim 7 is characterized in that the high-frequency circuit formed in the high-frequency circuit layer comprises a coplanar transmission line, and the laminated high-frequency circuit board according to claim 1.
The invention described in claim 8 is characterized in that the high-frequency circuit board provided on one surface of the high-frequency circuit layer is an antenna according to claim 1.

  According to the multilayer high-frequency circuit board of the present invention, the parasitic inductance of the via hole, which has been difficult in the past, can be canceled with a simple structure. As a result, a low-loss high-frequency circuit board in the GHz band can be provided at low cost.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic view showing a first embodiment of a multilayer high-frequency circuit board according to the present invention. FIG. 2 is a sectional view taken along line 2 in FIG. FIG. 3 is an enlarged schematic view showing a circle R portion of FIG. FIG. 4 is a bottom view of FIG.
1 to 4, a first high-frequency circuit is formed on the first surface of the first high-frequency circuit layer 1 by a microstrip transmission line 2. The second high-frequency circuit formed in the second high-frequency circuit layer 3 thereunder is electrically connected through a via hole 4 penetrating the first and second high-frequency circuit layers.
A ground conductor 5 is disposed between the first and second high-frequency circuit layers formed on the surfaces of the first and second high-frequency circuit layers, thereby forming a capacitance with the via hole 4.
In the figure, L ₁ and L ₂ are the parasitic inductances of the first high-frequency circuit layer and the second high-frequency circuit layer via hole 4, respectively, and t ₁ and t ₂ are the first high-frequency circuit layer and the second high-frequency circuit, respectively. Layer thickness, 6 is a land, 7 is a metal pad for via holes, d ₁ and d ₂ are via hole diameters of the first high frequency circuit layer and the second high frequency circuit layer, respectively, and g is a distance between the land and the ground conductor. is there.

・・・式１
したがって、Ｚ₁がビアホール４の寄生インダクタンスＬ／２（Ｌ＝Ｌ₁＋Ｌ₂）、Ｚ₂を新たに付加される接地導体５によるキャパシタンスＣとの対称Ｔ型回路を考え、影像インピーダンスＺ_oTと接続する回路のインピーダンスがＺ₀と等しくなるＴ型回路のキャパシタンスＣは式１から求められ、次式で与えられる。

・・・式２ ここで、ωは角周波数
式２にしたがえば、ビアホール４の寄生インダクタンスＬ＝１００ｐＨであると仮定すれば、周波数３０ＧＨｚにおける付加すべきキャパシタンスＣは３８．６ｆＦと見積られる。
シミュレーションによりその効果を確認すれば、インダクタンスだけの場合には３０ＧＨｚにおけるリターンロスは−１４．６５（ｄＢ）であるのに対して、Ｃを付加した本発明の構造にすることで、そのリターンロスは−９５．７５（ｄＢ）に改善されることが予測される。
また、式２から明らかなように、（ω²Ｌ²）／４＜＜Ｚ₀ ²であるから、本方式は周波数依存性が少なく、広帯域な整合を行うことができる利点がある。 FIG. 5 is a schematic diagram of an equivalent circuit serving as a symmetric T-type circuit showing high-frequency electrical characteristics in the structure of FIG. The principle by which the structure of the present invention cancels the influence of the parasitic inductance will be described next. The high-frequency electrical characteristics in the structure of FIG. 1 can be represented by an equivalent circuit as shown in FIG.
As shown in FIG. 5, the via hole 4 is a symmetric T-type circuit including an inductance L and a capacitance C between the ground conductor 5. In order to perform circuit impedance matching using an LC symmetrical T-type circuit, it is necessary to select an LC value that makes the image impedance Z _oT equal to the characteristic impedance Z _o of the input / output circuit to be connected. It has been.
The image impedance Z _oT of the symmetric T-type circuit can be expressed by the following equation.

... Formula 1
Therefore, consider a symmetrical T-type circuit in which Z ₁ is a parasitic inductance L / 2 (L = L ₁ + L ₂ ) of the via hole 4 and a capacitance C by the ground conductor 5 to which Z ₂ is newly added, and the image impedance Z _oT The capacitance C of the T-type circuit where the impedance of the circuit to be connected becomes equal to Z ₀ is obtained from Equation 1 and is given by the following equation.

(2) Here, ω is an angular frequency. According to Equation 2, assuming that the parasitic inductance L of the via hole 4 is 100 pH, the capacitance C to be added at a frequency of 30 GHz is estimated to be 38.6 fF.
If the effect is confirmed by simulation, the return loss at 30 GHz is -14.65 (dB) in the case of only the inductance, but the return loss is obtained by adopting the structure of the present invention with C added. Is expected to improve to -95.75 (dB).
Further, as is apparent from Equation 2, since (ω ² L ² ) / 4 << Z ₀ ² , this method has an advantage that the frequency dependence is small and broadband matching can be performed.

・・・式３
ここで、εrは材料の比誘電率、εoは真空の誘電率、ｇは距離、ａは線の直径、ｌは線の長さである。 The laminated high-frequency circuit according to the present invention is characterized in that a via hole 4 and a ground conductor 5 constituting a capacitance are arranged between upper and lower high-frequency circuit layers 1 and 3 and a matching T-type circuit is added. .
More specifically, the design method will be described. The capacitance C estimated by Expression 2 can form a desired additional capacitance by separating the via 6 at the center of the via hole from the thickness of the ground conductor and the distance therebetween. Is possible.
To be exact, the structural design of the capacitance part can be designed by calculating in detail using a three-dimensional electromagnetic field simulator, but the design method will be described from the equation of the parallel two-line capacitance for the purpose of explaining the design guideline.
The capacitance C between two parallel lines can be expressed by the following equation.

... Formula 3
Here, εr is the relative permittivity of the material, εo is the permittivity of vacuum, g is the distance, a is the diameter of the wire, and l is the length of the wire.

Now, the distance g between the opening of the ground conductor 5 and the land 6 required for setting the capacitance determined by the distance between the opening of the land 6 and the ground conductor 5 to a desired value, and the dielectric constant of the material 3.9. Assuming that the ground conductor thickness a = 1 μm, the via hole diameter φ100 μm, and the land diameter φ200 μm (outer periphery l = 6.28E-4 m), grounding is required to obtain the estimated capacitance C = 38.6 pF. The distance g between the conductor 5 and the land 6 is estimated to be 58.1 μm from Equation 3.
Therefore, when the via hole connection land is φ200 μm, if the outer shape of the ground conductor opening is φ316.2 μm and formed in the center of the upper and lower high-frequency circuit layers, a capacitance for canceling the parasitic inductance of the via hole 4 can be created. A matching T-type circuit can be realized.
In the above description, the desired capacitance is formed by adjusting the distance between the ground conductor 5 and the land 6, but the ground conductor 5 can also be adjusted to form the desired capacitance. As is clear from the above description, the multilayer high-frequency circuit board of the present invention can provide a parasitic inductance canceling method with a simpler structure and a wider band than in the past.
FIG. 6 is a schematic view showing a second embodiment of the multilayer high-frequency circuit board according to the present invention. FIG. 7 is a sectional view taken along line 7 of FIG. FIG. 8 is a bottom view of FIG. 6 to 8, the same parts as those in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof is omitted.
When the high-frequency circuit layer is thick, or when a plurality of ground conductors 5 are arranged on the multilayer substrate, a plurality of ground conductors 5 are arranged at equal intervals to form a predetermined capacitance, thereby matching multiple stages. A T-type circuit can be configured, and the same effect as in the first embodiment can be obtained. In the figure, reference numeral 8 denotes a third high-frequency circuit layer, and L ₃ denotes an inductance parasitic on the via hole 4.

FIG. 9 is a schematic view showing a third embodiment of the multilayer high-frequency circuit board according to the present invention. FIG. 10 is a cross-sectional view taken along line 10 of FIG. FIG. 11 is an enlarged schematic view showing a circle R portion of FIG. FIG. 12 is a bottom view of FIG.
In the first embodiment, the thickness of the high-frequency circuit layers to be stacked is the same as that of the present invention. However, the thickness of the high-frequency circuit layers to be stacked may be different. In such a case, the ground conductor 5 cannot be formed at the center of the two high-frequency circuit layers, resulting in an asymmetric T-type circuit, and Equation 1 does not hold.
FIG. 9 shows an embodiment in which the thickness t _{2 of} the second high-frequency circuit layer is thicker than the thickness t _{1 of the first} high-frequency circuit layer. 9 to 12, the same parts as those in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof is omitted.
In this case, with the same via hole diameter, the parasitic inductance of the via hole 4 of the first high-frequency circuit layer is small, and the parasitic inductance of the via hole 4 of the second high-frequency circuit layer is large, and is formed by the ground conductor 5 and the via hole 4. The T-type circuit for matching with the capacitance is an asymmetric T-type circuit, and Equation 1 does not hold.
Therefore, in the third embodiment, a structure is proposed in which the via hole diameter of the thick high frequency circuit layer is large and the via hole diameter of the thin high frequency circuit layer is small so that the inductances formed in the two high frequency circuit layers are equal. .
In this way, by adjusting the via hole diameter, equal parasitic inductances can be formed in the high-frequency circuit layers having different thicknesses, and a matching symmetric T-type circuit can be realized. The same effects as those of the first embodiment can be obtained. Can be obtained.

FIG. 13 is a schematic view showing a fourth embodiment of the multilayer high-frequency circuit board according to the present invention. 14 is a cross-sectional view taken along line 14 of FIG. FIG. 15 is a bottom view of the fourth embodiment of the multilayer high-frequency circuit board of FIG.
In the fourth embodiment, an antenna 16 is formed as a high-frequency circuit on one surface of the multilayer high-frequency circuit board, and another high-frequency circuit is formed on the other surface. In this embodiment, an example of a patch antenna 16 is shown as an antenna.
The patch antenna 16 employs a probe power feeding method that feeds a high-frequency signal through the antenna substrate as a general power feeding method. However, when the substrate is thick, the characteristics deteriorate due to the parasitic inductance of the power feeding unit. Resulting in.
In the past, inductance was canceled by providing a gap between the power supply unit and the patch antenna, or capacitance was created by providing a gap between the power supply unit and the patch antenna, but the structure was complicated. There were problems such as disturbing the radiation pattern.
In the antenna feeding portion structure 9 of the present invention, a patch antenna 16 is formed in the first high-frequency circuit layer, and another high-frequency circuit is formed in the second high-frequency circuit layer. Are electrically connected by via holes, a ground conductor 5 is arranged in the center of the substrate, and a capacitance for canceling the parasitic inductance is formed to constitute a symmetric T-type circuit for matching.
With such a power feeding unit structure, not only the parasitic inductance is canceled, but also the ground conductor 5 is shared and two high-frequency circuits using microstrip transmission lines can be formed on the upper and lower sides of the substrate. Figured.
As described above, when the canceling method of the present invention is used, the influence of the feeder inductance on the thick film substrate, which has been a problem in the integrated patch antenna, can be integrated with a simple structure without any disturbance of the radiation pattern. It is possible to provide a laminated high-frequency circuit board suitable for manufacturing.

1 is a schematic diagram showing a first embodiment of a multilayer high-frequency circuit board according to the present invention. FIG. 3 is a cross-sectional view taken along line 2 in FIG. 1. It is the schematic which expands and shows the circle R part of FIG. It is a bottom view of 1st Embodiment of the multilayer high frequency circuit board of FIG. It is the schematic of the equivalent circuit used as the symmetrical T-type circuit which shows the high frequency electric characteristic in the structure of FIG. It is the schematic which shows 2nd Embodiment of the laminated | stacked high frequency circuit board by this invention. It is sectional drawing which follows the line 7 of FIG. It is a bottom view of 2nd Embodiment of the laminated | stacked high frequency circuit board of FIG. It is the schematic which shows 3rd Embodiment of the lamination type high frequency circuit board by this invention. FIG. 10 is a cross-sectional view taken along line 10 of FIG. It is the schematic which expands and shows the circle R part of FIG. FIG. 10 is a bottom view of the third embodiment of the multilayer high-frequency circuit board of FIG. 9. It is the schematic which shows 4th Embodiment of the laminated | stacked high frequency circuit board by this invention. It is sectional drawing which follows the line 14 of FIG. It is a bottom view of 4th Embodiment of the laminated | stacked high frequency circuit board of FIG. It is the schematic which shows the example of the antenna which provided the gap between the electric power feeding part and the patch antenna, and formed the capacitance which is one of the prior arts. 10 is a plan view showing a high-frequency multilayer circuit board of Patent Document 1. FIG. It is a perspective view which shows the high frequency circuit module of patent document 2. It is a top view which shows 1 layer of each vertical transmission line of the high frequency circuit module of FIG. It is sectional drawing which shows the high frequency circuit module of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st high frequency circuit layer 2 Transmission line 3 2nd high frequency circuit layer 4 Via hole 5 Grounding conductor 6 Land 7 Metal for via hole 8 3rd high frequency circuit layer 9 Antenna electric power feeding part 16 Antenna (patch antenna)

Claims (8)

  A multi-layer high-frequency circuit board in which a plurality of high-frequency circuit layers are connected via a metal-coated via hole, wherein the grounding conductor for forming the via hole and the capacitance is disposed between the high-frequency circuit layers. Type high frequency circuit board.   2. The multilayer high-frequency circuit board according to claim 1, wherein the ground conductor is disposed at the center between the high-frequency circuit layers disposed above and below.   2. The multilayer high-frequency circuit board according to claim 1, wherein a plurality of the ground conductors are arranged between the high-frequency circuit layers arranged above and below, and the intervals are equal.   2. The laminated type according to claim 1, wherein the ground conductor is disposed so as to be shifted from the center between the high-frequency circuit layers disposed above and below, and the diameter of the via hole is different with respect to the position of the ground conductor. High frequency circuit board.   2. The multilayer high-frequency circuit board according to claim 1, wherein the high-frequency circuit formed in the high-frequency circuit layer is constituted by a microstrip transmission line.   2. The multilayer high-frequency circuit board according to claim 1, wherein the high-frequency circuit formed in the high-frequency circuit layer is composed of a triplate transmission line.   2. The multilayer high-frequency circuit board according to claim 1, wherein the high-frequency circuit formed in the high-frequency circuit layer is constituted by a coplanar transmission line.   2. The multilayer high-frequency circuit board according to claim 1, wherein the high-frequency circuit provided on one surface of the high-frequency circuit layer is an antenna.

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