JP2006073777A - Printed wiring board, its manufacturing method, and semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed wiring board which is capable of reducing a manufacturing cost of forming a build-up layer on the printed wiring board large in scale and suitable for multilayering, and to provide its manufacturing method and a semiconductor apparatus. <P>SOLUTION: The build-up layer 20 is composed of two or more wiring layers and insulating layers 23, 25, and 27 which are alternately laminated, the wiring layers are connected together with viaholes, the diameter of the opening of the viahole located on the first surface of the insulating layer where a semiconductor device 50 is arranged is set smaller than that of the other opening of the viahole located on the second surface of the insulating layer opposed to its first surface, and a bonding metal material layer is provided on the surface of the build-up layer 20 opposite to its other surface where the semiconductor device 50 is arranged and bonded to the through-holes 41 of a core board 40. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a printed wiring board, a manufacturing method thereof, and a semiconductor device, and more particularly to a printed wiring board suitable for multilayering, a manufacturing method thereof, and a semiconductor device.

  In recent years, with the high density integration of electronic devices, printed wiring boards having a build-up layer in which a plurality of wiring layers and insulating resin layers are alternately stacked and via layers are connected via vias have been increasingly multilayered. ing. As the number of printed wiring boards increases, the wiring is broken or short-circuited due to irregularities on the surface of the printed wiring board, resulting in a problem that the printed wiring board becomes defective and yield decreases. In order to solve such a problem, a technique for flattening unevenness on the surface of a printed wiring board has been proposed.

  For example, as a first conventional example, as shown in Patent Document 1, a core substrate having a bottomed via hole (a wiring layer or a substrate in which a wiring layer and an insulating layer are stacked on a core insulating layer) is blackened and reduced. After processing (a substrate on which a wiring layer or a wiring layer and an insulating layer are laminated on a core insulating layer), an epoxy resin filler is applied to the bottomed via hole by screen printing, and a vacuum is drawn in the bottomed via hole. There is a method of filling a bottomed via hole in which bubbles are removed and the filler is thermally cured and then the surface is polished and flattened. According to this, when the upper layer is further built up thereafter, the depression of the bottomed via hole is not hindered, the pattern processing accuracy of the upper layer is ensured, and it is convenient for component mounting. However, the above-described method has problems that the inner layer conductor thickness varies due to polishing, and that the inner layer substrate has large dimensional variations. Further, as the number of printed wiring boards is further increased, there is a limit to flattening the printed wiring boards. Furthermore, in the printed wiring board built up from the surface side of the core substrate described above, even if the core substrate is a non-defective product, the defective core substrate is also wasted if a failure occurs in the build-up layer in the manufacturing process. As a result, the manufacturing cost is high.

  On the other hand, the technique shown in Patent Document 2 is known as a second conventional example. That is, a wiring pattern is formed on a metal plate by electrolytic plating, an insulating film is formed on the wiring pattern, and a via hole and a conductor post are formed in the insulating film. Next, a bonding metal material layer is formed on the conductor post, and an adhesive layer is formed on the surface of the insulating film to obtain a connection substrate. Next, the connection substrate is bonded to a separately manufactured connected substrate. Next, a technique for forming a printed wiring board by etching and removing the metal plate of the connection substrate is known. In this way, the connection substrate and the connection substrate are manufactured separately, and the yield is improved by bonding a combination of these non-defective products.

  Furthermore, as a third conventional example, in Patent Document 3, a metal plate in which a wiring pattern, an insulating film, a via hole, and an adhesive layer are further formed is formed, and a connection substrate in which this metal plate is cut into small pieces is created, The portion of the region formed on the metal plate is laminated on the required region on the first wiring substrate of the core substrate using a glass epoxy substrate or the like as the core insulating layer. Thereafter, the metal plate that the original connection substrate had was removed by etching to form a printed wiring board, thereby improving the yield.

JP 2000-133937 A JP 2002-26171 A JP 2003-298232 A

  However, in the second conventional example, in order to form a printed wiring board having a thin insulating layer in which thin insulating films are joined to face each other, a printed wiring board having no reinforcing fiber is formed on the base material. There was a disadvantage that the mechanical strength was weak.

  In the third conventional example, the connection substrate is bonded to the first wiring substrate with an interlayer insulating layer such as a photosensitive adhesive, and the interlayer connection portion of the conductor is formed of Cu, Ni, or the like in a hole drilled in the interlayer insulating layer. It was formed by filling with metal electroplating or filling with conductive fine particles such as solder. For this reason, in order to align the 1st wiring board and connection board | substrate of a 3rd Example with a sufficient precision, there existed a fault that cost rose.

  An object of the present invention is to provide a printed wiring board, a manufacturing method thereof, and a semiconductor device, which can reduce the manufacturing cost when forming a large-sized printed wiring board and are suitable for multilayering.

  According to a first aspect of the present invention, in a printed wiring board, a plurality of wiring layers and insulating layers are alternately stacked, the wiring layers are connected by via holes, and the diameter of the via holes is determined by the semiconductor element. A build-up layer configured so that a diameter on the first surface side of the insulating layer is smaller than a diameter on the second surface side of the insulating layer on the opposite side of the first surface; A core substrate having the core substrate and the buildup layer are bonded together, and the through hole of the core substrate and the via hole of the buildup layer are bonded by a bonding metal material layer. It is characterized by.

  In the printed wiring board of the present invention, it is preferable that the bonding metal material layer is made of a metal material solidified after melting.

  In the printed wiring board of the present invention, a plurality of wiring layers and insulating layers are alternately stacked on the opposite side of the core substrate to which the build-up layer is bonded, and the wiring layers are connected by via holes. Preferably, the second buildup layer is bonded, and the diameter of the via hole of the second buildup layer is configured such that the diameter on the core substrate surface side is narrower than the diameter on the opposite surface side to the core substrate. .

  In the printed wiring board of the present invention, the via hole has a protruding portion on the second surface side of the insulating layer, the through hole has a protruding portion on the buildup layer side, and the via hole The protrusions of the through hole are in contact with the protrusions of the through hole or close to each other with a gap within several μm, and between the protrusions of the via hole and the protrusions around the contact part of the protrusion of the through hole. It is preferable that the bonding metal material layer fills the gap.

In a second aspect of the present invention, in the method for manufacturing a printed wiring board, a process of forming a buildup layer, a connecting metal material layer made of solder, and a bonding adhesive layer made of a thermoplastic resin on one metal plate A step of cutting and dividing the metal plate including a formation into a plurality of pieces, a step of forming a core substrate having a through hole, and overlapping each piece on the core substrate with the metal plate facing outside. The connecting metal material layer of each of the individual pieces is overlapped and installed in the through hole of the core substrate, the solder of the connecting metal material layer is melted by heating, and the bonding In a state where the thermoplastic resin of the adhesive layer is in a liquid state, the unit pieces of each build-up layer are collectively placed in a predetermined place on the core substrate by the self-alignment effect due to the surface tension of the molten solder. After automatically aligning the position of, and curing the bonding metal material layer and the bonding adhesive layer, a step of cutting the core substrate into a plurality of pieces,
It is characterized by including.

  According to a third aspect of the present invention, in a method for manufacturing a printed wiring board, a step of laminating a build-up layer and a connecting metal material layer made of solder on a single metal plate, and a metal plate including a formed product, A step of cutting and dividing into a plurality of pieces, a step of forming a core substrate having a through hole, a step of forming a liquid bonding adhesive layer at a predetermined position on the core substrate, and each of the pieces as the metal Overlaying the connecting metal material layer of each individual piece in the through hole of the core substrate by overlapping the core substrate with a plate outside, and heating the connecting metal material layer After the solder is melted and the individual pieces of each buildup layer unit are automatically aligned at a predetermined position on the predetermined core substrate by the self-alignment effect due to the surface tension of the molten solder, And a step of curing the bonding metal material layer and the bonding adhesive layer, curing the liquid bonding adhesive layer, and cutting the core substrate into a plurality of pieces. .

  In a fourth aspect of the present invention, in a method for manufacturing a printed wiring board, a step of forming a connection metal material layer made of a buildup layer and solder on a single metal plate, and a plurality of metal plates including a formed product Forming a core substrate having a through hole, forming a hole in a predetermined position of the prepreg corresponding to the through hole position of the core substrate, and connecting metal material to the hole A step of installing a layer, and each of the pieces is overlaid on the core substrate on which the prepreg is placed with the metal plate facing outside, and the via hole of each piece and the metal material layer for connection of the prepreg And the through hole of the core substrate are overlaid, and the prepreg is thermally cured by heating and pressing, and the via hole of each piece and the scan of the core substrate are cured. A step of bonding by the bonding metal material layer in a state of being close to Horu, characterized in that it and a step of cutting the core substrate into a plurality of pieces.

  According to a fifth aspect of the present invention, in the semiconductor device, a semiconductor element is mounted on the printed wiring board.

  According to the present invention (Embodiment 1), since the separately manufactured build-up layer and the core substrate are bonded together, the yield can be improved.

  In the present invention, the entire printed wiring board is formed by the core substrate 40 that can be manufactured at low cost, and the build-up layer 20 separately formed only in the region where a high-precision pattern is required is formed by the bonding metal material layer 29. Since it is installed above, there is an effect that the manufacturing cost of a printed wiring board having a highly accurate pattern portion can be reduced.

  In addition, the conductive pad of the printed wiring board, to which the minute bumps for connecting the printed wiring board and the semiconductor element 50 are connected, is formed with a small diameter, and the first via hole 24 immediately below the conductive pad is formed. The average diameter of the via hole 24 immediately below the electrode pad is formed to be larger by forming the lower diameter larger than the diameter of the conductive pad. That is, the via according to the printed wiring board of the present invention has a truncated cone shape and has a large volume. For this reason, the current capacity can be increased.

  Further, even when the buildup layer 20 and the core substrate 40 are initially placed so as not to be positioned so precisely, the thermosetting resin in the gap between the two melts into a liquid state. Therefore, since the via hole of the buildup layer 20 and the through hole 41 of the core substrate 40 are precisely aligned by the self-alignment effect of the molten bonding metal material layer 29, the accurate alignment can be finally performed. . Therefore, there is an effect that an increase in cost required for alignment can be prevented.

  Further, according to the present invention (Embodiment 2), the semiconductor element is arranged in the opening region of the metal plate 21 and connected to the surface of the flat buildup layer 20 without warping. The connection portion with the semiconductor element is stable and highly reliable. Moreover, since the buildup layer is provided on the flat metal plate, the flatness of the buildup layer is good, and there is an effect that the bonding with the core substrate is also good.

(Embodiment 1)
A semiconductor device and a printed wiring board according to Embodiment 1 of the present invention will be described with reference to the drawings. 1A is a perspective view from the front side, FIG. 1B is a perspective view from the back side, and FIG. 1C is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention. is there. The semiconductor device according to the first embodiment applies a flip chip ball grid array (FCBGA).

  Referring to FIG. 1A, the semiconductor device 1 includes a printed wiring board 10 and a semiconductor element 50. The printed wiring board 10 has a build-up layer on a core substrate. In the build-up layer, a plurality of wiring layers and insulating layers are alternately stacked, and the wiring layers are via-connected. The buildup layer in the printed wiring board 10 can be formed by a known buildup method. The semiconductor element 50 is mounted on the printed wiring board 10.

  Referring to FIG. 1B, a first bump 70 is mounted on the surface (back surface) opposite to the surface (front surface) on which the semiconductor element of the printed wiring board 10 is disposed.

  Referring to FIG. 1C, the semiconductor device 1 includes a buildup layer 20, a core substrate 40, a second conductive pad 44, a fifth insulating layer 45, a first bump 70, and a semiconductor. The element 50, the second bump 80, and the sealing resin 60 are included.

  First, the buildup layer 20 will be described. The buildup layer 20 includes a first conductive pad 22, a first insulating layer 23, a first via hole 24 via-connected to the first conductive pad 22, a second insulating layer 25, A second via hole 26 via-connected to the first via hole 24, a third insulating layer 27, a third via hole 28 via-connected to the second via hole 26, a bonding metal material layer 29, and a bonding adhesive layer 30 and a solder resist layer 33.

  The first conductive pad 22 is a conductive medium formed on the surface (on the second bump 80 side) of the first via hole 24. The first conductive pads 22 correspond to the corresponding second conductive pads 44 through at least the first via hole 24, the second via hole 26, the third via hole 28, the bonding metal material layer 29, and the through hole 41. And is electrically connected. For the first conductive pad 22, for example, at least one metal selected from gold, tin, nickel, and solder by electroless plating, electrolytic plating, or the like can be used, and an alloy thereof can be used. it can. The first conductive pad 22 may have not only a single-layer structure but also two or more layers. The first conductive pad 22 can be formed by considering the adhesiveness between the first conductive pad 22 and the second bump 80. In order from the via hole 24 side, a two-layer structure of a nickel plating layer having a thickness of 1 μm to 7 μm and a gold plating layer having a thickness of 0.3 μm to 3 μm is optimal.

  The first insulating layer 23 is an epoxy resin that is an insulating resin layer bonded to the solder resist 33, an acrylate compound resin having a fluorene skeleton, a polyimide resin, polybenzoxazole, polybenzocyclobutene, and a silicone resin. Or various insulating resins such as a mixture of two or more thereof. The thickness of the first insulating layer 23 is preferably 10 μm to 60 μm from the viewpoint of mounting reliability of the semiconductor element 50 on the printed wiring board and workability. The first insulating layer 23 has an opening for forming a first via hole 24 having a diameter of about 75 μm at a position corresponding to an electrode terminal (not shown) of the semiconductor element 50. The first via hole 24 is configured such that the diameter on the second insulating layer 25 side is wider than the diameter on the first conductive pad 22 side. Thereby, the diameter of the first conductive pad 22 is formed to a small diameter that matches the size of the minute second bump 80 bonded to the electrode terminal of the semiconductor element 50, and the average of the first via holes 24 is formed. There is an effect that the diameter of the first via hole 24 can be increased and the current capacity of the first via hole 24 can be increased. As the first insulating layer 23, for example, epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, bismaleimide triazine resin, polyphenylene ether resin, fluorine resin, benzocyclobutene resin, liquid crystal polymer, etc. 1 type or 2 or more types of insulating resins selected from these insulating resins may be used, and may be a thermosetting resin or a photosensitive resin. For example, a photosensitive solder resist (manufactured by Taiyo Ink Manufacturing Co., Ltd.) PSR4000 NAS-90-TY, Tamura Kaken DSR 2200 BGX-8, etc.) can be used. In order to increase the substrate strength, a glass cloth, a glass nonwoven fabric, an aramid nonwoven fabric, an aramid film, a polyimide film, or the like may be laminated on the insulating resin as a reinforcing material. Further, a resin film or a copper foil with resin (RCC) can be used for the first insulating layer 23. The first insulating layer 23 is particularly preferably made of a low elastic material having an elastic modulus of 0.1 GPa to 10 GPa at room temperature, for example, a silicone resin or a polyimide resin modified with a silicone resin. This is because the stress due to the difference in thermal expansion coefficient between the semiconductor element 50 and the printed wiring board 10 can be absorbed by the first insulating layer 23 and the occurrence of cracks in the printed wiring board can be suppressed.

  The first via hole 24 is a hole formed by carbon dioxide laser drilling in the first insulating layer 23 under the first conductive pad 22, and the diameter of the surface on the side where the semiconductor 50 is mounted is 50 μm, and vice versa. The diameter of the side surface is 80 μm and the thickness of the first insulating layer is 45 μm, or the hole formed by UV-YAG laser drilling, and the diameter of the surface on which the semiconductor 50 is mounted is 25 μm The via hole is formed by filling a conductor into a hole having a diameter of 45 μm on the opposite side and a thickness of the first insulating layer of 25 μm. The first via hole 24 is formed by electrolytic plating. In addition, on the front and back surfaces of the first insulating layer 23 connected to the first via hole 24, a conductor wiring layer is formed by a known full additive method, subtractive method using electroless plating, electrolytic plating, or the like. Form. For the first via hole 24 or the wiring layer connected to the first via hole 24, for example, at least one metal selected from gold, silver, copper, nickel or the like or an alloy thereof can be used. Is optimal. Further, the first via hole 24 may be formed by filling a conductive material such as a conductive paste.

  The second insulating layer 25 is an insulating resin layer formed on the surface of the first insulating layer 23. The second insulating layer 25 has an opening that is in electrical communication with the first via hole 24 via the conductor wiring layer, and the opening is filled with a conductor by a via hole 26 that makes electrical connection between the wiring layers. Formed. The opening in the second via hole 26 of the second insulating layer 25 is configured such that the diameter on the third insulating layer 27 side is larger than the diameter on the first via hole 24 side. The second insulating layer 25 can be formed using the same material as the first insulating layer 23.

  The second via hole 26 is a hole formed in the second insulating layer 25 by carbon dioxide laser drilling. The diameter of the surface on which the semiconductor 50 is mounted is 50 μm and the diameter of the opposite surface is 80 μm. In the hole where the thickness of the insulating layer 2 is 45 μm, or a hole formed by UV-YAG laser drilling, the diameter of the surface on which the semiconductor 50 is mounted is 25 μm, and the diameter of the opposite surface is 45 μm. Thus, a via hole is formed by filling a hole in the second insulating layer with a thickness of 25 μm and is electrically connected (via connection) to the first via hole 24 via the conductor wiring layer. The second via hole 26 can be made of the same material as that of the first via hole 24, and copper is optimal from the viewpoint of cost.

  The third insulating layer 27 is an insulating resin layer formed on the surface of the second insulating layer 25 including the second via hole 26. The third insulating layer 27 has an opening that is in electrical communication with the second via hole 26 via the conductor wiring layer, and the opening is filled with a conductor by a via hole 28 that makes electrical connection between the wiring layers. Formed. The opening in the third via hole 28 of the third insulating layer 27 is configured such that the diameter on the bonding adhesive layer 30 side is larger than the diameter on the second via hole 26 side. For the third insulating layer 27, a material similar to that of the first insulating layer 23 can be used, and a material different from that of the first insulating layer 23 and the second insulating layer 25 may be used. When the bonding metal material layer 29 is formed on the surface of the via hole 28, a solder resist may be used.

  The third via hole 28 is a hole formed in the third insulating layer 27 by a carbon dioxide laser drilling process. The diameter of the surface on which the semiconductor 50 is mounted is 50 μm, the diameter of the opposite surface is 80 μm, 3 is a hole in which the thickness of the insulating layer is 45 μm, or a hole formed by UV-YAG laser drilling, the diameter of the surface on which the semiconductor 50 is mounted is 25 μm, and the diameter of the opposite surface is 45 μm. Thus, the via hole is formed by filling the hole in which the thickness of the third insulating layer is 25 μm with a conductor, and is electrically connected (via connection) to the second via hole 26 via the wiring layer of the conductor. For the third via hole 28, the same material as that of the first via hole 24 can be used, and copper is optimal from the viewpoint of cost. The third via hole 28 has a structure in which the height is 5 μm to 30 μm and the diameter is 10 μm to 100 μm from the surface of the third insulating layer 27. As the shape of this protrusion, a plurality of protrusions of two points, three points, or more can be formed on the ring surrounding the central depression.

  The bonding metal material layer 29 is a conductive layer for metal-bonding the third via hole 28 and the through hole 41 (or a conductive pillar formed by filling a conductive filler 43 into the hole), and is at least a third layer. A metal layer having a thickness of 1 μm to 60 μm is interposed between the via hole 28 and the through hole 41 (or a conductive pillar formed by filling a conductive filler 43 into the hole). The bonding metal material layer 29 may be any metal that can be metal-bonded to the through-hole 41 (or the conductive pillar formed by filling the conductive filler 43 in the hole) and can be reflowed by heat. For example, solder can be used. Among solders, Sn, In, or Sn, Ag, Cu, Zn, Bi, Pd, Sb, Pb, In, Au, such as solder, such as Sn-Ag solder, Sn-Au solder, etc. It is preferable to use it. Particularly preferred is an environment-friendly Pb-free solder. Also, a solder paste containing powdered solder, resin, solvent, etc. disclosed in JP-A-8-174264 can be used. If the solder paste is used, there is an advantage that it is not necessary to perform cleaning.

  The bonding adhesive layer 30 joins (electrically connects) the third via hole 28 and the through hole 41 (or a conductive pillar formed by filling the hole with the conductive filler 43) via the bonding metal material layer 29. The insulating resin layer that adheres the build-up layer 20 (the third insulating layer 27) and the core substrate 40 (the fourth insulating layer 42). The bonding adhesive layer 30 can be made of a thermoplastic resin such as PMMA (polymethyl methacrylate). As shown in FIG. 3C, the bonding adhesive layer 30 is placed on the core substrate 40 connection surface of the buildup layer 20, and then the individual pieces of the buildup layer 20 are placed on the core substrate 40 to connect them. To do. At this time, the bonding adhesive layer 30 is made of a thermoplastic resin, and the resin is melted and liquefied by heating, so that the buildup layer 20 moves on the core substrate 40 and can be aligned. Alternatively, the bonding adhesive layer 30 may be a non-flow underfill material, and a liquid epoxy resin composition that can be a non-flow underfill material at the beginning of manufacture is dropped onto a predetermined position of the core substrate 40 by a dispenser or an inkjet method. After installing, the individual pieces of the metal plate 21 on which the buildup layer 20 is formed on the droplets of the core substrate 40 are installed so that the buildup layer and the core substrate face each other. And the core substrate 40. In addition, when a solder paste containing powdered solder, resin, solvent, etc. disclosed in JP-A-8-174264 is used for the bonding metal material layer 29, the non-flow underfill material for the bonding adhesive layer 30 is Alternatively, a liquid epoxy resin composition having no solder flux component may be used. Further, the protruding portion of 5 to 30 μm of the third via hole 28 is brought into contact with the protruding portion of the through hole 41 of the core substrate 40 in the bonding adhesive layer 30, or is close by a minute gap of at most several micrometers. Further, by filling the gap between the protruding portion of the third via hole 28 and the protruding portion around the contact portion of the protruding portion of the through hole 41 with the bonding metal material layer 29, the electrical connection can be further ensured. At the same time, the displacement of the gap between the protruding portion of the third via hole 28 and the protruding portion of the through hole 41 is kept within several μm to stabilize the relative position. Therefore, even if the bonding metal material layer 29 is remelted by heating when the semiconductor element 50 is flip-chip mounted later, the electrical connection reliability between the through hole 41 of the core substrate 40 and the third via hole 28 There is an effect that can be sufficiently secured. Here, as the protruding portion having a height of 5 μm to 30 μm of the third via hole 28, in the case where a plurality of protruding portions are formed in an annular shape surrounding the central depression, for bonding to the central depression of the annular ring The metal material layer 29 may be filled and metal-bonded. In this way, a strong metal bonding between the protrusions can be obtained by the bonding metal material layer 29 in the center of the annular ring, and the excess volume of the bonding metal material layer 29 includes a plurality of ring-shaped rings. There is an effect that the volume flows out from the gap between the protrusions to the outside of the ring and the volume is adjusted.

  The solder resist 33 is a protective layer disposed in a region excluding the region where the semiconductor element 50 is mounted on the surface of the first insulating layer 23 on the semiconductor element 50 side. In the first embodiment, the solder resist 33 has a frame shape. However, the present invention is not limited to this, and the solder resist 33 may not be formed depending on the specifications of the printed wiring board. Further, the solder resist 33 may have a form having an opening at each part of the second bump 80.

  Next, the core substrate 40 will be described. As schematically shown in FIG. 1C, the core substrate 40 is a double-sided wiring substrate or a multilayer substrate having a larger number of layers, and a fourth insulating layer 42 made of a material described later is drilled. A hole is formed by machining or laser drilling, and a through hole 41 formed by electroless copper plating and electrolytic copper plating is formed on the wall surface of the hole. A filler 43 is filled in the portion of the through hole 41. The thickness of the substrate is 0.1 mm or more. The through hole 41 can be made of the same material as the first via hole 24, and copper is optimal from the viewpoint of cost. The through hole 41 can also be formed by filling the through hole of the substrate with a filler 43 of a conductive paste having a metal powder component without metal plating on the wall surface. The through hole 41 is a conductor pillar or a hollow conductor pillar having a diameter of 0.08 mm to 1 mm, and is formed to protrude from the surface of the core substrate 40 at a height of 15 μm to 30 μm. Further, the following materials can be used for the fourth insulating layer 42. That is, glass fiber-containing resins such as glass fiber-containing epoxy resin material, glass fiber-containing bismaleimide-triazine resin (hereinafter referred to as BT resin) material, glass fiber-containing polyimide resin material, and glass fiber-containing PPE resin material can be used. In addition, as a reinforcing material of various materials such as the above, reinforcing materials such as polyester fiber, aramid fiber, or glass paper can be used instead of glass fiber. Moreover, what added the filler to resin can also be used as a reinforcing material. In this case, as the filler, for example, an inorganic filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide can be used. Instead of the above inorganic filler, an organic filler such as a phenol resin or a polymethacrylic acid polymer may be used, or an organic / inorganic mixed filler may be used. Further, for example, a conductive paste or the like can be used as the filler 43, but it is not always necessary to be conductive, and an insulating filler such as a resin may be used. Alternatively, the conductive paste may be exposed on the surface of the filler 43, that is, the end surface of the through hole 41, and bonded to the bonding metal material layer 29, or the end surfaces of the through hole 41 and the filler 43 may be plated with copper. May be formed, and the conductive pad and the bonding metal material layer 29 may be bonded. The structure in which the bonding metal material layer 29 is bonded immediately above the end surfaces of the through hole 41 and the filler 43 so that the straight electrical connection from the through hole 41 to the bonding metal material layer 29 is achieved by this structure. This is the most desirable structure because electrical connection provides excellent electrical properties with low inductance. A conductive pad electrically connected to the through hole 41 is formed at an end of the through hole 41 at a position shifted from the position directly above the through hole 41, and the bonding metal material layer 29 is bonded to the conductive pad. Is also possible.

  The second conductive pad 44 is a conductive medium formed on the surface of the through hole 41. The second conductive pads 44 correspond to the corresponding first conductive pads 22 through at least the through holes 41, the bonding metal material layer 29, the third via holes 28, the second via holes 26, and the first via holes 24. And is electrically connected. The second conductive pad 44 can be made of the same material as that of the first conductive pad 22, and considering the adhesion with the first bump 70, the second via hole 26 side in order. A two-layer structure of a nickel plating layer having a thickness of 1 μm to 7 μm and a gold plating layer having a thickness of 0.3 μm to 3 μm is optimal.

  The fifth insulating layer 45 is an insulating resin layer formed on the surface (on the first bump 70 side) of the core substrate 40. The fifth insulating layer 45 has an opening communicating with the through hole 41, and the second conductive pad 44 is disposed in the opening. For the fifth insulating layer 45, a material similar to that of the first insulating layer 23 can be used, and considering that it is a surface layer of the buildup layer 20, a solder resist is optimal.

  The first bump 70 has a hemispherical, cylindrical shape with a size of about the size of the through hole 41 for electrically connecting the second conductive pad 44 to an external printed wiring board (not shown). Alternatively, it is a quadrangular columnar conductive projection medium. For the first bump 70, a metal material such as gold, copper, or solder (Sn—Pb eutectic solder, Sn—Ag—Cu solder, etc.), a conductive resin, or the like is used.

  The semiconductor element 50 is a semiconductor chip such as an LSI, and the electrode terminals of the semiconductor element 50 are connected to the first conductive pads 22 via the corresponding second bumps 80. For the second bump 80, the same material as that of the first bump 70 can be used, and solder is optimal from the viewpoint of handling and the like.

  The sealing resin 60 is an insulating resin that seals a gap between the semiconductor element 50 and the first insulating layer 23. A known sealing material (for example, epoxy resin) can be selected and used for the sealing resin 60 according to the required characteristics.

  Next, a method for manufacturing a semiconductor device and a printed wiring board according to Embodiment 1 of the present invention will be described with reference to the drawings. 2 and 3 are partial cross-sectional views schematically showing the main manufacturing steps in the order of the steps of the build-up layer in the printed wiring board according to Embodiment 1 of the present invention. 4 and 5 are partial cross-sectional views schematically showing the cross-section of the printed wiring board according to the first embodiment of the present invention in the order of the main manufacturing steps. 2 and 3 and FIGS. 4 and 5 are simply divided for convenience of drawing. The semiconductor device manufacturing method according to the first embodiment can be roughly divided into two steps: (1) a build-up layer manufacturing stage and (2) a bonding stage.

  The manufacturing stage of the buildup layer will be described.

  First, a plating resist 31 having an opening 31a for forming the first conductive pad 22 is formed on the surface of a metal plate 21 (for example, a copper plate) having a thickness of 0.1 mm to 1.5 mm (step A1). ; See FIG. 2 (A)). Here, the plating resist 31 is formed by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like if the plating resist 31 is liquid, and a lamination method or the like if the plating resist 31 is a dry film. Then, it is hardened by performing a treatment such as drying, and if the plating resist 31 is photosensitive, it is patterned by a photolithography process or the like, and if it is non-photosensitive, it is patterned by a laser processing method or the like.

  Next, a first conductive pad 22 (for example, gold) is formed in the opening 31a of the plating resist 31 (step A2; see FIG. 2B). In addition, after forming the 1st electroconductive pad 22, the plating resist 31 is peeled off (step A3; refer FIG.2 (C)).

  Next, after the first insulating layer 23 is formed on the surfaces of the metal plate 21 and the first conductive pad 22, an opening 23 a communicating with the first conductive pad 22 is formed in the first insulating layer 23. (Step A4; see FIG. 2D). Here, as a method for forming the first insulating layer 23, for example, (1) a method in which a resin film is attached and the opening 23 a is formed by a laser beam such as a YAG laser or a carbon dioxide gas laser; A method of removing the unnecessary copper foil by attaching a copper foil (RCC), etching the copper foil of the opening 23a, forming the opening 23a by plasma processing or laser processing, and (3) thermosetting resin A method of forming the opening 23a with a laser beam such as a YAG laser or a carbon dioxide gas laser by printing, coating, etc., (4) As the first insulating layer 23, a photosensitive resin is printed, coated, etc., and cured. There is a method of forming the opening 23a by a photolithography method. By these methods, the first conductive pad 22 is formed in a portion where a via is formed by filling the opening 23a of the first insulating layer 23 with at least a conductive material connected to the first via hole 24. The diameter on the second insulating layer 25 side can be made wider than the diameter on the side. In addition, when the opening 23a is formed by laser light, it is preferable to wash with a permanganic acid solution in order to remove contamination attached to the wall surface of the opening 23a.

  Next, in the first insulating layer 23 including the first conductive pad 22, the first via hole 24, a conductor wiring layer on the surface thereof, the second insulating layer 25, the second via hole 26 and the conductor Wiring layer, the third insulating layer 27, the third via hole 28 and the conductor wiring layer are formed in this order, and a buildup layer in which the wiring layers are via-connected is formed (step A5; see FIG. 3A). ). Here, the first via hole 24 (for example, copper plating) performs, for example, chemical roughening (desmearing, resin roughening treatment, etc.) on the surface of the first insulating layer 23, and then the first insulating layer 23. After forming a seed layer on the surface (including the via bottom) by electroless copper plating, and then laminating a dry film for circuit formation on the substrate, and then forming a desired wiring pattern through mask exposure and development processes The wiring pattern can be formed by electrolytic plating, the dry film is peeled off, and then the seed layer is removed by etching. The second via hole 26 and the third via hole 28 (for example, copper plating) can also be formed by the same method as the first via hole 24. That is, the third via hole 28 has a surface of the third insulating layer 27 (including the bottom of the via hole) having a thickness of 10 μm to 60 μm formed on the surface of dimethylformamide (DMF), dimethyl sulfoxide (DMSO), N-methyl-2-pyrrolidone ( NMP), pyridine or the like is used to swell the insulating layer, and then chemical roughening treatment is performed using a chemical having an oxidizing power such as potassium permanganate, potassium dichromate or concentrated sulfuric acid. A plating seed in which a catalyst is adsorbed and then an electroless copper plating layer is formed from 0.3 μm to 10 μm using an electroless plating method using an EDTA-containing plating solution containing an ethylenediaminetetraacetic acid-copper complex (EDTA-Cu) A layer (electrolytic plating power supply conductor) is formed on the surface (including the via hole bottom) of the third insulating layer 27. Thereafter, a dry film for circuit formation is laminated on the substrate, and a desired wiring pattern is formed through mask exposure and development processes. Next, copper plating is performed with an electrolytic copper plating solution until the third via hole 28 is filled, and a copper wiring pattern is formed on the surface of the third insulating layer 27. Next, the dry film is peeled off, and then the plating seed layer is removed by etching, thereby forming the third via hole 28, the protruding portion on the surface thereof, and the wiring pattern. The second insulating layer 25 (for example, a copper foil with resin) can be formed by the same method as the first insulating layer 23 (for example, a method using a copper foil with resin). The via can be formed by a method such as metal plating, a method of filling a conductive material made of metal, or a method of filling a conductive paste by screen printing. A wiring layer and an insulating layer may be further formed between the second via hole 26 and the third via hole 28, and the layers may be via-connected. The third insulating layer 27 can be formed by a method similar to that of the first insulating layer 23 (for example, a method using a photosensitive resin (solder resist)).

  Next, a bonding metal material layer 29 is formed on the surface (tip) of the third via hole 28 (step A6; see FIG. 3B). Here, the bonding metal material layer 29 is formed by printing a solder alloy electroless plating, electrolytic plating, or a paste containing a solder alloy on the surface of the third via hole 28 as shown in FIG. 3B. Form. The shape of the bonding metal material layer 29 may be formed in a ball shape or a disk shape with an appropriate amount of solder. In the method of printing the paste containing the solder alloy, it is necessary to accurately align the printing mask with respect to the third via hole 28. However, in the method using electroless plating or electrolytic plating, the third via hole 28 Since the bonding metal material layer 29 can be formed with the position accurately adjusted, it is easy to cope with the miniaturization and high density of the third via hole 28. In particular, the electrolytic plating method is very suitable because the chemical solution can be easily managed. In FIG. 3B, the bonding metal material layer 29 is formed on the surface of the third via hole 28. The purpose of forming the bonding metal material layer 29 is to form the third via hole 28 and the through hole. 41 (FIG. 4A) is bonded to the surface of the through hole 41 (FIG. 4A), the bonding metal material layer 29 may be formed on the surface of the through hole 41 (FIG. 4A). You may form in the both surfaces of the hole 41 (FIG. 4 (A)).

  Next, a thermoplastic resin is formed as a bonding adhesive layer 30 on the surface of the buildup layer 20 to be connected to the core substrate 40 (step A7; see FIG. 3C). Alternatively, a liquid epoxy resin composition that can be a non-flow underfill material is dropped on a surface of the core substrate 40 on the side to which the buildup layer 20 is connected by a dispenser or an ink jet method, thereby dropping a predetermined position on the core substrate. A droplet-like bonding adhesive layer 30 is provided on the substrate.

  As mentioned above, the intermediate body of the buildup layer 20 before bonding and the joining contact bonding layer 30 are made by step A1-A7. When mass-producing the buildup layer 20, a plurality of buildup layers 20 are impositioned on a single metal plate 21, and then a metal plate on which a formation including the buildup layer is formed is bonded. Cut into easy-to-use units (for example, strip units). In addition, in order to align at the time of bonding with the core board | substrate 40 (refer FIG. 4 (A)) to the predetermined position of area | regions other than the part utilized as the buildup layer 20 among each unit before cutting. A positioning hole (not shown) may be formed. The positioning holes may be formed, for example, at diagonal positions (2 or 4 points) in the case of a strip-shaped unit, or may be formed one by one near the two opposing sides. You may also. Further, an alignment pad for self-alignment having a diameter of about 90 μm is formed on each unit and core substrate, and the thickness is about 35 μm, the diameter is about 80 μm, and the melting point is 183 ° C. on the alignment pad. Sn-Pb eutectic solder paste may be provided. Thus, by melting the solder at the time of bonding to the core substrate, the positions of the units can be aligned by the self-alignment effect due to the surface tension of the melted solder.

  Next, a bonding step in the case where the alignment pad described above is provided will be described.

  First, the individual pieces of the build-up layer 20 as an intermediate body having the metal plate 21 in which the thermoplastic resin is formed as the bonding adhesive layer 30 are aligned with the metal plate 21 facing upward, The unit alignment pad (not shown) is placed on the alignment pad (not shown) of the core substrate 40 with a solder paste in between (step B1; see FIG. 4A). Alternatively, a liquid epoxy resin composition droplet that can be a non-flow underfill material is placed at a predetermined position of the core substrate 40 as a material of the bonding adhesive layer 30, and an intermediate having the metal plate 21 on the droplet. The individual pieces of the build-up layer 20 are aligned with the metal plate 21 facing upward, and the alignment pads of the units of each build-up layer 20 are used as alignment pads of the core substrate 40 with solder paste interposed therebetween. Overlay and install. Here, the alignment is performed by the image recognition device (not shown) with reference to the positioning hole of the buildup layer 20 and the positioning hole of the core substrate 40 corresponding thereto. This operation is repeated, and a predetermined number of pieces of the build-up layer 20 as an intermediate body having the metal plate 21 are placed on the core substrate 40.

  Next, the aligned buildup layer 20 and the core substrate 40 are bonded together (step B2; see FIG. 4B). As a bonding method, the buildup layer 20 on the core substrate 40 is heated by an infrared reflow process in which the temperature is set to about 200 ° C., and the solder of the bonding metal material layer 29 is melted. Due to the self-alignment effect due to the surface tension of the molten bonding metal material layer 29, the build-up layer 20 having each metal plate 21 is automatically aligned at a predetermined position on each core substrate 40. At this time, since the bonding adhesive layer 30 is liquefied due to the thermoplastic resin, the movement of the build-up layer having the metal plate is not hindered. As a result, the bonding metal material layer 29 on the third via hole 28 eliminates the bonding adhesive layer 30 made of a resin or a liquid epoxy resin composition in which the thermoplastic resin is melted and liquefied. Join metal. At this time, the relative position between the third via hole 28 of the buildup layer 20 and the through hole 41 of the core substrate 40 is attracted to the optimum position by the surface tension in the molten state of the metal material layer 29, so that the buildup is performed. The layer 20 moves on the core substrate 40 to produce a self-alignment effect in which the layer 20 is accurately placed at the optimum position. Next, the buildup layer 20 is pressed onto the core substrate 40 using a pressure plate, and the protruding portion of the third via hole 28 and the protruding portion of the through hole 41 are brought into contact with each other, or a micro gap within a few micrometers at most. The bonding metal material layer 29 is cooled and solidified. Thereafter, the bonding adhesive layer 30 is cured by further cooling. As another manufacturing method, the bonding adhesive layer 30 is obtained by dropping a liquid non-flow underfill material made of a liquid epoxy resin composition or the like onto a predetermined position of the core substrate 40 by a dispenser or an inkjet method. Install. Thereafter, the piece of the metal plate 21 on which the buildup layer 20 is formed on the droplet is placed so that the buildup layer and the core substrate face each other. As a result, the bonding metal material layer 29 on the third via hole 28 eliminates the liquid non-flow underfill material and is metal-bonded to the through hole 41, so that the surface tension in the molten state of the metal material layer 29 is obtained. As a result, the relative position between the third via hole 28 of the buildup layer 20 and the through hole 41 of the core substrate 40 is attracted to the optimum position, and the buildup layer 20 moves on the core substrate 40 and is accurately installed at the optimum position. Produces a self-alignment effect. Next, the buildup layer 20 is pressed onto the core substrate 40 using a pressure plate, and the protruding portion of the third via hole 28 and the protruding portion of the through hole 41 are brought into contact with each other, or a micro gap within a few micrometers at most. The bonding metal material layer 29 is cooled and solidified, and the non-flow underfill material bonding adhesive layer 30 is thermally cured. As another method, the bonding adhesive layer 30 can be formed of the prepreg 110. That is, a prepreg 110 (or a B-stage resin sheet) having a thickness of 30 to 50 μm containing a reinforcing material such as glass fiber or aramid fiber is penetrated to a predetermined position corresponding to the position of the through hole 41 of the core substrate 40 in advance. The opening is filled with a conductive paste 111 such as a solder paste, an anisotropic conductive paste, or a conductive resin paste containing silver powder or copper powder. Thereafter, the prepreg 110 is sandwiched between the individual build-up layer 20 and the core substrate 40, and the third via hole 28 of each individual build-up layer 20 and the connecting metal material layer 29 at the opening of the prepreg 110 and the core substrate 40. The build-up layer 20 is pressed onto the core substrate 40 by stacking the through holes 41 and heated and pressed by vacuum pressing, so that the protrusions of the third via holes 28 and the protrusions of the through holes 41 are brought into contact with each other. The conductive paste 111 is filled in the gap between the projecting portions with a small gap of several micrometers or less. Then, the prepreg is thermally cured, and the via hole of each piece and the through hole of the core substrate are bonded together by the bonding metal material layer (see FIG. 6). Here, when the conductive paste 111 is composed of a conductive resin paste, the particle diameter of the silver powder or copper powder contained therein is preferably 3 μm or less. In the case where the conductive paste 111 is composed of an anisotropic conductive paste, the particle diameter of the conductive paste 111 is 0.1 μm or more in order to obtain the effect of the entrainment of the conductive particles or the anchor effect, and between the protrusions. In order to increase the contact area of the conductive joint portion, it is desirable to use one having a thickness of 5 μm or less. By sandwiching the conductive paste 111 containing these particles, the protruding portion of the third via hole 28 and the protruding portion of the through hole 41 are in contact with each other, or are close to each other with a very small gap of several micrometers or less. Can do.

  In FIG. 6, the size of the portion (land portion) connected to the conductive paste 111 of the through hole 41 is larger than the size of the portion (land portion) connected to the conductive paste 111 of the third via hole 28. However, the present invention is not limited to this, and the sizes of the opposing land portions may be the same. However, for the following reason, it is desirable that the size of one land portion is larger than the size of the opposite land portion. That is, the prepreg 110 filled with the conductive paste 111 in the penetrating portion has a thin sheet shape. For this reason, when the alignment hole provided in the buildup layer 20 can be visually recognized through the thin prepreg 110, when the prepreg 110 is stacked on the buildup layer 20, it is electrically conductive on the land portion of the third via hole 28. It is easy to align the conductive paste 111. However, when the core substrate 40 is further stacked on the prepreg, it can be said that it is difficult to align the land portion of the through hole 41 and the conductive paste 111. Therefore, if the size of the land of the through hole 41 is increased, even if the land portion of the through hole 41 and the conductive paste 111 are slightly misaligned, the land portion of the through hole 41 and the conductive paste 111 Can be connected. In other embodiments, the sizes of the opposing land portions of the build-up layer 20 and the core substrate 40 may be the same, but poor connection due to misalignment between the bonding metal material layer and the land portions. Therefore, it can be said that it is desirable to increase the size of one land portion.

  Next, after the fifth insulating layer 45 is formed on the surfaces of the fourth insulating layer 42 and the through hole 41, an opening 45a that communicates with the through hole 41 is formed in the fifth insulating layer 45 (step B3; (See FIG. 4C). The method for forming the fifth insulating layer 45 is the same as the method for forming the first insulating layer 23.

  Next, a second conductive pad 44 is formed on the surface of the through hole 41 (filler 43) exposed from the opening formed in the fifth insulating layer 45 (step B4; see FIG. 5A). . Here, the second conductive pad 44 (for example, a laminated structure of a nickel plating layer and a gold plating layer) can be formed by, for example, an electrolytic plating method.

  Next, the metal plate 21 is removed by etching, and a solder resist layer 33 is formed in a predetermined region on the exposed surface of the first insulating layer 23 (step B5; see FIG. 5B). Prior to the removal of the metal plate 21 by etching, an etching resist (not shown) is formed on the surface of the fifth insulating layer 45 including the second conductive pad 44 to protect the second conductive pad 44. May be.

  Thus, a substrate in which the individual buildup layers 20 are bonded to the surface of the core substrate 40 is formed. Next, the substrate is cut into pieces and separated.

  Finally, the semiconductor element 50 and this substrate are heated to about 220 ° C. and held for about 60 seconds, whereby the semiconductor element 50 is flip-chip connected to the first conductive pad 22 by the second bump 80 and sealed. The resin 60 is poured into the space between the semiconductor element 50 and the first insulating layer 23 to be cured, and the first bumps 70 are attached to the second conductive pads 44 (see step B6; FIG. 5C). ). Here, the 5 μm to 30 μm protruding portion of the third via hole 28 contacts the protruding portion of the through hole 41 of the core substrate 40 in the bonding adhesive layer 30, and the protruding portion of the third via hole 28 and the through hole In the case where the bonding metal material layer 29 is configured to fill the gap around the contact portion of the protruding portion 41, the semiconductor element 50 is heated by flip-chip mounting on the first conductive pad 22 here. Even if the bonding metal material layer 29 is remelted, the electrical connection reliability between the through hole 41 of the core substrate 40 and the third via hole 28 can be sufficiently secured.

  According to the printed wiring board configured as described above, since the buildup layer 20 and the core substrate 40 are separately manufactured, the yield can be improved. Furthermore, since the buildup layer 20 and the core substrate 40 can be bonded together after being manufactured in parallel, the manufacturing tact can be improved. Further, the diameter of the via hole connecting the wiring layers in the buildup layer 20 is configured such that the diameter on the surface side of the insulating layer on which the semiconductor element is arranged is narrower than the diameter on the surface side opposite to this surface. The diameter of the first conductive pad 22 is set to a small diameter that matches the size of the minute second bump 80 of the semiconductor element 50, and the average diameter of the first via hole 24 is set to a large diameter. Thus, the current capacity of the first via hole 24 can be increased.

(Embodiment 2)
Next, a semiconductor device and a printed wiring board according to Embodiment 2 of the present invention will be described with reference to the drawings. 7A is a perspective view from the front side, FIG. 7B is a perspective view from the back side, and FIG. 7C is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention. is there. The semiconductor device according to the second embodiment is different from the configuration of the semiconductor device according to the first embodiment in that the semiconductor device according to the second embodiment includes a metal plate 21 serving as a stiffener.

  Referring to FIG. 7A, the semiconductor device 1 includes a printed wiring board 10, a metal plate 21, and a semiconductor element 50. The metal plate 21 is laminated on the printed wiring board 10 and has a through-opening 21 a for accommodating the semiconductor element 50. The semiconductor element 50 is accommodated in the opening 21 a of the metal plate 21 and mounted on the printed wiring board 10.

  The metal plate 21 is a frame-shaped reinforcing plate (stiffener) in which an opening 21a penetrating in the center is formed. Further, since the metal plate 21 is made of metal, it has a function as the ground of the outermost layer. A semiconductor element 50 is accommodated in the opening 21 a of the metal plate 21. For the metal plate 21, for example, at least one metal selected from the group consisting of stainless steel, iron, nickel, copper and aluminum can be used, and an alloy thereof can be used. If so, copper is optimal. Moreover, the thickness of the metal plate 21 can be 0.1-1.5 mm, for example.

  Next, a method for manufacturing a semiconductor device and a printed wiring board according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 8 is a partial cross-sectional view schematically showing the main manufacturing process in the order of steps of the cross-section of the buildup layer in the printed wiring board according to Embodiment 2 of the present invention. 9 and 10 are partial cross-sectional views schematically showing the main manufacturing steps in the order of the steps of the printed wiring board according to Embodiment 2 of the present invention.

  The manufacturing stage of the buildup layer 20 will be described. First, the first conductive pad 22, the first insulating layer 23, the first via hole 24, and the second insulation are formed on the surface of the metal plate 21 (for example, a copper plate). A layer 25, a second via hole 26, a third insulating layer 27, and a third via hole 28 are formed (step C1; see FIG. 8A). In addition, the process of step C1 is the same as the process of step A1-A5 of Embodiment 1 (refer FIG.2 and FIG.3 (A)). Here, in the third via hole 28, a protruding portion protruding from the surface of the third insulating layer 27 at a height of 5 μm to 30 μm is formed. The protruding portion may have a protruding structure with a tip diameter of 1 μm to 10 μm and a diameter of 20 μm to 40 μm on the third via hole 28 side.

  Next, a pin-shaped bonding metal material layer 29 made of a solder alloy and projecting at a height of 20 μm to 100 μm is formed on the surface of the third via hole 28 (step C2; see FIG. 8B). . Here, as a method of making the bonding metal material layer 29 into a pin shape, a molten bonding metal material is attached to the surface of the third via hole 28, and a pin-shaped jig is brought into contact with the surface of the bonding metal material. Then, it can be formed by pulling up the jig. Further, as the protruding portion of the third via hole 28, a protruding portion having a protruding structure having a tip diameter of 1 μm to 10 μm and a diameter of 20 μm to 40 μm on the third via hole 28 side is formed, and the surface of the protruding portion is formed. It is also possible to form the bonding metal material layer 29 in a pin shape by bringing the bonding metal material into contact with the bonding metal material and then applying the material to the jig and pulling it up. In FIG. 8B, the bonding metal material layer 29 is formed on the surface of the third via hole 28. The purpose of forming the bonding metal material layer 29 is to form the third via hole 28 and the through hole. 41 (see FIG. 9A) is joined, and therefore, a joining metal material layer 29 may be formed on the surface of the through hole 41 (see FIG. 9A).

  Next, the bonding step will be described. First, the buildup layer 20 and the core substrate 40 are aligned with the metal plate 21 facing outside (step D1; see FIG. 9A). A bonding adhesive layer 30 is formed on the surface of the core substrate 40 on the buildup layer 20 side. The alignment method is the same as that in step B1 in the first embodiment.

  Next, the aligned buildup layer 20 and the core substrate 40 are bonded together (step D2; see FIG. 9B). The bonding method is the same as step B2 of the first embodiment.

  Next, a fifth insulating layer 45 and a second conductive pad 44 are formed on the surfaces of the fourth insulating layer 42 and the through hole 41 (step D3; see FIG. 10A). The method for forming the fifth insulating layer 45 and the second conductive pad 44 is the same as steps B3 to B4 in the first embodiment.

  Next, the metal plate 21 is removed by etching to form an opening 21a (step D4; see FIG. 10B). Here, at the time of etching, an etching resist 32 is formed on the surface of the metal plate 21 (and the surface of the fifth insulating layer 45 including the second conductive pad 44) excluding at least the region where the opening 21a is to be formed. By using this etching resist 32 as a mask, it can be formed by etching only the portion of the metal plate 21 exposed from the opening of the etching resist 32 (the first conductive pad 22 remains). The etching resist 32 can be formed by (1) a method of laminating the etching resist 32 by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like when the etching resist 32 is liquid, and (2) an etching resist. When 32 is a dry film, the etching resist 32 is laminated by a laminating method or the like, and then the etching resist 32 is hardened by performing a treatment such as drying. (3) When the etching resist 32 is photosensitive, by a photolithography method or the like There are a method of patterning the etching resist 32, and (4) a method of patterning the etching resist 32 by a laser processing method or the like when the etching resist 32 is non-photosensitive. Note that after the opening 21a is formed, the etching resist 32 is removed. The processes after Step D4 are the same as Step B6 of Embodiment 1 (see FIG. 5C).

  According to the printed wiring board configured as described above, since the printed wiring board 10 is provided on the flat metal plate 21, the flatness of the printed wiring board 10 is good. In the semiconductor device, since the semiconductor element 50 is disposed in the opening 21a region of the metal plate 21 and is connected to the outermost surface of the printed wiring board 10 that is flat and has no warpage, the printed wiring board 10 and the semiconductor element 50 are connected. The connection part is stable and reliable. Further, since the buildup layer 20 and the core substrate 40 are manufactured separately, the yield can be improved. Furthermore, since the build-up layer 20 and the core substrate 40 can be bonded together after being manufactured at the same time, the tact can be improved.

(Embodiment 3)
Next, a semiconductor device and a printed wiring board according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 11 is a partial cross-sectional view schematically showing a configuration of a semiconductor device according to Embodiment 3 of the present invention. The semiconductor device according to the third embodiment uses a second buildup instead of the second conductive pad and the fifth insulating layer (see 44 and 45 in FIG. 1C) in the semiconductor device according to the first embodiment. The layer 90 is bonded to the core substrate 40.

  The second buildup layer 90 includes a third conductive pad 92, a sixth insulating layer 93, a sixth via hole 94, a seventh insulating layer 95, a seventh via hole 96, and an eighth Insulating layer 97, eighth via hole 98, bonding metal material layer 99, and bonding adhesive layer 100.

  The third conductive pad 92 is a conductive medium formed on the surface (on the first bump 70 side of the sixth via hole 94) in the opening of the sixth insulating layer 93. The third conductive pad 92 includes at least a sixth via hole 94, a seventh via hole 96, an eighth via hole 98, a bonding metal material layer 99, a through hole 41, a bonding metal material layer 29, and a third via hole. 28, the second via hole 26, and the first via hole 24 are electrically connected to the corresponding first conductive pad 22. The third conductive pad 92 can be made of the same material as that of the first conductive pad 22, and considering the adhesion between the third conductive pad 92 and the sixth via hole 94, etc. The two-layer structure of a nickel plating layer and a gold plating layer is optimal in order from the via hole 94 side of 6.

  The sixth insulating layer 93 is an insulating resin layer disposed on the most first bump 70 side. The sixth insulating layer 93 has an opening at a position corresponding to the first bump 70, the opening is filled with a conductive material, and a connection via is formed. The opening of the sixth insulating layer 93 is such that the diameter on the seventh insulating layer 95 side is wider than the diameter on the third conductive pad 92 side at least in the portion filled with the conductive material. It is configured. The sixth insulating layer 93 can be made of the same material as that of the first insulating layer 23, and may be a solder resist in consideration of the surface layer of the printed wiring board 10.

  The sixth via hole 94 can be made of the same material as that of the first via hole 24, and copper is optimal from the viewpoint of cost.

  The seventh insulating layer 95 is an insulating resin layer formed on the surface (on the second bump 80 side) of the sixth insulating layer 93 including the sixth via hole 94. The seventh insulating layer 95 has an opening that communicates with the sixth via hole 94. The opening of the seventh insulating layer 95 is such that the diameter on the eighth insulating layer 97 side is wider than the diameter on the sixth via hole 94 side at least in the portion where the conductive material is filled and connected to the via. It is configured. For the seventh insulating layer 95, a material similar to that of the first insulating layer 23 can be used.

  The seventh via hole 96 is a conductive layer patterned on the surface (on the second bump 80 side) of the seventh insulating layer 95, and the sixth via hole 94 and the sixth via hole 94 through the opening of the seventh insulating layer 95. Connect electrically (via connection). The seventh via hole 96 may be further formed in multiple layers via the seventh insulating layer 95 to connect vias between the layers. For the seventh via hole 96, the same material as that of the first via hole 24 can be used.

  The eighth insulating layer 97 is an insulating resin layer formed on the surface (on the second bump 80 side) of the seventh insulating layer 95 including the seventh via hole 96. The eighth insulating layer 97 has an opening that leads to the seventh via hole 96. The opening of the eighth insulating layer 97 is configured such that the diameter on the bonding adhesive layer 100 side is larger than the diameter on the seventh via hole 96 side at least in the portion where the conductive material is filled and connected to the via. ing. The eighth insulating layer 97 can be made of the same material as that of the first insulating layer 23. When the bonding metal material layer 99 is formed on the surface of the eighth via hole 98, a solder resist is desirable. .

  The eighth via hole 98 is a conductive layer patterned on the surface (on the second bump 80 side) of the eighth insulating layer 97, and the seventh via hole 96 and the seventh via hole 96 through the opening of the eighth insulating layer 97. Connect electrically (via connection). The eighth via hole 98 can be made of the same material as that of the first via hole 24, and copper is optimal from the viewpoint of cost.

  Next, a method for manufacturing a semiconductor device and a printed wiring board according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 12 is a partial cross-sectional view schematically showing, in the order of steps, the main manufacturing process of the cross section of the second buildup layer in the printed wiring board according to Embodiment 3 of the present invention. 13 and 14 are partial cross-sectional views schematically showing the main manufacturing steps in the order of the steps of the printed wiring board according to Embodiment 3 of the present invention.

  First, the manufacturing process of a 2nd buildup layer is demonstrated.

  A plating resist 101 having an opening 101a for forming the third conductive pad 92 is formed on the surface of a metal plate 91 (for example, a copper plate) (step E1; see FIG. 12A). Here, the plating resist 101 can be formed by the same method as in step A1 of the first embodiment.

  Next, a third conductive pad 92 (for example, gold) is formed in the opening 101a of the plating resist 101 (step E2; see FIG. 12B). Note that after the third conductive pad 92 is formed, the plating resist 101 is peeled off (step E3; see FIG. 12C).

  Next, after a sixth insulating layer 93 is formed on the surfaces of the metal plate 91 and the third conductive pad 92, an opening 93 a communicating with the third conductive pad 92 is formed in the sixth insulating layer 93. (Step E4; see FIG. 12D). Here, the sixth insulating layer 93 can be formed by a method similar to the first insulating layer (23 in FIG. 2D) (for example, a method using a copper foil with resin).

  Next, on the surface of the sixth insulating layer 93 including the third conductive pad 92, a sixth via hole 94, a seventh insulating layer 95, a seventh via hole 96, an eighth insulating layer 97, an eighth Via holes 98 are formed in this order, a build-up layer in which the wiring layers are via-connected is formed, and then a bonding metal material layer 99 is formed on the surface (tip) of the eighth via hole 98, and the bonding metal material A bonding adhesive layer 100 is formed on the surface of the eighth insulating layer 98 including the layer 99 (step E5; see FIG. 12E). Here, the sixth via hole 94, the seventh via hole 96, and the eighth via hole 98 (for example, copper plating) are the same as those in the first wiring layer (24 in FIG. 3A; see step A5). It can be formed by a method. The seventh insulating layer 95 can be formed by a method similar to the first insulating layer (23 in FIG. 3A; see step A5) (for example, a method using a copper foil with resin). The eighth insulating layer 97 can be formed by a method similar to the first insulating layer (23 in FIG. 3A; see step A5) (for example, a method using a photosensitive resin (solder resist)). . The joining metal material layer 99 can be formed by the same method as the joining metal material layer (29 in FIG. 3B; see step A6). The bonding adhesive layer 100 can be formed by a method similar to that of the bonding adhesive layer (30 in FIG. 3C; see step A7). In addition, a wiring layer and an insulating layer may be formed in a multilayer between the seventh via hole 96 and the eighth via hole 98, and the layers may be via-connected.

  As mentioned above, the intermediate body of the 2nd buildup layer 90 before bonding is made by step E1-E5. In addition, when mass-producing the second buildup layer 90, as in the buildup layer 20, a plurality of second buildup layers 90 are formed on one metal plate 91, and a unit ( For example, it is cut into strip units. Then, alignment is performed at a predetermined position in a region other than a portion used as the second buildup layer 90 in the cut unit when bonding with the buildup layer (20 in FIG. 3C). A positioning hole for forming is formed.

  Next, the bonding step will be described.

  First, the assembly in which the core substrate 40 is bonded to the buildup layer 20 and the second buildup layer 90 are aligned and face each other so that the metal plates 21 and 91 face each other (step F1; (See FIG. 13A). The assembly in which the core substrate 40 is bonded to the buildup layer 20 is performed in the same manner as in steps A1 to A5, B1 and B2 (see FIGS. 2, 3A and 3B) of the first embodiment. Can be manufactured. The alignment can be performed by the same method as in step B1 (see FIG. 4A) of the first embodiment.

  Next, the assembly of the aligned buildup layer 20 and core substrate 40 is bonded to the second buildup layer 90 (step F2; see FIG. 13B). Note that the bonding method can be performed by a method similar to Step B2 of Embodiment 1 (see FIG. 4B).

  Next, the metal plate 21 is formed with an opening 21a in a region including the region where the first conductive pads 22 are formed, and the metal plate facing the metal plate 21 (91 in FIG. 13B). (Step F3; see FIG. 14A). Here, the metal plate (91 in FIG. 13B) is removed without forming an etching resist on the surface of the metal plate (91 in FIG. 13B). This is accomplished by etching the whole (the third conductive pad 92 remains). The method for forming the etching resist 32 is the same as that in Step B3 of Embodiment 1 (see FIG. 4C). Note that after the opening 21a is formed (the metal plate (91 in FIG. 13B) is removed), the etching resist 32 is removed.

  Finally, the semiconductor element 50 is flip-chip connected to the first conductive pad 22 by the second bump 80, and the sealing resin 60 is poured into the space between the semiconductor element 50 and the first insulating layer 23 and cured. Then, the first bump 70 is attached to the third conductive pad 92 (step F4; see FIG. 14B).

  According to the printed wiring board configured as described above, since the buildup layer 20 is provided on the flat metal plate 21, the flatness of the printed wiring board 10 is good. In the semiconductor device, since the semiconductor element 50 is disposed in the opening 21a region of the metal plate 21 and connected to the outermost surface of the flat buildup layer 20 without warping, the printed wiring board 10 and the semiconductor element 50 are connected. The connection part is stable and reliable. Further, since the buildup layer 20 and the second buildup layer 90 are manufactured separately, the yield can be improved. Furthermore, since the buildup layer 20 and the second buildup layer 90 can be bonded together after being manufactured at the same time, the lead time can be shortened and the tact can be improved. Depending on the specifications of the printed wiring board, all of the metal plate 21 may be removed by etching.

1A is a perspective view from the front surface side, FIG. 2B is a perspective view from the back surface side, and FIG. 2C is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention. It is the fragmentary sectional view which showed typically the cross section of the buildup layer in the printed wiring board concerning Embodiment 1 of this invention in order of the process about the first half of the main manufacturing processes. It is the fragmentary sectional view which showed typically the cross section of the buildup layer in the printed wiring board which concerns on Embodiment 1 of this invention about the latter half of the main manufacturing processes in order of the process. It is the fragmentary sectional view which showed typically the cross section of the printed wiring board which concerns on Embodiment 1 of this invention about the first half of the main manufacturing processes in order of the process. It is the fragmentary sectional view which showed typically the cross section of the printed wiring board which concerns on Embodiment 1 of this invention about the latter half of the main manufacturing processes in order of the process. It is the fragmentary sectional view which showed typically the cross section of the modification of the printed wiring board which concerns on Embodiment 1 of this invention in order of the process of the main manufacturing processes. FIG. 5A is a perspective view from the front surface side, (B) a perspective view from the back surface side, and (C) a partial cross-sectional view schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention. It is the fragmentary sectional view which showed typically the cross section of the buildup layer in the printed wiring board concerning Embodiment 2 of this invention the main manufacturing process in order of the process. It is the fragmentary sectional view which showed typically the cross section of the printed wiring board which concerns on Embodiment 2 of this invention about the first half of the main manufacturing processes in order of the process. It is the fragmentary sectional view which showed typically the cross section of the printed wiring board which concerns on Embodiment 2 of this invention about the latter half of the main manufacturing processes in order of the process. It is the fragmentary sectional view which showed typically the structure of the semiconductor device which concerns on Embodiment 3 of this invention. It is the fragmentary sectional view which showed typically the cross section of the 2nd buildup layer in the printed wiring board concerning Embodiment 3 of this invention about the main manufacturing process in order of the process. It is the fragmentary sectional view which showed typically the cross section of the printed wiring board which concerns on Embodiment 3 of this invention about the first half of the main manufacturing processes in order of the process. It is the fragmentary sectional view which showed typically the cross section of the printed wiring board which concerns on Embodiment 3 of this invention about the latter half of the main manufacturing processes in order of the process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Printed wiring board 20 Buildup layer 21 Metal plate 21a Opening part 22 1st electroconductive pad 23 1st insulating layer 23a Opening part 24 1st via hole 25 2nd insulating layer 26 2nd via hole 27 Third insulating layer 28 Third via hole 29 Bonding metal material layer 30 Bonding adhesive layer 31 Plating resist 31a Opening 32 Etching resist 33 Solder resist layer 40 Core substrate 41 Through hole 42 Fourth insulating layer 43 Filler 44 Second conductive pad 45 fifth insulating layer 45a opening 50 semiconductor element 60 sealing resin 70 first bump 80 second bump 90 second buildup layer 91 metal plate 92 third conductive pad 93 second 6 insulating layer 93a opening 94 sixth via hole 95 seventh insulating layer 96 seventh via hole 97 eighth insulating layer 98 eighth via hole 99 bonding metal material layer 100 bonding adhesive layer 101 plating resist 101a opening 110 prepreg 111 conductive paste

Claims (8)

A plurality of wiring layers and insulating layers are alternately stacked, the wiring layers are connected by via holes, and the diameter of the via holes is equal to the diameter of the first surface side of the insulating layer where the semiconductor element is arranged A buildup layer configured to be narrower than the diameter of the second surface side of the insulating layer on the opposite side of the first surface;
A core substrate having a through hole;
Have
The printed wiring board, wherein the core substrate and the build-up layer are bonded together, and the through hole of the core substrate and the via hole of the build-up layer are bonded by a bonding metal material layer.   The printed wiring board according to claim 1, wherein the bonding metal material layer is made of a metal material solidified after melting.   A plurality of wiring layers and insulating layers are alternately stacked on the opposite side of the core substrate to which the buildup layer is bonded, and a second buildup layer in which the wiring layers are connected by via holes is bonded, 3. The printed wiring according to claim 1, wherein the diameter of the via hole of the second buildup layer is configured such that the diameter on the core substrate surface side is narrower than the diameter on the opposite surface side to the core substrate. Board.   The via hole has a protruding portion on the second surface side of the insulating layer, the through hole has a protruding portion on the buildup layer side, and the protruding portion of the via hole has the protrusion of the through hole. The bonding metal material layer fills the space between the protrusions in contact with the protrusions or close to each other with a gap of several μm or less between the protrusions of the via holes and the contact parts of the protrusions of the through holes. It has a structure, The printed wiring board as described in any one of Claim 1 thru | or 3 characterized by the above-mentioned. Forming a buildup layer, a connecting metal material layer made of solder, and a bonding adhesive layer made of a thermoplastic resin on one metal plate;
A step of cutting and dividing the metal plate including a formed product into a plurality of pieces;
Forming a core substrate having a through hole;
A step of superimposing and placing the metal material layer for connection of each individual piece in the through hole of the core substrate by superimposing the individual piece on the core substrate with the metal plate facing outside; and
Each of the build-up layers has a self-alignment effect due to the surface tension of the melted solder in a state where the solder of the connecting metal material layer is melted by heating and the thermoplastic resin of the bonding adhesive layer is in a liquid state. A step of curing the unit metal material layer and the bonding adhesive layer after automatically aligning the individual pieces of the unit at a predetermined position of the predetermined core substrate; and
Cutting the core substrate into a plurality of pieces;
A printed wiring board manufacturing method comprising: Laminating a build-up layer and a connecting metal material layer made of solder on one metal plate;
Cutting and dividing a metal plate including a formation into a plurality of pieces;
Forming a core substrate having a through hole;
Forming a liquid bonding adhesive layer at a predetermined position on the core substrate;
A step of superimposing and placing the metal material layer for connection of each individual piece in the through hole of the core substrate by superimposing the individual piece on the core substrate with the metal plate facing outside; and
The solder of the connecting metal material layer is melted by heating, and the individual pieces of the units of the buildup layer are collectively put into a predetermined position of the core substrate by a self-alignment effect due to the surface tension of the molten solder. After the automatic alignment, the step of curing the bonding metal material layer and the bonding adhesive layer, and curing the liquid bonding adhesive layer;
Cutting the core substrate into a plurality of pieces;
A printed wiring board manufacturing method comprising: Forming a build-up layer and a connecting metal material layer made of solder on one metal plate;
Cutting and dividing a metal plate including a formation into a plurality of pieces;
Forming a core substrate having a through hole;
Forming a hole at a predetermined position corresponding to a through-hole position of the core substrate of the prepreg, and installing a connecting metal material layer in the hole;
The individual pieces are overlaid on the core substrate on which the prepreg is placed with the metal plate facing outside, and the via holes of the individual pieces, the connecting metal material layer of the prepreg, and the through of the core substrate are overlapped. A process of stacking the halls,
The step of thermosetting the prepreg by heating and pressurizing, and bonding the via hole of each piece and the through hole of the core substrate by the bonding metal material layer,
Cutting the core substrate into a plurality of pieces;
A printed wiring board manufacturing method comprising:   A semiconductor device comprising a semiconductor element mounted on the printed wiring board according to claim 1.

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