JP2006073572A - Semiconductor crystal defect testing method and equipment thereof, and semiconductor device manufacturing method using the semiconductor crystal defect testing equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor crystal defect testing method, etc. which uses cathode luminescence (CL) that enables checking of the measurement position at a high spacial resolution, and a sample analysis at a high spacial resolution. <P>SOLUTION: The semiconductor crystal defect testing method carries out the following processes in this order: a process of placing, on a stage 3, a substrate 2 containing a silicon layer on the front surface side; a process of cooling the substrate 2 to a temperature of 100-4 K; a process, wherein either the stage 3 or an electron beam for irradiating the substrate surface is moved two-dimensionally to irradiate the prescribed area of the substrate surface by the electron beam, with only a small portion of the region irradiated at a time and scanned over the prescribed region of the substrate surface to cover the entire region; a process of detecting near-infrared light, having a wavelength of 1,200-1,700 nm among the CL lights emitted from the substrate surface, and at the same time detecting secondary electrons generated from the substrate surface to check the detection position; and a process, wherein a secondary electron image which is an image of the substrate surface is displayed, based on the detected secondary electrons, and at the same time the intensity of the detected near-infrared light is displayed in correspondence with the secondary electron image to identify a portion of the substrate surface which has high intensity of near-infrared light. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor crystal defect inspection method and a semiconductor crystal defect inspection apparatus for inspecting a crystal defect generated when a semiconductor element is formed on a silicon layer on a surface side of the substrate. And a method of manufacturing a semiconductor device using the semiconductor crystal defect inspection apparatus.

  Conventionally, as a technique for inspecting semiconductor crystal defects, for example, there are those described in the following documents.

JP 56-35043 A Japanese Patent Publication No. 6-41915 Naoki Yamamoto "Applied Physics" Volume 69, No. 10 (2000)

  In the manufacture of a semiconductor device such as a semiconductor integrated circuit (hereinafter referred to as “IC”) or a large-scale semiconductor integrated circuit (hereinafter referred to as “LSI”), it is desirable that the semiconductor has no crystal defects as much as possible. However, it is very important to reduce defects by avoiding defects due to thermal stress, plasma or ion damage.

  Crystal defects include those in which atomic holes are vacant from lattice points (holes), and those in which atoms enter between lattice points (interstitial atoms), etc. There are four main types: point defects, line defects, surface defects, and body defects. Point defects include vacancies, self-interstitial atoms, interstitial impurities, and substitutional impurity types. In vacancies, tensile stress is applied to surrounding atoms, and in self-interstitial atoms, compressive stress is applied to surrounding atoms. It works and causes periodic fields in the crystal to be disturbed. Line defects include dislocations in which one of the crystals slips on a certain line, and rod-like defects that are aggregates of self-interstitial atoms with a thickness of about 10 μm and a thickness of about 10 μm. There is. A typical example of a plane defect is a stacking fault. This stacking fault is a defect in which the periodicity of the arrangement of lattice planes is caused by insertion or deletion of an extra atomic plane, and the boundary of the stacking fault is an edge dislocation. ing. In particular, in a semiconductor device, a dislocation with a large defect length greatly affects the semiconductor element characteristics, which is a serious problem.

  Various semiconductor crystal defect inspection methods and semiconductor crystal defect inspection apparatuses have been proposed so far. A typical example is a transmission electron microscope (hereinafter referred to as “TEM”) method. This is a method in which a specific portion of a sample is thinned, the thinned sample is irradiated with an electron beam, and crystal defects of the sample are evaluated from the transmitted electron beam. However, the thinning of the sample requires a lot of time and labor, and further, there is a problem that not all the samples can be examined, and only a specific place can be evaluated. Furthermore, since it is a destructive measurement, it was impossible to inspect all products.

  Other detection methods include an X-ray topography method and a Secco etching method. X-ray topography, also called X-ray diffraction microscopy, is a non-destructive method of observing the spatial distribution of defects. However, only relatively large defects can be detected, and the measurement takes time. Therefore, basically, the measured wafer cannot be returned to the manufacturing process. The Secco etching method is a method in which after removing the polysilicon electrode and the oxide film with a hydrofluoric acid solution, etching is performed with a Secco solution, and the etched surface is observed with an optical microscope. In this Secco etching method, it is necessary to remove all the patterns formed on the substrate. Therefore, nondestructive inspection cannot be performed, and quantitative and reproducibility is poor and time is required.

  In addition, a technique called emission microscopy has been devised, in which weak light emission generated from an abnormal part when an LSI is driven is detected and a faulty part is specified. Specifically, this apparatus is commercially available from Hamamatsu Photonics Co., Ltd. as a hot electron analysis apparatus PHEMOS series. With this apparatus, it is possible to identify a faulty part on the LSI. However, inspection was possible only when electricity was passed through the final product circuit with electrodes and the like, and could not be detected during the product manufacturing process. Also, the cause of the failure could not be identified.

  On the other hand, Patent Documents 1 and 2 and Non-Patent Document 1 have proposed luminescence devices using a scanning electron microscope (hereinafter referred to as “SEM”) that can be inspected nondestructively during the product manufacturing process.

  In Patent Document 1, in a sample evaluation apparatus using photoluminescence (hereinafter referred to as “PL”), means for irradiating a semiconductor element wafer with laser light, and light emission of the wafer by irradiating the laser light (luminescence). And detecting whether there is a decrease in emission intensity of a certain amount or more and means for selecting the wafer by the output of the detecting means, and non-destructive semiconductor crystals in the semiconductor manufacturing process Techniques for inspecting and evaluating defects are described.

  In patent document 2, as a main thing of the luminescence measuring device, a PL device that irradiates laser light to a sample in a cryogenic state and measures luminescence, a sample is placed in a vacuum, and the sample is irradiated with an electron beam. It is described that there is a cathodoluminescence (hereinafter referred to as “CL”) device for measuring luminescence. Information on the quality of the semiconductor crystal obtained from the CL measurement and the PL measurement is not necessarily the same. Rather, the measurement results of both may be in a complementary relationship in the semiconductor crystal evaluation. Measurement may be required. Therefore, in the technology of Patent Document 2, a CL apparatus and a PL apparatus are realized by the same apparatus, and a structure of a luminescence measuring apparatus that measures each luminescence independently or simultaneously at the same position of the same sample is proposed. Yes. In this luminescence measuring device, a semiconductor crystal is irradiated with an electron beam and a laser beam, the spectrum of luminescence generated by this irradiation and its intensity are measured, and the impurities, lattice defects and their complexes that are the origin of the spectrum are fixed. By doing so, the quality of the semiconductor crystal is analyzed.

  Non-Patent Document 1 describes the technology of the CL apparatus, which is commercially available, and includes the band gap, crystal state, and presence / absence of impurities such as compound semiconductors and dielectrics including gallium arsenide (GaAs). It has been applied in many evaluations.

  However, the conventional semiconductor crystal defect inspection method and semiconductor crystal defect inspection apparatus have the following problems.

  For example, in the case of detecting a crystal defect such as a compound semiconductor such as GaAs in a conventional CL apparatus, it can be detected with relatively high accuracy because a large amount of luminescence is generated when irradiated with an electron beam. However, when the semiconductor is silicon (Si), silicon is an indirect transition type semiconductor, and since the amount of luminescence generated even when irradiated with an electron beam is small, it is difficult to accurately detect crystal defects. Therefore, when trying to increase the detection accuracy by combining other inspection methods, the detection process becomes complicated, and it takes a long time to detect, and when used for manufacturing a semiconductor device such as an LSI having a large number of manufacturing processes, There was a problem that the manufacturing efficiency was lowered over time.

  The present invention solves the conventional problems, and a semiconductor crystal defect inspection method, a semiconductor crystal defect inspection apparatus, and a semiconductor device manufacturing method using the semiconductor crystal defect inspection apparatus capable of detecting a silicon crystal defect simply and with high sensitivity The purpose is to provide.

    In the semiconductor crystal defect inspection method of the present invention, a step of placing a substrate having a silicon layer on which a semiconductor element is to be formed on the surface side, a step of cooling the silicon layer of the substrate to a temperature of 100K to 4K, Two-dimensionally scanning either one of the support and an electron beam for irradiating the surface of the silicon layer, and sequentially irradiating a predetermined region of the surface of the silicon layer with the electron beam; Detecting near-infrared light having a wavelength of 1200 nm to 1700 nm generated from the silicon layer, detecting secondary electrons generated from the silicon layer, and a surface image of the silicon layer by the detected secondary electrons And the intensity of the detected near-infrared light having a wavelength of 1200 nm to 1700 nm corresponding to the secondary electron image is displayed. And a step of identifying a site intensity of the near-infrared light is large in the wavelength 1200nm~1700nm at the surface of the layer.

  The semiconductor crystal defect inspection apparatus of the present invention has an apparatus configuration using the semiconductor crystal defect inspection method.

  In the semiconductor device manufacturing method of the present invention, a semiconductor device such as an LSI is manufactured using the semiconductor crystal defect inspection apparatus.

  According to the semiconductor crystal defect inspection method and the semiconductor crystal defect inspection apparatus of the present invention, it is possible to inspect a silicon layer or a crystal defect of a semiconductor element formed on the silicon layer in a short time with high sensitivity.

  According to the method for manufacturing a semiconductor device of the present invention, it is possible to perform non-destructive inspection within a process for what kind of crystal defect exists in a silicon layer. It is possible to easily perform process design or Pann design that can be suppressed. Furthermore, as an index for inspecting the product quality, the crystal defect measurement can be used as an in-process inspection as in the case of the conventional dimension measurement and film thickness measurement, so that a high-quality product can be provided. Furthermore, since defective products having crystal defects can be selected at the initial stage, useless manufacturing processes can be reduced and manufacturing costs can be reduced.

  According to another method for manufacturing a semiconductor device of the present invention, a crystal defect generation process can be specified by measuring the same substrate a plurality of times in the manufacturing process. In addition, by standardizing the intensity of near-infrared light using a signal unrelated to crystal defects, it is possible to compare the number of defects with a small number, and link this with the control values for each manufacturing process. By doing so, it becomes an effective intra-manufacturing management method.

  In the semiconductor crystal defect inspection method of the present invention, a substrate having a silicon layer on the surface side on which a semiconductor element such as a MOS transistor is formed is prepared. Examples of the substrate include a silicon substrate, an SOS substrate in which a silicon layer is formed on a sapphire substrate by SOS (Si on sapphire) epitaxial growth by a chemical vapor deposition (hereinafter referred to as “CVD”) method, and a silicon on a glass substrate. There are substrates on which layers are formed.

  And a step of placing the prepared substrate on a support table, a step of cooling the silicon layer of the substrate to a temperature of 100K to 4K in order to efficiently emit luminescence caused by crystal defects, the support table and the Two-dimensionally scanning one of the electron beam for irradiating the surface of the silicon layer and sequentially irradiating a predetermined region of the surface of the silicon layer with the electron beam, and generated from the silicon layer Detecting near-infrared light having a wavelength of 1200 nm to 1700 nm and detecting secondary electrons generated from the silicon layer for confirmation of a detection position; and a surface of the silicon layer by the detected secondary electrons A secondary electron image as an image is displayed, and the intensity of the detected near infrared light having a wavelength of 1200 nm to 1700 nm is displayed in correspondence with the secondary electron image. A step of identifying a site intensity of the near-infrared light is large in the wavelength 1200nm~1700nm the surface of the silicon layer are sequentially performed.

  In such a semiconductor crystal defect inspection method, near-infrared light having a wavelength of 1200 nm to 1700 nm generated from the silicon layer may be detected after spectroscopy.

  In the semiconductor crystal defect inspection apparatus of the present invention, a movable or fixed support base that supports a substrate having a silicon layer on the surface side where semiconductor element formation processing is performed, and silicon of the substrate supported by the support base A cooling means such as a cryostat for cooling the layer to a temperature of 100K to 4K, and an electron beam for irradiating the surface of the silicon layer of the substrate supported by the support base under reduced pressure (for example, the beam diameter is several tens of nm) The fixed or movable electron beam generator such as an electron gun that emits the electron beam relative to the support base and sequentially irradiates a predetermined region on the surface of the silicon layer. First detection means such as an InGaAs multichannel detector that detects near-infrared light having a wavelength of 1200 nm to 1700 nm generated from the silicon layer by irradiation of the electron beam; A second detection unit that is a detector that detects secondary electrons generated from the silicon layer by irradiation of a line; and a surface image of the silicon layer by the secondary electrons detected by the second detection unit. Display means for displaying a secondary electron image and displaying the intensity of near infrared light having a wavelength of 1200 nm to 1700 nm detected by the first detection means in correspondence with the secondary electron image And.

  In such a semiconductor crystal defect inspection apparatus, the first detection means may detect the near-infrared light having a wavelength of 1200 nm to 1700 nm generated from the silicon layer after being spectrally separated by a spectroscope.

  In the method for manufacturing a semiconductor device of the present invention, damage to the silicon layer is predicted to be large before or after the semiconductor element forming process is performed on the silicon layer in the substrate having the silicon layer on the surface side. And a step of performing pass / fail judgment by inspecting the silicon layer of the substrate using the semiconductor crystal defect inspection apparatus after processing steps such as element isolation formation and active element formation in the initial stage. The semiconductor element formation process of the next process is sequentially performed on the substrate that has been determined to be non-defective based on the non-defective / non-defective determination result.

  In the semiconductor device manufacturing method of the present invention, the coordinate position of the secondary electron image is before and after each step of performing a plurality of semiconductor element formation processing steps on the silicon layer in the substrate having the silicon layer on the surface side. And the intensity of the near infrared light, and the recorded intensity is normalized to compare the intensity of the near infrared light before and after the semiconductor element formation processing step, It has a step of obtaining the occurrence and distribution of crystal defects unique to the element formation processing step.

(Semiconductor crystal defect inspection system)
FIG. 1 is a schematic configuration diagram of a semiconductor crystal defect inspection apparatus showing Embodiment 1 of the present invention.
This semiconductor crystal defect inspection apparatus has a chamber 1 that creates a vacuum state by reducing the pressure with a vacuum pump or the like. Inside the chamber 1 is a support base (for example, two-dimensionally movable) for supporting a substrate (for example, a silicon wafer when measurement is performed in the manufacturing process of a silicon LSI) 2 as a sample to be inspected. The stage 3 is provided, and the cooling means 4 is attached to the stage 3. The cooling means 4 cools the silicon wafer 2 and is constituted by a cooling method using a refrigerant such as liquid helium or liquid nitrogen, a closed-type circulation cryostat using helium gas, or the like. . The cooling temperature is required to cool the silicon wafer 2 to 100K to 4K. It is preferable that the temperature of the silicon wafer 2 is lower because the intensity of light emission derived from crystal defects and dislocations from the silicon wafer 2 increases. However, at a temperature lower than 4K, cooling is not easy and the temperature is kept constant. It is difficult to maintain, and there arises a problem that the silicon wafer 2 is likely to drift during inspection. Above 100 K, the probability of non-radiative transition increases, and the intensity of light emission resulting from crystal defects and dislocations from the silicon wafer 2 decreases.

  The stage 3 has a structure that can be moved in the X-axis direction and the Y-axis direction by a driving unit 5. The drive unit 5 is configured by a control motor or the like, and is a device that can accurately control the position of the stage 3 on which the silicon wafer 2 is placed. An electron beam generator (for example, an electron gun) 6 for generating an electron beam for irradiating the silicon wafer 2 placed thereon is provided on the stage 3. The electron gun 6 is provided in an SEM or TEM that can observe one or more of a secondary electron image, a reflected electron image, and a transmission electron image. It is preferable to use an electron gun provided in the SEM. The method of the electron gun 6 is not particularly limited. For example, any electron gun such as a thermionic emission type, a field emission type, a Schottky emission type, or a thermal field emission type can be used. From the viewpoint of high current density, a Schottky emission type or thermal field emission type electron gun is preferably used. The beam diameter of the electron beam is not particularly limited, but it is preferable that the beam diameter can be several tens of nm or less because the spatial resolution improves as the beam diameter decreases.

  In the first embodiment, the electron beam generated from the electron gun 6 is fixed, and the stage 3 supporting the silicon wafer 2 irradiated with the electron beam moves to scan the silicon wafer 2 two-dimensionally. It has become. Although there is no particular limitation on this scanning method, it is preferable that the widest possible range can be searched because a wider range of crystal defects of the silicon wafer 2 can be inspected at a time. For example, in SEM, an electron beam generated from an electron gun is scanned by a scanning coil provided between a fixed stage and an electron gun. good.

  Above the stage 3, in order to detect near-infrared light having a wavelength of 1200 nm to 1700 nm among CL light generated from the silicon wafer 2 by electron beam irradiation, a condenser mirror 7, an optical fiber 8, and a spectrometer. First detection means (for example, CL detector) 10 is provided through 9. In silicon, when dislocations are present, light emitted from defects or dislocations in the crystal is observed near CL light at D1 (1535 nm), D2 (1419 nm), D3 (1321 nm), and D4 (1244 nm). If near infrared light of 1200 nm to 1700 nm can be detected, inspection of crystal defects, dislocations, and the like can be performed. The condensing mirror 7 is provided to increase the condensing efficiency of CL light emitted from the surface of the silicon wafer 2 in all directions. The condensing mirror 7 has, for example, a concave mirror structure in which a through hole 7a of about 1 mmφ for passing an electron beam is formed in the vertical direction, and is composed of an elliptical mirror, a parabolic mirror, or the like. The structure of the CL detector 10 is not particularly limited, but is preferably cooled by a cooling means 11 such as liquid nitrogen. A photodiode, a photomultiplier tube, an InGaAs multichannel detector, an InGaAs, which are sensitive in the near infrared region. A camera etc. are mentioned and used preferably. Among them, the InGaAs multichannel detector is more preferable because it can detect the light split by the spectroscope 9 at a time, and can shorten the inspection time. At this time, CL light may be guided directly from the condenser mirror 7 to the CL detector 10, but CL light may be introduced into the CL detector 10 through the optical fiber 8. In this case, it is preferable to use the near-infrared optical fiber 8 having no absorption in the near-infrared region.

  Crystal defect inspection is possible without spectrally separating CL light, but it is more preferable to perform spectral analysis with the spectroscope 9 because the type and amount of defects can be examined. The method of the spectroscope 9 is not particularly limited, but at least one spectroscope selected from the group consisting of a diffraction grating type spectroscope, a prism type spectroscope, an optical filter type spectroscope, and a dichroic mirror type spectroscope is preferable. By providing the spectroscope 9, it becomes possible to measure the spectroscopic spectrum and to obtain more detailed information on crystal defects and dislocations in the silicon wafer 2. A CL signal amplifier 12 that amplifies the CL signal is connected to the output side of the CL detector 10.

  Above the stage 3, a second detection means (for example, a secondary electron detector) 13 and an SEM signal amplifier 14 constituting an SEM system for observing a wafer pattern and acquiring positional information are provided. Is provided. The secondary electron detector 13 detects secondary electrons generated from the silicon wafer 2 by irradiation with an electron beam, and the SEM signal of this output is amplified by the SEM signal amplifier 14.

  A controller 15 for controlling the entire apparatus is connected to the electron gun 6, the CL signal amplifier 12, and the SEM signal amplifier 14. The controller 15 receives a CL signal S12 output from the CL signal amplifier 12, a position signal S14 output from the SEM signal amplifier 14, device information (element information) to be formed on the silicon wafer 2, and the like. The whole apparatus including 5 etc. is controlled. A data storage unit 18 is connected to the controller 15 via a data processing unit 17, and a display 19 such as a CRT is connected. The controller 15, the data processing unit 17, the data storage unit 18, and the display device 19 can be configured by a computer system or the like.

  In the first embodiment, a display 19 for displaying secondary electrons from the silicon wafer 2 as an image is provided to confirm the position. Generally, in SEM or TEM, it is possible to display one or more of reflected electrons, secondary electrons, and transmitted electrons as an image. Although the position of the silicon wafer 2 can be confirmed by any of these, in the CL apparatus, the condensing mirror 7 is disposed on the upper part of the silicon wafer 2 in order to condense light from the silicon wafer 2. Since confirmation of the position using the secondary electron image is the simplest and the position accuracy is high, in the first embodiment, the secondary electron image is used for position confirmation.

(Semiconductor crystal defect inspection method)
A semiconductor crystal defect inspection method using the apparatus of FIG. 1 will be described.
In the first step, a substrate (for example, silicon wafer) 2 to be inspected is placed on the stage 3 in the chamber 1. The air in the chamber 1 is sucked with a vacuum pump or the like, and the inside of the chamber 1 is brought into a reduced pressure environment in which CL measurement can be performed.

  In the second step, the stage 3 is cooled by the cooling means 4, and the silicon wafer 2 on the stage 3 is cooled to a temperature of 100K to 4k.

  In the third step, the driving unit 5 is operated under the control of the controller 15 to align the electron beam irradiation position for detecting CL with the coordinates on the silicon wafer 2. An electron beam is radiated from the electron gun 6 to pass through the through-hole 7a of the condensing mirror 7, and the silicon wafer 2 on the stage 3 is moved in the X-axis direction and Y-axis direction of the plane by the drive unit 5, A predetermined area of the silicon wafer 2 is scanned. The stage 3 may be fixed and the electron beam may be moved. When the silicon wafer 2 is irradiated with an electron beam, CL light, secondary electrons, and the like are generated from the silicon wafer 2.

  In the third step, CL light generated from each coordinate on the silicon wafer 2 is collected by the condenser mirror 7, transmitted by the optical fiber 8, and dispersed by the spectroscope 9. The split CL light is input to the CL detector 10 and near infrared light having a wavelength of 1200 nm to 1700 nm is detected. The detected near-infrared light having a wavelength of 1200 nm to 1700 nm is amplified by the CL signal amplifier 12, and this amplified CL signal S 12 is sent to the controller 15. The secondary electrons generated from the coordinates of the silicon wafer 2 are detected by the secondary electron detector 13 and amplified by the SEM signal amplifier 14 to generate a position signal S14 as coordinate information and sent to the controller 15. .

  In the fourth step, when the CL signal S12, the position signal S14, the device information 16 and the like are input to the controller 15, the data processing unit 17 generates a secondary electron image that is a surface image of the silicon wafer 2 and Corresponding near-infrared light intensity of wavelengths 1200 nm to 1700 nm is calculated, and a portion of the surface of the silicon wafer 2 where the near-infrared light intensity of wavelengths 1200 nm to 1700 nm is high is specified and recorded in the data storage unit 18. . Further, the display device 19 controlled by the controller 15 displays the calculated secondary electron image and the intensity of near infrared light having a wavelength of 1200 nm to 1700 nm corresponding thereto, so that the near red light having a wavelength of 1200 nm to 1700 nm is displayed. A site where the intensity of external light is high can be visually observed.

  FIG. 2 is a diagram showing the spectrum of the measured CL signal S12. In FIG. 2, for example, in the step of forming an element isolation region in the silicon wafer 2, a nitride film having a film thickness of 230 nm is formed on the silicon wafer 2, and this film is referred to as chemical mechanical polishing (hereinafter referred to as “CMP”). ), The wavelength (Wavelength) nm is plotted on the horizontal axis, and the light intensity (Intensity) cps is plotted on the vertical axis.

  In the CL method, for example, when the electron acceleration voltage is set to 15 KeV, the penetration depth of the electron beam from the Si surface is about 3 μm. On the other hand, in the case of a semiconductor element using Si, the formation region is at most. Since the thickness is about 2 μm, defects that are problematic in the semiconductor manufacturing process can be almost detected. The range of the acceleration voltage of electrons is preferably about 10 KeV to 30 KeV.

  Si is an indirect transition semiconductor, and light emission accompanied by phonon emission is observed relatively strongly in the low-temperature PL spectrum and CL spectrum. These emission lines are attributed as follows.

Non-phonon (NP) bound excitons not involving phonons 1130 nm; bound excitons involving TO phonons 1200 nm; phonon replicas of bound excitons

  These emission lines are not due to defects or impurities, but are the original emission lines of the crystal. In contrast to the D-line described below, the intensity is increased when the crystal is good. In a sample in which dislocations exist in the crystal, several relatively sharp luminescence called D-line is observed around 1220 nm to 1600 nm. Among these, D3 and D4 are related to 60 ° dislocation, and D3 is a phonon replica of D4. D1 and D2 are due to dislocations and stacking faults starting from impurities, point defects trapped in the strain field around the dislocations, impurities, precipitated oxygen, and the like. In addition, an emission line called a Gcenter non-phonon (NP) line is observed in the vicinity of 1279 nm. This emission line is observed by irradiation with a high-energy particle beam, and the attribution is a composite center of interstitial Si and substitution position C ( C-Si-C). Therefore, by looking at the intensity of D1-D4-line detected in the observed area, it is possible to detect whether there is a defect in the area.

  Since this measurement is recorded in the data storage unit 18 together with the position information of the sample, the distribution and intensity of crystal defects can be output as a map and displayed on the display 19 after the measurement is completed. Also, the coordinate information can be used as input information of another inspection apparatus (for example, an optical inspection apparatus, an electron beam inspection apparatus, etc.) to observe a pattern of a location where an actual defect has occurred. In the apparatus of FIG. 1, since an SEM observation unit such as a display 19 is also mounted, it is possible to simultaneously detect and observe defects.

  As described above, in the semiconductor crystal defect inspection method according to the first embodiment, the silicon wafer 2 as a sample is inspected before or during the manufacturing process of the LSI using the silicon wafer 2 or after the manufacturing process. The silicon wafer 2 is inspected to determine which part of the silicon wafer 2 has a high intensity of near infrared light having a wavelength of 1200 nm to 1700 nm. If near infrared light with a wavelength of 1200 nm to 1700 nm is not detected, it is determined that there is no crystal defect in the silicon wafer 2 and there is no particular problem, but if near infrared light with a wavelength of 1200 nm to 1700 nm is detected, the silicon wafer 2 Since 2 has crystal defects, it is likely to be a defective product.

  The element process (process) that can be inspected by this semiconductor crystal defect inspection method is not particularly limited, but can be preferably applied to inspection of crystal defects generated in each process such as dry etching, ion implantation, CMP, epitaxial growth, and substrate.

(Effect of Example 1)
According to the first embodiment, a crystal defect such as an LSI manufactured on the silicon wafer 2 can be inspected in a short time with high sensitivity. The effects of the first embodiment will be further described below with specific implementation device examples (1) to (3).

(1) Example of Apparatus The condenser mirror 7 and the optical fiber 8 were attached to an S-4300SE Schottky emission type SEM manufactured by Hitachi, Ltd. The optical fiber 8 was guided to a single spectrometer HR-320 (9) manufactured by Joban Yvon, and near-infrared light having a wavelength of 1200 to 1700 nm was detected by a liquid nitrogen cooled InGaAs multichannel detector 10 manufactured by Joban Yvon. As the sample, a sample which has been subjected to an LSI element isolation process was used. The sample was cooled to 30K using a closed type low temperature cryostat (4) manufactured by Iwatani Gas. As a result, light emission from dislocations called D1, D2, D3, and D4 was observed at 1200 to 1700 nm in the specific circuit portion. From this, it was identified that dislocations were present in this sample. Note that at the measurement temperature of 120K, the signal intensity of the D1, D2, D3, and D4 lines was weak and took more than five times as long as the measurement at 30K, so it was not possible to examine all the positions of the sample.

(2) Comparative Example 1
A part of the sample used in the above (1) was sliced with a FIB apparatus and observed with a TEM (H-9000UHR) manufactured by Hitachi. However, crystal defects could not be detected.

(3) Comparative Example 2
The final product of the sample used in the above (1) was evaluated using an emission microscope PHEMOS-200 manufactured by Hamamatsu Photonics. An abnormality was shown in the specific circuit part, but the cause could not be specified.

(Method for manufacturing semiconductor device)
3A to 3F are manufacturing process diagrams showing a method for manufacturing a semiconductor device in Example 2 of the present invention using the semiconductor crystal defect inspection apparatus of FIG.

  When a semiconductor device such as an LSI is manufactured using the substrate (for example, silicon wafer) 2, for example, it is manufactured as described in the following (1) to (6).

(1) Step of FIG. 3A Before performing the semiconductor element formation processing on the silicon wafer 2, the silicon wafer 2 to be used is introduced into the semiconductor crystal defect inspection apparatus of FIG. Defects are inspected to determine whether the presence or absence and degree of crystal defects is below an allowable value. Except for defective products, only good products are introduced into the manufacturing process, and the subsequent semiconductor element formation processing is performed.

  After cleaning the good silicon wafer 2, it is thermally oxidized to form a thermal oxide film 21 having a thickness of about 5 to 30 nm on the surface of the silicon wafer 2. A nitride film having a thickness of about 120 nm to 250 nm is coated on the entire surface by CVD. The nitride film 22 and the thermal oxide film 21 are selectively etched by a photolithography technique, and silicon is etched using the nitride film as a mask to form an element isolation trench 23 having a depth of about 100 to 500 nm. Thereafter, an oxide film 24 is formed on the exposed silicon surface by a method such as thermal oxidation. Since a large stress is applied to the silicon layer around the groove 23, a large number of large and small crystal defects may occur. Many of the fine crystal defects on the exposed silicon surface disappear by a subsequent heat treatment or the like, but the crystal defects formed inside the crystal may remain as they are or may grow greatly by a subsequent manufacturing process or the like. .

(2) Step of FIG. 3B An oxide film 25 is deposited on the entire surface by CVD, and the groove 23 is filled with the oxide film 25 and the entire surface is covered.

(3) Step of FIG. 3C By CMP, the entire surface is polished to remove the oxide film 25 on the surface, and the nitride film 22 is exposed. The oxide film 25 filled in the trench 23 becomes a field oxide film 25a which is an element isolation region. After that, it is introduced into the semiconductor crystal defect inspection apparatus of FIG. 1 to inspect the crystal defects and determine whether or not the presence or degree of crystal defects is below an allowable value. In particular, since a large stress is applied to the silicon portion in contact with the field oxide film 25a, there is a possibility that a large crystal defect exists. Except for defective products whose crystal defects exceed the allowable value, only good products are returned to the manufacturing process.

(4) Step of FIG. 3D The nitride film 22 and the thermal oxide film 21 are removed by etching to expose silicon in a region where an element is to be formed. After that, it is introduced into the semiconductor crystal defect inspection apparatus of FIG. 1 to inspect the crystal defects and determine whether or not the presence or degree of crystal defects is below an allowable value. Except for defective products, only good products are returned to the manufacturing process.

(5) Step of FIG. 3E After forming an oxide film (not shown) in the element formation region by a method such as thermal oxidation, impurity ions are implanted as necessary, and reverse conductivity with respect to the silicon substrate. A well 26 which is an element forming region of the mold is formed. Once the oxide film formed on the surface is removed, a gate oxide film 27 is formed on the entire surface. After that, it is introduced into the semiconductor crystal defect inspection apparatus of FIG. 1 to inspect the crystal defects and determine whether or not the presence or degree of crystal defects is below an allowable value. Except for defective products, only good products are returned to the manufacturing process. Polysilicon to be the gate electrode 28 is deposited by the CVD method. The polysilicon is selectively etched by a photolithography technique to form the gate electrode 28. After that, it is introduced into the semiconductor crystal defect inspection apparatus of FIG. 1 to inspect the crystal defects and determine whether or not the presence or degree of crystal defects is below an allowable value. Except for defective products, only good products are returned to the manufacturing process.

(6) Step of FIG. 3F Impurity ions are implanted and ions are activated to form the diffusion layer 29. Next, if necessary, it is introduced into the semiconductor crystal defect inspection apparatus shown in FIG. 1 to inspect the crystal defects, excluding defective products, and returning only good products to the manufacturing process. A large number of semiconductor devices such as LSIs (chips) are formed by covering the entire surface with an insulating film 30 which is an insulating film and forming a wiring layer thereon.

  After completion of such a manufacturing process, a wafer prober which is an electrical characteristic inspection apparatus selects good / bad of each chip on the silicon wafer 2, and then a wafer dividing and assembling process is performed.

(Effect of Example 2)
(1) By using the CL method of FIG. 1 as a semiconductor crystal defect inspection apparatus used in the manufacturing process of a semiconductor device, the intensity data of the CL signal S12 is recorded in the data storage unit 18 together with the data of the position signal S14. In addition, since it is possible to perform non-destructive inspection within a process for what kind of crystal defects exist in a silicon layer, a process design that can prevent or suppress crystal defects, or a pan design Can be easily performed. Furthermore, as an index for inspecting the product quality, the crystal defect measurement can be used as an in-process inspection as in the case of the conventional dimension measurement and film thickness measurement, so that a high-quality product can be provided.

(2) An initial process step (for example, a step of forming an element isolation region, which is predicted to cause a large damage to the silicon layer by the semiconductor element formation process before the semiconductor element formation process is performed on the silicon wafer 2. After the subsequent active element formation step, etc., the crystal defect inspection is performed using the semiconductor crystal defect inspection apparatus shown in FIG. I have to. As a result, defective products having crystal defects can be selected in the initial stage, so that useless manufacturing processes can be reduced and manufacturing costs can be reduced.

(3) Instead of the silicon wafer 2, a substrate having another structure such as an SOS substrate may be used as long as the substrate has a silicon layer on the surface side.

  Example 3 is a method of manufacturing a semiconductor device using the semiconductor crystal defect inspection apparatus of FIG. 1 as in Example 2. However, the method of Example 2 was recorded for each of the manufacturing steps of FIG. The data of the position signal S14 and the intensity data of the CL signal S12 are compared between the manufacturing steps. In Example 3, near infrared rays having a wavelength of 1000 nm to 1700 nm generated from the silicon layer are detected.

The CL signal S12 obtained in each manufacturing process of FIG. 3 can be used as follows.
First, if the manufacturing process is different, the state of the surface of the silicon wafer 2 changes, and the occurrence and increase / decrease of defects cannot be compared as they are. Thus, comparison is possible by using a signal that is independent of crystal defects and that is stable regardless of the manufacturing process. For example, by converting the CL signal S12 obtained in each manufacturing process into an intensity ratio with respect to the original light emission line of the crystal, it becomes possible to compare the signal intensity between the manufacturing processes. Therefore, by comparing the CL signals S12 before and after the manufacturing process, it is possible to know the generation and distribution of crystal defects unique to the manufacturing process.

(Effect of Example 3)
(1) According to the third embodiment, a crystal defect generation process can be specified by measuring the same silicon wafer 2 a plurality of times in the manufacturing process.

(2) By normalizing the CL signal S12 using a signal that is not related to crystal defects, such as the crystal's original light-emitting line, it is possible to compare even a small number of defects. By linking with process control values, it becomes an effective in-process management method.

(3) Instead of the silicon wafer 2, a substrate having another structure such as an SOS substrate may be used as long as the substrate has a silicon layer on the surface side.

    In the present invention, an example of application to a semiconductor using silicon has been described, but application to other semiconductor materials having a crystal structure such as a compound semiconductor such as GaAs is also possible.

It is a schematic block diagram of the semiconductor crystal defect inspection apparatus which shows Example 1 of this invention. It is a figure which shows the spectrum of CL signal S12 measured using the apparatus of FIG. It is a manufacturing process figure which shows the manufacturing method of the semiconductor device in Example 2 of this invention using the apparatus of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Chamber 2 Silicon wafer 3 Stages 4, 11 Cooling means 5 Drive part 6 Electron gun 7 Focusing mirror 9 Spectroscope 10 CL detector 13 Secondary electron detector 15 Controller 18 Data storage part 19 Display

Claims (7)

Placing a substrate having a silicon layer on the surface side on which a semiconductor element formation process is performed, on a support base;
Cooling the silicon layer of the substrate to a temperature between 100K and 4K;
Two-dimensionally scanning either one of the support base and the electron beam for irradiating the surface of the silicon layer, and sequentially irradiating a predetermined region of the surface of the silicon layer with the electron beam;
Detecting near infrared light having a wavelength of 1200 nm to 1700 nm generated from the silicon layer, and detecting secondary electrons generated from the silicon layer;
A secondary electron image, which is a surface image of the silicon layer, is displayed by the detected secondary electrons, and the intensity of near-infrared light having a wavelength of 1200 nm to 1700 nm detected corresponding to the secondary electron image. Displaying a region where the intensity of near-infrared light having a wavelength of 1200 nm to 1700 nm is large on the surface of the silicon layer;
A method for inspecting a semiconductor crystal defect, comprising: The semiconductor crystal defect inspection method according to claim 1,
A method for inspecting a semiconductor crystal defect, comprising: detecting near infrared light having a wavelength of 1200 nm to 1700 nm generated from the silicon layer after performing spectroscopy. A support base for supporting a substrate having a silicon layer on the surface side on which a semiconductor element formation process is performed;
Cooling means for cooling the silicon layer of the substrate supported by the support to a temperature of 100K to 4K;
Under reduced pressure, an electron beam for irradiating the surface of the silicon layer of the substrate supported by the support table is generated, the electron beam is moved relative to the support table, and the silicon layer An electron beam generator for sequentially irradiating a predetermined area of the surface;
First detection means for detecting near-infrared light having a wavelength of 1200 nm to 1700 nm generated from the silicon layer by irradiation of the electron beam;
Second detection means for detecting secondary electrons generated from the silicon layer by irradiation of the electron beam;
A secondary electron image that is a surface image of the silicon layer is displayed by the secondary electrons detected by the second detection means, and detected by the first detection means in correspondence with the secondary electron image. Display means for displaying the intensity of near infrared light having a wavelength of 1200 nm to 1700 nm,
A semiconductor crystal defect inspection apparatus comprising: In the semiconductor crystal defect inspection apparatus according to claim 3,
The semiconductor crystal defect inspection apparatus, wherein the first detection means detects the near infrared light having a wavelength of 1200 nm to 1700 nm generated from the silicon layer after being dispersed. A semiconductor device manufacturing method using the semiconductor crystal defect inspection apparatus according to claim 3 or 4,
Before performing a semiconductor element forming process on the silicon layer in the substrate having a silicon layer on the surface side, or after an initial stage processing step that is expected to cause a large damage to the silicon layer by the semiconductor element forming process, A step of performing a crystal defect inspection on the silicon layer of the substrate using the semiconductor crystal defect inspection apparatus to determine pass / fail;
A step of performing a semiconductor element formation process of a next step on the substrate determined to be a non-defective product based on the non-defective / non-defective determination result;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 5,
The initial processing step is a step of forming an element isolation region in the silicon layer, or a step of forming an active element in the silicon layer isolated by the element isolation region. Production method. A semiconductor device manufacturing method using the semiconductor crystal defect inspection apparatus according to claim 3 or 4,
Before and after each step of performing a plurality of semiconductor element formation processing steps on the silicon layer on the substrate having the silicon layer on the surface side, the coordinate position of the secondary electron image and the intensity of the near infrared light are recorded. By normalizing the recorded intensity, the intensity of the near-infrared light before and after each semiconductor element forming process is compared, and the occurrence and distribution of crystal defects unique to each semiconductor element forming process A method for manufacturing a semiconductor device, comprising the step of:

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