JP2010197051A - Failure analyzer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To three-dimensionally locate failure places of a device to be tested. <P>SOLUTION: A failure analyzer 70 includes: a laser irradiation means for irradiating a semiconductor device (DUT) 21 which is a device to be tested with laser beams and heating a specific place of the device to be tested irradiated with laser beams to generate a thermoelectromotive current; a photographing means for photographing an optical heating resistance change image of the device to be tested by scanning the device horizontally and vertically by the laser beams; a first position coordinates setting means for overlapping the horizontal optical heating resistance change image to a planar layout image of the device to be tested so that horizontal position coordinates become identical; and a second position coordinates setting means for overlapping vertical optical stage position information with section information of the device to be tested so that vertical position coordinates become identical. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a failure analysis apparatus.

  In recent years, with the progress of miniaturization and low power consumption of semiconductor elements, semiconductor integrated circuits (LSIs) have been highly integrated. In a system LSI or SoC (System on a chip) including a highly integrated logic circuit or sequential circuit, it is very important to identify a failure mode and a failure location. EMS (Emission Micro Scope), OBIRCH (Optical Beam Induced Resistance Change), EBAC (Electron Beam Absorbed Current), SDL (Soft Defect Localization), EB tester, etc. are frequently used for failure analysis of system LSI and SoC. OBIRCH and EBAC are mainly applied to failure analysis of a wiring system by observing and imaging a current generated in a device under test. The SDL is mainly applied to the analysis of the FNC (Function) margin of the device under test by irradiating the device under test with a laser beam to monitor the change in the PASS / FAIL map of the device under test (for example, Patent Documents). 1 and 2).

  The analysis methods such as OBIRCH, EBAC, and SDL described in Patent Documents 1 and 2 can identify a defective portion in the horizontal direction with respect to the device under test, but the three-dimensional device under test including the vertical direction. There is a problem that it is impossible to identify the defective part.

JP 2006-64586 A JP 2008-300486 A

  An object of the present invention is to provide a failure analysis apparatus that can three-dimensionally specify the position of a defective portion of a device under test.

  A failure analysis apparatus according to an aspect of the present invention includes a laser irradiation unit that irradiates a device under test with laser light, heats a specific portion of the irradiated device under test to generate a thermoelectromotive current, and the laser light. An imaging unit that scans in a horizontal direction and a vertical direction to capture a light heating resistance change image of the device under test, a horizontal position coordinate of the light heating resistance change image in the horizontal direction and a planar layout image of the device under test First position coordinate setting means for superimposing the same so as to be the same, and a second position for superimposing the vertical optical stage position information and the cross-sectional information of the device under test so that the vertical position coordinates are the same. And a coordinate setting means for specifying a defective portion of the device under test three-dimensionally.

  Furthermore, a failure analysis apparatus according to another aspect of the present invention includes an irradiation unit that irradiates a device under test with laser light in a horizontal direction and a vertical direction, and supplies power and a signal to the device under test. An LSI tester for determining PASS or FAIL with respect to an FNC margin, creation means for creating a PASS / FAIL map of the device under test, scanning the laser light in the horizontal direction of the device under test, and the laser light irradiation state Counting the number of PASS / FAIL changes on the PASS / FAIL map of the device under test, and setting the number of PASS / FAIL changes as a first PASS / FAIL image; and The horizontal position coordinates of the PASS / FAIL image and the planar layout image of the device under test are the same. A first position coordinate setting unit that superimposes the laser light so that the laser beam is scanned in the vertical direction of the device under test, and the PASS on the PASS / FAIL map of the device under test in the laser light irradiation state A second image creating means that counts the number of changes in / FAIL and sets the number of changes in PASS / FAIL as a second PASS / FAIL image, and a cross-sectional image of the second PASS / FAIL image and the device under test. Second position coordinate setting means for superimposing the position coordinates in the vertical direction to be the same, superimposing the first PASS / FAIL image and the planar layout image of the device under test, By superimposing a PASS / FAIL image and a cross-sectional image of the device under test, the defective portion of the device under test is three-dimensionally displayed. And identifies the.

  ADVANTAGE OF THE INVENTION According to this invention, the failure analysis apparatus which can specify the position of the defect location of a to-be-tested device three-dimensionally can be provided.

1 is a schematic configuration diagram showing a failure analysis apparatus according to Embodiment 1 of the present invention. The schematic block diagram which shows the defect investigation part which concerns on Example 1 of this invention. 5 is a flowchart showing the relationship between analysis information and design information according to Embodiment 1 of the present invention. The flowchart which shows the wiring system defect analysis of SoC which concerns on Example 1 of this invention. 1 is a schematic diagram showing laser irradiation on a device under test according to Example 1 of the present invention. FIG. The figure which shows the electric current change with respect to laser irradiation in the X direction or Y direction which concerns on Example 1 of this invention. The figure which shows the superimposition with the electric current change image and planar layout figure in the XY direction which concern on Example 1 of this invention. The figure which shows the electric current change with respect to laser irradiation in the Z direction which concerns on Example 1 of this invention. The figure which shows the superimposition with the electric current change synthetic | combination image and sectional drawing in the Z direction which concern on Example 1 of this invention. The schematic block diagram which shows the failure analysis apparatus which concerns on Example 2 of this invention. The schematic block diagram which shows the defect investigation part which concerns on Example 2 of this invention. The flowchart which shows the FNC margin analysis of SoC which concerns on Example 2 of this invention. The figure which shows PASS / FAIL with respect to the power supply voltage and clock signal of SoC which concerns on Example 2 of this invention. The figure which shows PASS / FAIL with respect to the power supply voltage and clock signal of SoC in the laser irradiation state which concerns on Example 2 of this invention. The figure which shows the change of the PASS / FAIL change number with respect to laser irradiation in the X direction or the Y direction which concerns on Example 2 of this invention. The figure which shows the change of the PASS / FAIL change number with respect to laser irradiation in the Z direction which concerns on Example 2 of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a failure analysis apparatus according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a schematic configuration diagram showing a failure analysis apparatus, and FIG. 2 is a schematic configuration diagram showing a defect investigation unit. In this embodiment, the position of the defective part of the device under test is specified three-dimensionally using OBIRCH.

  As shown in FIG. 1, the failure analysis unit 70 is provided with a failure analysis unit 1 and an EWS 2. The failure analysis apparatus 70 mainly includes a failure of a device under test (DUT Device under Test) which is a system LSI or SoC (System on a chip) including highly integrated logic circuits or sequential circuits. It can be applied to the analysis and identification of the failure mode and failure location of the wiring system. The defect analysis unit 1 and the EWS 2 are connected to a LAN (Local Area Network).

  The defect analysis unit 1 is provided with a defect investigation unit 11 and a control / analysis unit 12. The defect investigation unit 11 performs a defect analysis of a device under test (DUT) such as a system LSI or SoC. The defect investigation unit 11 performs EMS (Emission Micro Scope) analysis and OBIRCH (Optical Beam Induced Resistance Change) analysis. The control / analysis unit 12 controls the defect investigation unit 11 and analyzes the information investigated by the defect investigation unit 11. The control / analysis unit 12 is provided with a display unit 13. The display unit 13 displays, for example, information processed by the control / analysis unit 12 or information transmitted via the LAN.

  An EWS (engineering workstation) 2 is provided with an information storage unit 14 and a display unit 15. The information storage unit 14 stores design layout information, process information, support software information, and the like. The display unit 15 displays, for example, information processed by the EWS 2 or information transmitted via the LAN.

  Here, the design layout information refers to planar layout information of a device under test (DUT), horizontal information such as element formation region, source / drain region, gate electrode and gate electrode wiring, contact, metal wiring, and via. Say. Among design layout information, metal wiring, a gate electrode and a gate electrode wiring, a metal via, and the like that are clearly displayed in an optical image created by a microscope are particularly important information.

  Process information includes the depth of the element formation region, the depth of the source / drain region, the thickness of the insulating film, the thickness of the gate electrode, the height of the contact, the thickness of the wiring, the height of the via, etc. This is information in the vertical direction of a device under test (DUT) that is a system LSI or SoC.

  Support software information includes analysis and identification of failure mode and failure location of the device under test (DUT), video correction of the video information acquired by the failure investigation unit 11, plane layout display and cross section of the device under test (DUT) Support software used for 3D display, overlay and display of analysis information and design information.

  As shown in FIG. 2, the defect investigation unit 11 includes a semiconductor device (DUT) 21, a DUT stage 22, a prober 23, an amplifier 24, a microscope unit 26, an optical stage 27, and a laser generation / light detection unit 28. .

  The semiconductor device (DUT) 21 is placed on the DUT stage 22. A semiconductor device (DUT) 21 which is a device under test is a highly integrated and multi-layered silicon device such as a system LSI, SoC (System on a Chip), memory LSI, etc., and a silicon semiconductor device And compound devices.

  The semiconductor device (DUT) 21 is irradiated with laser light scanned in the X direction, the Y direction, and the Z direction on the front surface or the back surface. The X direction and the Y direction are horizontal directions, and the Z direction is a vertical direction. Here, the surface of the semiconductor device (DUT) 21 is irradiated with laser light, but the front surface or the back surface is appropriately selected according to the assumed failure mode or failure location of the semiconductor device (DUT) 21. When the semiconductor device (DUT) 21 is, for example, a system LSI or SoC (System on a Chip) having six or more layers of metal wiring, a metal wiring with a thick laser beam or a stacked metal wiring used for OBIRCH analysis is used. Since it is difficult to transmit, it is preferable to irradiate the laser beam from the back surface of the semiconductor device (DUT) 21. In addition, when irradiating a laser beam from a back surface, it is better to make the thickness of the silicon substrate of the semiconductor device (DUT) 21 thin so that the laser beam is not attenuated.

  A terminal or evaluation metal pattern (not shown) provided on the surface of the semiconductor device (DUT) 21 and the prober 23 are electrically connected, and an amplifier 24 is provided on one probe 23 side, and on the other probe side. Is provided with a constant voltage source. The amplifier 24 detects a thermoelectromotive current generated by the semiconductor device (DUT) 21 at the time of laser light irradiation and monitored by the probe 23, and amplifies the detected signal. The thermoelectromotive current detected and amplified by the amplifier 24 is displayed in gradation on the display unit 13 as an OBIRCH image that is a light heating resistance change image by the control / analysis unit 12. An apparatus having a function for acquiring the light heating resistance change image by the control / analysis unit 12 is defined as an imaging unit.

  The microscope unit 26 is provided under the optical stage 27 and acquires an optical image of the semiconductor device (DUT) 21. Here, a laser beam having a wavelength of 1300 nm used for OBIRCH analysis is used for optical image acquisition (laser microscope). When the wavelength is 1300 nm, the resolution is about 0.42 μm.

  When displaying a miniaturized and highly integrated system LSI or SoC with higher resolution, laser light having a wavelength shorter than 1300 nm (for example, wavelength 405 nm (resolution 0.13 μm)) may be used ( High resolution laser microscope). It should be noted that short-wavelength laser light has high energy and may destroy the device under test, so it is preferably not used for OBIRCH analysis or SDL analysis of the device under test but only for image display.

  The microscope unit 26 sends heat generation information (such as infrared rays) generated from the heat generation point of the semiconductor device (DUT) 21 to the laser generation / light detection unit 28 via the optical stage 27.

  The optical stage 27 is provided between the microscope unit 26 and the laser generation / light detection unit 28 and accurately controls and sets the coordinates of the optical system and the coordinates of the laser system based on instructions from the control / analysis unit 12. The optical stage 27 sets the irradiation position of the laser beam scanned in the X direction, the Y direction, and the Z direction (position where the laser beam is condensed) with high accuracy based on an instruction from the control / analysis unit 12. .

  The laser generation / light detection unit 28 is provided on the optical stage 27. The laser generation / light detection unit 28 includes a laser generation unit that generates laser light, a photodiode (for example, an InSb photodiode) that detects heat generation information (such as infrared rays) of the semiconductor device (DUT) 21 with high sensitivity, and the like. A sensitivity CCD is installed. The heat generation information (infrared rays or the like) sent to the laser generation / light detection unit 28 is displayed as gradation on the display unit 13 as an EMS image by the control / analysis unit 12. A plurality of lasers that generate optimum wavelengths according to the semiconductor device (DUT) 21 are mounted on the laser generator. Here, a function for detecting heat generation information and light emission information is installed, but may be omitted. Note that at least a laser generator and an optical stage function are used as laser irradiation means.

  When the semiconductor device (DUT) 21 is, for example, a system LSI or SoC that is a silicon device, the laser wavelength is selected from a wavelength range of 1060 nm to 1400 nm. A wavelength range of 1060 nm to 1160 nm is selected for the failure analysis of the transistor system, and a wavelength range of 1300 nm to 1400 nm is selected for the failure analysis of the wiring system.

  When the semiconductor device (DUT) 21 is, for example, a GaAs-based device, the wavelength range of 900 nm to 1400 nm is selected as the laser wavelength. A wavelength range of 900 nm to 1000 nm is selected for failure analysis of the transistor system, and a wavelength range of 1300 nm to 1400 nm is selected for failure analysis of the wiring system.

  In the OBIRCH analysis, when the metal wiring or the gate electrode wiring is irradiated with laser light, a current decrease or an increase due to a thermal resistance change (OBIRCH effect) can be observed. When laser light is irradiated around the via, an increase in current or a decrease in current due to the Seebeck effect can be observed. When laser light is irradiated to the metal wiring or the gate electrode wiring, an increase in current or a decrease in current due to the Seebeck effect can be observed. At a place where the metal and the semiconductor substrate are in direct contact (Schottky diode), it is possible to observe the generation of current due to photoexcitation.

From these information, the failure analysis of the wiring system by OBIRCH is preferably in the range of short-circuit failure (resistance value is about zero) to resistance value of 10 ⁵ Ω.

  Next, the relationship and correspondence between analysis information and design information using OBIRCH will be described with reference to FIG. FIG. 3 is a flowchart showing the relationship between analysis information and design information.

  Regarding the comparison between the analysis information and the design information and the image display, as shown in FIG. 3, optical system information as an optical image of the surface of the semiconductor device (DUT) 21 is acquired by the defect investigation unit 11 (step S11).

  The acquired optical system information is sent to the EWS 2 via, for example, a LAN, and the image is corrected by the EWS 2. Specifically, shredding correction, distortion correction, magnification aberration correction, and the like are performed, and video correction is performed so that the horizontal position coordinates are the same as the planar layout image (pattern layout image) of the semiconductor device (DUT) 21. (Step S12).

The thermal electromotive current generated in the semiconductor device (DUT) 21 at the time of laser light irradiation is acquired as an OBIRCH image that is a light heating resistance change image by the control / analysis unit 12 (imaging means) (step S21).
The acquired OBIRCH image is sent to the EWS 2 via, for example, the LAN, and the optical system information and the horizontal position coordinates are the same as those of the planar layout image (pattern layout image) of the semiconductor device (DUT) 21 by the EWS 2. Similarly, the image is corrected (step S22).

  The planar layout information (design data) of the semiconductor device (DUT) 21 is sent to the EWS 2 via the LAN (step S31). The vertical direction information (process information) of the semiconductor device (DUT) 21 is sent to the EWS 2 via the LAN (step S32).

  The planar layout information (design data) of the semiconductor device (DUT) 21 and the vertical direction information (process information) of the semiconductor device (DUT) 21 are stored in the information storage unit 14 and irradiated with laser in parallel using support software. A plane layout diagram and a cross-sectional view of the region to be generated are appropriately created (step S33).

  In superimposing images, the following processing is performed. The optical system information subjected to the image correction and the OBIRCH image subjected to the image correction are subjected to an overlay process so that the position coordinates in the horizontal direction are the same. The image-corrected OBIRCH image and the planar layout image (pattern layout image) of the semiconductor device (DUT) 21 are overlaid so that the horizontal position coordinates are the same (first position coordinate setting means).

  The vertical optical stage position information and the cross-sectional information of the semiconductor device (DUT) 21 are overlaid so that the vertical position is the same (second position coordinate setting means). The plurality of OBIRCH images acquired by scanning the laser beam in the vertical direction are corrected and then created as OBIRCH images synthesized in the vertical direction. The OBIRCH image synthesized in the vertical direction and the cross-sectional view of the semiconductor device (DUT) 21 are overlaid so that the vertical position coordinates are the same (third position coordinate setting means) (step S41).

  Superimposed optical system information after video correction and OBIRCH image after video correction, OBIRCH image after video correction after superposition processing and planar layout image (pattern layout image) of semiconductor device (DUT) 21, superposition The processed longitudinally synthesized OBIRCH image and the cross-sectional view of the semiconductor device (DUT) 21 are appropriately displayed on the display unit 13 or the display unit 15 in the laser irradiation target region during or after the OBIRCH analysis.

  Next, the SoC wiring system failure analysis will be described with reference to FIGS. FIG. 4 is a flowchart showing the SoC wiring system failure analysis, FIG. 5 is a schematic diagram showing laser irradiation to the device under test, FIG. 6 is a diagram showing current changes with respect to laser irradiation in the X direction or Y direction, and FIG. FIG. 8 is a diagram showing a superposition of a current change image in the XY direction and a plane layout diagram, FIG. 8 is a diagram showing a current change with respect to laser irradiation in the Z direction, and FIG. 9 is a current change composite image and a sectional view in the Z direction. FIG.

  OBIRCH analysis can be directly executed for wiring system failure analysis of SoC (silicon device), which is the device under test, but in order to reliably identify the true failure location of the device under test, IDDQ test / software analysis / EMS analysis is used here. OBIRCH analysis is executed after narrowing down the defective position.

  As shown in FIG. 4, first, electrical evaluation of a semiconductor device (DUT) 21 that is a SoC is performed using an LSI tester (not shown). Specifically, an IDDQ test, a scan test, an FNC test, or the like (step S1).

  Next, failure diagnosis is performed from the test result of the semiconductor device (DUT) 21 which is SoC by the LSI tester. Specifically, the failure mode of the semiconductor device (DUT) 21 that is the SoC is classified into a current system failure and a timing system failure, and in parallel, in which circuit area of the semiconductor device (DUT) 21 that is the SoC is defective. It is estimated whether it has occurred (step S2).

  Subsequently, a voltage is applied to the semiconductor device (DUT) 21 that is a SoC in which a current system failure has occurred, and heat generation information (such as infrared rays) generated from the defective portion is sensed. The optical image and the EMS image are overlapped to roughly identify the defective position in the horizontal direction. In addition, when the defect position of the semiconductor device (DUT) 21 which is SoC can be roughly specified by the software analysis, the OBIRCH analysis is performed without performing the EMS analysis (step S3).

  Then, an OBIRCH analysis is performed by irradiating, for example, a laser beam having a wavelength of 1300 nm (scanning in the X direction, the Y direction, and the Z direction) to the region where the defect position is roughly specified by the EMS analysis shown in FIG.

  In the OBIRCH analysis, first, the laser beam is scanned in the X direction and the Y direction (that is, the horizontal direction), for example, with the focal position set on the surface of the silicon substrate. The change in the thermoelectromotive current generated in the irradiated area is monitored, and an OBIRCH image is created for each irradiated area. At this time, the current change in the maximum luminance portion is monitored in the OBIRCH image.

  Next, as shown in FIG. 6, the current change monitored with respect to the irradiation position of the laser beam is illustrated, and the maximum portion of the current change is specified. Here, the identified region is referred to as region A.

  Subsequently, as shown in FIG. 7, the OBIRCH image of the region A and the planar layout diagram of the semiconductor device (DUT) 21 that is the SoC of the region irradiated with the laser are superimposed. The horizontal position of the current change portion is specified from the superimposed image. That is, it specifies which part of the SoC chip the area A corresponds to.

  Then, in the region A, the laser beam is scanned in the vertical direction (the cross-sectional direction of the semiconductor device (DUT) 21 as SoC). Specifically, laser scanning is performed from the silicon substrate surface in the direction in which the wiring layer is formed (upward direction in FIG. 5). The change in the thermoelectromotive current generated in the irradiated area is monitored, and an OBIRCH image is created for each irradiated area. At this time, the current change in the maximum luminance portion is monitored in the OBIRCH image.

  Next, as shown in FIG. 8, the current change monitored with respect to the irradiation position of the laser beam is illustrated, and the maximum part of the current change is specified. Here, the identified region is referred to as region B. The obtained OBICH image in the vertical direction (the cross-sectional direction of the semiconductor device (DUT) 21 that is the SoC) is synthesized.

  Subsequently, as shown in FIG. 9, the image-combined OBIRCH image and the cross-sectional view of the semiconductor device (DUT) 21 that is the SoC in the region B are superimposed. The vertical position of the current change portion is specified from the superimposed image. It is specified to which part of the SoC chip the region B corresponds. That is, the defective part of the wiring system of the semiconductor device (DUT) 21 that is the SoC is specified three-dimensionally. Here, it is estimated that the wiring system is defective due to a via (2′nd via) between the second layer wiring and the third layer wiring (step S4).

  Next, the area where the defect position is identified three-dimensionally by OBIRCH analysis is examined by SEM or TEM in the vertical or horizontal direction (appearance check), and the abnormal part is analyzed (AES or EELS). Is called. As a result, it is possible to three-dimensionally identify a defective portion of the wiring system of the semiconductor device (DUT) 21 that is a SoC and estimate the cause of the defect.

  If the wiring layer is laminated and the laser light is absorbed by the wiring layer, and it is difficult to irradiate the laser light to the wiring layer behind the laser, the vicinity of the laminated wiring region is defective in the wiring system. If this is the case, the OBIRCH analysis in the horizontal direction is roughly specified, and the insulating layer, wiring layer, via, etc. in this region are appropriately removed by etching, a new wiring layer is formed, and a test terminal such as tungsten is provided on the wiring layer. It is preferable to perform a three-dimensional identification of a defective part of the wiring system by OBIRCH analysis in the vertical direction.

  As described above, in the failure analysis apparatus of this embodiment, the failure analysis unit 1 and the EWS 2 are provided. The defect analysis unit 1 is provided with a defect investigation unit 11 and a control / analysis unit 12. The defect investigation unit 11 includes a semiconductor device (DUT) 21, a DUT stage 22, a prober 23, an amplifier 24, a microscope unit 26, an optical stage 27, and a laser generation / light detection unit 28. The laser generation / light detection unit 28 irradiates a semiconductor device (DUT) 21 as a device under test with laser light via the optical stage 27 and the microscope unit 26, and heats a specific portion of the irradiated device under test. Thus, a thermoelectromotive current is generated. The control / analysis unit 12 scans the laser light in the horizontal direction and the vertical direction, and takes a photoheating resistance change image of the device under test. The EWS 2 superimposes the horizontal light heating resistance change image and the planar layout image of the device under test so that the horizontal position coordinates are the same, and the vertical optical stage position information and the cross-section information of the device under test are displayed. Overlapping so that the vertical position coordinates are the same, the vertical position coordinates of the composite image obtained by combining multiple horizontal photothermal resistance change images and the cross-sectional image of the device under test are the same. Overlapping so that.

  Therefore, by superimposing the horizontal light heating resistance change image and the planar layout image of the device under test, and superimposing the composite image and the cross-sectional image of the device under test, the semiconductor device (DUT) 21 that is the device under test is overlapped. The defective part can be specified three-dimensionally. Further, in the failure analysis of the semiconductor device (DUT) 21 using the failure analysis apparatus 70, the failure analysis of the semiconductor device (DUT) 21 can be performed only by irradiating the semiconductor device (DUT) 21 with laser light. Even when there are many locations or failure modes other than the assumptions are mixed, failure analysis of the semiconductor device (DUT) 21 in a non-destructive manner is possible, and combined use with other failure analysis devices is possible.

  In this embodiment, it is assumed that the wiring system of the silicon-based semiconductor device (DUT) is defective when it is related to the wiring layer or via. For this reason, laser light having a laser wavelength of 1300 nm is used. However, in the case of a defective wiring system of a silicon semiconductor device (DUT) involving contacts, sources / drains, gates, etc., the laser wavelength is, for example, You may employ | adopt the laser beam which has 1060 nm.

  Next, a failure analysis apparatus according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 10 is a schematic configuration diagram showing a failure analysis apparatus, and FIG. 11 is a schematic configuration diagram showing a defect investigation unit. In the present embodiment, a three-dimensional FNC margin analysis of SoC is performed using the SDL method.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 10, the failure analysis device 71 is provided with a failure analysis unit 1a, an EWS 2, and an LSI tester 3. The failure analysis apparatus 71 mainly includes a failure mode of a failure of a device under test (DUT Device under Test), which is a system LSI or SoC (System on a chip) including highly integrated logic circuits and sequential circuits. Applied to the analysis and identification of defective parts. The failure analysis unit 1a, EWS 2, and LSI tester 3 are connected to the LAN.

  The defect analysis unit 1a is provided with a defect investigation unit 11a and a control / analysis unit 12a. The defect investigation unit 11a performs defect analysis of the semiconductor device (DUT) 21 that is a device under test. The defect investigation unit 11a performs, for example, SDL (Soft Defect Localization) analysis. The control / analysis unit 12a controls the defect investigation unit 11a and analyzes the information investigated by the defect investigation unit 11a. The control / analysis unit 12a is provided with a display unit 13a. The display unit 13a displays, for example, information processed by the control / analysis unit 12a and information transmitted via the LAN.

  The LSI tester 3 outputs a power supply voltage, an input signal, a clock signal, and the like to the semiconductor device (DUT) 21 in the defect investigation unit 11a, and inputs an output signal output from the semiconductor device (DUT) 21 to the semiconductor device (DUT) 21 DUT) 21 is judged as PASS (good) or FAIL (bad).

  Here, in SDL (Soft Defect Localization) analysis, a laser beam that is converged finely is irradiated onto a semiconductor device (DUT) 21 that is, for example, a system LSI or SoC, and is subjected to local heating, photoexcitation current, or local semiconductor. Failure analysis is performed based on operational changes of the device (DUT) 21 and the like. In this failure analysis, for example, it is possible to specify a transistor having an insufficient operation margin, specify a disconnection or short-circuit portion of a wiring, specify a high-resistance portion of a via or a contact, and the like.

  As shown in FIG. 11, the defect investigation unit 11 a includes a semiconductor device (DUT) 21, a microscope unit 26, an optical stage 27, a laser generation / light detection unit 28, and an interface 30. Although not shown, the defect investigation unit 11a is provided with an amplifier 24 and a prober 23 as in the first embodiment.

  The semiconductor device (DUT) 21 is irradiated with laser light scanned in the X direction, Y direction, and Z direction on the front surface or the back surface (irradiation means). Here, the surface of the semiconductor device (DUT) 21 is irradiated with laser light, but the front surface or the back surface is appropriately selected according to the assumed failure mode or failure location of the semiconductor device (DUT) 21.

  The interface 30 outputs the power supply voltage, the input signal Sin, the clock signal Sclk, and the like output from the LSI tester 3 to the semiconductor device (DUT) 21, and outputs the output signal Sout that is the determination result of the semiconductor device (DUT) 21 to the LSI. Output to tester 3.

  In the SDL analysis, when the semiconductor device (DUT) 21 is a system LSI or SoC which is a silicon device, for example, a wavelength range of 1060 nm to 1400 nm is selected. A wavelength range of 1060 nm to 1160 nm is selected for the failure analysis of the transistor system, and a wavelength range of 1300 nm to 1400 nm is selected for the failure analysis of the wiring system.

  Next, SoC FNC (Function) margin analysis by the SDL method will be described with reference to FIGS. 12 is a flowchart showing SoC FNC margin analysis, FIG. 13 is a diagram showing PASS / FAIL with respect to the power supply voltage and clock signal of SoC, FIG. 14 is a diagram showing PASS / FAIL with respect to the clock signal in the laser irradiation state, and FIG. FIG. 16 is a diagram showing a change in the PASS / FAIL change number with respect to laser irradiation in the X direction or the Y direction, and FIG. 16 is a diagram showing a change in the PASS / FAIL change number with respect to laser irradiation in the Z direction. Here, for the FNC margin analysis of the SoC (silicon device) that is the device under test, the wavelength of the laser beam is selected to be 1300 nm, assuming that the wiring system is defective.

  As shown in FIG. 12, in the SoC FNC margin analysis, a power supply voltage, an input signal, a clock signal, and the like are output from the LSI tester 3 to the semiconductor device (DUT) 21 that is the SoC, and the semiconductor device (DUT) 21 outputs the semiconductor device. An output signal Sout which is a determination result of (DUT) 21 is output to the LSI tester 3. The LSI tester 3 determines whether the output signal Sout satisfies a predetermined standard.

  The determination result is created as, for example, a PASS / FAIL map for the clock signal Sclk and the power supply voltage as shown in FIG. 13 (creating means). In the PASS / FAIL map, the faster the clock signal Sclk, the greater the number of PASSs, and the higher the power supply voltage, the greater the number of PASSs. When the clock signal Sclk exceeds a predetermined speed, the semiconductor device (DUT) 21 cannot respond and becomes FAIL (not shown). When the power supply voltage becomes equal to or higher than a predetermined voltage, for example, a leakage current is generated in the semiconductor device (DUT) 21 and becomes FAIL. Although the PASS / FAIL map for the clock signal Sclk and the power supply voltage is selected here, the PASS / FAIL map for the input signal Sin and the power supply voltage may be selected (step S51).

  Next, the semiconductor device (DUT) 21 is irradiated with laser light (scanned in the X direction and Y direction), and a PASS / FAIL map in the laser irradiation state is sequentially created at the laser irradiation position. The focal position of laser irradiation is set, for example, on the surface of the silicon substrate.

  When laser irradiation is performed, in the semiconductor device (DUT) 21 in the laser irradiation region, a thermal excitation current is generated, and the operation margin of the laser irradiation region changes. For this reason, as shown in FIG. 14, for example, the location of the PASS in contact with the FAIL region is changed to FAIL, and the number of PASS is reduced. Here, eight PASS locations in contact with the FAIL region are changed to FAIL (four locations on the high power supply voltage side and four locations on the low power supply voltage side). In FIG. 14, the number of PASS is decreased, but the FAIL location adjacent to the PASS region may be changed to PASS, and the number of FAIL may be decreased (step S52).

  Subsequently, the number of changes in PASS or FAIL when laser irradiation is performed is counted. As shown in FIG. 15, the number of changes in PASS or FAIL is plotted with respect to the irradiation position of the laser beam. Thereafter, the number of changes in PASS or FAIL is two-dimensionally displayed as a PASS / FAL image (I) with respect to the irradiation position of the laser beam (first image creation means). Note that the display image displayed two-dimensionally is corrected so that the position coordinates in the horizontal direction match the planar layout diagram of the semiconductor device (DUT) 21. For example, the PASS / FAIL image (I) and the planar layout diagram of the semiconductor device (DUT) 21 are superimposed (first position coordinate setting means) (step S53).

  Then, the region I shown in FIG. 15 (that is, the horizontal position of the semiconductor device (DUT) 21), which is the position where the number of changes in PASS or FAIL is the largest, is specified. In parallel, the OBIRCH image may be monitored in the same manner as in the first embodiment (step S54).

  Next, the laser beam irradiation is scanned in the vertical direction (the cross-sectional direction of the SoC) in the region I where the position is specified and the peripheral portion thereof. Specifically, laser scanning is performed from the surface of the silicon substrate in the direction in which the wiring layer is formed (step S55).

  Subsequently, the number of changes in PASS or FAIL when laser irradiation is performed is counted. As shown in FIG. 16, the number of changes in PASS or FAIL is plotted against the irradiation position of the laser beam. Thereafter, the number of changes in PASS or FAIL is two-dimensionally displayed as a PASS / FAIL image (II) with respect to the irradiation position of the laser beam (second image display creation means). The display image displayed two-dimensionally is corrected so that the position coordinates in the vertical direction match the cross-sectional view of the semiconductor device (DUT) 21. For example, the PASS / FAIL image (II) and the cross-sectional view of the semiconductor device (DUT) 21 are overlapped (second position coordinate setting means) (step S56).

  Then, the region II shown in FIG. 16 (that is, the vertical position of the semiconductor device (DUT) 21), which is the position where the number of changes in PASS or FAIL is the largest, is specified. In parallel, the OBIRCH image may be monitored in the same manner as in the first embodiment (step S57).

  As a result, the defective part of the wiring system related to the SoC FNC margin is identified three-dimensionally. Similar to the first embodiment, a defective portion of the wiring system related to the SoC FNC margin may be specified three-dimensionally using the OBIRCH image.

  As described above, the failure analysis apparatus according to the present embodiment includes the failure analysis unit 1a, the EWS 2, and the LSI tester 3. The defect analysis unit 1a is provided with a defect investigation unit 11a and a control / analysis unit 12a. The defect investigation unit 11a is provided with a semiconductor device (DUT) 21, a microscope unit 26, an optical stage 27, a laser generation / light detection unit 28, and an interface 30. The laser generation / light detection unit 28 irradiates the semiconductor device (DUT) 21 which is a device under test with the laser beam in the horizontal direction and the vertical direction via the optical stage 27 and the microscope unit 26. The LSI tester 3 supplies power and signals to the semiconductor device (DUT) 21 to determine PASS or FAIL for the FNC margin of the semiconductor device (DUT) 21. The EWS 2 creates a PASS / FAIL map of the semiconductor device (DUT) 21. The control / analysis unit 12a controls the scanning of the laser beam in the horizontal direction of the semiconductor device (DUT) 21, and the number of changes in PASS / FAIL on the PASS / FAIL map of the semiconductor device (DUT) 21 in the laser beam irradiation state by EWS2. Are counted, and the number of PASS / FAIL changes is created as the first PASS / FAIL image. The EWS 2 superimposes the first PASS / FAIL image and the planar layout image of the semiconductor device (DUT) 21 so that the horizontal position coordinates are the same. The control / analysis unit 12a controls the scanning of the laser beam in the vertical direction of the semiconductor device (DUT) 21, and the number of changes in PASS / FAIL on the PASS / FAIL map of the semiconductor device (DUT) 21 in the laser beam irradiation state by EWS2. Are counted, and the number of PASS / FAIL changes is created as a second PASS / FAIL image. The EWS 2 superimposes the second PASS / FAIL image and the cross-sectional image of the semiconductor device (DUT) 21 so that the position coordinates in the vertical direction are the same.

  For this reason, the first PASS / FAIL image and the planar layout image of the semiconductor device (DUT) 21 are overlaid, and the second PASS / FAIL image and the cross-sectional image of the semiconductor device (DUT) 21 are overlaid. The defective portion of the semiconductor device (DUT) 21 can be identified three-dimensionally. In the failure analysis of the semiconductor device (DUT) 21 using the failure analysis apparatus 71, the failure analysis of the semiconductor device (DUT) 21 can be performed only by irradiating the semiconductor device (DUT) 21 with a laser beam. Even when there are many locations or failure modes other than the assumptions are mixed, failure analysis of the semiconductor device (DUT) 21 in a non-destructive manner is possible, and combined use with other failure analysis devices is possible.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, the device under test (DUT) is SoC or system LSI (silicon device), but memory LSI (silicon device), analog IC (silicon device), analog digital IC (silicon device), power device, etc. The present invention can also be applied to a semiconductor device (silicon device) or a GaAs compound device. In that case, it is preferable to appropriately select conditions such as the wavelength and power of the laser light in consideration of the failure mode and the substrate.

  In the second embodiment, the FNC margin analysis is performed on the assumption that the wiring system of the silicon semiconductor device (DUT) is defective when it is related to the wiring layer or via. For this reason, laser light having a laser wavelength of 1300 nm is used, but for FNC margin analysis in the case of a defective wiring system of a silicon-based semiconductor device (DUT) involving contacts, sources / drains, gates, etc. A laser beam having a laser wavelength of, for example, 1060 nm may be employed.

  In the embodiment, the device under test (DUT) is irradiated with laser light. Instead, the device under test (DUT) is irradiated with an electron beam as a charged beam, and the absorbed current of the device under test (DUT). May be imaged three-dimensionally. Alternatively, the device under test (DUT) may be irradiated with an electron beam as a charged beam, and the potential gradient of the device under test (DUT) may be imaged three-dimensionally.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) Irradiation means for irradiating a device under test with a charged beam and generating an excitation current at a specific location of the irradiated device under test; and scanning device for scanning the charged beam horizontally and vertically. A plurality of first position coordinate setting means for superimposing the horizontal current absorption current image and the planar layout image of the device under test so that the plane position coordinates are the same; A second position coordinate setting unit that superimposes the synthesized image obtained by synthesizing the absorption current image in the horizontal direction in the vertical direction and the cross-sectional image of the device under test so that the position coordinates in the vertical direction are the same, The absorption current image in the horizontal direction and the planar layout image of the device under test are overlaid, and the composite image and the cross-sectional image of the device under test are overlaid. A failure analysis apparatus that three-dimensionally identifies a defective portion of the device under test by

(Supplementary Note 2) Irradiation means for irradiating a device under test with a charged beam and generating an excitation current at a specific location of the irradiated device under test, and the test device by scanning the charged beam horizontally and vertically First potential coordinate setting for superimposing the potential gradient image in the horizontal direction and the planar layout image of the device under test so that the plane position coordinates are the same. And second position coordinate setting means for superimposing a composite image obtained by combining a plurality of horizontal potential gradient images in the vertical direction and a cross-sectional image of the device under test so that the vertical position coordinates are the same. A horizontal layout of the potential gradient image and a planar layout image of the device under test, and a cut-off between the composite image and the device under test. The failure analysis apparatus for identifying the defective portion of the DUT three-dimensionally by superimposing images.

(Supplementary note 3) The failure analysis apparatus according to supplementary note 1 or 2, wherein the charged beam is an electron beam.

1, 1a Defect analysis unit 2 EWS
3 LSI tester 11, 11a Defect investigation unit 12, 12a Investigation analysis unit 13, 13a, 15 Display unit 14 Information storage unit 21 Semiconductor device (DUT)
22 DUT stage 23 prober 24 amplifier 26 microscope unit 27 optical stage 28 laser generation unit / light detection unit 30 interface 70, 71 failure analysis device Sclk clock signal Sin input signal Sout output signal

Claims (5)

A laser irradiation means for irradiating the device under test with laser light and heating a specific portion of the irradiated device under test to generate a thermoelectromotive current;
An imaging unit that scans the laser light in a horizontal direction and a vertical direction to capture a light heating resistance change image of the device under test;
A first position coordinate setting means for superimposing the light heating resistance change image in the horizontal direction and the planar layout image of the device under test so that the position coordinates in the horizontal direction are the same;
A second position coordinate setting means for superimposing the vertical optical stage position information and the cross-sectional information of the device under test so that the vertical position coordinates are the same;
A failure analysis apparatus characterized by three-dimensionally identifying a defective portion of the device under test.   Third position coordinate setting means for superimposing a composite image obtained by combining a plurality of horizontal photothermal resistance change images in the vertical direction and a cross-sectional image of the device under test so that the vertical position coordinates are the same. Then, the photothermal resistance change image in the horizontal direction and the planar layout image of the device under test are overlaid, and the composite image and the cross-sectional image of the device under test are overlaid so that three defective portions of the device under test are obtained. The failure analysis device according to claim 1, wherein the failure analysis device is specified dimensionally. Irradiating means for irradiating the device under test with laser light in a horizontal direction and a vertical direction;
An LSI tester that supplies power and signals to the device under test to determine PASS or FAIL for the FNC margin of the device under test;
Creating means for creating a PASS / FAIL map of the device under test;
The laser beam is scanned in the horizontal direction of the device under test, the number of PASS / FAIL changes on the PASS / FAIL map of the device under test in the laser light irradiation state is counted, and the number of PASS / FAIL changes A first image creating means that takes the first PASS / FAIL image as a first PASS / FAIL image;
First position coordinate setting means for superimposing the first PASS / FAIL image and the planar layout image of the device under test so that the position coordinates in the horizontal direction are the same;
The laser beam is scanned in the vertical direction of the device under test, and the number of PASS / FAIL changes on the PASS / FAIL map of the device under test in the laser light irradiation state is counted, and the number of PASS / FAIL changes. A second image creation means that takes the second PASS / FAIL image as a second PASS / FAIL image;
Second position coordinate setting means for superimposing the second PASS / FAIL image and the cross-sectional image of the device under test so that the position coordinates in the vertical direction are the same;
The device under test by superimposing the first PASS / FAIL image and the planar layout image of the device under test, and superimposing the second PASS / FAIL image and the cross-sectional image of the device under test. A failure analysis apparatus characterized by three-dimensionally identifying a defective portion.   4. The failure analysis apparatus according to claim 1, wherein when the device under test is a silicon device, the laser beam has a wavelength in the range of 1060 nm to 1400 nm.   5. The failure analysis apparatus according to claim 1, wherein the laser light is applied to a front surface or a back surface of the device under test.

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