JP2006066797A - Ferroelectric memory and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the plug of a second contact hole from being oxidized and to improve reliability by forming a coating layer on a region including the plug of the second contact hole. <P>SOLUTION: This method of manufacturing the ferroelectric memory includes the steps of (a) forming first and second contact holes 22 and 24 in an insulating layer 20 formed above a substrate 10, (b) forming plugs 42 and 44 each having an upper surface lower than the upper surface of the insulating layer 20 in the interiors of the first and second contact holes 22 and 24. And, the method includes the steps of (c) forming a barrier layer 51 in a region including the plugs 42 and 44 of the first and second contact holes 22 and 24, and (d) forming a laminate 81 by sequentially laminating a lower electrode 82, the ferroelectric layer 84 and an upper electrode 86. Further, the method includes the steps of (e) forming a ferroelectric capacitor 80 in a region including the upper part of the plug 42 of the first contact hole 22 by etching the laminate 81. In addition, the method includes the steps of (f) forming a coating layer 90 in a region including the upper part of the plug 44 of the second contact hole 24, and (g) annealing it in an oxygen atmosphere. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a ferroelectric memory and a method for manufacturing the same.

As a ferroelectric memory, a structure in which a ferroelectric capacitor is stacked on a selection transistor is known. An insulating layer is interposed between the ferroelectric capacitor and the selection transistor, and electrical connection between the two is achieved by a plug embedded in the contact hole of the insulating layer. The plug is formed by forming a conductive layer, which is a plug material, on the insulating layer inside and around the contact hole, and polishing the whole by applying a chemical mechanical polishing (CMP) method or the like. However, in this case, a recess (concave portion) of the conductive layer is generated in the contact hole due to a difference in polishing rate between the conductive layer and the surrounding insulating layer. If the recess is left as it is, the ferroelectric capacitor cannot be formed on a flat surface, and the stabilization of the manufacturing process may be impaired, leading to a decrease in reliability. In the manufacturing process of the ferroelectric capacitor, it is necessary to prevent oxidation of the plug because the ferroelectric layer needs to be oxidized.
JP-A-11-74488

  An object of the present invention is to provide a ferroelectric memory capable of improving reliability and a method for manufacturing the same.

(1) A method for manufacturing a ferroelectric memory according to the present invention includes:
(A) forming first and second contact holes in an insulating layer formed above the substrate;
(B) forming a plug having an upper surface lower than the upper surface of the insulating layer in each of the first and second contact holes;
(C) forming a barrier layer in a region including the upper part of each of the first and second contact holes;
(D) stacking a lower electrode, a ferroelectric layer, and an upper electrode in order to form a stacked body;
(E) forming a ferroelectric capacitor in a region including the upper part of the plug of the first contact hole by etching the stacked body;
(F) forming a coating layer in a region including the upper part of the plug of the second contact hole;
including.

  According to the present invention, since the coating layer is formed in the region including on the plug of the second contact hole, for example, in the annealing process of the ferroelectric capacitor, the oxidation of the plug of the second contact hole can be prevented. . That is, even when the thickness of the barrier layer is insufficient or when the barrier layer is etched away, the plug of the second contact hole can be prevented from being oxidized.

  In the present invention, the B layer is provided above the specific A layer means that the B layer is provided directly on the A layer and the B layer via another layer on the A layer. Is provided. The same applies to the following inventions.

(2) In this method of manufacturing a ferroelectric memory,
In the step (c), the barrier layer is formed in a region further including the upper part of the insulating layer,
In the step (e), the barrier layer may be etched simultaneously with the stacked body.

  According to this, since not only the stacked body but also the barrier layer is etched, for example, even when the barrier layer on the plug of the second contact hole is removed, it is possible to prevent the plug from being oxidized by the covering layer. it can.

(3) In this ferroelectric memory,
In the step (f), the coating layer may be formed in a region further including the surface of the ferroelectric capacitor.

  According to this, a coating layer is also formed on the surface of the ferroelectric capacitor. By controlling the thickness of the coating layer, for example, an annealing effect on the ferroelectric capacitor is achieved.

(4) In this method of manufacturing a ferroelectric memory,
In the step (f), the coating layer may be formed by sputtering.

  According to this, since the coating layer is thinly formed on the side surface of the ferroelectric capacitor due to the coverage characteristic by the sputtering method, for example, an annealing effect on the ferroelectric capacitor is achieved.

(5) In this method of manufacturing a ferroelectric memory,
The covering layer may be made of an inorganic insulating material.

(6) In this method of manufacturing a ferroelectric memory,
After the step (f), annealing may be further performed in an oxygen atmosphere.

(7) A method for manufacturing a ferroelectric memory according to the present invention includes:
(A) forming first and second contact holes in an insulating layer formed above the substrate;
(B) forming a plug having an upper surface lower than the upper surface of the insulating layer in each of the first and second contact holes;
(C) forming a barrier layer in a region including the upper part of each plug of the first and second contact holes and the upper part of the insulating layer;
(D) stacking a lower electrode, a ferroelectric layer, and an upper electrode in order to form a stacked body;
(E) forming a ferroelectric capacitor in a region including the upper part of the plug of the first contact hole by etching the stacked body so that the barrier layer remains;
(F) performing an annealing treatment in an oxygen atmosphere;
(G) removing a portion of the barrier layer above the insulating layer;
including.

  According to the present invention, since the etching process of the multilayer body for forming the ferroelectric capacitor is performed so that the barrier layer remains, in the subsequent annealing process of the ferroelectric capacitor, the plug of the second contact hole is formed. It is possible to prevent oxidation. Further, it is not necessary to provide a new layer for preventing oxidation, and the manufacturing process can be simplified.

(8) In this method of manufacturing a ferroelectric memory,
Before the step (b), further comprising forming another barrier layer on the inner surface of each of the first and second contact holes;
In the step (b), the plug may be formed inside the other barrier layer.

(9) In this method of manufacturing a ferroelectric memory,
In the step (b),
Forming a first conductive layer inside each of the first and second contact holes and above the insulating layer;
The plug may be formed by polishing the first conductive layer until the insulating layer is exposed.

(10) In this method of manufacturing a ferroelectric memory,
After the polishing step of the step (b), an upper portion of the first conductive layer in at least one of the first and second contact holes may be further removed by etching.

  According to this, since the upper portion of the first conductive layer is further removed, the barrier layer can be formed thicker, and the barrier effect can be improved.

(11) In this method of manufacturing a ferroelectric memory,
In the step (c),
Forming a second conductive layer inside each of the first and second contact holes and above the insulating layer;
The barrier layer may be formed by polishing the second conductive layer so that a predetermined thickness remains above the insulating layer.

(12) In this method of manufacturing a ferroelectric memory,
An adhesion layer may be further formed above the barrier layer after the polishing step of the step (c).

(13) In this method of manufacturing a ferroelectric memory,
The polishing step of at least one of the steps (b) and (c) may include a step by a chemical mechanical polishing method.

(14) A ferroelectric memory according to the present invention comprises:
A substrate;
A first insulating layer formed above the substrate;
A first contact hole penetrating the first insulating layer;
A second contact hole penetrating the first insulating layer;
A first contact portion formed in the first contact hole;
A second contact portion formed in the second contact hole;
A ferroelectric capacitor formed by sequentially laminating a lower electrode, a ferroelectric layer, and an upper electrode in a region including above the first contact portion;
A second insulating layer formed above the first insulating layer;
A third contact hole formed above the second contact portion and penetrating the second insulating layer;
A third contact portion formed in the third contact hole;
Including
The first contact portion includes a first plug and a first barrier layer formed above the first plug,
An upper surface of the second contact portion is formed lower than an upper surface of the first barrier layer;
The lower surface of the third contact portion is connected to the upper surface of the second contact portion inside the second contact hole.

(15) In this ferroelectric memory,
The second contact portion includes a second plug and a second barrier layer formed above the second plug,
The upper surface of the second barrier layer may be formed lower than the upper surface of the first barrier layer.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
1 to 8 are views schematically showing a method of manufacturing a ferroelectric memory according to the first embodiment of the present invention.

  As shown in FIG. 1, a base 10 is prepared. The base 10 is a semiconductor substrate (for example, a silicon substrate). A plurality of transistors (not shown) are formed on the base 10. The transistor includes an impurity region serving as a source region or a drain region, a gate insulating layer, and a gate electrode. An element isolation region (not shown) is formed between the transistors, and electrical insulation between the transistors is achieved. In this embodiment, as an example, a ferroelectric memory having a 1T1C type stack structure is manufactured.

First, the insulating layer 20 is formed on the base 10. When the base 10 is a silicon substrate, the insulating layer 20 may be formed from, for example, a silicon oxide layer (SiO ₂ layer). The insulating layer 20 is formed on the surface of the substrate 10 on which a plurality of transistors are formed. The insulating layer 20 may be formed so as to cover the entire upper surface of the substrate 10, and can be formed by applying a known technique such as a CVD (Chemical Vapor Deposition) method.

  As shown in FIG. 1, first and second contact holes 22 and 24 are formed in the insulating layer 20. The first and second contact holes 22 and 24 are formed in different planar regions of the insulating layer 20, respectively. The source region or drain region of any one transistor is exposed from the first contact hole 22, and the source region or drain region of another transistor is exposed from the second contact hole 24. Note that a photolithography technique or the like can be applied as a method of forming the first and second contact holes 22 and 24.

  As shown in FIGS. 2 to 6, the first contact portion 60 is formed in the first contact hole 22, and the second contact portion 70 is formed in the second contact hole 24. The first and second contact portions 60 and 70 have electrical conductivity.

  First, as shown in FIG. 2, a barrier layer (another barrier layer) 30 is formed on the inner surfaces of the first and second contact holes 22 and 24. The barrier layer 30 can be formed by sputtering or the like. The barrier layer 30 is formed on the side surface (end surface of the insulating layer 20) and the bottom surface (upper surface of the substrate 10) of each of the first and second contact holes 22 and 24, and further formed on the upper surface of the insulating layer 20. However, the barrier layer 30 is formed so as not to fill the first and second contact holes 22 and 24. The barrier layer 30 may be formed of at least one of a titanium aluminum nitride layer (TiAlN layer) and a titanium nitride layer (TiN layer), for example.

  Next, as shown in FIG. 3, a first conductive layer 40 is formed inside each of the first and second contact holes 22, 24 and on the insulating layer 20. The first conductive layer 40 is formed so as to fill the insides of the first and second contact holes 22 and 24 (specifically, the inside surrounded by the barrier layer 30). In the case of forming the barrier layer 30, the first conductive layer 40 is formed on the barrier layer 30. The first conductive layer 40 may be formed by a CVD method or the like. The first conductive layer 40 may be formed from, for example, a tungsten layer (W layer).

  Thereafter, as shown in FIG. 4, the first conductive layer 40 is polished to form plugs 42 and 44. In the polishing process, a process by a chemical mechanical polishing (CMP) method may be applied. In this embodiment, a part of the first conductive layer 40 and a part of the barrier layer 30 are polished and removed. That is, the first conductive layer 40 (and the barrier layer 30) is polished until the insulating layer 20 serving as a stopper is exposed. In that case, the insulating layer 20 (for example, silicon oxide material) is harder to be polished (the polishing rate is lower) than that of the first conductive layer 40 (for example, tungsten material), so that the first and second contact holes 22 and 24 Inside, recesses (first and second recesses 26 and 28) of the first conductive layer 40 occur. If the insulating layer 20 is harder to be polished than the barrier layer 30, the upper portions of the barrier layers 32 and 34 are also polished and removed inside the first and second contact holes 22 and 24, respectively.

  After the above polishing step, the upper portion of the first conductive layer 40 in at least one of the first and second contact holes 22 and 24 may be further removed by etching (for example, dry etching). Such an etching process may be performed only on the first contact hole 22, or may be performed only on the second contact hole 24, and may be performed on both the first and second contact holes 22 and 24. You may go. According to this step, the recesses (first and second recesses 26 and 28) of the first conductive layer 40 described above further advance (become deeper), so that barrier layers 52 and 54 described later are formed thick. Thus, the barrier effect can be improved.

  Thus, the barrier layer 32 can be formed along the inner surface of the first contact hole 22, and the plug 42 can be formed on the inner side surrounded by the barrier layer 32. Similarly, the barrier layer 34 can be formed along the inner surface of the second contact hole 24, and the plug 44 can be formed inside the barrier layer 34. Each of the plugs 42 and 44 has an upper surface lower than the upper surface of the insulating layer 20. That is, the first and second recesses 26 and 28 are formed on the plugs 42 and 44 in the first and second contact holes 22 and 24.

  Next, as shown in FIG. 5, in the same manner as the first conductive layer 40, the second conductive layer 50 is formed into the first and second contact holes 22, 24 (specifically, the first and second concave portions). 26, 28) and on the insulating layer 20. The second conductive layer 50 is formed so as to fill the first and second recesses 26 and 28. The second conductive layer 50 may be formed by sputtering or the like. The second conductive layer 50 may be formed of at least one of a titanium aluminum nitride layer (TiAlN layer) and a titanium nitride layer (TiN layer), for example. The second conductive layer 50 may be formed from the same material as the barrier layer 30 described above. As shown in FIG. 5, in the second conductive layer 50, depressions 56 and 58 may be formed above the first and second contact holes 22 and 24, respectively.

  Thereafter, as shown in FIG. 6, the second conductive layer 50 is polished to form a barrier layer 51. The second conductive layer 50 may be polished by a chemical mechanical polishing (CMP) method. The content of the polishing process of the second conductive layer 50 corresponds to the content of the polishing process of the first conductive layer 40 described above. However, in this step, the second conductive layer 50 is polished so that a predetermined thickness remains on the insulating layer 20. That is, in this step, the polishing step is terminated before the insulating layer 20 is exposed so that the insulating layer 20 that is the base of the second conductive layer 50 is not exposed. According to this, it is sufficient to polish only the second conductive layer 50 (for example, it is not necessary to polish the second conductive layer 50 and the insulating layer 20 at the same time). It is possible to prevent the occurrence of recesses. The second conductive layer 50 is preferably polished so that at least the depressions 56 and 58 are eliminated. By doing so, the upper surface of the second conductive layer 50 (barrier layer 51) can be flattened.

  Alternatively, as a modification, the second conductive layer 50 may be polished so that the insulating layer 20 is exposed. In this case, the barrier layer formed from the second conductive layer 50 is formed inside the first and second contact holes 22 and 24 and is not formed on the insulating layer 20.

  Thus, the first contact portion 60 can be formed in the first contact hole 22, and the second contact portion 70 can be formed in the second contact hole 24. According to this, since the recesses (first and second recesses 26 and 28) generated in the process of forming the plugs 42 and 44 are eliminated by the formation of the barrier layer 51, the first and second contact portions The upper surfaces of 60 and 70 and the upper surface of the insulating layer 20 can be substantially flush. By doing so, a ferroelectric capacitor 80 described later can be formed on a flat surface. In addition, the barrier layers 32 and 51 of the first contact portion 60 can prevent diffusion and oxidation of the plug 42, and the resistance of the first contact portion 60 can be reduced. The same applies to the barrier layers 34 and 51 of the second contact portion 70.

  If necessary, an adhesion layer (not shown) may be formed on the barrier layer 51. The adhesion layer may be formed from the same material as the barrier layer 51 (for example, a TiAlN layer or a TiN layer), or may be formed from a different material. If an adhesion layer made of the same material as that of the barrier layer 51 is formed, a thin portion or a peeled portion of the barrier layer 51 can be covered, so that the barrier effect can be further improved. The adhesion layer has a greater adhesion to the lower electrode 82 described later than the plugs 42 and 44. Alternatively, the barrier layer 51 may also serve as an adhesion function. When the adhesion layer is formed of a material different from that of the barrier layer 51, the adhesion layer may have a greater adhesion force to the lower electrode 82 than the barrier layer 51.

  As shown in FIGS. 7 and 8, a ferroelectric capacitor 80 is formed in a region including on the first contact portion 60 (plug 42). For example, the ferroelectric capacitor 80 is formed in a region including the first contact hole 22 and its peripheral region (insulating layer 20) in a plan view perpendicular to the surface of the substrate 10. In the present embodiment, the ferroelectric capacitor 80 is not formed on the second contact portion 70 (plug 44).

  First, as shown in FIG. 7, a lower electrode 82, a ferroelectric layer 84, and an upper electrode 86 are sequentially stacked to form a stacked body 81. The stacked body 81 is formed in a region including the first and second contact portions 60 and 70 (plugs 42 and 44). The stacked body 81 is also formed on the region of the insulating layer 20 around the first and second contact holes 22 and 24.

The lower electrode 82 is made of, for example, Pt, Ir, Ir oxide (IrO _x ), Ru, Ru oxide (RuO _x ), SrRu composite oxide (SrRuO _x ), or the like. The lower electrode 82 is formed of a single layer or a plurality of layers. As a method for forming the lower electrode 82, a sputtering method, a vacuum evaporation method, a CVD method, or the like can be applied.

The ferroelectric layer 84 may be formed using a PZT-based ferroelectric made of an oxide containing Pb, Zr, and Ti as constituent elements. Alternatively, Pb (Zr, Ti, Nb) O ₃ (PZTN system) doped with Nb at the Ti site may be applied. Alternatively, the ferroelectric layer 84 is not limited to these materials, and for example, any of SBT type, BST type, BIT type, and BLT type may be applied. As a method of forming the ferroelectric layer 84, a solution coating method (including a sol-gel method, a MOD (Metal Organic Decomposition) method, etc.), a sputtering method, a CVD (Chemical Vapor Deposition) method, a MOCVD (Metal Organic Chemical Vapor Deposition). ) Law etc. can be applied.

  The upper electrode 86 can be formed by applying the same material and method as the lower electrode 82.

  Thereafter, the laminate 81 is patterned into a predetermined shape. First, a resist layer R is formed on the stacked body 81 by applying a photolithography technique. In this case, the resist layer R is formed in a region including the first contact portion 60 (plug 42) and is not formed on the second contact portion 70 (plug 44). Then, a portion of the multilayer body 81 exposed from the resist layer R (a portion including the second contact portion 70 (plug 44)) is etched. As shown in FIG. 7, when the barrier layer 51 is also formed on the insulating layer 20, the barrier layer 51 is also etched simultaneously with the stacked body 81. That is, unnecessary portions of the barrier layer 51 are also removed by over-etching the stacked body 81. Depending on the progress of etching, the barrier layer 54 may be thinly left on the plug 44 of the second contact hole 24 as shown in FIG. 8, or the plug 44 may be exposed without leaving the barrier layer 54. Good. For the etching of the stacked body 81 and the barrier layer 51, an appropriate method can be selected according to the material, film thickness, etc., and a dry etching method or a wet etching method can be exemplified.

  Unlike the example shown in FIG. 7, even when the barrier layer 51 is not formed on the insulating layer 20 and is formed only inside the first and second contact holes 22 and 24, the stacked body The etching of 81 may remove at least a part of the barrier layer inside the second contact hole 24. In the present embodiment, it is possible to provide a manufacturing process with a high effect of preventing plug oxidation regardless of the form of the barrier layer.

  Thus, the ferroelectric capacitor 80 can be formed as shown in FIG. In the example shown in FIG. 8, the barrier layer 52 of the first contact portion 60 is formed. The barrier layer 52 is formed so as to extend from the first contact hole 22 to the surrounding insulating layer 20. Further, as described above, in the second contact hole 24, the plug 44 is exposed or the thin barrier layer 54 remains.

Therefore, in the present embodiment, the coating layer 90 is formed as shown in FIG. 9 before the annealing treatment in an oxygen atmosphere for stabilizing the ferroelectric layer 84 (for example, recovery from etching damage). The covering layer 90 may be formed of an inorganic insulating material, and examples thereof include an aluminum oxide layer (Al ₂ O ₃ layer). The covering layer 90 is formed in a region including at least the second contact portion 70 (plug 44).

  According to the present embodiment, since the covering layer 90 is formed in a region including the top of the plug 44 of the second contact hole 24, for example, in the annealing process of the ferroelectric capacitor 80, the plug 44 of the second contact hole 24. Can be prevented from being oxidized. That is, even when the thickness of the barrier layer 54 is insufficient or when the barrier layer 54 is etched away, the plug 44 of the second contact hole 24 can be prevented from being oxidized. Further, as described above, if the barrier layer 54 is left on the plug 44 of the second contact hole 24, the coating layer 90 and the barrier layer 54 can further improve the antioxidant effect.

  As shown in FIG. 9, the covering layer 90 may be formed in a region further including the surface (upper surface and side surface) of the ferroelectric capacitor 80. In that case, the entire surface of the ferroelectric capacitor 80 may be covered. Even when the surface of the ferroelectric capacitor 80 is coated, the annealing effect on the ferroelectric capacitor 80 is achieved by controlling the thickness of the coating layer 90. Specifically, the coating layer 90 is formed by applying a sputtering method or the like, and a portion of the coating layer 90 formed on the side surface of the ferroelectric capacitor 80 can be thinned by the coverage characteristics by such a method. Good. By so doing, an annealing effect can be gradually achieved from the side surface of the ferroelectric capacitor 80. Further, the covering layer 90 may be formed on the entire upper portion of the base body 10. According to this, since the coating layer 90 can be formed without patterning, the manufacturing process can be facilitated.

  In the case where the coating layer 90 has an insulating property, after the annealing process, the coating layer 90 is patterned to achieve a predetermined electrical connection. For example, the second contact portion 70 may be exposed from the covering layer 90, or the upper electrode 86 of the ferroelectric capacitor 80 may be exposed (see FIG. 10).

  According to the method for manufacturing a ferroelectric memory according to the present embodiment, as described above, the oxidation of the plug can be prevented, so that the reliability can be improved.

  FIG. 10 is a diagram schematically showing a ferroelectric memory according to the present embodiment. This ferroelectric memory may be manufactured by the above-described method, and includes contents that can be derived from the description of the above-described method.

  The ferroelectric memory according to the present embodiment includes a base 10, an insulating layer (first insulating layer) 20, first and second contact portions 60 and 70, and a ferroelectric capacitor 80. .

  Each of the first and second contact portions 60 and 70 is formed to extend in a direction perpendicular to the surface of the base body 10 and penetrates the insulating layer 20. A transistor (either one of the source region and the drain region) of the base 10 is electrically connected to one end of the first contact portion 60, and a ferroelectric capacitor 80 is electrically connected to the other end. It is connected to the. That is, the first contact portion 60 electrically connects the transistor and the ferroelectric capacitor 80.

  As described in the above manufacturing method, the upper surface (the barrier layer (second barrier layer) 54 or the plug (second plug) 44) of the second contact portion 70 is the barrier layer of the first contact portion 60. (First barrier layer) 52 is formed lower than the upper surface. The second contact part 70 is formed on the insulating layer 20 at the same level as the first contact part 60.

  As shown in FIG. 10, the second insulating layer 100 is formed on the insulating layer 20, and the third contact hole 102 is formed in the second insulating layer 100. The third contact hole 102 is located on the second contact portion 70. In other words, at least a part of the second and third contact holes 24 and 102 overlap each other. A third contact portion 104 having electrical conductivity is formed in the third contact hole 102. In the present embodiment, the lower surface of the third contact portion 104 is connected to the upper surface of the second contact portion 70 inside the second contact hole 24. The third contact part 104 may have the same structure as the first or second contact part 60, 70. Electrical connection between the transistor of the base 10 and the wiring (or pad) 110 is achieved by the second and third contact portions 70 and 104.

  In the example shown in FIG. 10, the fourth contact hole 106 is formed in the second insulating layer 100. The fourth contact hole 106 is located on the ferroelectric capacitor 80. The ferroelectric capacitor 80 (specifically, the upper electrode 86) and the wiring (or pad) 112 are electrically connected by the fourth contact portion 108 having electrical conductivity formed in the fourth contact hole 106. Is planned. Note that the coating layer 90 described in the above manufacturing method may be interposed between the insulating layer 20 and the second insulating layer 100.

  In the ferroelectric memory according to the present embodiment, the lower electrode 82 of the ferroelectric capacitor 80 is electrically connected to the bit line, and the upper electrode 86 of the ferroelectric capacitor 80 is electrically connected to the plate line. The gate electrode of the transistor is electrically connected to the word line.

  According to the ferroelectric memory in accordance with the present embodiment, it is possible to prevent the plug from being oxidized by applying the above-described manufacturing process, so that the reliability can be improved.

(Second Embodiment)
FIG. 11 is a diagram schematically showing a ferroelectric memory according to the second embodiment of the present invention.

  In the present embodiment, first, a barrier layer is formed in a region including the plugs 42 and 44 of the first and second contact holes 22 and 24 and the insulating layer 20. As described above, the barrier layer may be formed into a single layer by polishing the second conductive layer to the point before the insulating layer 20 is exposed (see FIG. 6 above), or the second conductive layer may be insulated. After polishing until the layer 20 is exposed, a plurality of layers may be formed by forming a film thereon by a sputtering method or the like.

  Next, after forming a laminated body to be the ferroelectric capacitor 80 (see FIG. 7 described above), the laminated body is etched so that the barrier layer 53 remains. In that case, the barrier layer 53 is left at least on the insulating layer 20. For this purpose, the progress of etching (etching time, etchant properties, etc.) may be controlled. The barrier layer 53 may be left entirely, or the surface portion may be removed so that the barrier layer 53 is thinner than the underlying portion of the ferroelectric capacitor 80 as shown in FIG. If the barrier layer 53 is left on the insulating layer 20, a sufficiently thick barrier layer can be left on the plug 44 of the second contact hole 24. Therefore, annealing in an oxidizing atmosphere is possible. In the processing, the plug 44 can be prevented from being oxidized.

  After the annealing process, the portion of the barrier layer 53 on the insulating layer 20 is removed by etching or the like. In that case, all or part of the inside of the second contact hole 24 in the barrier layer 53 may be further removed. After the removal process of the barrier layer 53, the plug 44 in the second contact hole 24 may be exposed, or a thin barrier layer may be left on the plug 44 (see FIG. 8 described above).

  According to the present embodiment, the etching process of the multilayer body 81 for forming the ferroelectric capacitor 80 is performed so that the barrier layer remains. Therefore, in the subsequent annealing process of the ferroelectric capacitor 80, the second step is performed. It is possible to prevent oxidation of the plug 44 of the contact hole 24. Further, it is not necessary to provide a new layer for preventing oxidation, and the manufacturing process can be simplified.

  Note that the ferroelectric memory according to the present embodiment includes the above-described manufacturing method and the contents (excluding the coating layer) that can be derived from the above-described embodiment (see FIG. 8 of the above-described embodiment).

  The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

FIG. 1 is a diagram showing a method of manufacturing a ferroelectric memory according to the first embodiment of the present invention. FIG. 2 is a diagram showing a method for manufacturing a ferroelectric memory according to the first embodiment of the present invention. FIG. 3 is a diagram showing a method for manufacturing a ferroelectric memory according to the first embodiment of the present invention. FIG. 4 is a diagram showing a method for manufacturing a ferroelectric memory according to the first embodiment of the present invention. FIG. 5 is a diagram showing a method of manufacturing the ferroelectric memory according to the first embodiment of the present invention. FIG. 6 is a diagram showing a method for manufacturing a ferroelectric memory according to the first embodiment of the present invention. FIG. 7 is a diagram showing a method for manufacturing a ferroelectric memory according to the first embodiment of the present invention. FIG. 8 is a diagram showing a method for manufacturing a ferroelectric memory according to the first embodiment of the present invention. FIG. 9 is a diagram showing a method of manufacturing the ferroelectric memory according to the first embodiment of the present invention. FIG. 10 is a diagram showing a ferroelectric memory according to the first embodiment of the present invention. FIG. 11 is a diagram showing a method for manufacturing a ferroelectric memory according to the second embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Base | substrate 20 ... Insulating layer 22 ... 1st contact hole 24 ... 2nd contact hole 30, 32, 34 ... Barrier layer 40 ... 1st conductive layer 42, 44 ... Plug 50 ... 2nd conductive layer 51, 52, 53, 54 ... barrier layer 60 ... first contact portion 70 ... second contact portion 80 ... ferroelectric capacitor 81 ... laminated body 82 ... lower electrode 84 ... ferroelectric layer 86 ... upper electrode 90 ... covering layer DESCRIPTION OF SYMBOLS 100 ... 2nd insulating layer 102 ... 3rd contact hole 104 ... 3rd contact part

Claims (15)

(A) forming first and second contact holes in an insulating layer formed above the substrate;
(B) forming a plug having an upper surface lower than the upper surface of the insulating layer in each of the first and second contact holes;
(C) forming a barrier layer in a region including the upper part of each of the first and second contact holes;
(D) stacking a lower electrode, a ferroelectric layer, and an upper electrode in order to form a stacked body;
(E) forming a ferroelectric capacitor in a region including the upper part of the plug of the first contact hole by etching the stacked body;
(F) forming a coating layer in a region including the upper part of the plug of the second contact hole;
A method for manufacturing a ferroelectric memory, comprising: The method of manufacturing a ferroelectric memory according to claim 1.
In the step (c), the barrier layer is formed in a region further including the upper part of the insulating layer,
A method for manufacturing a ferroelectric memory, wherein the barrier layer is etched simultaneously with the stacked body in the step (e). The ferroelectric memory according to claim 1 or 2,
In the step (f), the covering layer is formed in a region further including the surface of the ferroelectric capacitor. In the manufacturing method of the ferroelectric memory in any one of Claims 1-3,
A method for manufacturing a ferroelectric memory, wherein, in the step (f), the coating layer is formed by a sputtering method. In the manufacturing method of the ferroelectric memory in any one of Claims 1-4,
The method for manufacturing a ferroelectric memory, wherein the covering layer is made of an inorganic insulating material. In the manufacturing method of the ferroelectric memory in any one of Claims 1-5,
A method of manufacturing a ferroelectric memory, further comprising performing an annealing process in an oxygen atmosphere after the step (f). (A) forming first and second contact holes in an insulating layer formed above the substrate;
(B) forming a plug having an upper surface lower than the upper surface of the insulating layer in each of the first and second contact holes;
(C) forming a barrier layer in a region including the upper part of each plug of the first and second contact holes and the upper part of the insulating layer;
(D) stacking a lower electrode, a ferroelectric layer, and an upper electrode in order to form a stacked body;
(E) forming a ferroelectric capacitor in a region including the upper part of the plug of the first contact hole by etching the stacked body so that the barrier layer remains;
(F) performing an annealing treatment in an oxygen atmosphere;
(G) removing a portion of the barrier layer above the insulating layer;
A method for manufacturing a ferroelectric memory, comprising: In the manufacturing method of the ferroelectric memory in any one of Claims 1-7,
Before the step (b), further comprising forming another barrier layer on the inner surface of each of the first and second contact holes;
A method of manufacturing a ferroelectric memory, wherein the plug is formed inside the other barrier layer in the step (b). In the manufacturing method of the ferroelectric memory in any one of Claims 1-8,
In the step (b),
Forming a first conductive layer inside each of the first and second contact holes and above the insulating layer;
A method of manufacturing a ferroelectric memory, wherein the plug is formed by polishing the first conductive layer until the insulating layer is exposed. The method of manufacturing a ferroelectric memory according to claim 9.
Manufacturing of a ferroelectric memory in which the upper portion of the first conductive layer inside at least one of the first and second contact holes is further removed by etching after the polishing step of the step (b). Method. In the manufacturing method of the ferroelectric memory in any one of Claims 1-10,
In the step (c),
Forming a second conductive layer inside each of the first and second contact holes and above the insulating layer;
A method of manufacturing a ferroelectric memory, wherein the barrier layer is formed by polishing the second conductive layer so that a predetermined thickness remains above the insulating layer. The method of manufacturing a ferroelectric memory according to claim 11.
A method for manufacturing a ferroelectric memory, further comprising forming an adhesion layer above the barrier layer after the polishing step of the step (c). The method of manufacturing a ferroelectric memory according to any one of claims 9 to 12,
The method for manufacturing a ferroelectric memory, wherein at least one of the polishing steps (b) and (c) includes a step by a chemical mechanical polishing method. A substrate;
A first insulating layer formed above the substrate;
A first contact hole penetrating the first insulating layer;
A second contact hole penetrating the first insulating layer;
A first contact portion formed in the first contact hole;
A second contact portion formed in the second contact hole;
A ferroelectric capacitor formed by sequentially laminating a lower electrode, a ferroelectric layer, and an upper electrode in a region including above the first contact portion;
A second insulating layer formed above the first insulating layer;
A third contact hole formed above the second contact portion and penetrating the second insulating layer;
A third contact portion formed in the third contact hole;
Including
The first contact portion includes a first plug and a first barrier layer formed above the first plug;
An upper surface of the second contact portion is formed lower than an upper surface of the first barrier layer;
The ferroelectric memory, wherein a lower surface of the third contact portion is connected to the upper surface of the second contact portion inside the second contact hole. 14. The ferroelectric memory according to claim 13, wherein
The second contact portion includes a second plug and a second barrier layer formed above the second plug,
A ferroelectric memory, wherein an upper surface of the second barrier layer is formed lower than an upper surface of the first barrier layer.

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