JP2006066658A - Manufacturing method of circuit substrate - Google Patents

Manufacturing method of circuit substrate Download PDF

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JP2006066658A
JP2006066658A JP2004247661A JP2004247661A JP2006066658A JP 2006066658 A JP2006066658 A JP 2006066658A JP 2004247661 A JP2004247661 A JP 2004247661A JP 2004247661 A JP2004247661 A JP 2004247661A JP 2006066658 A JP2006066658 A JP 2006066658A
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conductor
circuit board
manufacturing
insulating substrate
recess
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Kenji Sugimoto
健治 杉本
Michio Imayoshi
三千男 今吉
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Kyocera Corp
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Kyocera Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit substrate with a penetrating conductor formed for conduction between upper and lower surfaces of an insulating substrate and high in connective reliability. <P>SOLUTION: A recess 3 is formed by applying blast process on one main surface of the insulating substrate 1 consisting of ceramics, then, base layers 4, 5 are formed on the inner surface of the recess 3, and, subsequently, the recess 3 is filled with a conductor 7 and thereafter both of the main surfaces of insulating substrate 1 are polished whereby the conductor 7 on the bottom 3b side of the recess 3 is exposed to form the penetrating conductor. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、回路基板の製造方法に関し、さらに詳しくは上下面を導通するための貫通導体を有する回路基板および積層型の回路基板の製造方法に関する。   The present invention relates to a method for manufacturing a circuit board, and more particularly to a circuit board having a through conductor for conducting upper and lower surfaces and a method for manufacturing a multilayer circuit board.

近年の電子部品の著しい小型化、高密度実装化に伴い、電子部品がマウントされる回路基板も高性能化が望まれている。その方法としては、パターン状の回路導体を微細化してサイズを縮小する方法、或いは、回路導体を3次元的に多層化する方法等が採用されている。   Along with the recent remarkable miniaturization and high-density mounting of electronic components, circuit boards on which electronic components are mounted are also required to have high performance. As the method, a method of reducing the size by miniaturizing a patterned circuit conductor, a method of multilayering the circuit conductor three-dimensionally, or the like is adopted.

回路導体を3次元的に多層化する方法としては、絶縁基板が貫通導体によって上下面が電気的に接続された回路基板を複数積層する方法が採用され、各層間での所望の導通を確保することによって小型化、高集積化等に対応すべく回路設計が行われている。   As a method of multilayering circuit conductors three-dimensionally, a method of laminating a plurality of circuit boards in which the upper and lower surfaces are electrically connected by penetrating conductors is adopted, and desired conduction between each layer is ensured. As a result, circuit design has been performed to cope with downsizing, high integration, and the like.

このような3次元高密度配線を有する回路基板は、加工性が良好な樹脂製の基板を用いたプリント配線基板の分野では広く実用化されているが、絶縁特性や放熱特性に優れるセラミック基板(アルミナ質焼結体、窒化アルミニウム質焼結体、炭化ケイ素質焼結体等)においても需要が高まっている。このようなセラミック基板を用いた上記多層回路基板の製造方法に用いられる回路基板の製造方法としては、所謂コファイア法とポストファイア法が知られている。   A circuit board having such a three-dimensional high-density wiring is widely put into practical use in the field of printed wiring boards using a resin-made substrate having good workability, but a ceramic substrate having excellent insulation characteristics and heat dissipation characteristics ( There is also an increasing demand for alumina sintered bodies, aluminum nitride sintered bodies, silicon carbide sintered bodies, and the like. As a circuit board manufacturing method used in the multilayer circuit board manufacturing method using such a ceramic substrate, a so-called cofire method and a postfire method are known.

コファイア法とは、セラミックグリーンシート(以下、グリーンシートともいう)と呼ばれる焼結前のセラミック前駆体にスルーホールを穿孔した後にこのスルーホールに金属粉末を有機バインダー中に分散させたペースト状の物質(以下、金属ペーストともいう)を充填し、ついで脱脂,焼成する方法である。   The cofire method is a paste-like substance in which a through hole is drilled in a ceramic precursor before sintering called a ceramic green sheet (hereinafter also referred to as a green sheet), and then metal powder is dispersed in the organic binder in the through hole. (Hereinafter, also referred to as a metal paste), followed by degreasing and firing.

一方ポストファイア法とは、スルーホールが形成されたセラミック焼結体に金属ペーストを充填して再焼成する方法であり、スルーホールの形成方法としては、汎用的な方法としてグリーンシートを穿孔し、脱脂,焼成する方法、セラミック焼結体に直接ドリルを用いて加工する方法が知られている。また、特許文献1に述べられているようなレーザ法およびCuめっき法を用いたポストファイア法が考えられている。いずれの方法においても、セラミック前駆体又はセラミック基板に穿孔した後、上下面の導通のための貫通導体を形成する方法である。
特開2003−218518号公報
On the other hand, the post-fire method is a method of filling a ceramic paste in which a through hole is formed with a metal paste and refiring, and as a through hole forming method, a general-purpose method is used to drill a green sheet, A method of degreasing and firing, and a method of directly processing a ceramic sintered body using a drill are known. Further, a post-fire method using a laser method and a Cu plating method as described in Patent Document 1 is considered. In any method, after penetrating the ceramic precursor or the ceramic substrate, the through conductors for conduction on the upper and lower surfaces are formed.
JP 2003-218518 A

しかしながら、特許文献1に述べられているようなポストファイア法によれば、セラミック前駆体またはセラミック基板に穿孔し、形成されたスルーホール内壁の表面上に導体化膜を形成してスルーホールの導体化を行ない、さらにスルーホールの電気抵抗をより低くするために上記のように形成した導体化膜上に更に金属導体をめっき法等を用いて充填するが、セラミック前駆体またはセラミック基板に穿孔を施してあることから、めっき法の導体化膜上からの金属析出過程において、スルーホール内壁面のみの金属析出であり、底辺からの金属析出が行われないことから金属導体の金属析出工程に時間を要し、金属析出速度のバラツキによる充填不良(凹み,ピンホール、ボイド等)が発生する問題があった。   However, according to the post-fire method as described in Patent Document 1, the conductor of the through hole is formed by drilling the ceramic precursor or the ceramic substrate and forming a conductive film on the surface of the inner wall of the formed through hole. In order to further reduce the electrical resistance of the through-hole, the conductor film formed as described above is further filled with a metal conductor using a plating method or the like, but the ceramic precursor or the ceramic substrate is perforated. Therefore, in the process of metal deposition from the conductor film of the plating method, metal deposition is only on the inner wall surface of the through hole, and metal deposition from the bottom is not performed. There is a problem that poor filling (dents, pinholes, voids, etc.) occurs due to variations in the metal deposition rate.

本発明は、かかる従来技術の問題点に鑑み完成されたものであり、その目的は、絶縁基板の上下面導通のための貫通導体が形成された接続信頼性の高い回路基板を提供することにある。   The present invention has been completed in view of the problems of the prior art, and an object of the present invention is to provide a circuit board with high connection reliability in which through conductors for conducting the upper and lower surfaces of an insulating board are formed. is there.

本発明の回路基板の製造方法は、セラミックスから成る絶縁基板の一主面にブラスト加工を施すことにより凹部を形成し、次に前記凹部の内面に下地層を形成し、次に前記凹部を導体によって充填し、しかる後、前記絶縁基板の両主面を研磨することによって前記凹部の底面側の前記導体を露出させて貫通導体を形成することを特徴とする。   In the method of manufacturing a circuit board according to the present invention, a concave portion is formed by blasting one main surface of an insulating substrate made of ceramics, and then a base layer is formed on the inner surface of the concave portion, and then the concave portion is formed into a conductor. Then, both the main surfaces of the insulating substrate are polished to expose the conductor on the bottom surface side of the recess, thereby forming a through conductor.

本発明の回路基板の製造方法は、好ましくは、上記製造方法において、前記下地層は、チタン,クロム,アルミニウム,モリブデン,タングステン,銅およびニッケル−クロム合金のうちの少なくとも1種から成ることを特徴とする。   The method for manufacturing a circuit board according to the present invention is preferably characterized in that, in the manufacturing method, the underlayer is made of at least one of titanium, chromium, aluminum, molybdenum, tungsten, copper, and a nickel-chromium alloy. And

本発明の回路基板の製造方法は、好ましくは、上記製造方法において、前記導体は、銅,銀,およびチタンのうちの少なくとも1種から成ることを特徴とする。   The circuit board manufacturing method of the present invention is preferably characterized in that, in the above manufacturing method, the conductor is made of at least one of copper, silver, and titanium.

本発明の回路基板の製造方法は、好ましくは、上記製造方法において、前記導体は、めっき法により前記下地層上に形成されるとともに前記凹部に充填されることを特徴とする。   The method for manufacturing a circuit board according to the present invention is preferably characterized in that, in the above manufacturing method, the conductor is formed on the base layer by a plating method and is filled in the recess.

本発明の回路基板の製造方法は、好ましくは、上記製造方法において、前記絶縁基板は、両主面の研磨後の表面の算術平均粗さRaが0.3μm以下であることを特徴とする。   The method for manufacturing a circuit board according to the present invention is preferably characterized in that, in the above manufacturing method, the insulating substrate has an arithmetic average roughness Ra of the surface after polishing of both main surfaces of 0.3 μm or less.

本発明の回路基板の製造方法は、好ましくは、上記製造方法において製造された回路基板を複数積層することを特徴とする。   The circuit board manufacturing method of the present invention is preferably characterized in that a plurality of circuit boards manufactured by the above manufacturing method are stacked.

本発明の回路基板の製造方法によれば、絶縁基板は、ブラストを用いた穿孔方法を用いて絶縁基板に凹部を形成されていることにより、絶縁基板に対して、ブラストの投射材を吹き付けるため、絶縁基板の凹部が物理的に削られ、凹部内壁面の面粗さが粗く均一であることと、レーザ法のように熱が絶縁基板に加わらないことにより、絶縁基板中のガラス質の変質が無いことから、凹部内壁面とその壁面に密着する下地層との間の密着強度が高く、信頼性の高い回路基板を供給することができる。   According to the method for manufacturing a circuit board of the present invention, the insulating substrate is formed with a recess in the insulating substrate using a blasting method using blast, so that a blasting projection material is sprayed onto the insulating substrate. The insulation substrate is physically cut, the surface roughness of the inner wall of the recess is rough and uniform, and heat is not applied to the insulation substrate as in the laser method. Therefore, it is possible to supply a highly reliable circuit board having high adhesion strength between the inner wall surface of the recess and the base layer in close contact with the wall surface.

さらに本発明によれば、セラミックグリーンシートを焼成したのちにブラストにより凹部を加工するため、凹部加工時や加工後に高温での熱処理が加わることがないことから、絶縁基板の熱収縮を有効に防止することができ、微細な貫通導体が複雑に配置された基板も高精度で製造することができる。   Furthermore, according to the present invention, since the concave portion is processed by blasting after firing the ceramic green sheet, heat treatment at a high temperature is not applied at the time of processing the concave portion or after processing, thereby effectively preventing thermal contraction of the insulating substrate. In addition, a substrate on which fine through conductors are arranged in a complicated manner can be manufactured with high accuracy.

また、本発明の回路基板の製造方法によれば、下地層は、チタン,クロム,アルミニウム,モリブデン,タングステン,銅およびニッケル−クロム合金のうちの少なくとも1種から成ることにより、凹部内壁面内の下地層と導体との間で高い密着強度をえることができるため、高信頼性の回路基板を得ることができる。   According to the circuit board manufacturing method of the present invention, the underlayer is made of at least one of titanium, chromium, aluminum, molybdenum, tungsten, copper, and nickel-chromium alloy. Since high adhesion strength can be obtained between the base layer and the conductor, a highly reliable circuit board can be obtained.

また、本発明の回路基板の製造方法によれば、導体は、銅,銀,およびチタンのうちの少なくとも1種から成ることにより、絶縁基板の上下面間を熱伝導性および電気伝導性の良好な導体からなる貫通導体により電気的に接続することができ、電気抵抗が小さいとともに熱引き特性に優れた回路基板を簡便に効率よく製造することができる。   Further, according to the method for manufacturing a circuit board of the present invention, the conductor is made of at least one of copper, silver, and titanium, so that the thermal conductivity and electrical conductivity between the upper and lower surfaces of the insulating substrate are good. The circuit board can be electrically connected by a through conductor made of a simple conductor, and can easily and efficiently produce a circuit board having a low electrical resistance and an excellent heat drawing characteristic.

また、本発明の回路基板の製造方法によれば、導体は、めっき法により下地層上に形成されるとともに前記凹部に充填されることにより、その後の熱履歴がないため、熱膨張差による熱衝撃による下地層及び導体内の亀裂が発生することがなく、上下面の導通抵抗において高い信頼性を得ることができる。   In addition, according to the method for manufacturing a circuit board of the present invention, the conductor is formed on the underlayer by plating and filled in the concave portion, so that there is no subsequent thermal history. Cracks in the underlying layer and conductor due to impact do not occur, and high reliability can be obtained in the conduction resistance on the upper and lower surfaces.

また、本発明の回路基板の製造方法によれば、絶縁基板は、両主面の研磨後の表面の算術平均粗さRaが0.3μm以下であることにより、回路基板表面の平面度が向上し、フォトリソグラフィの加工精度が向上するため、回路基板表面上に高精度かつ微細な配線を形成することかできる。   In addition, according to the circuit board manufacturing method of the present invention, the flatness of the circuit board surface is improved because the insulating board has an arithmetic average roughness Ra of 0.3 μm or less of the polished surfaces of both main surfaces. In addition, since the processing accuracy of photolithography is improved, highly accurate and fine wiring can be formed on the surface of the circuit board.

また、本発明の回路基板の製造方法によれば、上記本発明の製造方法によって製造された回路基板を複数積層することにより、基板に熱収縮が無いため、基板収縮に左右されない、位置精度に優れた接続信頼性の高い多層回路基板を得ることができる。   In addition, according to the method for manufacturing a circuit board of the present invention, by laminating a plurality of circuit boards manufactured by the above-described manufacturing method of the present invention, there is no thermal shrinkage on the board, so that the position accuracy is not affected by the board shrinkage. A multilayer circuit board having excellent connection reliability can be obtained.

本発明の回路基板の製造方法を図1に基づいて詳細に説明する。   A method of manufacturing a circuit board according to the present invention will be described in detail with reference to FIG.

図1(a)〜(g)は、本発明の回路基板の製造方法の実施の形態の代表的な例を説明するための各工程毎の回路基板の断面図であり、これらの図において1は絶縁基板、2はドライフィルムレジスト(1次)、3は凹部、3aは凹部深さ、3bは凹部底面の寸法、4は第1下地層、5は第2下地層、6はドライフィルムレジスト(2次)、7は導体、8は回路基板、8aと8bは回路基板8の開口寸法を示す。 1 (a) to 1 (g) are cross-sectional views of a circuit board for each step for explaining a representative example of an embodiment of a method for manufacturing a circuit board of the present invention. Is the insulating substrate, 2 is the dry film resist (primary), 3 is the recess, 3a is the depth of the recess, 3b is the size of the bottom of the recess, 4 is the first underlayer, 5 is the second underlayer, and 6 is the dry film resist. (Secondary), 7 is a conductor, 8 is a circuit board, 8a and 8b are opening dimensions of the circuit board 8.

本発明の回路基板8の製造方法は、以下の各工程により実施される。   The manufacturing method of the circuit board 8 of the present invention is performed by the following steps.

まず、図1(a)の断面図に示すような絶縁基板1を用意する。このような絶縁基板1は、酸化アルミニウム(アルミナ:Al)質焼結体,窒化アルミニウム(AlN)質焼結体等のセラミック絶縁材料等から成り、絶縁基板1が例えば酸化アルミニウム質焼結体から成る場合、先ずアルミナ(Al)やシリカ(SiO),カルシア(CaO),マグネシア(MgO)等の原料粉末に適当な有機溶剤,溶媒を添加混合して泥漿状と成し、これを従来周知のドクターブレード法やカレンダーロール法等によりシート状に成形してセラミックグリーンシート(以下、グリーンシートともいう)を得る。その後、グリーンシートを所定形状に打ち抜き加工するとともに必要に応じて複数枚積層し、これを約1600℃の温度で焼成することにより製作される。また、その後、必要に応じて絶縁基板1の主面に研磨加工を施す場合もある。 First, an insulating substrate 1 as shown in the sectional view of FIG. Such an insulating substrate 1 is made of a ceramic insulating material such as an aluminum oxide (alumina: Al 2 O 3 ) sintered body or an aluminum nitride (AlN) sintered body. In the case of a composite, first, a suitable organic solvent or solvent is added to and mixed with raw material powders such as alumina (Al 2 O 3 ), silica (SiO 2 ), calcia (CaO), and magnesia (MgO) to form a slurry. Then, this is formed into a sheet shape by a conventionally known doctor blade method, calendar roll method or the like to obtain a ceramic green sheet (hereinafter also referred to as a green sheet). Thereafter, the green sheet is punched into a predetermined shape, and a plurality of sheets are laminated as necessary, and the green sheet is fired at a temperature of about 1600 ° C. Thereafter, the main surface of the insulating substrate 1 may be polished as necessary.

なお、絶縁基板1の材料として、特に酸化アルミニウム質焼結体や窒化アルミニウム質焼結体を用いた場合には、これらの材料の熱伝導率が40W/m・K以上と高いため、高放熱性という観点から、LD(レーザダイオード),LED(Light Emitting Diode),高速CPU(Central Processing Unit)等の発熱量の大きい各種半導体素子を搭載する配線基板に好適に使用することができる。   In particular, when an aluminum oxide sintered body or an aluminum nitride sintered body is used as the material of the insulating substrate 1, the thermal conductivity of these materials is as high as 40 W / m · K or higher, so that high heat dissipation. From the viewpoint of performance, it can be suitably used for a wiring board on which various semiconductor elements having a large calorific value such as LD (laser diode), LED (Light Emitting Diode), and high-speed CPU (Central Processing Unit) are mounted.

次に図1(b)の断面図に示すように、絶縁基板1表面にドライフィルムレジスト(1次)2を熱圧着により貼付け、従来周知のフォトリソグラフィ法により絶縁基板1の凹部3となる部分上のドライフィルムレジスト(1次)2を開口させる。   Next, as shown in the cross-sectional view of FIG. 1 (b), a dry film resist (primary) 2 is attached to the surface of the insulating substrate 1 by thermocompression bonding and becomes a recess 3 of the insulating substrate 1 by a conventionally known photolithography method. The upper dry film resist (primary) 2 is opened.

次に図1(c)の断面図に示すように、図1(b)で開口されたドライフィルムレジスト(1次)2の面から、SiC等のブラスト投射材(例えば、シナノランダム社製GP#320)を投射し、ドライフィルムレジスト(1次)2を開口させた部分の絶縁基板1を物理的に削ることにより凹部3を形成する。このとき、ブラスト条件を調整し、凹部深さ3aを管理し、凹部底面の寸法3bを保持した凹部3を形成する。この凹部深さ3aは基板厚み−0.1mm程度、すなわち凹部底部の絶縁基板1の厚みが0.1mm程度が好ましい。また、凹部3の寸法は開口部が100〜500μm、深さが300〜650μm、凹部3の開口面と凹部3の側面との間の角度が60〜80°程度がよい。これを逸脱する場合、その後の電解Cuめっきによる導体7の埋め込み工程にてスルーホールを完全に埋めるのが困難になる、もしくは、導体7内部にボイドが発生しやすくなる。   Next, as shown in the sectional view of FIG. 1C, a blast projection material such as SiC (for example, GP manufactured by Shinano Random Co., Ltd.) is formed from the surface of the dry film resist (primary) 2 opened in FIG. The concave portion 3 is formed by projecting # 320) and physically scraping the portion of the insulating substrate 1 where the dry film resist (primary) 2 is opened. At this time, the blast condition is adjusted, the recess depth 3a is managed, and the recess 3 holding the recess bottom surface dimension 3b is formed. The recess depth 3a is preferably about -0.1 mm of the substrate thickness, that is, the thickness of the insulating substrate 1 at the bottom of the recess is about 0.1 mm. Further, the dimensions of the recess 3 are preferably such that the opening is 100 to 500 μm, the depth is 300 to 650 μm, and the angle between the opening surface of the recess 3 and the side surface of the recess 3 is about 60 to 80 °. When deviating from this, it becomes difficult to completely fill the through hole in the subsequent step of filling the conductor 7 by electrolytic Cu plating, or a void is likely to be generated inside the conductor 7.

次に図1(d)の断面図に示すように、絶縁基板1上のドライフィルムレジスト(1次)2を除去した後、ブラスト法を用いて形成された凹部3の内壁面および絶縁基板1表面にスパッタリング法により例えばTiから成る下地層を積層する。本例では、例えばTiから成る第1下地層4および例えばCuから成る第2下地層5を順次成膜積層した例を示す。これらの第1下地層4および第2下地層5は、それぞれ第2下地層5との密着金属およびめっき導通膜として用いられ、第1下地層4の厚みは0.05〜0.15μmが良い。これを下回る場合は凹部3の内壁面との密着性が低下しやすくなり、上回る場合は、第1下地層4であるTi等が導体7中へ拡散し、導通抵抗にバラツキが発生しやすくなる。   Next, as shown in the sectional view of FIG. 1 (d), after removing the dry film resist (primary) 2 on the insulating substrate 1, the inner wall surface of the recess 3 and the insulating substrate 1 formed by using the blast method. An underlayer made of Ti, for example, is laminated on the surface by sputtering. This example shows an example in which a first underlayer 4 made of Ti, for example, and a second underlayer 5 made of Cu, for example, are sequentially deposited. The first underlayer 4 and the second underlayer 5 are used as an adhesion metal with the second underlayer 5 and a plating conductive film, respectively, and the thickness of the first underlayer 4 is preferably 0.05 to 0.15 μm. . If the thickness is less than this, the adhesion to the inner wall surface of the recess 3 is likely to be reduced, and if it is greater, Ti or the like as the first base layer 4 diffuses into the conductor 7 and the conduction resistance is likely to vary. .

また、第2下地層5の厚みは0.5〜1.5μm程度がよい。これを下回る場合、導体7との密着性が低下しやすくなり、上回る場合は、絶縁基板1表面の下地層の厚みが増すため、その後の研磨工程での作業性が低下しやすくなる。   The thickness of the second underlayer 5 is preferably about 0.5 to 1.5 μm. If the thickness is less than this, the adhesiveness with the conductor 7 is likely to be lowered, and if it is greater, the thickness of the underlying layer on the surface of the insulating substrate 1 is increased, and hence the workability in the subsequent polishing step is likely to be lowered.

次に図1(e)の断面図に示すように、上記絶縁基板1に第1下地層4および第2下地層5が成膜された面上にめっき用のドライフィルムレジスト(2次)6を熱圧着により貼付け、従来周知のフォトリソグラフィ法により絶縁基板1の凹部3上のドライフィルムレジスト(2次)6を開口させる。   Next, as shown in the sectional view of FIG. 1E, a dry film resist (secondary) 6 for plating is formed on the surface on which the first underlayer 4 and the second underlayer 5 are formed on the insulating substrate 1. Is attached by thermocompression bonding, and a dry film resist (secondary) 6 on the recess 3 of the insulating substrate 1 is opened by a conventionally known photolithography method.

次に図1(f)の断面図に示すように、電解めっき法により第1下地層4および第2下地層5が順次成膜された凹部3内にCuめっき等を施し、導体7を部分的に形成する。このとき、凹部3内に導体7が完全に埋まった時点でめっき終了とする。   Next, as shown in the cross-sectional view of FIG. 1 (f), Cu plating or the like is applied to the recess 3 in which the first underlayer 4 and the second underlayer 5 are sequentially formed by electrolytic plating, and the conductor 7 is partially formed. Form. At this time, the plating is finished when the conductor 7 is completely buried in the recess 3.

次に図1(g)の断面図に示すように、図1(f)で導体7を施された絶縁基板1上のドライフィルムレジスト(2次)6を除去した後、絶縁基板1上下面から研磨法を用いた研磨を行ない、回路基板8を形成する。このとき、絶縁基板1の下面側の開口寸法8aと絶縁基板1の上面側の開口径8bを管理する。その際の研磨の手順としては、まず絶縁基板1上面に凸上に盛り上がった導体7のみを粗研磨にて除去し、その後絶縁基板1下面側から研磨を行ない、凹部3に埋め込まれた導体7を絶縁基板1の下面に露出させ、その露出した導体7の開口寸法を指定された寸法になるまで研磨を行ない、更に絶縁基板1上面から指定された絶縁基板1の厚み寸法になるまで研磨を行なう。   Next, as shown in the sectional view of FIG. 1 (g), after removing the dry film resist (secondary) 6 on the insulating substrate 1 to which the conductor 7 is applied in FIG. Then, polishing using a polishing method is performed to form the circuit board 8. At this time, the opening size 8a on the lower surface side of the insulating substrate 1 and the opening diameter 8b on the upper surface side of the insulating substrate 1 are managed. As a polishing procedure at that time, first, only the conductor 7 protruding convexly on the upper surface of the insulating substrate 1 is removed by rough polishing, and then the polishing is performed from the lower surface side of the insulating substrate 1 and the conductor 7 embedded in the concave portion 3 is then removed. Is exposed to the lower surface of the insulating substrate 1, and polishing is performed until the opening size of the exposed conductor 7 reaches a specified size, and further polishing is performed from the upper surface of the insulating substrate 1 to the specified thickness of the insulating substrate 1. Do.

以上の工程により本発明の回路基板8を得ることができる。本発明の回路基板8は絶縁基板1上にドライフィルムレジスト(1次)2を熱圧着により貼付け、従来周知のフォトリソグラフィ法により絶縁基板1の凹部3となる部分上のドライフィルムレジスト(1次)2を開口させ、ブラスト投射材をドライフィルムレジスト(1次)2の開口させた面より投射することにより、凹部深さ3aを基板管理し、凹部底面の寸法3bを保持した凹部3を形成し、その内壁面に第1下地層4および第2下地層5を成膜し、さらにドライフィルムレジスト(2次)6を熱圧着により貼付け、従来周知のフォトリソグラフィ法により絶縁基板1の凹部3上のドライフィルムレジスト(2次)6を開口させ、凹部3内に電解めっき法により導体7を部分的に形成し、絶縁基板1の上下面を研磨して回路基板8を形成することから、特許文献1に述べられているようなポストファイア法に比べ、導体7が凹部底面からも析出されることから、短時間での導体7の埋め込みが可能となり、導体7析出時間のバラツキ等による充填不良(凹み,ピンホール)の発生しない回路基板8を提供することができる。   The circuit board 8 of the present invention can be obtained through the above steps. In the circuit board 8 of the present invention, a dry film resist (primary) 2 is attached to the insulating substrate 1 by thermocompression bonding, and the dry film resist (primary) on the portion that becomes the concave portion 3 of the insulating substrate 1 by a conventionally known photolithography method. ) 2 is opened, and the blast projection material is projected from the opened surface of the dry film resist (primary) 2, thereby controlling the depth 3 a of the substrate and forming the recess 3 that holds the size 3 b of the bottom of the recess. Then, the first underlayer 4 and the second underlayer 5 are formed on the inner wall surface, and further, a dry film resist (secondary) 6 is attached by thermocompression bonding, and the recess 3 of the insulating substrate 1 is formed by a conventionally well-known photolithography method. The upper dry film resist (secondary) 6 is opened, the conductor 7 is partially formed in the recess 3 by electrolytic plating, and the upper and lower surfaces of the insulating substrate 1 are polished to form the circuit board 8. Therefore, as compared with the post-fire method as described in Patent Document 1, the conductor 7 is deposited also from the bottom of the recess, so that the conductor 7 can be embedded in a short time, and the conductor 7 deposition time can be reduced. It is possible to provide a circuit board 8 that does not cause filling defects (dents, pinholes) due to variations or the like.

尚、ブラストを用いて凹部3を穿孔した場合、レーザを用いて穿孔した場合のように、レーザによる改質層(レーザ熱光源の影響によりガラス成分が焼結してできる非常にもろく、剥離しやすい層)の発生が無く、更にはアンカー効果もあり、導体7と絶縁基板1との密着強度が高くなって絶縁基板1に形成した凹部3の内壁と導体化膜との界面に隙間を発生させることのない回路基板8を提供することができる。   In addition, when the recess 3 is drilled using blasting, the modified layer by laser (as the glass component is sintered by the influence of the laser heat source is very brittle and peeled off), as in the case of drilling using laser. There is no generation of an easy layer, and there is also an anchor effect, the adhesion strength between the conductor 7 and the insulating substrate 1 is increased, and a gap is generated at the interface between the inner wall of the recess 3 formed in the insulating substrate 1 and the conductive film. It is possible to provide the circuit board 8 that is not allowed to occur.

さらには、フォトリソグラフィ法を用いたブラストによる穿孔加工のため、当該スルーホールの位置精度が極めて高く、かつ、Cuめっきによる導体7埋め込み基板のため、上下面の電気抵抗が小さい回路基板8を提供することができる。   Furthermore, because of the piercing process by blasting using the photolithography method, the circuit board 8 is provided that has extremely high positional accuracy of the through hole and has a low electrical resistance on the upper and lower surfaces because the conductor 7 is embedded in the Cu plating. can do.

以下、本発明の回路基板の製造方法の実施例について説明する。まず、厚さ500μmの酸化アルミニウム質焼結体からなる絶縁基板1の表面にドライフィルムレジスト(1次)2を貼り付け、凹部3形成用の直径300μmの開口を形成した。   Examples of the circuit board manufacturing method of the present invention will be described below. First, a dry film resist (primary) 2 was attached to the surface of an insulating substrate 1 made of an aluminum oxide sintered body having a thickness of 500 μm, and an opening having a diameter of 300 μm for forming the recess 3 was formed.

次にブラスト投射材(シナノランダム社製GP♯320)を用いたブラスト法により、絶縁基板1に深さ400μmの凹部3を形成した。   Next, a recess 3 having a depth of 400 μm was formed on the insulating substrate 1 by a blasting method using a blast projection material (GP # 320 manufactured by Shinano Random Co.).

そして、ドライフィルムレジスト(1次)2を除去した後、凹部3の内壁面および絶縁基板1の表面に厚さ0.1μmのTiから成る第1下地層4および厚さ1.0μmのCuから成る第2下地層5を順次スパッタリング法にて形成した。   Then, after removing the dry film resist (primary) 2, the inner wall surface of the recess 3 and the surface of the insulating substrate 1 are made of the first underlayer 4 made of Ti having a thickness of 0.1 μm and the Cu having a thickness of 1.0 μm. The second underlayer 5 thus formed was sequentially formed by a sputtering method.

さらに、絶縁基板1の表面の凹部3を除く部位にドライフィルムレジスト(2次)6を形成し、凹部3内にCuめっきを施し、導体7を充填した。   Furthermore, a dry film resist (secondary) 6 was formed on the surface of the insulating substrate 1 excluding the recesses 3, Cu plating was performed in the recesses 3, and the conductors 7 were filled.

次にドライフィルムレジスト(2次)6を除去した後、絶縁基板1の上下面を研磨した。このとき、絶縁基板1の表面の算術平均粗さRaを0.02μm乃至0.50μmの種々の値に設定し、その回路基板8表面に薄膜状の回路導体を形成し、回路導体の密着性、回路導体の抵抗バラツキの有無、回路基板8表面へのドライフィルムレジストの残渣の有無について評価を行った。   Next, after removing the dry film resist (secondary) 6, the upper and lower surfaces of the insulating substrate 1 were polished. At this time, the arithmetic average roughness Ra of the surface of the insulating substrate 1 is set to various values of 0.02 μm to 0.50 μm, a thin circuit conductor is formed on the surface of the circuit substrate 8, and the adhesion of the circuit conductor Then, the presence or absence of resistance variation of the circuit conductor and the presence or absence of the residue of the dry film resist on the surface of the circuit board 8 were evaluated.

各評価方法について以下に説明する。回路導体の密着性は回路基板8表面の上下面にNiCr合金およびAuを蒸着法により順次成膜し、従来周知のフォトリソグラフィ法によりパターン状の回路導体を形成した後、テープ(NITTO製、セロテープ、No.29)を回路導体上に貼り付けた後にテープを剥がすというテープピール試験を行い、回路導体が剥がれなかったものを良好(○)とし、剥がれたものを不良(×)とした。   Each evaluation method will be described below. The adhesion of the circuit conductor is such that NiCr alloy and Au are sequentially formed on the upper and lower surfaces of the circuit board 8 by vapor deposition, and a patterned circuit conductor is formed by a conventionally well-known photolithography method, followed by tape (manufactured by NITTO, cello tape , No. 29) was applied to the circuit conductor, and then the tape peel test was performed to peel off the tape. The case where the circuit conductor was not peeled off was evaluated as good (◯), and the case where the circuit conductor was peeled off was rated as poor (×).

回路導体の抵抗バラツキは、回路基板8表面上にTaをスパッタリングにより成膜し、従来周知のフォトリソグラフィ法により、回路導体の一部としての抵抗体を形成し、420℃ヒーターブロック上5分耐熱後の抵抗上昇率が10%以下のものを良品(○)とし、10%を超えるものを不良(×)とした。   As for the resistance variation of the circuit conductor, a film of Ta is formed on the surface of the circuit board 8 by sputtering, a resistor as a part of the circuit conductor is formed by a well-known photolithography method, and the heat resistance is 5 minutes on the 420 ° C. heater block. Those having a subsequent resistance increase rate of 10% or less were evaluated as non-defective (◯), and those exceeding 10% were determined as defective (×).

回路基板8表面のドライフィルムレジストの残渣は、回路基板8表面上に有機系のドライフィルムレジストを全面に塗布し、その後130℃/60分の乾燥を行った後、フェノール系の溶剤中に浸漬し、ドライフィルムレジストを除去した後、実体顕微鏡を用いた外観検査により、回路基板8表面上にドライフィルムレジスト残渣が残っていなければ良品(○)、ドライフィルムレジスト残渣が残っていれば不良(×)とした。これらの評価結果を表1に示す。

Figure 2006066658
The dry film resist residue on the surface of the circuit board 8 is applied to the entire surface of the circuit board 8 with an organic dry film resist, dried at 130 ° C. for 60 minutes, and then immersed in a phenolic solvent. Then, after removing the dry film resist, by a visual inspection using a stereomicroscope, if the dry film resist residue does not remain on the surface of the circuit board 8, it is a non-defective product (○), and if the dry film resist residue remains, it is defective ( X). These evaluation results are shown in Table 1.
Figure 2006066658

評価結果より、表面粗さ(Ra)が0.3μm以下が良好であることがわかった。   From the evaluation results, it was found that the surface roughness (Ra) was 0.3 μm or less.

なお、本発明は上記実施の形態および実施例に限定されず、本発明の要旨を逸脱しない範囲で種々の変更を行うことは何等差し支えない。   The present invention is not limited to the above-described embodiment and examples, and various modifications can be made without departing from the scope of the present invention.

本発明の回路基板の製造方法を説明するための工程ごとの回路基板の断面図である。It is sectional drawing of the circuit board for every process for demonstrating the manufacturing method of the circuit board of this invention.

符号の説明Explanation of symbols

1 :絶縁基板
3 :凹部
4,5 :下地層
7 :導体
8 :回路基板
1: Insulating substrate 3: Concave parts 4 and 5: Underlayer 7: Conductor 8: Circuit board

Claims (6)

セラミックスから成る絶縁基板の一主面にブラスト加工を施すことにより凹部を形成し、次に前記凹部の内面に下地層を形成し、次に前記凹部を導体によって充填し、しかる後、前記絶縁基板の両主面を研磨することによって前記凹部の底面側の前記導体を露出させて貫通導体を形成することを特徴とする回路基板の製造方法。 A concave surface is formed by blasting one main surface of an insulating substrate made of ceramics, then a base layer is formed on the inner surface of the concave portion, and then the concave portion is filled with a conductor, and then the insulating substrate is formed. A method of manufacturing a circuit board, comprising: forming a through conductor by polishing both main surfaces of the first and second surfaces to expose the conductor on the bottom surface side of the recess. 前記下地層は、チタン,クロム,アルミニウム,モリブデン,タングステン,銅およびニッケル−クロム合金のうちの少なくとも1種から成ることを特徴とする請求項1記載の回路基板の製造方法。 2. The method of manufacturing a circuit board according to claim 1, wherein the underlayer is made of at least one of titanium, chromium, aluminum, molybdenum, tungsten, copper, and nickel-chromium alloy. 前記導体は、銅,銀,およびチタンのうちの少なくとも1種から成ることを特徴とする請求項1または請求項2記載の回路基板の製造方法。 3. The circuit board manufacturing method according to claim 1, wherein the conductor is made of at least one of copper, silver, and titanium. 前記導体は、めっき法により前記下地層上に形成されるとともに前記凹部に充填されることを特徴とする請求項1乃至請求項3のいずれかに記載の回路基板の製造方法。 4. The method for manufacturing a circuit board according to claim 1, wherein the conductor is formed on the base layer by a plating method and is filled in the recess. 前記絶縁基板は、両主面の研磨後の表面の算術平均粗さRaが0.3μm以下であることを特徴とする請求項1乃至請求項4のいずれかに記載の回路基板の製造方法。 5. The method of manufacturing a circuit board according to claim 1, wherein the insulating substrate has an arithmetic average roughness Ra of 0.3 μm or less of the polished surfaces of both main surfaces. 請求項1乃至請求項5のいずれかに記載の製造方法によって製造された回路基板を複数積層することを特徴とする積層型の回路基板の製造方法。 A method for manufacturing a laminated circuit board, comprising stacking a plurality of circuit boards manufactured by the manufacturing method according to claim 1.
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Cited By (7)

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JP2007250679A (en) * 2006-03-14 2007-09-27 Mitsubishi Electric Corp Ceramic wiring board and manufacturing method thereof
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007250679A (en) * 2006-03-14 2007-09-27 Mitsubishi Electric Corp Ceramic wiring board and manufacturing method thereof
JP2007278734A (en) * 2006-04-03 2007-10-25 Asahi Kasei Electronics Co Ltd Magnetic sensor and its manufacturing method
JP2007278733A (en) * 2006-04-03 2007-10-25 Asahi Kasei Electronics Co Ltd Magnetic sensor and its manufacturing method
US8169215B2 (en) 2006-04-13 2012-05-01 Asahi Kasei Emd Corporation Magnetic sensor and method of manufacturing thereof
JP2008263188A (en) * 2007-04-13 2008-10-30 Samsung Electro-Mechanics Co Ltd Circuit substrate manufacturing method
JP6446155B1 (en) * 2018-07-17 2018-12-26 株式会社日立パワーソリューションズ Double-sided circuit non-oxide ceramic substrate and manufacturing method thereof
JP2020013862A (en) * 2018-07-17 2020-01-23 株式会社日立パワーソリューションズ Double-sided circuit non-oxide ceramic substrate and manufacturing method thereof
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