JP2006059924A - 発光素子用パッケージ - Google Patents
発光素子用パッケージ Download PDFInfo
- Publication number
- JP2006059924A JP2006059924A JP2004238677A JP2004238677A JP2006059924A JP 2006059924 A JP2006059924 A JP 2006059924A JP 2004238677 A JP2004238677 A JP 2004238677A JP 2004238677 A JP2004238677 A JP 2004238677A JP 2006059924 A JP2006059924 A JP 2006059924A
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- emitting element
- light
- reflecting surface
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
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- Led Device Packages (AREA)
Abstract
【解決手段】主表面に発光素子の実装領域が形成された基板本体部と、貫通孔が形成された上部基板とを備える発光素子用パッケージであり、貫通孔は、発光素子からの発光光束が放射される光取出し側開口部と、光取出し側開口部よりも開口部の面積の小さい基板本体部側開口部と、内壁面とを有し、内壁面には発光素子からの発光光束を反射する光反射面を備える。そして光反射面と主表面とのなす角が65°以上89°以下の範囲で形成されている。
【選択図】図1
Description
主表面に発光素子の実装領域が形成された基板本体部と、
貫通孔が形成された上部基板とを備え、
貫通孔は、発光素子からの発光光束が放射される光取出し側開口部と、光取出し側開口部よりも開口部の面積の小さい基板本体部側開口部と、内壁面とを有し、
内壁面には発光素子からの発光光束を反射する光反射面を備え、
上部基板は、基板本体部の実装領域が形成された面上に開口部から実装領域が露出するように積層され、
光反射面と主表面とのなす角が65°以上89°以下の範囲で形成されていることを特徴とする。望ましくは、光反射面は、主表面と71°以上80°以下の角度をなして外側へ広がって形成されている。さらに望ましくは、光反射面は、主表面と72°以上75°以下の角度をなして外側へ広がって形成されている。
3 キャビティ
4 内壁面
6 光反射面
7 メタライズ層
15 セラミック基板
17 セラミック基板本体部
18 上部基板
48 金属上部基板
Claims (1)
- 主表面に発光素子の実装領域が形成された基板本体部と、
貫通孔が形成された上部基板とを備え、
前記貫通孔は、前記発光素子からの発光光束が放射される光取出し側開口部と、光取出し側開口部よりも開口部の面積の小さい基板本体部側開口部と、内壁面とを有し、
前記内壁面には前記発光素子からの発光光束を反射する光反射面を備え、
前記上部基板は、前記基板本体部の前記実装領域が形成された面上に前記開口部から前記実装領域が露出するように積層され、
前記光反射面と前記主表面とのなす角が65°以上89°以下の範囲で形成されていることを特徴とする発光素子用パッケージ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004238677A JP2006059924A (ja) | 2004-08-18 | 2004-08-18 | 発光素子用パッケージ |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004238677A JP2006059924A (ja) | 2004-08-18 | 2004-08-18 | 発光素子用パッケージ |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006059924A true JP2006059924A (ja) | 2006-03-02 |
Family
ID=36107159
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004238677A Pending JP2006059924A (ja) | 2004-08-18 | 2004-08-18 | 発光素子用パッケージ |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2006059924A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007121973A1 (en) | 2006-04-21 | 2007-11-01 | Lexedis Lighting Gmbh | Led platform having a led chip on a membrane |
-
2004
- 2004-08-18 JP JP2004238677A patent/JP2006059924A/ja active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007121973A1 (en) | 2006-04-21 | 2007-11-01 | Lexedis Lighting Gmbh | Led platform having a led chip on a membrane |
JP2009534818A (ja) * | 2006-04-21 | 2009-09-24 | レクセディス ライティング ゲー・エム・ベー・ハー | 膜上にledチップを有するledプラットフォーム |
EP2387082A3 (en) * | 2006-04-21 | 2014-08-06 | Tridonic Jennersdorf GmbH | LED platform having a LED chip on a membrane |
US8946740B2 (en) | 2006-04-21 | 2015-02-03 | Lexedis Lighting Gmbh | LED platform with membrane |
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