JP2006054496A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2006054496A
JP2006054496A JP2005316184A JP2005316184A JP2006054496A JP 2006054496 A JP2006054496 A JP 2006054496A JP 2005316184 A JP2005316184 A JP 2005316184A JP 2005316184 A JP2005316184 A JP 2005316184A JP 2006054496 A JP2006054496 A JP 2006054496A
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conductive path
conductive
semiconductor device
back surface
insulating resin
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JP4439459B2 (en
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Noriaki Sakamoto
則明 坂本
Yoshiyuki Kobayashi
義幸 小林
Junji Sakamoto
純次 阪本
Shigeaki Mashita
茂明 真下
Katsumi Okawa
克実 大川
Eiju Maehara
栄寿 前原
Yukitsugu Takahashi
幸嗣 高橋
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of semiconductor devices equipped with semiconductor elements of printed boards, ceramic substrates, and flexible sheets etc. as increase in thickness of supporting substrates causes the increase in the size of the semiconductor device and results in the structure from which heat of the semiconductor elements built in the device cannot be easily radiated. <P>SOLUTION: After isolation grooves 14 are made in a conductive foil 60, circuit elements are mounted and insulation resin 10 is coated on the conductive foil 60 as a supporting substrate. This is reversed and the conductive foil with a supporting substrate of the insulation resin 10 is polished to isolate conductive paths 11. This method provides the semiconductor device 13 with the conductive paths 11 and semiconductor chip 12 backed by the insulation resin 10 without using a supporting substrate. Moreover, since the semiconductor chip 12 is fixed to be thermally connected to a first conductive path 11A, heat of the semiconductor chip 12 is radiated to the outside. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置およびその製造方法に関し、特に半導体チップの外側から半導体チップ裏面に配線を延在させ、半導体チップの裏面で外部接続電極が形成された半導体装置およびその製造方法に関するものである。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which wiring is extended from the outside of a semiconductor chip to the back surface of the semiconductor chip and an external connection electrode is formed on the back surface of the semiconductor chip, and a manufacturing method thereof. .

近年、ICパッケージは携帯機器や小型・高密度実装機器への採用が進み、従来のICパッケージとその実装概念が大きく変わろうとしている。詳細は、例えば下記非特許文献1で述べられている。   In recent years, IC packages are increasingly used in portable devices and small / high-density mounting devices, and conventional IC packages and their mounting concepts are about to change drastically. Details are described in, for example, Non-Patent Document 1 below.

図10は、フレキシブルシート50をインターポーザー基板として採用するもので、このフレキシブルシート50の上には、接着剤を介して銅箔パターン51が貼り合わされている。この銅箔パターン51には、ICチップ52が固着され、このICチップの周囲にボンディング用パッド53が形成されている。またこのボンディング用パッド53と一体で形成される配線を介して半田ボール接続用パッド54が形成され、この半田ボール接続用パッド54に半田ボール55が形成されている。   FIG. 10 employs a flexible sheet 50 as an interposer substrate, and a copper foil pattern 51 is bonded onto the flexible sheet 50 via an adhesive. An IC chip 52 is fixed to the copper foil pattern 51, and bonding pads 53 are formed around the IC chip. A solder ball connection pad 54 is formed through a wiring formed integrally with the bonding pad 53, and a solder ball 55 is formed on the solder ball connection pad 54.

そして半田ボール接続用パッド54の裏側は、フレキシブルシートが開口された開口部56が設けられており、この開口部56を介して半田ボール55が形成されている。そしてフレキシブルシート50を基板にして全体が絶縁性樹脂58で封止されている。
電子材料(1998年9月号22頁〜)の特集「CSP技術とそれを支える実装材料・装置」
The back side of the solder ball connecting pad 54 is provided with an opening 56 in which a flexible sheet is opened, and a solder ball 55 is formed through the opening 56. The flexible sheet 50 is used as a substrate and the whole is sealed with an insulating resin 58.
Special issue on electronic materials (September 1998, page 22) "CSP technology and mounting materials and equipment that support it"

しかしながら、全体が絶縁性樹脂58で封止されている点、ICチップ52の裏面は、フレキシブルシート50が設けられている点、および熱伝導良好な材料より成る熱伝導パスは、金属細線57、銅箔パターン51および半田ボール55から成る点により、前述したパッケージは、駆動時に十分な放熱ができない構造であった。よって、駆動時、ICチップが温度上昇し、駆動電流を十分流せない問題があった。   However, the point that the whole is sealed with the insulating resin 58, the back surface of the IC chip 52 is provided with the flexible sheet 50, and the heat conduction path made of a material with good heat conduction is the metal thin wire 57, Due to the fact that it consists of the copper foil pattern 51 and the solder balls 55, the above-described package has a structure that cannot sufficiently dissipate heat during driving. Therefore, there is a problem that the temperature of the IC chip rises at the time of driving, and the driving current cannot sufficiently flow.

また絶縁性樹脂58とICチップ52との熱膨張係数の差によって、絶縁性樹脂の溶融温度(または硬化温度)から常温に冷却するまでの温度差により絶縁性樹脂58に収縮力が働く。このような収縮力により、常温まで冷却すると、パッケージ端部が持ち上がり、外形寸法に変化をもたらし、パッケージの水平が維持できなくなり、実装基板に実装する際に予期せぬトラブルが発生する問題もあった。   Further, due to the difference in thermal expansion coefficient between the insulating resin 58 and the IC chip 52, a contraction force acts on the insulating resin 58 due to a temperature difference from the melting temperature (or curing temperature) of the insulating resin to cooling to room temperature. When cooled to room temperature due to such shrinkage force, the edge of the package is lifted, the external dimensions are changed, the level of the package cannot be maintained, and there is a problem that unexpected trouble occurs when mounting on the mounting board. It was.

本発明の半導体装置は、導電路と、前記導電路に電気的に接続された回路素子と、少なくとも前記導電路の裏面が外部に露出した状態で、前記導電路および前記回路素子を封止する絶縁性樹脂とを具備し、前記導電路の裏面は、前記絶縁性樹脂よりも外部に突出することを特徴とする。   The semiconductor device of the present invention seals the conductive path and the circuit element with a conductive path, a circuit element electrically connected to the conductive path, and at least a back surface of the conductive path exposed to the outside. An insulating resin, and the back surface of the conductive path protrudes outside the insulating resin.

更に本発明の半導体装置は、半導体素子と、金属細線を介して前記半導体素子と電気的に接続されたボンディングパッドと、少なくとも前記ボンディングパッドの裏面が外部に露出した状態で、前記ボンディングパッドおよび前記回路素子を封止する絶縁性樹脂とを具備し、前記ボンディングパッドの裏面は、前記絶縁性樹脂よりも外部に突出することを特徴とする。   Furthermore, the semiconductor device according to the present invention includes a semiconductor element, a bonding pad electrically connected to the semiconductor element through a thin metal wire, and at least a back surface of the bonding pad exposed to the outside. And an insulating resin that seals the circuit element, and the back surface of the bonding pad protrudes more outward than the insulating resin.

本発明の半導体装置の製造方法は、表面に分離溝が形成されることで、導電路が凸状に形成された導電箔を用意する工程と、前記導電路に回路素子を電気的に接続する工程と、前記回路素子が被覆されて前記分離溝に充填されるように絶縁性樹脂を形成する工程と、前記分離溝に対応する前記導電箔の裏面を選択的に除去することで、前記導電路の裏面が前記絶縁性樹脂よりも外部に突出した状態で、前記導電路同士を分離させる工程とを具備することを特徴とする。   The method for manufacturing a semiconductor device according to the present invention includes a step of preparing a conductive foil having a conductive path formed in a convex shape by forming a separation groove on the surface, and electrically connecting a circuit element to the conductive path. A step of forming an insulating resin so that the circuit element is covered and filled in the separation groove, and the back surface of the conductive foil corresponding to the separation groove is selectively removed, And a step of separating the conductive paths from each other in a state in which a back surface of the path protrudes to the outside from the insulating resin.

以上の説明から明らかなように、本発明では、前記第1の導電路11Aは、熱伝導性の優れた材料により構成されてあるため、そのサイズは、半導体チップよりも小さくて良い。従って第1の導電路と第2の導電路との間には、空きスペースが発生する。従ってこの空きスペースに、第2の導電路よりもサイズの大きな第3の導電路を配置することができる。   As is apparent from the above description, in the present invention, since the first conductive path 11A is made of a material having excellent thermal conductivity, the size thereof may be smaller than that of the semiconductor chip. Accordingly, an empty space is generated between the first conductive path and the second conductive path. Therefore, the third conductive path having a size larger than that of the second conductive path can be arranged in this empty space.

またリング状に配置された第2の導電路に囲まれて第3の導電路が配置されているため、実装基板と実装基板に固着された半導体装置との熱膨張係数の違いにより、接続部分に応力が働いても、実装基板側に形成された電極と第3の導電路との固着部分には前記応力が働きずらい構成となっている。   Further, since the third conductive path is arranged surrounded by the second conductive path arranged in a ring shape, the connection portion is caused by the difference in thermal expansion coefficient between the mounting substrate and the semiconductor device fixed to the mounting substrate. Even if a stress is applied, the stress is difficult to act on the fixed portion between the electrode formed on the mounting substrate side and the third conductive path.

また分離溝で電気的に分離された複数の導電路と、所望の該導電路上に固着された半導体チップと、該半導体チップを被覆し且つ前記導電路間の前記分離溝に充填され前記導電路の裏面のみを露出して一体に支持する絶縁性樹脂とを備えたことにより、導電路および絶縁性樹脂の必要最小限で構成され、資源に無駄のない回路装置となる。よって完成するまで余分な構成要素が無く、コストを大幅に低減できる回路装置を実現できる。また絶縁性樹脂の被覆膜厚、導電箔の厚みを最適値にすることにより、非常に小型化、薄型化および軽量化された回路装置を実現できる。   A plurality of conductive paths electrically separated by the separation grooves; a semiconductor chip fixed on the desired conductive path; and the conductive paths that cover the semiconductor chip and are filled in the separation grooves between the conductive paths. By providing an insulating resin that exposes only the back surface of the substrate and supports it integrally, a circuit device that is configured with the minimum necessary conductive paths and insulating resin and that does not waste resources. Therefore, it is possible to realize a circuit device in which there are no extra components until completion and the cost can be significantly reduced. Further, by optimizing the coating thickness of the insulating resin and the thickness of the conductive foil, it is possible to realize a circuit device that is extremely reduced in size, thickness, and weight.

また導電路の裏面のみを絶縁性樹脂から露出しているため、導電路の裏面が直ちに外部との接続に供することができ、図10の如き従来構造の支持基板を不要にできる利点を有する。   Further, since only the back surface of the conductive path is exposed from the insulating resin, the back surface of the conductive path can be immediately used for connection to the outside, and there is an advantage that a support substrate having a conventional structure as shown in FIG. 10 can be dispensed with.

しかも半導体チップが直接導電路と固着され、しかもこの導電路の裏面が露出されてため、回路素子から発生する熱を導電路を介して直接実装基板に熱を伝えることができる。特にこの放熱により、半導体チップの駆動能力を向上させることができる。   In addition, since the semiconductor chip is directly fixed to the conductive path and the back surface of the conductive path is exposed, heat generated from the circuit element can be directly transferred to the mounting substrate via the conductive path. In particular, this heat dissipation can improve the driving capability of the semiconductor chip.

また本半導体装置に於いて、分離溝の表面と導電路の表面は、実質一致している平坦な表面を有する構造となる場合、半導体装置自身をそのまま水平に移動できるので、リードずれの修正が極めて容易となる。   In addition, in this semiconductor device, when the surface of the separation groove and the surface of the conductive path have a flat surface that is substantially coincident, the semiconductor device itself can be moved horizontally as it is, so that the correction of lead misalignment is possible. It becomes extremely easy.

また導電路の側面に湾曲構造を形成した場合、アンカー効果を発生させることができ、導電路の反り、抜けを防止することができる。   In addition, when a curved structure is formed on the side surface of the conductive path, an anchor effect can be generated, and warping and disconnection of the conductive path can be prevented.

半導体装置を説明する第1の実施の形態
まず本発明の半導体装置について図1を参照しながらその構造について説明する。尚、図1Aは、半導体装置の平面図であり、図1Bは、A−A線の断面図である。
First Embodiment Explaining Semiconductor Device First, the structure of a semiconductor device of the present invention will be described with reference to FIG. 1A is a plan view of the semiconductor device, and FIG. 1B is a cross-sectional view taken along line AA.

図1には、絶縁性樹脂10に埋め込まれた導電路11A〜11Dを有し、前記第1の導電路11Aは、ダイパッドとなり、この上には半導体チップ12が固着され、前記絶縁性樹脂10で導電路11A〜11Dを支持して成る半導体装置13が示されている。また前記導電路11A〜11Dの側面は湾曲構造を有しても良い。詳細は、図4を参照。   In FIG. 1, conductive paths 11 </ b> A to 11 </ b> D embedded in an insulating resin 10 are provided, and the first conductive path 11 </ b> A serves as a die pad, on which a semiconductor chip 12 is fixed, and the insulating resin 10. A semiconductor device 13 configured to support the conductive paths 11A to 11D is shown. The side surfaces of the conductive paths 11A to 11D may have a curved structure. See FIG. 4 for details.

本構造は、半導体チップ12、複数の導電路11A〜11Dと、この導電路11A〜11Dを埋め込む絶縁性樹脂10の3つの材料で構成され、導電路11A〜11D間には、この絶縁性樹脂10で充填された分離溝14が設けられる。そして絶縁性樹脂10により前記導電路11A〜11Dが支持されている。   This structure is composed of three materials of a semiconductor chip 12, a plurality of conductive paths 11A to 11D, and an insulating resin 10 that embeds the conductive paths 11A to 11D, and the insulating resin is interposed between the conductive paths 11A to 11D. A separation groove 14 filled with 10 is provided. The conductive paths 11A to 11D are supported by the insulating resin 10.

絶縁性樹脂としては、エポキシ樹脂等の熱硬化性樹脂、ポリイミド樹脂、ポリフェニレンサルファイド等の熱可塑性樹脂を用いることができる。また絶縁性樹脂は、金型を用いて固める樹脂、ディップ、塗布をして被覆できる樹脂であれば、全ての樹脂が採用できる。また導電路11A〜11Dとしては、Cuを主材料とした導電箔、Alを主材料とした導電箔、またはFe−Ni等の合金から成る導電箔等を用いることができる。もちろん、他の導電材料でも可能であり、特にエッチングできる導電材、レーザで蒸発する導電材が好ましい。   As the insulating resin, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin or polyphenylene sulfide can be used. As the insulating resin, any resin can be adopted as long as it is a resin that can be hardened using a mold, a resin that can be coated by dipping or coating. As the conductive paths 11A to 11D, a conductive foil mainly made of Cu, a conductive foil mainly made of Al, or a conductive foil made of an alloy such as Fe-Ni can be used. Of course, other conductive materials are possible, and a conductive material that can be etched and a conductive material that evaporates with a laser are particularly preferable.

本発明では、絶縁性樹脂10が前記分離溝14にも充填され、絶縁性樹脂10で前記導電路11A〜11Dが支持されているために、導電路11A〜11Dの抜けが防止できる特徴を有する。またエッチングとしてドライエッチング、あるいはウェットエッチングを採用して非異方性的なエッチングを施すことにより、図4に示すように、導電路11の側面を湾曲構造15とし、アンカー効果を発生させることもできる。その結果、導電路11A〜11Dが絶縁性樹脂10から抜けない構造を実現できる。   In the present invention, since the insulating resin 10 is also filled in the separation groove 14 and the conductive paths 11A to 11D are supported by the insulating resin 10, the conductive paths 11A to 11D can be prevented from coming off. . Further, by applying dry etching or wet etching as etching, non-anisotropic etching is performed, so that the side surface of the conductive path 11 has a curved structure 15 and an anchor effect can be generated as shown in FIG. it can. As a result, it is possible to realize a structure in which the conductive paths 11 </ b> A to 11 </ b> D do not come off from the insulating resin 10.

しかも第1の導電路11Aは、絶縁性樹脂10から成るパッケージの裏面に露出し、半導体チップ12の裏面と直接ロウ材等により固着されている。例えば、第1の導電路11Aを実装基板上の電極と固着すると、半導体チップ12から発生する熱は、第1の導電路11Aを介して外部に放熱でき、半導体チップ12の温度上昇を防止でき、その分半導体チップ12の駆動電流を増大させることができる。   Moreover, the first conductive path 11A is exposed on the back surface of the package made of the insulating resin 10, and is directly fixed to the back surface of the semiconductor chip 12 with a brazing material or the like. For example, when the first conductive path 11A is fixed to the electrode on the mounting substrate, the heat generated from the semiconductor chip 12 can be radiated to the outside through the first conductive path 11A, and the temperature rise of the semiconductor chip 12 can be prevented. Accordingly, the drive current of the semiconductor chip 12 can be increased accordingly.

また半導体チップ12の接続手段は、金属細線16、半田等のロウ材17(またはAgペースト等の導電ペースト、導電被膜または異方性導電性樹脂等)である。   The connecting means of the semiconductor chip 12 is a metal thin wire 16 and a brazing material 17 such as solder (or a conductive paste such as an Ag paste, a conductive film or an anisotropic conductive resin).

また半導体チップ12と導電路11Aとの固着は、電気的接続が不要であれば、熱伝導を助けるフィラーが混入された絶縁性接着剤が選択される。   In addition, when the electrical connection is not required for fixing the semiconductor chip 12 and the conductive path 11A, an insulating adhesive mixed with a filler that helps heat conduction is selected.

本半導体装置は、導電路11を封止樹脂である絶縁性樹脂10で支持しているため、支持基板が不要となり、導電路11、半導体チップ12および絶縁性樹脂10で構成される。この構成は、本発明の特徴である。従来の技術の欄でも説明したように、従来の半導体装置の導電路は、支持基板(フレキシブルシート、プリント基板またはセラミック基板)で支持されていたり、リードフレームで支持されているため、本来不要にしても良い構成が付加されている。しかし、本回路装置は、必要最小限の構成要素で構成され、支持基板を不要としているため、薄型で安価となる特徴を有する。   In this semiconductor device, since the conductive path 11 is supported by the insulating resin 10 that is a sealing resin, a support substrate is not necessary, and the conductive path 11, the semiconductor chip 12, and the insulating resin 10 are included. This configuration is a feature of the present invention. As described in the section of the prior art, the conductive path of a conventional semiconductor device is supported by a support substrate (flexible sheet, printed circuit board or ceramic substrate) or supported by a lead frame. The structure which may be sufficient is added. However, since this circuit device is composed of the minimum necessary components and does not require a support substrate, it is characterized by being thin and inexpensive.

また半導体チップ12のボンディング電極18が、金属細線16の一端と接続されるため、金属細線16の他端と接続される第2の導電路11Bは、半導体チップ12の周辺に配置される。半導体チップは、複数の回路に対応できるようにボンディングパッドが用意されており、ボンディング電極18は、半導体装置13を使って構成される回路Aに必要な入出力電極、半導体装置13を使って構成される回路Bに必要な入出力電極、半導体チップ評価用のテスト電極等に分類される。   In addition, since the bonding electrode 18 of the semiconductor chip 12 is connected to one end of the fine metal wire 16, the second conductive path 11 </ b> B connected to the other end of the fine metal wire 16 is arranged around the semiconductor chip 12. The semiconductor chip is provided with bonding pads so as to be compatible with a plurality of circuits, and the bonding electrode 18 is configured by using the semiconductor device 13, input / output electrodes necessary for the circuit A configured using the semiconductor device 13. Are classified into input / output electrodes necessary for the circuit B, test electrodes for semiconductor chip evaluation, and the like.

本発明では、前記回路Aを構成する半導体装置13としてパッケージされているため、必要とされる入出力電極、テスト電極が金属細線16を介して第2の導電路11Bと接続されている。そして前記テスト電極と接続される第2の導電路11Bは、フローバー等で当接して測定されるためにそのサイズは小さくて良い。しかし入出力電極と電気的に接続される第2の導電路11Bは、電流容量等の問題からそのサイズを大きくする必要がある。そのため、この入出力電極と電気的に接続される第2の導電路11Bは、配線11Dを介して半導体チップ12の裏面に延在され、半導体チップ12の周囲と第1の導電路11Aとの間の空きスペースに第3の導電路11Cが電気的に接続されて配置される。   In the present invention, since it is packaged as the semiconductor device 13 constituting the circuit A, necessary input / output electrodes and test electrodes are connected to the second conductive path 11B through the fine metal wires 16. Since the second conductive path 11B connected to the test electrode is measured by contact with a flow bar or the like, the size may be small. However, it is necessary to increase the size of the second conductive path 11B electrically connected to the input / output electrodes because of problems such as current capacity. Therefore, the second conductive path 11B electrically connected to this input / output electrode extends to the back surface of the semiconductor chip 12 via the wiring 11D, and the periphery of the semiconductor chip 12 and the first conductive path 11A are connected to each other. The third conductive path 11C is electrically connected to the space between them.

前記第1の導電路11Aは、熱伝導性の優れたCu等により構成されているため、そのサイズは、半導体チップ12よりも小さくて良い。従って第1の導電路11Aと第2の導電路11Bとの間には、空きスペースが発生する。従ってこの空きスペースに、第2の導電路11Bよりもサイズの大きな第3の導電路11Cを配置することができる。   Since the first conductive path 11A is made of Cu or the like having excellent thermal conductivity, the size thereof may be smaller than that of the semiconductor chip 12. Accordingly, an empty space is generated between the first conductive path 11A and the second conductive path 11B. Accordingly, the third conductive path 11C having a size larger than that of the second conductive path 11B can be disposed in this empty space.

またリング状に配置された第2の導電路11Bの中に第3の導電路11Cが配置されていた。実装基板に本半導体装置13を固着した場合、以下のメリットが発生する。つまり実装基板と半導体装置13との熱膨張係数の違いにより、接続部分に応力が働いても、実装基板側に形成された電極と第2の導電路11Bがロウ材により固着されるため、実装基板側に形成された電極と第3の導電路11Cとの固着部分には前記応力が働きずらい構成となっている。   Further, the third conductive path 11C is arranged in the second conductive path 11B arranged in a ring shape. When the semiconductor device 13 is fixed to the mounting board, the following merits occur. In other words, due to the difference in thermal expansion coefficient between the mounting substrate and the semiconductor device 13, even if stress is applied to the connection portion, the electrode formed on the mounting substrate side and the second conductive path 11B are fixed by the brazing material. The stress is hard to act on the fixed portion between the electrode formed on the substrate side and the third conductive path 11C.

また、分離溝14の表面と導電路11の表面は、実質一致させることも、導電路11を飛び出させることも可能な構造となっている。裏面電極11A〜11Dと絶縁性樹脂に段差が設けられないと、半導体装置13をそのまま水平に移動できる特徴を有する。つまりロウ材による固着を実装基板上で実現する場合、溶融したロウ材の表面張力により実装基板上で前記半導体装置13が自らセルフアライメントする。また裏面電極11A〜11Dを絶縁性樹脂から飛び出させると、ロウ材の飛散、フラックスの飛散があっても、配線は、実装基板上の導電路と短絡しない構造となる。   Further, the surface of the separation groove 14 and the surface of the conductive path 11 can be substantially matched or the conductive path 11 can be protruded. If there is no step between the back electrodes 11A to 11D and the insulating resin, the semiconductor device 13 can be moved horizontally as it is. In other words, when the fixation by the brazing material is realized on the mounting substrate, the semiconductor device 13 self-aligns itself on the mounting substrate by the surface tension of the molten brazing material. Further, when the back electrodes 11A to 11D are protruded from the insulating resin, the wiring does not short-circuit with the conductive path on the mounting substrate even if the brazing material and the flux are scattered.

図10において、絶縁性樹脂58として熱硬化性樹脂または熱可塑性樹脂を用いた金型モールドによって封止成形され場合がある。この工程は絶縁性樹脂58を硬化するための熱処理を伴い、このモールド時の線膨張係数が30ppm/℃にも達する。その為、ICチップ52のシリコンの線膨張係数(3ppm/℃)との差によって、前記処理温度から常温に冷却するまでの温度差により絶縁性樹脂58に収縮力が働く。   In FIG. 10, there are cases where sealing molding is performed by a mold mold using a thermosetting resin or a thermoplastic resin as the insulating resin 58. This process involves a heat treatment for curing the insulating resin 58, and the linear expansion coefficient at the time of molding reaches 30 ppm / ° C. Therefore, due to the difference from the silicon linear expansion coefficient (3 ppm / ° C.) of the IC chip 52, the contraction force acts on the insulating resin 58 due to the temperature difference from the processing temperature to cooling to room temperature.

このような収縮力により、絶縁性樹脂58を成形後、常温まで冷却すると、半導体装置の端部が持ち上がり、外形寸法に変化(反り)をもたらす問題が発生した。   Due to such shrinkage force, when the insulating resin 58 is molded and then cooled to room temperature, the end of the semiconductor device is lifted, causing a problem in that the outer dimensions are changed (warped).

本発明は、導電路11A〜11Dを支持する支持基板を採用しない点、更には導電路11A〜11Dが個別分離され、導電路11A〜11Dの間に絶縁性樹脂10が配置されている点から、半導体装置13の裏面に位置する所の熱膨張係数を絶縁性樹脂の熱膨張係数に近づけることができ、その反りを抑制することができる。   The present invention does not employ a support substrate that supports the conductive paths 11A to 11D, and further separates the conductive paths 11A to 11D and disposes the insulating resin 10 between the conductive paths 11A to 11D. The coefficient of thermal expansion located on the back surface of the semiconductor device 13 can be brought close to the coefficient of thermal expansion of the insulating resin, and the warpage can be suppressed.

回路装置の製造方法を説明する第2の実施の形態
次に図2〜図9を使って半導体装置13の製造方法について説明する。
Second Embodiment Explaining Method of Manufacturing Circuit Device Next, a method of manufacturing the semiconductor device 13 will be described with reference to FIGS.

まず図2の如く、シート状の導電箔60を用意する。この導電箔60は、ロウ材の付着性、ボンディング性、メッキ性が考慮されてその材料が選択され、材料としては、Cuを主材料とした導電箔、Alを主材料とした導電箔またはFe−Ni等の合金から成る導電箔等が採用される。   First, as shown in FIG. 2, a sheet-like conductive foil 60 is prepared. The conductive foil 60 is selected in consideration of the adhesiveness, bonding property, and plating property of the brazing material. As the material, a conductive foil mainly composed of Cu, a conductive foil mainly composed of Al, or Fe is used. A conductive foil made of an alloy such as Ni is employed.

導電箔の厚さは、後のエッチングを考慮すると10μm〜300μm程度が好ましく、ここでは70μm(2オンス)の銅箔を採用した。しかし300μm以上でも10μm以下でも基本的には良い。後述するように、導電箔60の厚みよりも浅い分離溝61が形成できればよい。   The thickness of the conductive foil is preferably about 10 μm to 300 μm in consideration of the later etching, and here, a copper foil of 70 μm (2 ounces) is employed. However, it is basically good if it is 300 μm or more and 10 μm or less. As will be described later, it is only necessary that the separation groove 61 shallower than the thickness of the conductive foil 60 can be formed.

尚、シート状の導電箔60は、所定の幅でロール状に巻かれて用意され、これが後述する各工程に搬送されても良いし、所定の大きさにカットされた導電箔が用意され、後述する各工程に搬送されても良い。   In addition, the sheet-like conductive foil 60 is prepared by being wound in a roll shape with a predetermined width, and this may be conveyed to each step described later, or a conductive foil cut into a predetermined size is prepared, You may convey to each process mentioned later.

続いて、少なくとも導電路11A〜11Dとなる領域を除いた導電箔60を、導電箔60の厚みよりも薄く除去する工程がある。そしてこの除去工程により形成された導電路11A〜11Dに半導体チップ12を実装し、分離溝61および導電箔60に絶縁性樹脂10を被覆する工程がある。   Subsequently, there is a step of removing the conductive foil 60 excluding the region that becomes at least the conductive paths 11 </ b> A to 11 </ b> D thinner than the thickness of the conductive foil 60. Then, there is a step of mounting the semiconductor chip 12 on the conductive paths 11 </ b> A to 11 </ b> D formed by this removing step, and covering the insulating groove 10 and the conductive foil 60 with the insulating resin 10.

まず、図3の如く、Cuより成る導電箔60の上に、ホトレジストPR(耐エッチングマスク)を形成し、導電路11A〜11Dとなる領域を除いた導電箔60が露出するようにホトレジストPRをパターニングする。そして、前記ホトレジストPRを介してエッチングしている。   First, as shown in FIG. 3, a photoresist PR (etching resistant mask) is formed on a conductive foil 60 made of Cu, and the photoresist PR is exposed so that the conductive foil 60 excluding the regions to be the conductive paths 11A to 11D is exposed. Pattern. Etching is performed through the photoresist PR.

図3では、分離溝61は、ストレートで形成されているが、本製造方法ではウェットエッチングまたはドライエッチングで、非異方性的にエッチングされ、その側面は、粗面となり、しかも図4に示すように湾曲となる特徴を有する。しかし異方性エッチング、レーザによる金属蒸発を採用するならば、図3の様に分離溝61の側壁はストレートに形成される。尚、エッチングにより形成された分離溝61の深さは、約50μmである。   In FIG. 3, the separation groove 61 is formed straight, but in this manufacturing method, it is etched non-anisotropically by wet etching or dry etching, and its side surface becomes a rough surface, and as shown in FIG. Thus, it has a characteristic of being curved. However, if anisotropic etching or laser metal evaporation is employed, the side wall of the separation groove 61 is formed straight as shown in FIG. The depth of the separation groove 61 formed by etching is about 50 μm.

ウェットエッチングの場合、エッチャントは、塩化第二鉄または塩化第二銅が採用され、前記導電箔は、このエッチャントの中にディッピングされるか、このエッチャントがシャワーリングされる。   In the case of wet etching, ferric chloride or cupric chloride is used as the etchant, and the conductive foil is dipped in the etchant or showered.

特に図4の如く、エッチングマスクとなるホトレジストPRの直下は、横方向のエッチングが進みづらく、それより深い部分が横方向にエッチングされる。図のように分離溝61の側面のある位置から上方に向かうにつれて、その位置に対応する開口部の開口径が小さくなるので、逆テーパー構造となり、アンカー構造を有する構造となる。またシャワーリングを採用することで、深さ方向に向かいエッチングが進み、横方向のエッチングは抑制されるため、このアンカー構造が顕著に現れる。   In particular, as shown in FIG. 4, the etching directly in the lateral direction is difficult to proceed immediately below the photoresist PR serving as an etching mask, and a deeper portion is etched in the lateral direction. As shown in the figure, the opening diameter of the opening corresponding to the position decreases from the position where the side surface of the separation groove 61 is located upward, so that a reverse taper structure is formed and an anchor structure is obtained. Further, by adopting a shower ring, etching proceeds in the depth direction and lateral etching is suppressed, so that this anchor structure appears remarkably.

またドライエッチングの場合は、異方性、非異方性でエッチングが可能である。現在では、Cuを反応性イオンエッチングで取り除くことは不可能といわれているが、スパッタリングで除去できる。またスパッタリングの条件によって異方性、非異方性でエッチングできる。   In the case of dry etching, etching can be performed anisotropically or non-anisotropically. At present, it is said that Cu cannot be removed by reactive ion etching, but it can be removed by sputtering. Etching can be anisotropic or non-anisotropic depending on sputtering conditions.

尚、図3、図4に於いて、ホトレジストPRの代わりにエッチング液に対して耐食性のある導電被膜を選択的に被覆しても良い。導電路と成る部分に選択的に被着すれば、この導電被膜がエッチング保護膜となり、レジストを採用することなく分離溝をエッチングできる。この導電被膜として考えられる材料は、Ag、Au、PtまたはPd等である。しかもこれら耐食性の導電被膜は、ダイパッド、ボンディングパッドとしてそのまま活用できる特徴を有する。   In FIGS. 3 and 4, instead of the photoresist PR, a conductive film resistant to the etching solution may be selectively coated. If the conductive film is selectively deposited on the conductive path, this conductive film becomes an etching protective film, and the separation groove can be etched without employing a resist. Possible materials for the conductive film are Ag, Au, Pt, Pd, and the like. In addition, these corrosion-resistant conductive films have the feature that they can be used as they are as die pads and bonding pads.

例えばAg被膜は、Auと接着するし、ロウ材とも接着する。よってチップ裏面にAu被膜が被覆されていれば、そのまま導電路51上のAg被膜にチップを熱圧着でき、また半田等のロウ材を介してチップを固着できる。またAgの導電被膜にはAu細線が接着できるため、ワイヤーボンディングも可能となる。従ってこれらの導電被膜をそのままダイパッド、ボンディングパッドとして活用できるメリットを有する。   For example, the Ag coating adheres to Au and also to the brazing material. Therefore, if the Au coating is coated on the back surface of the chip, the chip can be thermocompression bonded to the Ag coating on the conductive path 51 as it is, and the chip can be fixed via a brazing material such as solder. Further, since an Au fine wire can be adhered to the Ag conductive film, wire bonding is also possible. Accordingly, there is an advantage that these conductive films can be used as they are as die pads and bonding pads.

続いて、図5の如く、分離溝61が形成された導電箔60に半導体チップ12を電気的に接続して実装する工程がある。   Subsequently, as shown in FIG. 5, there is a process of electrically connecting the semiconductor chip 12 to the conductive foil 60 in which the separation groove 61 is formed and mounting it.

半導体チップ12としては、トランジスタ、ダイオード、ICチップ等の半導体素子である。   The semiconductor chip 12 is a semiconductor element such as a transistor, a diode, or an IC chip.

ここでは、ベアのICチップ12がハーフエッチングにより形成された第1の導電路11Aにダイボンディングされ、ICチップのボンディング電極と第2の導電路11Bが熱圧着によるボールボンディングあるいは超音波によるウェッヂボンデイング等で固着される接続手段(例えば金属細線)16を介して接続される。   Here, the bare IC chip 12 is die-bonded to the first conductive path 11A formed by half etching, and the bonding electrode of the IC chip and the second conductive path 11B are ball bonded by thermocompression bonding or wedge bonding by ultrasonic waves. It connects via the connection means (for example, metal fine wire) 16 fixed by the above.

尚、半導体チップ12の裏面と配線11D、半導体チップ12の裏面と第3の導電路11Cとの短絡を防止するために、絶縁材料19が形成されている。ここで絶縁材料19として、絶縁性樹脂が半導体チップ12または導電箔60に形成され、第1の導電路11Aに対応する部分が取り除かれて形成されている。   An insulating material 19 is formed in order to prevent a short circuit between the back surface of the semiconductor chip 12 and the wiring 11D and between the back surface of the semiconductor chip 12 and the third conductive path 11C. Here, as the insulating material 19, an insulating resin is formed on the semiconductor chip 12 or the conductive foil 60, and a portion corresponding to the first conductive path 11A is removed.

更に、図6に示すように、前記導電箔60および分離溝61に絶縁性樹脂10を付着する工程がある。これは、トランスファーモールド、インジェクションモールド、またはディッピングにより実現できる。樹脂材料としては、エポキシ樹脂等の熱硬化性樹脂がトランスファーモールドで実現でき、ポリイミド樹脂、ポリフェニレンサルファイド等の熱可塑性樹脂はインジェクションモールドで実現できる。   Further, as shown in FIG. 6, there is a step of attaching the insulating resin 10 to the conductive foil 60 and the separation groove 61. This can be realized by transfer molding, injection molding, or dipping. As the resin material, a thermosetting resin such as an epoxy resin can be realized by transfer molding, and a thermoplastic resin such as polyimide resin or polyphenylene sulfide can be realized by injection molding.

本実施の形態では、導電箔60表面に被覆された絶縁性樹脂10の厚さは、接続手段16の頂部から上に約100μmが被覆されるように調整されている。この厚みは、回路装置の強度を考慮して厚くすることも、薄くすることも可能である。   In the present embodiment, the thickness of the insulating resin 10 coated on the surface of the conductive foil 60 is adjusted so that about 100 μm is coated from the top of the connecting means 16. This thickness can be increased or decreased in consideration of the strength of the circuit device.

本工程の特徴は、絶縁性樹脂10を被覆するまでは、導電路11となる導電箔60が支持基板となることである。従来では、図10の様に、本来必要としない支持基板50を採用して導電路51を形成しているが、本発明では、支持基板となる導電箔60は、電極材料として必要な材料である。そのため、構成材料を極力省いて作業できるメリットを有し、コストの低下も実現できる。   The feature of this step is that the conductive foil 60 that becomes the conductive path 11 becomes the support substrate until the insulating resin 10 is coated. Conventionally, as shown in FIG. 10, the conductive path 51 is formed by using a support substrate 50 that is not originally required. However, in the present invention, the conductive foil 60 that is a support substrate is a material necessary as an electrode material. is there. Therefore, there is a merit that the work can be performed with the constituent materials omitted as much as possible, and the cost can be reduced.

また分離溝61は、導電箔の厚みよりも浅く形成されているため、導電箔60が導電路11A〜11Dとして個々に分離されていない。従ってシート状の導電箔60として一体で取り扱え、絶縁性樹脂10をモールドする際、金型への搬送、金型への実装の作業が非常に楽になる特徴を有する。   Moreover, since the separation groove 61 is formed shallower than the thickness of the conductive foil, the conductive foil 60 is not individually separated as the conductive paths 11A to 11D. Therefore, the sheet-like conductive foil 60 can be handled as a single unit, and when the insulating resin 10 is molded, it has a feature that the work of transporting to the mold and mounting to the mold becomes very easy.

更には、湾曲構造15を持った分離溝61に絶縁性樹脂10が充填されると、この部分でアンカー効果が発生し、絶縁性樹脂10の剥がれが防止でき、逆に後の工程で分離される導電路11の抜けが防止できる。   Furthermore, when the insulating resin 10 is filled in the separation groove 61 having the curved structure 15, an anchor effect is generated in this portion, and the peeling of the insulating resin 10 can be prevented. It is possible to prevent the conductive path 11 from coming off.

続いて、導電箔60の裏面を化学的および/または物理的に除き、導電路11として分離する工程がある。ここでこの除く工程は、研磨、研削、エッチング、レーザの金属蒸発等により施される。   Subsequently, there is a step of chemically and / or physically removing the back surface of the conductive foil 60 and separating it as the conductive path 11. Here, this removal step is performed by polishing, grinding, etching, laser metal evaporation, or the like.

例えば研磨装置または研削装置により全面を30μm程度削り、分離溝61から絶縁性樹脂10を露出させている。この露出される面を図6では点線で示している。その結果、約40μmの厚さの導電路51となって分離される。また絶縁性樹脂50が露出する手前まで、導電箔60を全面ウェトエッチングし、その後、研磨または研削装置により全面を削り、絶縁性樹脂50を露出させても良い。更には、図7に示すように、前記導電路11A〜11Dに対応する裏面にホトレジストPRを形成し、ホトレジストを耐エッチングマスクとして活用し、エッチング加工しても良い。   For example, the entire surface is cut by about 30 μm by a polishing apparatus or a grinding apparatus, and the insulating resin 10 is exposed from the separation groove 61. This exposed surface is indicated by a dotted line in FIG. As a result, the conductive path 51 having a thickness of about 40 μm is separated. Alternatively, wet etching may be performed on the entire surface of the conductive foil 60 until the insulating resin 50 is exposed, and then the entire surface may be shaved by a polishing or grinding apparatus to expose the insulating resin 50. Furthermore, as shown in FIG. 7, a photoresist PR may be formed on the back surface corresponding to the conductive paths 11A to 11D, and the photoresist may be used as an anti-etching mask for etching.

この結果、絶縁性樹脂10に導電路11の表面が露出する構造となる。そして分離溝61が図1の分離溝14となる。   As a result, the surface of the conductive path 11 is exposed to the insulating resin 10. The separation groove 61 becomes the separation groove 14 of FIG.

また図6に示す点線まで研磨すると、絶縁性樹脂10と導電路11は、その表面が一致する。そのため、半導体装置裏面が平坦になる。またホトレジストPRを採用すると、図8のように、導電路11A〜11Dは、絶縁性樹脂10の裏面より突出する構造となる。   When the polishing is performed up to the dotted line shown in FIG. 6, the surfaces of the insulating resin 10 and the conductive path 11 coincide. Therefore, the back surface of the semiconductor device becomes flat. When the photoresist PR is employed, the conductive paths 11A to 11D have a structure protruding from the back surface of the insulating resin 10 as shown in FIG.

尚、導電路11の裏面に導電被膜を被着する場合、図7の導電箔の裏面に、前もって導電被膜を形成しても良い。この場合、導電路に対応する部分を選択的に被着すれば良い。被着方法は、例えばメッキである。またこの導電被膜は、エッチングに対して耐性がある材料がよい。またこの導電被膜を採用した場合、研磨をせずにエッチングだけで導電路51として分離できる。   When a conductive film is applied to the back surface of the conductive path 11, a conductive film may be formed in advance on the back surface of the conductive foil in FIG. In this case, a portion corresponding to the conductive path may be selectively attached. The deposition method is, for example, plating. The conductive film is preferably made of a material that is resistant to etching. Further, when this conductive film is employed, the conductive path 51 can be separated only by etching without polishing.

最後に、必要によって露出した導電路11に半田等の導電材を被着し、回路装置として完成し、これを図9に示すように実装基板70に実装する。   Finally, a conductive material such as solder is applied to the exposed conductive path 11 as necessary, and the circuit device is completed, and this is mounted on the mounting substrate 70 as shown in FIG.

実装基板70には、導電路11A〜11Dに対応する電極が設けられ、例えば半田等のロウ材71を介して電気的に接続されて固着される。   The mounting substrate 70 is provided with electrodes corresponding to the conductive paths 11A to 11D, and is electrically connected and fixed via a brazing material 71 such as solder.

図9の矢印は、半導体チップ12に発生する熱が、第1の導電路11Aを介して実装基板70側に伝わることを示している。図10の従来構造のように、支持基板(フレキシブルシート)50を採用すると、支持基板が熱抵抗が高く、半導体チップが発熱し、駆動電流を高く取れない問題が発生する。しかし、本発明では半導体チップ12の裏面は、ロウ材17、第1の導電路11A、ロウ材71を介して実装基板70の導電パターンと固着されるため、半導体チップ12の熱を実装基板側へ伝えることができる。従って半導体チップ12の温度上昇を防止でき、その分駆動電流を増大させることができる。   The arrows in FIG. 9 indicate that heat generated in the semiconductor chip 12 is transmitted to the mounting substrate 70 side via the first conductive path 11A. When the support substrate (flexible sheet) 50 is employed as in the conventional structure of FIG. 10, the support substrate has a high thermal resistance, the semiconductor chip generates heat, and the drive current cannot be increased. However, in the present invention, the back surface of the semiconductor chip 12 is fixed to the conductive pattern of the mounting substrate 70 through the brazing material 17, the first conductive path 11 </ b> A, and the brazing material 71. Can tell. Therefore, the temperature rise of the semiconductor chip 12 can be prevented, and the drive current can be increased accordingly.

尚、本製造方法では、導電箔60にトランジスタとチップ抵抗が実装されているだけであるが、これを1単位としてマトリックス状に配置しても良いし、どちらか一方の回路素子を1単位としてマトリックス状に配置しても良い。また複数の半導体チップ、複数の受動素子およびこれらを電気的に接続する配線を前記導電路で形成し、所望の機能を有する回路を構成し、これをマトリックス状に配置しても良い。この場合は、ダイシング装置で半導体装置を個々に分離する工程が付加される。   In this manufacturing method, the transistor and the chip resistor are only mounted on the conductive foil 60. However, the transistor and the chip resistor may be arranged in a matrix shape as one unit, or one of the circuit elements is set as one unit. They may be arranged in a matrix. Further, a plurality of semiconductor chips, a plurality of passive elements, and wirings that electrically connect them may be formed by the conductive paths to constitute a circuit having a desired function, and these may be arranged in a matrix. In this case, a step of individually separating the semiconductor devices with a dicing apparatus is added.

また図6の様に、半導体装置13の裏面の実質全域に導電箔60が貼り合わされていると、導電箔60と絶縁性樹脂10の線膨張係数の違いにより、半導体装置13は大きく反る。しかしこの後に、導電路11として分離され、導電箔60の厚みよりも薄く導電路11が形成されると同時に、導電路間には絶縁性樹脂10が埋め込まれた形状となる。従ってこのバイメタル効果は、抑制され、反りが少なくなるメリットも有する。   Further, as shown in FIG. 6, when the conductive foil 60 is bonded to substantially the entire back surface of the semiconductor device 13, the semiconductor device 13 warps greatly due to the difference in coefficient of linear expansion between the conductive foil 60 and the insulating resin 10. However, after that, the conductive path 11 is separated, and the conductive path 11 is formed thinner than the thickness of the conductive foil 60. At the same time, the insulating resin 10 is embedded between the conductive paths. Therefore, this bimetal effect is suppressed and has the merit of less warping.

本製造方法の特徴は、絶縁性樹脂10を支持基板として活用し導電路11の分離作業ができることにある。絶縁性樹脂10は、導電路11を埋め込む材料として必要な材料であり、図10で示す従来の製造方法のように、不要な支持基板50を必要としない。従って、最小限の材料で製造でき、コストの低減が実現できる特徴を有する。
A feature of this manufacturing method is that the insulating path 10 can be used as a support substrate to separate the conductive path 11. The insulating resin 10 is a material necessary as a material for embedding the conductive path 11, and does not require an unnecessary support substrate 50 unlike the conventional manufacturing method shown in FIG. Therefore, it has the characteristics that it can be manufactured with a minimum amount of material and cost can be reduced.

本発明の半導体装置を説明する図である。It is a figure explaining the semiconductor device of the present invention. 本発明の半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the semiconductor device of this invention. 従来の回路装置の実装構造を説明する図である。It is a figure explaining the mounting structure of the conventional circuit device.

符号の説明Explanation of symbols

10 絶縁性樹脂
11A〜11D 導電路
12 半導体チップ
13 半導体装置
14 分離溝
15 湾曲構造
70 実装基板
DESCRIPTION OF SYMBOLS 10 Insulating resin 11A-11D Conductive path 12 Semiconductor chip 13 Semiconductor device 14 Separation groove 15 Curved structure 70 Mounting board

Claims (14)

導電路と、前記導電路に電気的に接続された回路素子と、少なくとも前記導電路の裏面が外部に露出した状態で、前記導電路および前記回路素子を封止する絶縁性樹脂とを具備し、
前記導電路の裏面は、前記絶縁性樹脂よりも外部に突出することを特徴とする半導体装置。
A conductive path; a circuit element electrically connected to the conductive path; and an insulating resin that seals the conductive path and the circuit element with at least a back surface of the conductive path exposed to the outside. ,
The back surface of the said conductive path protrudes outside rather than the said insulating resin, The semiconductor device characterized by the above-mentioned.
前記導電路の側面の一部および裏面が前記絶縁性樹脂から外部に露出することを特徴とする請求項1記載の半導体装置。   The semiconductor device according to claim 1, wherein a part of the side surface and the back surface of the conductive path are exposed to the outside from the insulating resin. 前記導電路の側面は湾曲構造を有することを特徴とする請求項1記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a side surface of the conductive path has a curved structure. 前記導電路の裏面には、前記導電路のエッチャントに対して耐性のあるメッキ膜が設けられ、前記メッキ膜のパターンと前記導電路の裏面は実質同じ形状であることを特徴とする請求項1、請求項2または請求項3に記載の半導体装置。   The plating film having a resistance against an etchant of the conductive path is provided on a back surface of the conductive path, and the pattern of the plating film and the back surface of the conductive path have substantially the same shape. The semiconductor device according to claim 2 or claim 3. 半導体素子と、金属細線を介して前記半導体素子と電気的に接続されたボンディングパッドと、少なくとも前記ボンディングパッドの裏面が外部に露出した状態で、前記ボンディングパッドおよび前記回路素子を封止する絶縁性樹脂とを具備し、
前記ボンディングパッドの裏面は、前記絶縁性樹脂よりも外部に突出することを特徴とする半導体装置。
A semiconductor element, a bonding pad electrically connected to the semiconductor element through a fine metal wire, and an insulating property for sealing the bonding pad and the circuit element with at least a back surface of the bonding pad exposed to the outside Resin,
The back surface of the said bonding pad protrudes outside rather than the said insulating resin, The semiconductor device characterized by the above-mentioned.
前記ボンディングパッドの側面の一部および裏面が前記絶縁性樹脂から外部に露出することを特徴とする請求項5記載の半導体装置。   6. The semiconductor device according to claim 5, wherein a part of the side surface and the back surface of the bonding pad are exposed to the outside from the insulating resin. 前記ボンディングパッドの側面は湾曲構造を有することを特徴とする請求項5記載の半導体装置。   6. The semiconductor device according to claim 5, wherein a side surface of the bonding pad has a curved structure. 前記ボンディングパッドの裏面には、前記ボンディングパッドのエッチャントに対して耐性のあるメッキ膜が設けられ、前記メッキ膜のパターンと前記ボンディングパッドの裏面は実質同じ形状であることを特徴とする請求項5、請求項6または請求項7に記載の半導体装置。   6. The plating film according to claim 5, wherein a plating film resistant to an etchant of the bonding pad is provided on the back surface of the bonding pad, and the pattern of the plating film and the back surface of the bonding pad have substantially the same shape. The semiconductor device according to claim 6 or 7. 表面に分離溝が形成されることで、導電路が凸状に形成された導電箔を用意する工程と、
前記導電路に回路素子を電気的に接続する工程と、
前記回路素子が被覆されて前記分離溝に充填されるように絶縁性樹脂を形成する工程と、
前記分離溝に対応する前記導電箔の裏面を選択的に除去することで、前記導電路の裏面が前記絶縁性樹脂よりも外部に突出した状態で、前記導電路同士を分離させる工程とを具備することを特徴とする半導体装置の製造方法。
A step of preparing a conductive foil having a conductive path formed into a convex shape by forming a separation groove on the surface;
Electrically connecting a circuit element to the conductive path;
Forming an insulating resin so that the circuit element is covered and filled in the separation groove;
Selectively removing the back surface of the conductive foil corresponding to the separation groove, thereby separating the conductive paths from each other in a state where the back surface of the conductive path protrudes outside the insulating resin. A method of manufacturing a semiconductor device.
前記導電路同士を分離させる工程では、
前記導電路に対応する領域の前記導電箔の裏面を被覆した後に、前記導電箔を裏面からエッチングすることを特徴とする請求項9記載の半導体装置の製造方法。
In the step of separating the conductive paths,
The method for manufacturing a semiconductor device according to claim 9, wherein the conductive foil is etched from the back surface after the back surface of the conductive foil in a region corresponding to the conductive path is covered.
前記分離溝の側壁を湾曲形状にすることを特徴とする請求項9記載の半導体装置の製造方法。   10. The method of manufacturing a semiconductor device according to claim 9, wherein the side wall of the separation groove is curved. 前記回路素子は半導体素子であり、前記半導体素子は金属細線を介して前記導電路に接続されることを特徴とする請求項9記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 9, wherein the circuit element is a semiconductor element, and the semiconductor element is connected to the conductive path through a thin metal wire. 表面に分離溝が形成されることで、凸状の導電路が設けられ、前記導電路には回路素子が電気的に接続された導電箔を用意し、
前記回路素子を被覆するように絶縁性樹脂を設けた後に、前記導電路に対応して設けられたメッキ膜を介して、前記導電箔の裏面を選択的に除去することで、前記導電路の裏面が前記絶縁性樹脂よりも外部に突出した状態で、前記導電路を分離することを特徴とする半導体装置の製造方法。
By forming a separation groove on the surface, a convex conductive path is provided, and a conductive foil in which circuit elements are electrically connected to the conductive path is prepared,
After providing an insulating resin so as to cover the circuit element, the back surface of the conductive foil is selectively removed through a plating film provided corresponding to the conductive path, thereby A method for manufacturing a semiconductor device, characterized in that the conductive path is separated in a state in which a back surface protrudes outside the insulating resin.
前記導電路は、前記回路素子が設けられた第1の導電路と、前記回路素子の周囲に設けられ、前記回路素子と電気的に接続された第2の導電路を有し、凸状に形成された前記第1の導電路と前記第2の導電路を、実装基板の電極に接続することを特徴とする請求項13に記載の半導体装置の製造方法。   The conductive path includes a first conductive path provided with the circuit element and a second conductive path provided around the circuit element and electrically connected to the circuit element. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the formed first conductive path and the second conductive path are connected to an electrode of a mounting substrate.
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