JP2006049859A5 - - Google Patents
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- JP2006049859A5 JP2006049859A5 JP2005189573A JP2005189573A JP2006049859A5 JP 2006049859 A5 JP2006049859 A5 JP 2006049859A5 JP 2005189573 A JP2005189573 A JP 2005189573A JP 2005189573 A JP2005189573 A JP 2005189573A JP 2006049859 A5 JP2006049859 A5 JP 2006049859A5
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- film
- semiconductor device
- thin film
- element group
- layer
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- 239000010408 film Substances 0.000 claims 33
- 239000004065 semiconductor Substances 0.000 claims 28
- 239000010409 thin film Substances 0.000 claims 22
- 238000000034 method Methods 0.000 claims 16
- 238000004519 manufacturing process Methods 0.000 claims 15
- 239000000463 material Substances 0.000 claims 14
- 239000000758 substrate Substances 0.000 claims 10
- 238000000926 separation method Methods 0.000 claims 3
- 208000031872 Body Remains Diseases 0.000 claims 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 239000003795 chemical substances by application Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 229910052736 halogen Inorganic materials 0.000 claims 1
- -1 halogen fluoride Chemical class 0.000 claims 1
- 239000007788 liquid Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 238000007650 screen-printing Methods 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
Claims (21)
前記剥離層上に第１の素子群と第２の素子群を含む層を形成し、
前記第１の素子群に前記剥離層に達する第１の開口部を、前記第２の素子群に前記剥離層に達する第２の開口部を、それぞれ形成し、
前記第１の素子群と前記第２の素子群の間の領域上に、当該領域と重なる材料体を形成し、
前記第１の開口部及び前記第２の開口部にエッチング剤を導入して、前記第１の素子群と前記第２の素子群の間の領域と重なる前記剥離層の一部が残存するように前記剥離層を選択的に除去し、
前記絶縁表面を有する基板から前記第１の素子群及び前記第２の素子群を切り離すことを特徴とする半導体装置の作製方法。 Forming a release layer over a substrate having an insulating surface;
A layer including a first element group and the second element group is formed on the release layer,
A first opening reaching the peeling layer in the first element group, said second opening reaching the peeling layer, respectively formed in the second element group,
On the region between the first element group and the second element group, a material body overlapping the region is formed,
An etchant is introduced into the first opening and the second opening so that a part of the peeling layer that overlaps a region between the first element group and the second element group remains . Selectively removing the release layer,
A method for manufacturing a semiconductor device, wherein the first element group and the second element group are separated from a substrate having the insulating surface.
前記絶縁表面を有する基板から前記第１の素子群及び前記第２の素子群を切り離すことによって、前記第１の素子群及び前記第２の素子群から前記材料体を切り離すことを特徴とする半導体装置の作製方法。A semiconductor characterized in that the material body is separated from the first element group and the second element group by separating the first element group and the second element group from the substrate having the insulating surface. Device fabrication method.
前記第１の素子群及び前記第２の素子群は、それぞれ半導体素子を有することを特徴とする半導体装置の作製方法。 In claim 1 or claim 2 ,
The first element group and the second element group, the method for manufacturing a semiconductor device characterized by having a semiconductor element, respectively.
前記材料体の上面形状は、前記第１の素子群及び前記第２の素子群をそれぞれ囲む格子形状であることを特徴とする半導体装置の作製方法。A method for manufacturing a semiconductor device, wherein the upper surface shape of the material body is a lattice shape surrounding each of the first element group and the second element group.
前記剥離層上に第１の薄膜集積回路及び第２の薄膜集積回路を含む層を形成し、
前記第１の薄膜集積回路に前記剥離層に達する第１の開口部を、前記第２の薄膜集積回路に前記剥離層に達する第２の開口部を、それぞれ形成し、
前記第１の薄膜集積回路及び前記第２の薄膜集積回路を含む層上であって、前記第１の薄膜集積回路と前記第２の薄膜集積回路の境界に材料体を形成し、
前記第１の開口部及び前記第２の開口部にエッチング剤を導入して、前記材料体の下方の前記剥離層の一部が残存するように前記剥離層を選択的に除去し、
前記絶縁表面を有する基板から前記第１の薄膜集積回路及び前記第２の薄膜集積回路を切り離すことを特徴とする半導体装置の作製方法。 Forming a release layer over a substrate having an insulating surface;
Forming a layer including a first thin film integrated circuit and a second thin film integrated circuit on the release layer;
A first opening reaching the peeling layer on the first thin film integrated circuit, wherein a second opening reaching the peeling layer, respectively formed on the second thin film integrated circuit,
A layer on including the first thin film integrated circuit and the second thin film integrated circuits, the material body is formed in the boundary of the first thin film integrated circuit and the second thin film integrated circuit,
By introducing an etchant into the first opening and the second opening, the separation layer is selectively removed so that a portion of the release layer beneath the material body remains,
A method for manufacturing a semiconductor device, wherein the first thin film integrated circuit and the second thin film integrated circuit are separated from a substrate having an insulating surface.
前記絶縁表面を有する基板から前記第１の薄膜集積回路及び前記第２の薄膜集積回路を切り離すことによって、前記第１の薄膜集積回路及び前記第２の薄膜集積回路から前記材料体を切り離すことを特徴とする半導体装置の作製方法。Separating the material body from the first thin film integrated circuit and the second thin film integrated circuit by separating the first thin film integrated circuit and the second thin film integrated circuit from the substrate having the insulating surface. A method for manufacturing a semiconductor device.
前記剥離層上に複数の薄膜集積回路を含む層を形成し、
前記複数の薄膜集積回路を含む層に、前記剥離層に達する第１の開口部及び第２の開口部を形成し、
前記複数の薄膜集積回路を含む層上であって、隣り合う薄膜集積回路の境界に材料体を形成し、
前記第１の開口部及び前記第２の開口部にエッチング剤を導入して、前記材料体の下方の前記剥離層の一部が残存するように前記剥離層を選択的に除去し、
前記複数の薄膜集積回路を、接着面を備える基体へ転置し、
前記複数の薄膜集積回路を個々に分断することを特徴とする半導体装置の作製方法。 Forming a release layer over a substrate having an insulating surface;
A layer containing a plurality of thin film integrated circuits over the separation layer,
A layer containing a plurality of thin film integrated circuits to form a first opening and a second opening reaching the peeling layer,
A over the layer including a plurality of thin film integrated circuits, the material body is formed in the boundary of the adjacent thin film integrated circuit,
By introducing an etchant into the first opening and the second opening, the separation layer is selectively removed so that a portion of the release layer beneath the material body remains,
Said plurality of thin film integrated circuits, transposed to the substrate with an adhesive surface,
The method for manufacturing a semiconductor device comprising individually a partial sectional to Turkey the plurality of thin film integrated circuits.
前記複数の薄膜集積回路を前記接着面を備える基体へ転置することによって、前記複数の薄膜集積回路から前記材料体を切り離すことを特徴とする半導体装置の作製方法。A method for manufacturing a semiconductor device, wherein the material body is separated from the plurality of thin film integrated circuits by transferring the plurality of thin film integrated circuits to a substrate having the bonding surface.
前記材料体の上面形状は、前記絶縁表面を有する基板の一辺と平行な直線形状であることを特徴とする半導体装置の作製方法。 In any one of claims 1 to 3 and claims 5 to 8,
Upper surface shape of the material body, the method for manufacturing a semiconductor device wherein the parallel straight shape and one side of the substrate having an insulating surface.
前記エッチング剤としてフッ化ハロゲンを含む気体又は液体を用いることを特徴とする半導体装置の作製方法。A method for manufacturing a semiconductor device, wherein a gas or a liquid containing halogen fluoride is used as the etchant.
前記第１の開口部及び前記第２の開口部は、多数の穴であることを特徴とする半導体装置の作製方法。 In any one of claims 1 to 10,
The first opening and the second opening, the method for manufacturing a semiconductor device which is a large number of holes.
前記第１の開口部及び前記第２の開口部は、多数の溝であることを特徴とする半導体装置の作製方法。The method for manufacturing a semiconductor device, wherein the first opening and the second opening are a plurality of grooves.
前記材料体をスクリーン印刷法または液滴吐出法により形成することを特徴とする半導体装置の作製方法。 In any one of claims 1 to 12,
A method for manufacturing a semiconductor device, wherein the material body is formed by a screen printing method or a droplet discharge method.
前記材料体は、前記エッチング剤と化学反応しない材料であることを特徴とする半導体装置の作製方法。 In any one of claims 1 to 13,
The method of manufacturing a semiconductor device, wherein the material body is a material that does not chemically react with the etching agent .
前記材料体として樹脂を用いることを特徴とする半導体装置の作製方法。A method for manufacturing a semiconductor device, wherein a resin is used as the material body.
第２のフィルムと、
前記第１のフィルムと前記第２のフィルムとの間に、第１の絶縁膜と、前記第１の絶縁膜上に設けられた半導体素子を含む層と、前記半導体素子を含む層を覆う第２の絶縁膜と、を有し、
前記第１のフィルムは、前記第１の絶縁膜と接し、且つ、前記第２のフィルムは前記第２の絶縁膜と接していることを特徴とする半導体装置。 A first film;
A second film ;
Between the second film and the first film, the first cover and the first insulating film, a layer containing a semiconductor element provided on the first insulating film, a layer containing the semiconductor element a second insulating and film, and
The semiconductor device, wherein the first film is in contact with the first insulating film, and the second film is in contact with the second insulating film.
第２のフィルムと、
前記第１のフィルムと前記第２のフィルムとの間に、第１の絶縁膜と、前記第１の絶縁膜上に設けられた半導体素子およびアンテナを含む層と、前記半導体素子および前記アンテナを含む層を覆う第２の絶縁膜と、を有し、
前記第１のフィルムは、前記第１の絶縁膜と接し、且つ、前記第２のフィルムは前記第２の絶縁膜と接していることを特徴とする半導体装置。 A first film;
A second film ;
Between the second film and the first film, a first insulating film, a layer including a semiconductor element and an antenna provided on the first insulating film, said semiconductor element and said antenna and a second insulating film covering the layer containing the,
The semiconductor device, wherein the first film is in contact with the first insulating film, and the second film is in contact with the second insulating film.
前記第１の絶縁膜は、窒化珪素または酸化珪素を主成分とする無機絶縁膜であることを特徴とする半導体装置。 In claim 16 or claim 17 ,
The semiconductor device according to claim 1, wherein the first insulating film is an inorganic insulating film containing silicon nitride or silicon oxide as a main component.
第２のフィルムと、
前記第１のフィルムと前記第２のフィルムとの間に、絶縁膜と、前記第１の絶縁膜上に設けられた半導体素子を含む層と、前記半導体素子を含む層上に設けられたアンテナと、を有し、
前記第１のフィルムは、前記絶縁膜と接し、且つ、前記第２のフィルムは前記アンテナと接していることを特徴とする半導体装置。 A first film;
A second film ;
Between the first film and the second film, and absolute Enmaku, a layer including a semiconductor element provided on the first insulating film, provided on a layer containing the semiconductor element An antenna, and
The first film before contact with Kize' Enmaku, and said second film is a semiconductor device which is characterized in that in contact with the antenna.
前記第１のフィルムは積層構造を有していることを特徴とする半導体装置。 In any one of claims 16 to 19 ,
The semiconductor device, wherein the first film has a laminated structure.
前記第２のフィルムは積層構造を有していることを特徴とする半導体装置。 In any one of claims 16 to 20 ,
The semiconductor device, wherein the second film has a laminated structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005189573A JP2006049859A (en) | 2004-06-29 | 2005-06-29 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004192117 | 2004-06-29 | ||
| JP2005189573A JP2006049859A (en) | 2004-06-29 | 2005-06-29 | Semiconductor device and its manufacturing method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012185122A Division JP5509280B2 (en) | 2004-06-29 | 2012-08-24 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2006049859A JP2006049859A (en) | 2006-02-16 |
| JP2006049859A5 true JP2006049859A5 (en) | 2008-06-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005189573A Withdrawn JP2006049859A (en) | 2004-06-29 | 2005-06-29 | Semiconductor device and its manufacturing method |
Country Status (1)
| Country | Link |
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| JP (1) | JP2006049859A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5469799B2 (en) * | 2006-03-15 | 2014-04-16 | 株式会社半導体エネルギー研究所 | Semiconductor device that communicates data by wireless communication |
| JP2010026457A (en) * | 2008-07-24 | 2010-02-04 | Technology Research Association For Advanced Display Materials | Thin film semiconductor substrate and apparatus for manufacturing the same |
| KR20100027526A (en) * | 2008-09-02 | 2010-03-11 | 삼성전기주식회사 | Fabrication method of thin film device |
| KR101004849B1 (en) * | 2008-09-02 | 2010-12-28 | 삼성전기주식회사 | Fabrication method of thin film device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1159036A (en) * | 1997-08-21 | 1999-03-02 | Hitachi Maxell Ltd | Non-contact ic card and its manufacture |
| FR2781925B1 (en) * | 1998-07-30 | 2001-11-23 | Commissariat Energie Atomique | SELECTIVE TRANSFER OF ELEMENTS FROM ONE MEDIUM TO ANOTHER MEDIUM |
| JP4748859B2 (en) * | 2000-01-17 | 2011-08-17 | 株式会社半導体エネルギー研究所 | Method for manufacturing light emitting device |
| JP2002236896A (en) * | 2001-02-07 | 2002-08-23 | Toppan Printing Co Ltd | Ic tag having heat seal performance |
| JP4211256B2 (en) * | 2001-12-28 | 2009-01-21 | セイコーエプソン株式会社 | Semiconductor integrated circuit, semiconductor integrated circuit manufacturing method, electro-optical device, and electronic apparatus |
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2005
- 2005-06-29 JP JP2005189573A patent/JP2006049859A/en not_active Withdrawn
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