JP2006049576A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device forming a resistance element having a high resistance mixed-loaded together with a transistor on a semiconductor substrate, with an excellent controllability without increasing mandays on a manufacture, and also to provide a manufacturing method for the semiconductor device. <P>SOLUTION: A transistor forming region in which a transistor TR1 is formed through an element isolation film 3, and a resistance-element forming region having the formed resistance element R1, are partitioned and formed on the semiconductor substrate 1. A diffused resistor utilizing a low-concentration diffusion layer 14c in the semiconductor substrate 1 is formed in the resistance-element forming region as the resistance element R1. A plurality of linear patterns 11a being composed of a gate electrode material (polysilicon) forming a gate electrode for the transistor TR1 and being orthogonal to the conductive direction as the resistance element R1 are arrayed at regular intervals in the resistance-element forming region. The diffused resistors formed in each adjacent region in the lower sections of a plurality of these linear patterns 11a are connected electrically in the semiconductor substrate 1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device including a diffusion resistor on the same substrate as a semiconductor substrate including an element such as a transistor, and a manufacturing method thereof.

  In a semiconductor device such as an LSI (Large Scale Integrated Circuit), various elements such as a capacitor and a resistor constituting the circuit are often mounted on the same semiconductor substrate together with an active element such as a transistor. In recent years, with increasing demands for high integration, high density, and high speed as a semiconductor device, there is an increasing demand for miniaturization and miniaturization of such various elements.

  In general, a region where an electrode portion of a transistor is formed, that is, a region where a contact hole is formed, desirably has a lower resistance from the viewpoint of speeding up. Therefore, as a technique for reducing the resistance of the electrode portion of the transistor, a salicide technique is known in which a high-melting point metal is selectively reacted with a region on a substrate to form a high-conductivity silicide.

  On the other hand, as a resistance element formed in such a semiconductor device, there is a diffusion resistance using an impurity diffusion layer formed in a substrate, that is, a conductive region. Such diffusion resistance generally becomes low resistance when a diffusion layer having a high concentration and a deep junction depth is formed in the substrate, and becomes high resistance if a diffusion layer having a low concentration and a shallow junction depth is formed.

  In addition, it is desirable that the resistance in the region in which the input / output circuit and the circuit for controlling the power supply voltage are formed among the resistance elements is higher, and these resistors can be formed in a smaller area. It has been demanded.

  Here, conventionally, as a semiconductor device provided with a transistor and such a high-resistance resistance element on the same semiconductor substrate, for example, devices described in Patent Documents 1 to 3 are known. An example of a manufacturing method generally employed for manufacturing such a semiconductor device including the devices described in Patent Documents 1 to 3 will be described with reference to FIGS.

  17A to 17F schematically show the cross-sectional structure of such a semiconductor device according to the manufacturing process. Of these, for the cross-sectional structures shown in FIGS. 17A, 17C, and 17F, the corresponding planar structures are shown in FIGS. 18, 19, and 20, respectively.

  First, as shown in FIGS. 17A and 18, a well 2 is formed in a substrate 1 made of silicon, and the well 2 is formed by using, for example, a well-known STI structure or a LOCOS method. By being separated by the element isolation film 3, a resistive element formation region and a transistor formation region are partitioned on the substrate 1 respectively. Then, after an oxide film (gate oxide film) 4 is formed on the surface of the resistance element formation region and the transistor formation region in the substrate 1, for example, a polysilicon film is formed and then patterned, and the transistor is formed only in the transistor formation region. A gate electrode material (polysilicon) layer 71b to be a gate electrode is formed. Then, impurities are ion-implanted over the entire surface of the substrate 1 using the gate electrode material layer 71b as a mask.

  As a result, as shown in FIG. 17B, a low-concentration diffusion layer 74a is formed in the resistance element formation region in the substrate 1, and the transistor LDD is formed in the transistor formation region in the substrate 1. A low concentration diffusion layer 74b to be a layer is formed. Next, after depositing an insulating film on the entire surface of the substrate 1, a resist 90 is formed so as to partially cover the resistance element formation region. Then, after the insulating film exposed from the resist 90 is removed by performing anisotropic etching such as reactive ion etching (RIE), the gate electrode material layer is further etched back until the substrate 1 is exposed. A side wall 73b is formed on the side wall of 71b. Incidentally, at this time, the insulating film 73a remains under the resist 90 on the resistance element formation region.

  Next, after removing the resist 90, as shown in FIGS. 17C and 19, impurities are ion-implanted over the entire surface of the substrate 1 using the insulating film 73a, the sidewall 73b and the gate electrode material layer 71b as a mask. .

  As a result, as shown in FIG. 17D, a high concentration diffusion layer 75a is formed in the substrate 1 in the resistance element formation region, and the source / drain of the transistor is formed in the substrate 1 in the transistor formation region. A high concentration diffusion layer 75b to be a region is formed. When the substrate 1 is heat-treated, the impurities in the low concentration diffusion layers 74a and 74b and the high concentration diffusion layers 75a and 75b in the substrate 1 are activated.

  Next, as shown in FIG. 17E, a titanium film 77 is deposited on the entire surface of the substrate 1 and heat-treated. Thereby, a silicide reaction selectively occurs only on the surface of the substrate 1 made of silicon and the surface of the gate electrode material layer 71b made of polysilicon which are in contact with the titanium film 77. Thereafter, when the unreacted titanium film 77 is removed, silicide 77a and 77b are selectively formed in the region on the substrate 1 as shown in FIG. 17 (f) and FIG. Specifically, in the resistance element formation region, a resistance element R7 composed of a low concentration diffusion layer 74a and functioning as a diffusion resistance and an electrode portion RA7 of the resistance element R7 composed of a high concentration diffusion layer 75a are formed. A transistor TR7 is formed in the transistor formation region. In this semiconductor device, silicide 77a is formed on the high-concentration diffusion layer 75a in the resistance element formation region, and silicide is formed on the gate electrode material layer 71b in the transistor formation region and the high-concentration diffusion layer 75b as the source / drain regions. By forming 77b, the resistance of each of these electrode portions is reduced. Since no silicide is formed on the low-concentration diffusion layer 74a in the resistance element formation region, the resistance element R7 is maintained at a high resistance.

  As described above, in the method of manufacturing the semiconductor device, the insulating film 73a is partially formed in the region where the resistance element R7 is formed, and by suppressing the formation of silicide on the resistance element R7, a high resistance is achieved. A resistance element is formed. The insulating film 73a is formed by patterning using a mask such as a resist 90.

  On the other hand, for such a manufacturing method, a method of forming a high-resistance resistance element in a semiconductor device of the same type without requiring patterning using the above-described mask has been conventionally known. There is a way that is. Next, the outline and structure of the manufacturing process of the same type of general semiconductor device including the semiconductor device described in Patent Document 4 will be described with reference to FIGS.

  Of these drawings, FIG. 21 schematically shows a planar structure of the semiconductor device, FIG. 22 shows a cross-sectional structure taken along line GG of FIG. 21, and FIG. The cross-sectional structures along the line H-H are respectively shown. As shown in FIGS. 21 to 23, this semiconductor device includes a transistor TR8, a high-resistance resistive element R8 made of a diffused resistor, and an electrode portion RA8 on the same substrate 1, and the structure thereof is as follows. Although similar to the semiconductor device described above with reference to FIGS. 17 to 20, the structure of the resistor element R8 is different. That is, in the resistance element formation region on the substrate 1, the gate electrode material layer 81a formed of, for example, a polysilicon film is arranged in a pattern having a predetermined width and a gap therebetween. A low concentration diffusion layer 84a is formed in a portion of the substrate 1 corresponding to the gap. The width of the gap is set to be about twice the thickness of the insulating film deposited to form the sidewalls 83a and 83b. A sidewall 83a is formed in such a manner as to fill the side wall of the gate electrode material layer 81a and the gap portion of the gate electrode material layer 81a pattern.

  On the other hand, FIGS. 24A to 24E schematically show the cross-sectional structure of the semiconductor device corresponding to FIG. 22 in accordance with the manufacturing process. FIGS. 25A to 25E show the cross-sectional structure of the semiconductor device corresponding to FIG. 23 in the form corresponding to FIGS. 24A to 24E, respectively. Furthermore, among these, the planar structures corresponding to FIGS. 24 (a) and 25 (a) or FIGS. 24 (c) and 25 (c) are shown in FIGS. 26 and 27, respectively. Hereinafter, a manufacturing method of such a semiconductor device will be described while omitting the details of the processes similar to the processes described in FIGS. 17A to 17F.

  First, as shown in FIG. 24A, FIG. 25A, and FIG. 26, a resistive element formation region and a transistor formation region are partitioned on the substrate 1 by the element isolation film 3. Then, after an oxide film (gate oxide film) 4 is formed in each of these regions on the surface of the substrate 1, for example, a polysilicon film is further formed and then patterned to form a gate electrode material layer 81b in the transistor formation region. . At this time, unlike the example described above, the gate electrode material layer 81a is also formed in a pattern in a manner having a predetermined width and a predetermined gap in the resistance element forming region. The gap of the pattern of the gate electrode material layer 81a is set to about twice the film thickness of the insulating film deposited for forming the sidewall 83a in a later step. Then, impurities are ion-implanted over the entire surface of the substrate 1 using the gate electrode material layers 81a and 81b as a mask.

  Thus, as shown in FIGS. 24B and 25B, the low-concentration diffusion layer 84a is formed in the resistance element formation region, and the LDD layer of the transistor TR8 is formed in the transistor formation region. A low concentration diffusion layer 84b is formed. Here, the low-concentration diffusion layer 84a formed in the resistance element formation region is formed in the substrate 1 along the gap portion of the pattern of the gate electrode material layer 81a. Next, after an insulating film is deposited on the entire surface of the substrate 1, anisotropic etching such as reactive ion etching (RIE) is performed and etched back until the substrate 1 is exposed, whereby the gate electrode material layers 81a and 81b are formed. Side walls 83a and 83b are formed on the side walls of the gate electrodes, and the side walls 83a are buried in the gap portions of the pattern of the gate electrode material layer 81a.

  Next, as shown in FIGS. 24C, 25C, and 27, impurities are ion-implanted over the entire surface of the substrate 1 using the gate electrode material layers 81a and 81b and the sidewalls 83a and 83b as masks.

  As a result, as shown in FIGS. 24D and 25D, the high concentration diffusion layer 85a is formed in the resistance element formation region, and the transistor formation region becomes the source / drain region of the transistor TR8. A high concentration diffusion layer 85b is formed. When the substrate 1 is heat-treated, the impurities in the low concentration diffusion layers 84a and 84b and the high concentration diffusion layers 85a and 85b in the substrate 1 are activated.

  Next, as shown in FIGS. 24E and 25E, after a titanium film 87 is deposited on the entire surface of the substrate 1, a salicide process is performed in the same manner as in the above-described example, so that Silicides 87a and 87b are selectively formed. Thus, finally, the semiconductor device having the structure shown in FIGS. 21 to 23 is obtained.

As described above, in the manufacturing method of the semiconductor device, the sidewall 83a is formed in the region where the resistance element R8 is formed, so that the formation of silicide on the resistance element R8 is prevented, and a high resistance resistance element is formed. can get. The sidewall 83a is formed in the same step as the step of forming the sidewall 83b of the transistor TR8, thereby forming a high-resistance resistance element without requiring a new patterning step using a mask. Will be able to.
JP-A-5-259115 Japanese Patent Laid-Open No. 10-98186 JP 2000-31295 A JP 2000-196019 A

  Thus, in the manufacturing method of the semiconductor device described in Patent Documents 1 to 4, by reducing the resistance of the semiconductor device by the salicide technology, while preventing the formation of silicide on the resistance element, A high-resistance resistor element R7 or R8 is formed.

  However, in the methods described in Patent Documents 1 to 3, it is necessary to selectively form an insulating film for preventing the formation of silicide in advance in the region where the high-resistance resistance element R7 is to be formed. It is necessary to add a photolithographic process or the like using. In such a manufacturing process, the length of the resistance element R7 is determined by the length of the low-concentration diffusion layer 74a formed in the resistance element formation region. That is, it is determined in the photolithography process of the insulating film. For this reason, in order to make the resistance element R7 have a desired resistance value, it is necessary to form this length to a desired length, and a more accurate photolithography technique and etching technique are required. Similarly, in such a manufacturing process, the width of the resistance element R 7 is determined by the opening width of the element isolation film 3 formed on the substrate 1. For this reason, when such an element isolation film 3 is formed by, for example, the LOCOS method, the size variation occurs due to the occurrence of bird's beaks, and the resistance value of the resistance element R7 also varies.

  On the other hand, in the manufacturing method described in Patent Document 4, the sidewall 83a made of an insulating film can be left on the resistance element formation region without adding a photolithography process using a mask. Thus, the number of manufacturing process steps has been improved. However, in order to form the sidewall 83a by filling the gap of the gate electrode material layer 81a on the low concentration diffusion layer 84a, the gap of the pattern of the gate electrode material layer 81a forms the sidewall 83a. It is necessary to be defined to be at least twice the film thickness of the insulating film deposited on the substrate. Therefore, in this semiconductor device, the shape of the resistive element R8 that can be formed is limited, and as a result, the resistance value is naturally limited.

  The present invention has been made in view of the above circumstances, and forms a high-resistance resistance element mixed with a transistor or the like on a semiconductor substrate without increasing the number of manufacturing steps and with a high degree of freedom and good controllability. An object of the present invention is to provide a semiconductor device and a manufacturing method thereof.

  In order to achieve such an object, in the invention described in claim 1, a transistor formation region in which a transistor is formed and a resistance element formation region in which a resistance element is formed are formed on a semiconductor substrate via an element isolation film. And forming a gate electrode of the transistor in the resistance element formation region as a semiconductor device in which a diffusion resistance using an impurity diffusion layer in a substrate is formed as the resistance element in the resistance element formation region. A plurality of linear patterns made of a gate electrode material perpendicular to the energization direction as the resistive element are arranged at equal intervals, and diffusion resistors formed in adjacent regions below the plurality of linear patterns are The structure is such that it is electrically connected in the semiconductor substrate.

  According to such a structure as a semiconductor device, the diffusion resistance formed below the linear pattern made of the gate electrode material is formed in a form having a fine pattern with the same controllability as the linear pattern. Will be able to. In addition, the diffusion resistance thus formed is electrically connected in the semiconductor substrate, so that a physically desired size according to the number and length of the linear patterns and a desired resistance value are obtained. It becomes possible to form a resistance element having a high accuracy with a higher degree of freedom.

  According to a second aspect of the present invention, a transistor formation region in which a transistor is formed and a resistance element formation region in which a resistance element is formed are partitioned on a semiconductor substrate via an element isolation film, As a semiconductor device in which a diffusion resistance using an impurity diffusion layer in a substrate is formed as the resistance element in the resistance element formation region, the resistance element formation region is made of a gate electrode material for forming a gate electrode of the transistor. A plurality of linear patterns orthogonal to the energizing direction as the resistive elements are arranged at equal intervals, and diffusion resistors are formed in adjacent regions below the linear patterns to bias the linear patterns. Each of the diffused resistors is electrically connected in the semiconductor substrate based on voltage application.

  Even with such a structure, the diffusion resistance using the impurity diffusion layer in the substrate can be formed in a form having a fine pattern with the same controllability as the linear pattern. Moreover, according to the above structure, even if such diffusion resistors are formed in the substrate without being physically connected to each other, the bias voltage is applied to each linear pattern made of the gate electrode material. Thus, each of these diffused resistors is electrically connected in the substrate, for example, as in the on-control of the transistor. For this reason, also in this case, a resistance element having a physically desired size and a desired resistance value according to the number and length of the linear patterns can be formed with higher degree of freedom and high accuracy. It becomes like this. In addition, since the potential of the gate electrode material is fixed by applying a bias voltage to each linear pattern in this way, charge is accumulated in the gate electrode material and is caused by this. A change in the resistance value of the diffused resistor is suppressed, and the resistance element can be maintained in a more stable state.

As for the structure according to claim 2, for example, according to the invention according to claim 3,
(A) Each of the linear patterns arranged in the resistance element forming region is electrically connected by the same gate electrode material laid at least one of its end portions in parallel with the energization direction as the resistance element. Structure.
Alternatively, as in the invention according to claim 4,
(B) Each of the linear patterns arranged in the resistance element formation region is electrically connected by the same gate electrode material laid both in parallel with the energization direction as the resistance element, A structure in which the length of each diffusion resistor that determines the width as the resistance element is regulated by the gate electrode material laid in parallel.
Is particularly effective.

  That is, when at least one of the ends of the linear patterns of the gate electrode material arranged in the resistance element formation region is electrically connected as in the structure (a), the structure according to claim 2. In addition to the effects of the invention, it is possible to narrow down the location where the bias voltage is applied to the gate electrode material to one location, and the wiring structure can be simplified.

  Further, as in the structure (b), both ends of each linear pattern of the gate electrode material are electrically connected, and the length of the diffusion resistance is regulated by the gate electrode material. Then, in addition to the effect of the invention according to claim 2 or 3, the length of each diffused resistor, that is, the width on the side orthogonal to the energizing direction as the resistance element can be set without depending on the formation accuracy of the element isolation film. It can be formed finely with good controllability.

  Further, in the structure according to any one of claims 1 to 4, as in the invention according to claim 5, the plurality of linear patterns made of the gate electrode material has a minimum line width in the transistor. It is desirable to have a structure that is narrower than the minimum gate length that can ensure the length. By adopting such a structure, each diffused resistor formed in each adjacent region below each linear pattern is also brought into proximity in a manner corresponding to such a line width. It becomes possible to short-circuit easily. That is, the electrical connection of each diffusion resistor can be realized more easily.

  Moreover, in the structure according to any one of claims 1 to 5, as in the invention according to claim 6, the resistance element is positioned at both ends as an electrode portion thereof in the energization direction as the resistance element. Impurity diffusion layers that are electrically connected to the diffusion resistors and in which impurities having a concentration higher than that of the respective diffusion resistors are diffused are formed, and at least the impurity diffusion layers that form the electrode portions include the source of the transistor.・ By using a structure that forms silicide together with the impurity diffusion layer that forms the drain region, the resistance of the electrode can be reduced, and as a result, the speed of the semiconductor device can be increased. become.

  Further, in this case, as in the invention described in claim 7, sidewalls are formed on the respective side walls of the plurality of linear patterns made of the gate electrode material, and the arrangement interval of the respective linear patterns is determined by the side walls of the side walls. It is particularly effective to have a structure that is set to be twice or less the width. According to such a structure, the sidewalls are formed in such a manner that the gaps between the linear patterns are filled, and thus no silicide is formed on the sidewalls. That is, it is possible to suppress the formation of silicide on the lower part of the gap between the linear patterns, that is, on the diffusion resistance formed in the semiconductor substrate, and it becomes easy to maintain such diffusion resistance at a high resistance.

  In the structure according to any one of the first to seventh aspects, it is effective to use polysilicon as the gate electrode material as in the invention according to the eighth aspect. Since this polysilicon is a material generally used for forming a gate electrode of a transistor, it is advantageous in terms of cost in manufacturing the semiconductor device, and has high controllability in forming the linear pattern and the like. Maintained.

On the other hand, a transistor formation region in which a transistor is formed and a resistance element formation region in which a resistance element is formed are partitioned on a semiconductor substrate via an element isolation film, and the resistance element formation region includes the resistance element as the resistance element. As a manufacturing method of a semiconductor device for forming a diffusion resistance using an impurity diffusion layer in a substrate, in the invention according to claim 9,
(A) A gate electrode material for forming a gate electrode of the transistor is deposited and formed in each of the transistor formation region and the resistance element formation region on the semiconductor substrate each covered with an insulating film.

  (B) The deposited gate electrode material is etched to form a gate electrode in the transistor formation region, and a plurality of linear patterns orthogonal to the energization direction as the resistance element are formed in the resistance element formation region. An array is formed at equal intervals.

(C) Impurities are implanted into the semiconductor substrate using the etched gate electrode material as a mask, and an impurity diffusion layer is formed in the semiconductor substrate.
(D) The semiconductor substrate is heat-treated to promote physical connection in the semiconductor substrate of the impurity diffusion layer formed in each adjacent region below the plurality of linear patterns.
The process is provided.

  According to such a manufacturing method, a linear pattern made of the gate electrode material can be formed in the resistance element forming region in the same step as the step of forming the gate electrode in the transistor forming region. Therefore, an impurity diffusion layer can be formed in the substrate using the linear pattern itself as a mask, without requiring additional steps such as a photolithography process and an etching process using the mask. Further, since the shape of each of the impurity diffusion layers, that is, the diffusion resistance is determined by the linear pattern, a desired resistance element is formed with high accuracy as high as the accuracy obtained by the etching process. Will be able to. That is, by setting such a linear pattern to an arbitrary shape, it is possible to easily form a resistance element having a high accuracy and a desired resistance value.

Similarly, a transistor formation region where a transistor is formed and a resistance element formation region where a resistance element is formed are partitioned on a semiconductor substrate via an element isolation film, and the resistance element formation region includes the resistance element. In the invention according to claim 10, as a manufacturing method of a semiconductor device that forms a diffusion resistance using an impurity diffusion layer in a substrate as an element,
(A) A gate electrode material for forming a gate electrode of the transistor is deposited and formed in each of the transistor formation region and the resistance element formation region on the semiconductor substrate each covered with an insulating film.

  (B) The deposited gate electrode material is etched to form a gate electrode in the transistor formation region, and a plurality of equidistant lines orthogonal to the energization direction as the resistance element in the resistance element formation region A frame-like pattern connected to a strip-like line extending in parallel with the energizing direction as the resistance element at both ends thereof is formed.

(C) Impurities are implanted into the semiconductor substrate using the etched gate electrode material as a mask, and an impurity diffusion layer is formed in the semiconductor substrate.
(D) The semiconductor substrate is heat-treated to promote physical connection in the semiconductor substrate of the impurity diffusion layer formed in each adjacent region below the plurality of linear patterns.
The process is provided.

  Also by such a manufacturing method, a linear pattern made of the gate electrode material can be formed in the resistance element formation region in the same step as the step of forming the gate electrode in the transistor formation region. Therefore, an impurity diffusion layer can be formed in the substrate using the linear pattern itself as a mask, without requiring additional steps such as a photolithography process and an etching process using the mask. Further, since the linear pattern is formed in a frame shape, both the width and the length of the impurity diffusion layer, that is, the diffusion resistance are regulated by the linear pattern. It can be formed with high accuracy as much as the accuracy obtained by processing. That is, also in this case, it is possible to easily form a resistance element having a desired resistance value with high accuracy by setting the frame-like pattern to an arbitrary shape.

  In this case, as in the eleventh aspect of the present invention, the frame-shaped pattern is etched into the resistance element formation region as the resistance element between the resistance element formation region and the element isolation film. It is desirable that the boundary line parallel to the energization direction is covered with the belt-like line extending in parallel with the energization direction as the resistance element.

  As described above, according to the manufacturing method, the impurity diffusion layers formed in the adjacent regions below the linear pattern, that is, the diffusion resistors are formed without being in contact with the element isolation film. For this reason, even if such a device isolation film is formed by using, for example, the LOCOS method, even if there is a concern about bird's beaks or the like, the shape of the resistance element can be maintained with high accuracy without being affected by this. .

  Moreover, regarding the manufacturing method according to any one of the ninth to eleventh aspects, as in the invention according to the twelfth aspect, the etching formation of the linear patterns in the resistance element forming region is performed in the same line. It is particularly effective that the line width of the pattern is made narrower than the minimum gate length that can ensure the minimum channel length in the transistor.

  According to such a manufacturing method, each of the diffusion resistors formed in each adjacent region below each of the linear patterns is also brought into proximity in a manner corresponding to the line width of these linear patterns, and these diffusions are made. The physical connection of each of the resistors is further facilitated, and thus the electrical connection of the diffused resistors is more easily realized.

  Further, according to the method for manufacturing a semiconductor device according to any one of claims 9 to 12, according to the invention according to claim 13, the semiconductor substrate using the etched gate electrode material as a mask. It is particularly desirable that the impurity is implanted by oblique implantation of impurity ions with respect to the energization direction as the resistance element.

  According to such a manufacturing method, the impurity implanted into the semiconductor substrate is introduced in such a manner as to enter the lower portion of the gate electrode material used as a mask. For this reason, the physical connection of each diffusion resistance composed of the impurity diffusion layer formed in each adjacent region below each linear pattern is further promoted.

Moreover, regarding the manufacturing method of the semiconductor device according to any one of the ninth to thirteenth aspects, as a process prior to the process (d),
(D1) A sidewall is formed on each sidewall of the etched gate electrode material.

(D2) After the sidewalls are formed, impurities are again injected into the semiconductor substrate to form impurity diffusion layers that serve as the electrode portions of the resistance elements and the source / drain regions of the transistors.
And as a subsequent step of the step (d),
(D3) Silicide is selectively formed on the surface of the etched gate electrode material, the electrode portion of the resistance element, and the surface of the impurity diffusion layer serving as the source / drain region of the transistor.
It is desirable to further include such a process.

  According to such a manufacturing method, the sidewall is formed on the region where the diffusion resistance composed of the impurity diffusion layer is formed in the same step as the step of forming the sidewall on the sidewall of the gate electrode material of the transistor. Will be able to. In the subsequent step, that is, in the step of forming a silicide in a selective region on the substrate, the silicide is not formed on these sidewalls, so that the diffusion resistance can be maintained at a high resistance. . At this time, the silicide is formed on the selective region on the substrate, that is, on the surface of the impurity diffusion layer serving as the electrode portion of the resistive element and the source / drain region of the transistor. As a result, the speed of the semiconductor device can be increased.

  Further, in this case, as in the invention according to claim 15, the etching formation of each of the linear patterns in the resistance element forming region has an arrangement interval of the linear patterns of not more than twice the width of the sidewall. It is further desirable to carry out in such a manner. According to such a manufacturing method, the sidewalls are formed in such a manner that the gaps between the linear patterns are embedded. For this reason, it is possible to suppress the formation of silicide on the lower part of the gap between the linear patterns, that is, on the diffusion resistance formed in the semiconductor substrate, and to maintain such diffusion resistance at a high resistance.

Further, regarding the manufacturing method according to any one of claims 9 to 15, according to the invention according to claim 16,
(E) A wiring for applying a bias voltage is applied to the gate electrode material existing in the resistance element formation region.
You may make it further provide these processes.

  According to such a manufacturing method, even if each diffusion resistance composed of the impurity diffusion layer is formed without being physically connected to each other in the substrate, each linear shape composed of the gate electrode material is formed. By applying a bias voltage to the pattern, each of these diffused resistors can be electrically connected in the substrate. For this reason, the freedom degree about the arrangement | positioning aspect etc. of the said linear pattern can further be raised, and also the freedom degree concerning the setting of the resistance value as a diffused resistance will also be improved. In addition, since the potential of the gate electrode material is fixed by applying a bias voltage to the gate electrode material in this way, the charge is accumulated in the gate electrode material, resulting from this. The change in resistance value of the diffused resistor is suppressed, and the resistance element can be maintained in a more stable state.

  Further, regarding the manufacturing method according to any one of claims 9 to 16, it is effective to use polysilicon as the gate electrode material as in the invention according to claim 17. As described above, since this polysilicon is a material generally used for forming the gate electrode of a transistor, it is advantageous in terms of cost in manufacturing the semiconductor device, and the linear pattern or the frame shape is used. High controllability is maintained even when forming a pattern or the like.

(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 schematically shows a plan view of a semiconductor device according to this embodiment. FIGS. 2 and 3 show cross-sectional structures taken along lines AA and BB in FIG. Each is shown. The semiconductor device according to this embodiment is also basically a semiconductor device provided with a MOS transistor and a resistance element on the same semiconductor substrate as shown in FIGS. 21 to 23. In the following drawings, the same elements as those shown in FIGS. 21 to 23 are denoted by the same reference numerals and described.

  As shown in FIGS. 1 to 3, this semiconductor device includes a transistor TR1, a high-resistance resistance element R1 made of a diffused resistor, and an electrode portion RA1 on the same semiconductor substrate 1. The transistor TR1, the resistance element R1, and its electrode portion RA1 are formed in regions partitioned by the element isolation film 3 on the substrate 1, respectively.

  Of these transistors, the transistor TR1 is roughly formed on the substrate 1 via an oxide film (gate oxide film) 4 via a gate electrode 11b of the transistor and an LDD layer (electric field relaxation layer) of the transistor formed in the substrate 1. ) And a high concentration diffusion layer (n +) 15b which becomes a source / drain region of the transistor. The gate electrode 11b is made of polysilicon, and a sidewall 13b made of an insulating film is formed on the sidewall thereof. A silicide 17b is formed on the gate electrode 11b and the high-concentration diffusion layer 15b, and the resistance of each electrode portion of the transistor TR1 is reduced.

  On the other hand, the resistance element R1 is formed in the substrate 1 below the linear pattern 11a made of a gate electrode material (polysilicon) which is formed on the substrate 1 via the oxide film 4 and forms the gate electrode 11b. It consists of diffusion resistance using the low concentration diffusion layer 14c. The linear patterns 11a are orthogonal to the energizing direction as the resistor element R1, and are arranged at equal intervals. The line widths of these linear patterns 11a are formed narrower than the minimum gate length that can ensure the minimum channel length in the transistor TR1. Further, sidewalls 13a made of an insulating film are formed on the respective side walls of the linear patterns 11a, and the arrangement interval of the linear patterns 11a is set to be twice or less the width of the side walls. That is, sidewalls 13a are formed in such a manner that the gaps between these linear patterns 11a are filled, and low-concentration diffusion layers 14c are formed in the substrates 1 below these linear patterns 11a and sidewalls 13a. . High-concentration diffusion layers (n +) 15a to be the electrode portions RA1 of the resistance element R1 are formed at both ends of the low-concentration diffusion layer 14c in the energizing direction as the resistance element R1, and the silicide 17a is formed thereon. As a result, the resistance of the electrode portion RA1 is reduced. Similarly, silicide 17a is formed on each linear pattern 11a made of polysilicon, whereas no silicide is formed on the sidewall 13a. Thus, since silicide is selectively formed on the low concentration diffusion layer 14c, the resistance value of the diffusion resistance composed of the low concentration diffusion layer 14c is maintained at a high resistance.

  Next, a method for manufacturing the semiconductor device according to this embodiment will be described with reference to FIGS. 4A to 4E schematically show the cross-sectional structure corresponding to FIG. 2 in the cross-sectional structure of the semiconductor device according to this embodiment in accordance with the manufacturing process. FIGS. 5A to 5E schematically show a cross-sectional structure corresponding to FIG. 3 in the cross-sectional structure of the semiconductor device according to this embodiment in accordance with the manufacturing process. Furthermore, among these, the planar structures corresponding to FIGS. 4A and 5A, or FIGS. 4C and 5C are shown in FIGS. 6 and 7, respectively.

First, as shown in FIGS. 4A, 5A, and 6, for example, boron ions as a P-type impurity are implanted into a semiconductor substrate 1 made of silicon at about 1 × 10 ¹³ / cm ² by ion implantation. The well 2 is formed on the substrate 1 by introducing and performing heat treatment at about 1000 to 1050 ° C. An element isolation film 3 is formed on the substrate 1 on which the well 2 is formed by using, for example, an STI (shallow trench isolation) technique. Although the details of the process of forming the element isolation film 3 by the STI technique are not shown, specifically, the process is performed as follows. First, the substrate 1 is thermally oxidized at 850 to 900 ° C. to form a thermal oxide film having a thickness of 40 to 50 nm, and then a silicon nitride film is formed by LPCVD (low pressure vapor phase chemical deposition), and a photoresist mask is formed. The surface of the substrate 1 except the region where the element isolation film 3 is formed is covered. In this state, the thermal oxide film and the silicon nitride film are dry etched, the substrate 1 is dry etched using the photoresist mask, and a trench is formed by digging to a depth of 0.4 to 0.6 nm. Form. Thereafter, the photoresist mask is removed and thermal oxidation is performed. Then, a buried oxide film having a thickness of about 0.8 to 1.5 μm is deposited by, eg, CVD (chemical vapor deposition). After heat treatment at 1050 ° C., the silicon nitride film is polished by CMP (chemical mechanical polishing) as a stopper, and then the silicon nitride film is removed. Thereby, the element isolation film 3 is formed.

  Then, the element isolation film 3 formed in this manner partitions the resistance element formation region where the resistor element R1 and its electrode portion RA1 are formed on the substrate 1 and the transistor formation region where the transistor TR1 is formed. Is done. Next, the substrate 1 is subjected to, for example, wet thermal oxidation at 850 ° C. or dry oxidation at 950 to 1050 ° C., and the surface of the substrate 1 exposed in the resistance element formation region and the transistor formation region has a thickness of several nm to An oxide film (gate oxide film) 4 made of an insulating film such as a 20 nm silicon oxide film is formed.

Next, a polysilicon film having a thickness of about 180 to 200 nm is deposited and formed on the entire surface of the element isolation film 3 and the oxide film 4 by, for example, a CVD method. As this polysilicon film, for example, a film doped with an impurity such as phosphorus is used, and the impurity concentration can be adjusted to be about 1 × 10 ^{20 to} 3 × 10 ²⁰ / cm ³ . Then, a photoresist film (not shown) is formed on the polysilicon film, and the polysilicon film is etched by using a dry etching apparatus or the like using the photoresist film as a mask to pattern the polysilicon. Then, after the photoresist film is removed by, for example, a plasma ashing apparatus, a carros cleaning process or the like is performed to remove foreign matters generated in the etching process.

  The polysilicon film formed in the resistance element formation region by this etching process is composed of a plurality of linear patterns 11a orthogonal to the energizing direction as the resistance element R1, and the linear patterns 11a are arranged at equal intervals. . The line width of each linear pattern 11a is set to be narrower than the minimum gate length that can ensure the minimum channel length in the transistor TR1. In addition, the arrangement interval of the linear patterns 11a is set to be not more than twice the film thickness of the insulating film deposited to form the sidewall 13a formed in a later step.

  Thus, a plurality of linear patterns 11a made of polysilicon are formed in the resistance element formation region, and the gate electrode 11b is formed in the transistor formation region. Then, for example, by performing wet oxidation at about 850 ° C., an oxide film (not shown) of about 10 nm is formed on the side surfaces of the linear pattern 11a and the gate electrode 11b.

Next, in order to form an LDD layer (electric field relaxation layer) of the transistor, a photoresist (not shown) is applied on the substrate 1 and patterned by an exposure apparatus. When, for example, phosphorus ions are implanted using the linear pattern 11a, the gate electrode 11b, and the photoresist as a mask, for example, phosphorus ions are injected into the substrate 1 under the condition of acceleration energy of 40 to 70 keV. Ions are implanted so that the concentration of the impurity diffusion layer to be formed is about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm ³ . For example, when boron ions are implanted, the ions are similarly implanted under the condition of acceleration energy of about 20 to 40 keV. At this time, a predetermined conductivity type and junction depth are further obtained by repeating a plurality of photolithography steps and ion implantation steps in the transistor formation region in accordance with the type of transistor (for example, CMOS) and the target LDD layer. It is also possible to form an LDD layer having an impurity concentration. Then, after the photoresist is removed by ashing or the like, the substrate is washed to remove the photoresist in the substrate 1 corresponding to the space between the linear patterns 11a in the resistance element formation region, as shown in FIGS. 4B and 5B. A low-concentration diffusion layer (n−) 14a is formed, and a low-concentration diffusion layer (n−) 14b is formed in the substrate 1 in the transistor formation region. That is, the low-concentration diffusion layer 14a formed here is formed so as to be separated from each other through a gap substantially corresponding to the line width of each linear pattern 11a.

  Next, an insulating film made of an oxide film or a nitride film having a thickness of about 100 to 150 nm is formed on the entire surface of the substrate 1 by, for example, the CVD method. Then, when this insulating film is subjected to a well-known anisotropic dry etching process, the insulating film remains on the side wall of each linear pattern 11a in the resistance element forming region, thereby forming the sidewall 13a. The gap between the patterns 11a is filled. At this time, the side wall 13b is also formed on the side wall of the gate electrode 11b in the transistor formation region. Further, in the above process, the oxide film 4 on the region where the sidewall is not formed is removed by the etch back so that the surface of the substrate 1 is exposed. Then, in order to protect the exposed upper surface of the substrate 1 made of silicon, a protective film (not shown) having a thickness of about 5 nm is formed on the upper surface of the substrate 1 by performing a dry oxidation process or a wet oxidation process at about 850 ° C. To do.

Next, as shown in FIGS. 4C, 5C, and 7, a photoresist (not shown) is applied on the substrate 1 and patterned to form the source / drain regions of the transistor TR1. Then, impurities are ion-implanted into the substrate 1 using the sidewalls 13a and 13b, the linear pattern 11a, the gate electrode 11b, and the photoresist as a mask. In this step, for example, when the resistance of the source / drain region of the N-channel transistor is formed, arsenic ions are applied so that the concentration of the high-concentration diffusion layer is about 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ^3. Ions are implanted under the condition of acceleration energy of 40 to 70 keV. Further, for example, when forming a resistance of the source / drain region of a P-channel transistor, boron difluoride ions are ion-implanted under the condition of acceleration energy of 30 to 40 keV. In this way, the high concentration diffusion layer (n +) 15a that becomes the electrode portion RA1 of the resistance element R1 is formed in the area where the linear patterns 11a and the sidewalls 13a are not formed in the resistance element formation area on the substrate 1. In the transistor formation region, a high concentration diffusion layer (n +) 15b to be a source / drain region is formed.

  Next, after removing the photoresist, the substrate 1 is annealed at about 850 ° C. so that the low concentration diffusion layers 14a formed at equal intervals in the substrate 1 are electrically connected to the adjacent low concentration diffusion layers 14a. As shown in FIG. 4D and FIG. 5D, a low concentration diffusion layer (n−) 14c is formed. By this annealing treatment, the impurities in the low concentration diffusion layer 14c thus formed, the low concentration diffusion layer 14b, and the high concentration diffusion layers 15a and 15b are activated. Then, by performing wet processing or dry etching, the protective film described above is removed to expose the upper surface of the substrate 1 made of silicon and the upper surfaces of the linear patterns 11a made of polysilicon and the gate electrodes 11b.

  Next, as shown in FIGS. 4E and 5E, for example, a titanium film 17 is deposited on the entire surface of the substrate 1 as a refractory metal film by, for example, sputtering. Next, when the substrate 1 is heat-treated at about 650 to 700 ° C., a silicidation reaction occurs in a selective region on the substrate 1. That is, the titanium film 17 does not react with the sidewalls 13a and 13b and the element isolation film 3, and a silicide reaction occurs in other regions to form a silicide compound (silicic acid titanate). Then, the unreacted titanium film 17 is removed by wet etching, and a heat treatment at about 800 ° C. is performed, so that a selective region on the substrate 1 is finally obtained as shown in FIGS. Silicides 17a and 17b are formed only in the regions. That is, the silicide is not formed on the sidewall 13a in the upper portion of the low concentration diffusion layer 14c, so that the resistance element R1 is maintained at a high resistance.

  Further, in the resistance element R1 finally obtained in this manner, since the length of the diffusion resistance formed in parallel with the energizing direction is determined by each of the linear patterns 11a, the length of the diffusion resistance is set as described above. It can be formed with the same accuracy as the etching accuracy of each linear pattern 11a.

  As described above, in the method of manufacturing a semiconductor device according to this embodiment, a technique for finely forming the linear pattern 11a in the resistance element formation region and a salicide technique for selectively forming the silicides 17a and 17b on the substrate 1 are used. As a result, the resistance element R1 with high accuracy and high resistance can be formed while reducing the resistance of the semiconductor device.

As described above, according to the semiconductor device and the method of manufacturing a semiconductor substrate according to this embodiment, the effects listed below can be obtained.
(1) In the resistance element forming region in the substrate 1, a plurality of linear patterns 11a made of polysilicon are arranged at equal intervals perpendicular to the energizing direction as the resistance element R1, and the plurality of linear patterns are arranged. The low concentration diffusion layer 14a formed in each adjacent region below 11a is electrically connected to form a low concentration diffusion layer 14c. Thus, since the polysilicon used for the linear pattern 11a is a material generally used for forming a gate electrode of a transistor, it is advantageous in terms of cost in manufacturing the semiconductor device. Further, high controllability is maintained when forming the linear pattern and the like, and the length of the diffusion resistor formed in parallel with the energizing direction of the resistive element R1 is controlled to the same extent as the linear pattern. It becomes possible to form a fine pattern with good properties. In addition, the diffusion resistance formed in this way is configured to be electrically connected in the substrate 1, so that it can be physically desired in size and desired resistance value according to the number and length of the linear patterns. It becomes possible to form a resistance element having a high accuracy with a higher degree of freedom.

  (2) The plurality of linear patterns 11a have a structure in which the line width is formed narrower than the minimum gate length capable of ensuring the minimum channel length in the transistor TR1. As a result, each of the low concentration diffusion layers 14a formed in each adjacent region below each linear pattern 11a is also brought into proximity in a manner corresponding to such a line width. It becomes possible to short-circuit easily. That is, the electrical connection of each low concentration diffusion layer 14a can be realized more easily.

  (3) The resistance element R1 is electrically connected to the low concentration diffusion layers 14a located at both ends in the energizing direction as the resistance element R1 as the electrode portion RA1, and from the low concentration diffusion layer 14a. Also, a high concentration diffusion layer 15a in which high concentration impurities are diffused is formed. At least in the high concentration diffusion layer 15a that forms the electrode portion RA1, silicides 17a and 17b are formed together with the high concentration diffusion layer 15b that forms the source / drain region of the transistor TR1. As a result, it is possible to reduce the resistance of the electrode portion, and to increase the speed of the semiconductor device.

  (4) A sidewall 13a is formed on each side wall of the plurality of linear patterns 11a, and the arrangement interval of the linear patterns 11a is set to be twice or less the width of the sidewall 13a. As a result, the sidewalls 13a are formed in such a manner that the gaps between the linear patterns 11a are filled. Since no silicide is formed on the side wall 13a, it is possible to suppress the formation of silicide on the lower part of the gap between the linear patterns 11a, that is, on the low concentration diffusion layer 14c formed in the substrate 1. It is possible to maintain such a diffused resistance at a high resistance.

  (5) In manufacturing, first, polysilicon for forming the gate electrode of the transistor TR1 is deposited on each of the transistor formation region and the resistance element formation region on the substrate 1 each covered with an insulating film. To do. Thereafter, the deposited polysilicon film is etched to form a gate electrode 11b in the transistor formation region, and a plurality of linear patterns 11a orthogonal to the energizing direction as the resistance element R1 in the resistance element formation region. Are arranged at equal intervals. Then, impurities are implanted into the substrate 1 using the etched linear pattern 11a and gate electrode 11b as a mask, and low concentration diffusion layers 14a and 14b are formed in the substrate 1. Then, the low-concentration diffusion layer 14a is heat-treated to promote physical connection in the substrate 1 of the low-concentration diffusion layer 14a formed in each adjacent region below the plurality of linear patterns 11a. 14c was formed. According to such a manufacturing method, the linear pattern 11a can be formed in the same step as the step of forming the gate electrode of the transistor TR1. Therefore, the low concentration diffusion layer 14a can be formed in the substrate 1 using the linear pattern 11a itself as a mask without requiring a new process. In addition, since the shape of each of the low-concentration diffusion layers 14a, that is, the diffusion resistors is determined by the linear pattern 11a, a desired resistance element can be obtained with the same accuracy as that obtained by the etching process. R1 can be formed. That is, by setting such a linear pattern to an arbitrary shape, it is possible to easily form a resistance element having a high accuracy and a desired resistance value. Further, since the polysilicon employed as the gate electrode material is a material generally used for forming the gate electrode of a transistor as described above, it is advantageous in terms of cost in manufacturing the semiconductor device. High controllability is maintained even when the linear pattern 11a is formed.

  (6) As a step prior to the step of heat-treating the substrate 1, first, sidewalls 13a are formed on the respective side walls of the etched linear pattern 11a. Thereafter, impurities were again injected into the substrate 1 to form the high concentration diffusion layers 15a and 15b serving as the electrode portion RA1 of the resistor element R1 and the source / drain regions of the transistor TR1. Similarly, after the step of heat-treating the substrate 1, the surface of the etched linear pattern 11a, the electrode portion RA1 of the resistance element R1, and the high-concentration diffusion layer 15a serving as the source / drain regions of the transistor TR1, Silicides 17a and 17b were selectively formed on the surface of 15b. According to such a manufacturing method, the sidewall 13a can be formed on the region where the diffusion resistance is formed in the same step as the step of forming the sidewall 13b on the sidewall of the gate electrode 11b of the transistor TR1. It becomes like this. In the subsequent step, that is, in the step of forming the silicides 17a and 17b in the selective region on the substrate 1, the silicides 17a and 17b are not formed on the sidewalls 13a and 13b. Be able to maintain resistance. At this time, the silicides 17a and 17b are formed in selective regions on the substrate 1, that is, on the surfaces of the high-concentration diffusion layers 15a and 15b serving as the electrode portion RA1 of the resistor element R1 and the source / drain regions of the transistor TR1. Therefore, the resistance of these regions can be reduced, and as a result, the speed of the semiconductor device can be increased.

(Second Embodiment)
Next, a second embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. FIG. 8 schematically shows a plan view of the semiconductor device according to this embodiment, and FIGS. 9 and 10 show cross-sectional structures taken along lines CC and DD in FIG. Each is shown. The basic structure of the semiconductor device according to this embodiment is similar to that of the first embodiment, but the structure of the resistance element and the manufacturing method thereof are the same as those of the first embodiment. The form is different. In these drawings, the same elements as those shown in FIGS. 1 to 7 are denoted by the same reference numerals, and overlapping description of these elements is omitted.

  As shown in FIGS. 8 to 10, the semiconductor device according to this embodiment includes a transistor TR2, a high-resistance resistor element R2 made of a diffused resistor, and an electrode portion RA2 on the same substrate 1. ing. The transistor TR2, the resistance element R2, and its electrode portion RA2 are formed in regions partitioned by the element isolation film 3 on the substrate 1, respectively.

  Among these, the structure of the transistor TR3 is the same as the structure shown in the first embodiment. More specifically, a gate electrode 21b formed on the substrate 1 with the gate oxide film 4 interposed therebetween, and a low-concentration diffusion layer 24b formed in the substrate 1 and serving as an LDD layer (electric field relaxation layer) of the transistor TR3 And a high-concentration diffusion layer 25b serving as a source / drain region. A side wall 23b is formed on the side wall of the gate electrode 21b, and a silicide 27b is formed on the gate electrode 21b and the high-concentration diffusion layer 25b.

  On the other hand, the resistance element R2 is formed of a diffusion resistance using a low concentration diffusion layer 24a formed below the linear pattern 21a made of polysilicon formed on the substrate 1 via the oxide film 4. The shape and arrangement of the linear pattern 21a made of polysilicon are the same as those in the first embodiment, and the line width of each linear pattern 21a is the minimum channel length in the transistor TR2. It is set narrower than the minimum gate length that can be secured. In addition, the arrangement interval of the linear patterns 21a is set to be not more than twice the film thickness of the insulating film deposited to form the sidewalls 23a formed in the subsequent process. Embedded. A low concentration diffusion layer 24a is formed in the substrate 1 below the sidewall 23a so as to be separated from the adjacent low concentration diffusion layer 24a. Further, high-concentration diffusion layers 25a serving as electrode portions RA2 of the resistance element R2 are formed at both ends of the low-concentration diffusion layer 24a in the energizing direction as the resistance element R2. A silicide 27a is formed on the high concentration diffusion layer 25a and the linear pattern 21a.

  Here, in the semiconductor device according to this embodiment, a bias voltage is applied from the power supply terminal T to each of the silicides 27a formed on the respective linear patterns 21a. As a result, the low-concentration diffusion layers 24a formed in the substrate 1 so as to be separated from each other are short-circuited and are electrically connected.

  Next, a method for manufacturing the semiconductor device according to this embodiment will be described. The manufacturing method of the semiconductor device according to this embodiment is basically the same as the manufacturing method described in the first embodiment. That is, the gate electrode material (polysilicon) is deposited and formed on the transistor formation region and the resistance element formation region on the substrate 1 via the oxide film (gate oxide film) 4. Next, the deposited gate electrode material is etched to form gate electrodes 21b in the transistor formation region, and linear patterns 21a made of polysilicon are arranged in the resistor element formation region at regular intervals. Next, impurities are ion-implanted into the substrate 1 using the linear patterns 21a and the gate electrodes 21b as masks to form low concentration diffusion layers (n−) 24a and 24b in the substrate 1. Then, side walls 23a and 23b are formed on the side walls of the linear patterns 21a and the gate electrodes 21b, respectively, and impurities are ion-implanted again into the substrate 1, and the electrode portion RA2 of the resistance element R2 and the source / drain of the transistor TR2 are formed. (N +) high-concentration diffusion layers 25a and 25b serving as regions are formed. Silicides 27a and 27b are formed on the electrode portion RA2 of the resistor element R2 and the electrode portions of the transistor TR2.

  In the method of manufacturing the semiconductor device according to this embodiment, wiring for applying a bias voltage from the power supply terminal T is formed in each linear pattern 21a formed in the resistance element formation region. That is, a bias voltage is applied to the silicide 27a formed on the upper part of each linear pattern 21a arranged at equal intervals as described above. As a result, the low-concentration diffusion layer (n−) 24a formed in the substrate 1 without being physically connected to each other and separated from each other is electrically connected, for example, as in the on-control of the transistor. Become. Further, by applying a bias voltage to each linear pattern 21a in this way, the potential of these linear patterns 21a made of polysilicon is fixed, and charge accumulation in each linear pattern 21a can be reduced. Thus, a change in the resistance value of the diffused resistor caused by this is suppressed. For this reason, the formed resistance element R2 is maintained in a more stable state.

  As described above, the semiconductor device and the manufacturing method thereof according to the second embodiment also have effects equivalent to or equivalent to the effects (1) to (6) according to the first embodiment. In addition, the following effects can be obtained.

  (7) In the resistive element formation region in the substrate 1, a plurality of linear patterns 21a made of polysilicon are arranged at equal intervals orthogonal to the energizing direction as the resistive element R2, and the linear patterns 21a The low concentration diffusion layer 24a is formed in each adjacent region below. Each of the low-concentration diffusion layers 24a is electrically connected in the substrate 1 based on application of a bias voltage to each linear pattern 21a. As a result, the diffusion resistance using the low-concentration diffusion layer 24a in the substrate 1 can be formed in a form having a fine pattern with the same controllability as the linear pattern 21a. Moreover, according to the above structure, even if such diffused resistors are formed in the substrate 1 without being physically connected to each other, they are separated by application of the bias voltage of each linear pattern 21a. Each of these diffused resistors is electrically connected in the substrate as in the case of on control. For this reason, it becomes possible to form a resistance element having a physically desired size and a desired resistance value according to the number and length of the linear patterns with higher flexibility and high accuracy. In addition, by applying a bias voltage to each linear pattern 21a in this way, the potential of the linear pattern 21a made of polysilicon is fixed, so that charge accumulation in each linear pattern 21a Further, the change in resistance value of the diffused resistor caused by this is suppressed, and the resistance element R2 can be maintained in a more stable state.

(Other embodiments)
The semiconductor device and the manufacturing method thereof according to the present invention are not limited to the structure or the manufacturing method shown as the first and second embodiments, and may be implemented in the following modes appropriately changed. it can.

  In each of the above embodiments, the element isolation film 3 for partitioning the resistance element formation region and the transistor formation region is formed on the semiconductor substrate 1 by the STI technique, but the formation method is arbitrary, for example, You may make it form by the LOCOS method.

  In the first embodiment, as illustrated in FIG. 1, a plurality of linear patterns 11a made of a gate electrode material formed in the resistance element formation region and having a predetermined line width are arranged at equal intervals. They were arranged independently. Instead, as shown in FIGS. 11 to 13, one or both of the end portions of each linear pattern 11 a are the same gate laid in parallel with the energizing direction as the resistive element. It is good also as a structure electrically connected by electrode material. Here, FIG. 11 schematically shows the planar structure of such a semiconductor device. FIGS. 12, 13A and 13B are respectively the EE line and the FF line of FIG. And a cross-sectional structure along the line F′-F ′. The structure of such a semiconductor device will be described with reference to these drawings. This semiconductor device includes a transistor TR3, a resistance element R3, and its electrode portion RA3 on the same substrate 1, and the basic structure as a semiconductor device is the same as that of each of the previous embodiments. However, the pattern made of the gate electrode material formed in the resistance element formation region is a frame-shaped pattern 31a in which the linear patterns are connected by a strip-like line extending in parallel with the energization direction as the resistance element R3. Accordingly, the structure of the low concentration diffusion layer 34c formed in the substrate 1 therebelow is also different from the above embodiments. That is, of the shape of the low-concentration diffusion layer 34c, the width on the side orthogonal to the energizing direction as the resistance element R3 is regulated by the frame-shaped pattern 31a. It is formed without touching. Next, a method for manufacturing this semiconductor device will be described with reference to FIGS. 14 and 15 schematically show the planar structure corresponding to FIG. 11 according to the manufacturing process. The manufacturing method of this semiconductor device is basically the same as the manufacturing method shown in each of the previous embodiments. That is, first, as shown in FIG. 14, a gate electrode material layer is deposited and formed in the transistor formation region and the resistance element formation region on the substrate 1 through the oxide film (gate oxide film) 4. Next, the deposited gate electrode material layer is etched to form the gate electrode 31b in the transistor formation region and the frame-shaped pattern 31a made of the gate electrode material in the resistance element formation region formation region. At this time, the frame-shaped pattern 31a is formed in such a manner that a boundary line parallel to the energizing direction as the resistive element between the resistive element forming region and the element isolation film 3 is covered. Next, impurities are ion-implanted into the substrate 1 using the frame-shaped pattern 31a and the gate electrode 31b as a mask to form low-concentration diffusion layers (n−) 34b and 34c in the substrate 1. Then, as shown in FIG. 15, side walls 33a and 33b are formed on the side walls of the frame-shaped pattern 31a and the gate electrode 31b, respectively, and impurities are ion-implanted into the substrate 1 again. High-concentration diffusion layers (n +) 35a and 35b are formed as source / drain regions of the electrode portion RA3 and the transistor TR3. As shown in FIG. 11, silicides 37a and 37b are finally formed on the electrode portion RA3 of the resistance element R3 and the electrode portions of the transistor TR3. Thus, by forming the frame-shaped pattern 31a made of the gate electrode material, both the width and the length of the diffused resistor are regulated. It can be formed with high accuracy as high as the accuracy obtained by the etching process of 31a. Further, by setting such a frame-shaped pattern 31a to an arbitrary shape, it is possible to easily form a resistance element having a high accuracy and a desired resistance value. In addition, since each of the diffusion resistors does not contact the element isolation film 3, even if there is a concern about bird's beak when the element isolation film 3 is formed using, for example, the LOCOS method, the above-described diffusion resistance is not affected. The shape of the resistive element R3 can be maintained with high accuracy.

  The frame-shaped pattern made of such a gate electrode material can also be applied to the semiconductor device shown in the second embodiment. In this case, the location where the bias voltage is applied to the pattern made of such a gate electrode material can be narrowed down to one location, and the wiring structure can be simplified. A semiconductor device having such a structure will be described with reference to FIG. This semiconductor device includes a transistor TR4, a resistor element R4, and its electrode portion RA4 on the same substrate 1, and a frame-like pattern made of a gate electrode material is formed in the resistor element formation region, thereby forming a transistor. A gate electrode is formed in the region. Further, side walls 43a and 43b are formed on these side walls, respectively. Then, the high concentration diffusion layer (n +) 45a serving as the electrode portion RA4 of the resistance element R4 and the high concentration diffusion layer (n +) 45b serving as the source / drain region of the transistor TR4 are selectively formed on each electrode portion. Silicides 47a and 47b are formed on the substrate. Then, a wiring for applying the bias voltage from the power supply terminal T is formed at one position of the silicide 47a formed on the frame pattern made of the gate electrode material. As a result, the location where the bias voltage is applied to the pattern made of the gate electrode material can be reduced to one location, and the wiring structure can be simplified. By applying such a bias voltage, the low-concentration diffusion layer (n−) formed in the substrate 1 is more reliably connected electrically, and the potential of the pattern made of the gate electrode material is fixed, so that the resistance The resistance value as the element R4 is also maintained in a more stable state.

  In each of the above embodiments, in order to form the low concentration diffusion layer (n−) serving as the diffusion resistance and the low concentration diffusion layer (n−) serving as the LDD layer of the transistor, a step of ion implantation into the substrate is provided. However, this ion implantation may be performed by oblique implantation of impurity ions with respect to the energization direction as the resistance element. Specifically, by implanting ions from an oblique direction so as to form an angle of, for example, about 30 to 40 ° with respect to the substrate 1, the impurity implanted into the substrate becomes a pattern (line) made of the gate electrode material. The linear pattern 21a, or the linear portion of the frame-shaped pattern 31a) is introduced in a mode of entering. For this reason, the physical connection of each diffusion resistance composed of the low-concentration diffusion layer formed in the adjacent region below each linear pattern is further promoted.

  Each of the above embodiments is known as a structure for suppressing the short channel effect of a transistor, for example, and also in a transistor having a halo structure having an impurity diffusion layer of the same conductivity type as that of the substrate 1 at the source / drain region end of the transistor. Can be applied. In this Halo structure transistor, since a method of introducing impurities into the substrate by oblique implantation of impurity ions is generally employed, oblique ions of impurity ions into the resistance element formation region as described above. When the implantation is employed, the impurity can be implanted into the transistor region in the same process.

  In each of the above embodiments, the well 2 and the low-concentration diffusion layer and the high-concentration diffusion layer are formed by implanting impurities into the substrate. The impurity introduced in each of these steps is arbitrary as long as it provides p-type or n-type conductivity. For example, boron, indium and the like can be appropriately used for p-type impurities, and phosphorus, arsenic, antimony and the like can be appropriately used for n-type impurities.

  The manufacturing methods such as various materials constituting the semiconductor device employed in each of the above embodiments, the film forming method, and the patterning method are not limited to these. For example, the gate electrode material is not limited to polysilicon, and any material can be used as long as it can be patterned with the same controllability. Further, for example, any other material can be adopted for the titanium film formed during silicide formation as long as it is a refractory metal material.

The top view which shows typically the planar structure about 1st Embodiment of the semiconductor device concerning this invention. FIG. 2 is a cross-sectional view schematically showing a cross-sectional structure along the line AA in FIG. 1. Sectional drawing which shows typically the cross-sectional structure along the BB line of FIG. (A)-(e) is sectional drawing which shows typically the manufacturing procedure about the manufacturing method of the semiconductor device of the 1st Embodiment. (A)-(e) is sectional drawing which shows typically the manufacturing procedure about the manufacturing method of the semiconductor device of the 1st Embodiment. FIG. 5 is a plan view schematically showing a planar structure of the semiconductor device corresponding to FIG. FIG. 5 is a plan view schematically showing a planar structure of a semiconductor device corresponding to FIG. The top view which shows typically the planar structure about 2nd Embodiment of the semiconductor device concerning this invention. Sectional drawing which shows the cross-section along the CC line | wire of FIG. Sectional drawing which shows the cross-sectional structure along the DD line | wire of FIG. The top view which shows typically the planar structure about one Embodiment of the semiconductor device concerning this invention. FIG. 12 is a cross-sectional view schematically showing a cross-sectional structure along the line EE in FIG. 11. (A) is sectional drawing which shows typically the cross-section along the FF line of FIG. FIG. 12B is a cross-sectional view schematically showing a cross-sectional structure along the line F′-F ′ in FIG. 11. The top view which shows typically the manufacture procedure about the manufacturing method of the semiconductor device of one Embodiment of the semiconductor device concerning this invention. The top view which shows typically the manufacture procedure about the manufacturing method of the semiconductor device of one Embodiment of the semiconductor device concerning this invention. The top view which shows typically the planar structure about one Embodiment of the semiconductor device concerning this invention. (A)-(f) is sectional drawing which shows the manufacturing procedure typically about the manufacturing method of the conventional semiconductor device. FIG. 18 is a plan view schematically showing a planar structure of the semiconductor device corresponding to FIG. FIG. 18 is a plan view schematically showing a planar structure of the semiconductor device corresponding to FIG. FIG. 18 is a plan view schematically showing a planar structure of the semiconductor device corresponding to FIG. The top view which shows typically the planar structure about the structure of the conventional semiconductor device. FIG. 22 is a cross-sectional view schematically showing a cross-sectional structure along the line GG in FIG. 21. FIG. 22 is a cross-sectional view schematically showing a cross-sectional structure along the line HH in FIG. 21. (A)-(e) is sectional drawing which shows the manufacturing procedure typically about the manufacturing method of the conventional semiconductor device. (A)-(e) is sectional drawing which shows the manufacturing procedure typically about the manufacturing method of the conventional semiconductor device. FIG. 25 is a plan view schematically showing a planar structure of the semiconductor device corresponding to FIG. FIG. 25 is a plan view schematically showing a planar structure of the semiconductor device corresponding to FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Well, 3 ... Element isolation film, 4 ... Oxide film (gate oxide film), 11a ... Linear pattern, 11b ... Gate electrode, 13a, 13b ... Side wall, 14a-14c ... Low concentration diffusion 15a, 15b ... high concentration diffusion layer, 17 ... titanium film, 17a, 17b ... silicide, 21a ... linear pattern, 21b ... gate electrode, 23a, 23b ... sidewall, 24a, 24b ... low concentration diffusion layer, 25a 25b ... High concentration diffusion layer, 27a, 27b ... Silicide, 31a ... Frame-shaped pattern, 31b ... Gate electrode, 33a, 33b ... Side wall, 34b, 34c ... Low concentration diffusion layer, 35a, 35b ... High concentration diffusion layer 37a, 37b ... silicide, 43a, 43b ... sidewall, 47a, 47b ... silicide, 71a, 71b ... gate electrode material 73a, 73b ... sidewalls, 74a, 74b ... low concentration diffusion layer, 75a, 75b ... high concentration diffusion layer, 77 ... titanium film, 77a, 77b ... silicide, 81a ... gate electrode material layer, 81b ... gate electrode, 83a 83b ... sidewalls, 84a, 84b ... low concentration diffusion layers, 85a, 85b ... high concentration diffusion layers, 87 ... titanium films, 87a, 87b ... silicide, 90 ... resists, R1-R4, R7, R8 ... resistance elements, TR1 to TR4, TR7, TR8... Transistor, RA1 to RA4, RA7, RA8.

Claims (17)

On the semiconductor substrate, a transistor formation region in which a transistor is formed and a resistance element formation region in which a resistance element is formed are partitioned through an element isolation film, and the resistance element formation region includes the resistance element as the resistance element. A semiconductor device in which a diffusion resistance using an impurity diffusion layer in a substrate is formed,
In the resistance element formation region, a plurality of linear patterns made of a gate electrode material for forming the gate electrode of the transistor and perpendicular to the energizing direction as the resistance element are arranged at equal intervals. A diffused resistor formed in each adjacent region below a pattern is electrically connected in the semiconductor substrate. On the semiconductor substrate, a transistor formation region in which a transistor is formed and a resistance element formation region in which a resistance element is formed are partitioned through an element isolation film, and the resistance element formation region includes the resistance element as the resistance element. A semiconductor device in which a diffusion resistance using an impurity diffusion layer in a substrate is formed,
In the resistance element formation region, a plurality of linear patterns made of a gate electrode material for forming the gate electrode of the transistor and perpendicular to the energizing direction as the resistance element are arranged at equal intervals, and each of these linear patterns A diffusion resistor is formed in each adjacent region below the pattern, and each of the diffusion resistors is electrically connected in the semiconductor substrate based on application of a bias voltage to each linear pattern. A semiconductor device. Each of the linear patterns arranged in the resistance element formation region is electrically connected by the same gate electrode material laid at least one of the end portions in parallel with the energization direction as the resistance element. Item 3. The semiconductor device according to Item 2. Each of the linear patterns arranged in the resistance element formation region is electrically connected by the same gate electrode material laid in parallel to the energization direction as the resistance element at both ends thereof, The semiconductor device according to claim 2, wherein a length of each diffusion resistance that determines a width as a resistance element is regulated by the gate electrode material laid in parallel. 5. The plurality of linear patterns made of the gate electrode material are formed so that a line width thereof is narrower than a minimum gate length capable of ensuring a minimum channel length in the transistor. 6. Semiconductor device. Impurity diffusion in which the resistance element is electrically connected to diffusion resistors located at both ends in the energizing direction as the resistance element, and impurities having a higher concentration than the diffusion resistance are diffused as electrode portions of the resistance element. A silicide is formed together with the impurity diffusion layers forming the source / drain regions of the transistor, at least in the impurity diffusion layers forming the electrode portions. The semiconductor device according to one item. 7. A sidewall is formed on each side wall of the plurality of linear patterns made of the gate electrode material, and an arrangement interval between the linear patterns is set to be twice or less a width of the sidewall. A semiconductor device according to 1. The semiconductor device according to claim 1, wherein the gate electrode material is made of polysilicon. A transistor formation region in which a transistor is formed and a resistance element formation region in which a resistance element is formed are partitioned on a semiconductor substrate via an element isolation film, and the resistance element formation region includes the resistance element in the substrate. A method for manufacturing a semiconductor device for forming a diffusion resistance using an impurity diffusion layer of
Depositing and forming a gate electrode material for forming a gate electrode of the transistor in each of the transistor formation region and the resistance element formation region on the semiconductor substrate each covered with an insulating film;
The deposited gate electrode material is etched to form a gate electrode in the transistor formation region, and a plurality of linear patterns orthogonal to the energizing direction as the resistance element are formed at equal intervals in the resistance element formation region. An array forming step;
Injecting impurities into the semiconductor substrate using the etched gate electrode material as a mask, and forming an impurity diffusion layer in the semiconductor substrate;
And a step of heat-treating the semiconductor substrate to promote physical connection in the semiconductor substrate of impurity diffusion layers formed in each adjacent region below the plurality of linear patterns. A method for manufacturing a semiconductor device. A transistor formation region in which a transistor is formed and a resistance element formation region in which a resistance element is formed are partitioned on a semiconductor substrate via an element isolation film, and the resistance element formation region includes the resistance element in the substrate. A method for manufacturing a semiconductor device for forming a diffusion resistance using an impurity diffusion layer of
Depositing and forming a gate electrode material for forming a gate electrode of the transistor in each of the transistor formation region and the resistance element formation region on the semiconductor substrate each covered with an insulating film;
The deposited gate electrode material is etched to form a gate electrode in the transistor formation region, and a plurality of equally spaced linear patterns orthogonal to the energizing direction as the resistance element are formed in the resistance element formation region. Forming a frame-like pattern connected to a strip-like line extending in parallel with the energization direction as the resistance element at both ends;
Injecting impurities into the semiconductor substrate using the etched gate electrode material as a mask, and forming an impurity diffusion layer in the semiconductor substrate;
And a step of heat-treating the semiconductor substrate to promote physical connection in the semiconductor substrate of impurity diffusion layers formed in each adjacent region below the plurality of linear patterns. A method for manufacturing a semiconductor device. Etching formation of the frame-shaped pattern in the resistance element formation region has a boundary line parallel to the current direction as the resistance element between the resistance element formation region and the element isolation film as a current direction as the resistance element. The method for manufacturing a semiconductor device according to claim 10, wherein the method is performed in such a manner as to be covered by the strip-like lines extending in parallel. The etching formation of each of the linear patterns in the resistance element forming region is performed in such a manner that the line width of the linear pattern is narrower than the minimum gate length that can ensure the minimum channel length in the transistor. The manufacturing method of the semiconductor device as described in any one of -11. The impurity implantation into the semiconductor substrate using the etched gate electrode material as a mask is performed by oblique implantation of impurity ions with respect to the energization direction as the resistive element. The manufacturing method of the semiconductor device of description. In the manufacturing method of the semiconductor device according to any one of claims 9 to 13,
As a step prior to the step of heat-treating the semiconductor substrate, a step of forming a sidewall on each side wall of the etched gate electrode material, and an impurity is injected again into the semiconductor substrate after the formation of the sidewall, A step of forming an impurity diffusion layer serving as an electrode portion of the resistance element and a source / drain region of the transistor, and a surface of the etched gate electrode material as a subsequent step of the step of heat-treating the semiconductor substrate The method further includes the step of selectively forming silicide on the surface of the impurity diffusion layer serving as the electrode portion of the resistance element and the source / drain region of the transistor. The manufacturing of a semiconductor device according to claim 14, wherein the etching of the linear patterns in the resistance element forming region is performed in a mode in which an arrangement interval of the linear patterns is equal to or less than twice the width of the sidewall. Method. In the manufacturing method of the semiconductor device according to any one of claims 9 to 15,
A method of manufacturing a semiconductor device, further comprising a step of providing a wiring for applying a bias voltage to the gate electrode material existing in the resistance element formation region. The method for manufacturing a semiconductor device according to claim 9, wherein polysilicon is used as the gate electrode material.

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