JP2006048015A5 - - Google Patents
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- JP2006048015A5 JP2006048015A5 JP2005189275A JP2005189275A JP2006048015A5 JP 2006048015 A5 JP2006048015 A5 JP 2006048015A5 JP 2005189275 A JP2005189275 A JP 2005189275A JP 2005189275 A JP2005189275 A JP 2005189275A JP 2006048015 A5 JP2006048015 A5 JP 2006048015A5
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Claims (9)
前記複数の画素の各々は、発光素子、第１のトランジスタ、第２のトランジスタ及び容量素子を有し、
前記第１のトランジスタは、ゲートはゲート線に、ソース又はドレインの一方はソース線に、ソース又はドレインの他方は前記第２のトランジスタのゲートに電気的に接続され、
前記第２のトランジスタは、ソース又はドレインの一方は電源線に、ソース又はドレインの他方は前記発光素子に電気的に接続され、
前記容量素子は、一方の電極は前記第２のトランジスタのゲートに、他方の電極は前記第２のトランジスタのソース又はドレインの一方に電気的に接続され、
前記ソースドライバは、パルス出力回路、ラッチ回路及び前記信号を生成する回路から出力される第１の信号に基づき動作する選択回路を有し、
前記第１のゲートドライバと前記第２のゲートドライバの各々は、パルス出力回路と、前記信号を生成する回路から出力される第２の信号と第３の信号に基づき動作するバッファ回路を有することを特徴とする表示装置。 A pixel area including a plurality of pixels, a source driver, a first gate driver, a circuit for generating a second gate driver and signals,
Each of the plurality of pixels includes light emitting element, a first transistor capacitor, a second transistor motor, and a capacitor,
In the first transistor, the gate is electrically connected to the gate line, one of the source and the drain is electrically connected to the source line, and the other of the source and the drain is electrically connected to the gate of the second transistor,
In the second transistor, one of a source and a drain is electrically connected to a power supply line, and the other of the source and the drain is electrically connected to the light-emitting element,
The capacitor element has one electrode electrically connected to the gate of the second transistor and the other electrode electrically connected to one of a source and a drain of the second transistor,
The source driver includes a pulse output circuits, the selection circuit operates based on a first signal output from the circuit for generating the latch circuits and the signal,
Each of the first gate driver and the second gate driver includes a pulse output circuit, and a buffer circuit that operates based on the second signal and the third signal output from the circuit that generates the signal. A display device.
前記複数の画素の各々は、発光素子、第１のトランジスタ、第２のトランジスタ及び容量素子を有し、
前記第１のトランジスタは、ゲートはゲート線に、ソース又はドレインの一方はソース線に、ソース又はドレインの他方は前記第２のトランジスタのゲートに電気的に接続され、
前記第２のトランジスタは、ソース又はドレインの一方は電源線に、ソース又はドレインの他方は前記発光素子に電気的に接続され、
前記容量素子は、一方の電極は前記第２のトランジスタのゲートに、他方の電極は前記第２のトランジスタのソース又はドレインの一方に電気的に接続され、
前記ソースドライバは、パルス出力回路、ラッチ回路及び前記信号を生成する回路から出力される第１の信号に基づき動作する選択回路を有し、
前記第１のゲートドライバと前記第２のゲートドライバの各々は、パルス出力回路と、前記信号を生成する回路から出力される第２の信号と第３の信号に基づき動作するバッファ回路を有し、
前記バッファ回路は、少なくとも３つの入力ノードと、１つの出力ノードとを有し、
前記３つの入力ノードのうち、１つは前記パルス出力回路に電気的に接続され、１つは第１の信号線を介して前記信号を生成する回路に電気的に接続され、残りの１つは第２の信号線を介して前記信号を生成する回路に電気的に接続され、
前記出力ノードは前記ゲート線に電気的に接続されることを特徴とする表示装置。 A pixel area including a plurality of pixels, a source driver, a first gate driver, a circuit for generating a second gate driver and signals,
Each of the plurality of pixels includes light emitting element, a first transistor capacitor, a second transistor motor, and a capacitor,
In the first transistor, the gate is electrically connected to the gate line, one of the source and the drain is electrically connected to the source line, and the other of the source and the drain is electrically connected to the gate of the second transistor,
In the second transistor, one of a source and a drain is electrically connected to a power supply line, and the other of the source and the drain is electrically connected to the light-emitting element,
The capacitor element has one electrode electrically connected to the gate of the second transistor and the other electrode electrically connected to one of a source and a drain of the second transistor,
The source driver includes a pulse output circuits, the selection circuit operates based on a first signal output from the circuit for generating the latch circuits and the signal,
Each of said first gate driver second gate driver includes a pulse output circuit, a buffer circuit operating on the basis of the second and third signals that will be output from the circuit for generating the signal ,
The buffer circuit has at least three input nodes and one output node;
Among the three input nodes, one is electrically connected to the pulse output circuit, one is electrically connected to a circuit for generating the signal through a first signal line, the remaining one Is electrically connected to a circuit for generating the signal via a second signal line,
Display said output node, wherein Rukoto is electrically connected to the gate line.
前記第１の信号は、ソース用制御信号であることを特徴とする表示装置。The display device, wherein the first signal is a source control signal.
前記第２の信号は第１のゲート用制御信号であり、前記第３の信号は第２のゲート用制御信号であることを特徴とする表示装置。The display device, wherein the second signal is a first gate control signal, and the third signal is a second gate control signal.
前記第２の信号はゲート用制御信号であり、前記第３の信号はパルス幅制御信号であることを特徴とする表示装置。The display device, wherein the second signal is a gate control signal, and the third signal is a pulse width control signal.
前記第２の信号と前記第３の信号の少なくとも一方は、第１の電位のときの第１の期間と、第２の電位のときの第２の期間の長さが異なる信号であることを特徴とする表示装置。 In claim 1 or claim 2,
At least one of the second signal and the third signal is a signal in which the length of the first period at the first potential is different from the length of the second period at the second potential. Characteristic display device.
前記第２のトランジスタは、線形領域で動作することを特徴とする表示装置。 In any one of Claims 1 thru | or 6 ,
The display device, wherein the second transistor operates in a linear region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005189275A JP4879522B2 (en) | 2004-06-29 | 2005-06-29 | Display device and electronic apparatus using the same |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004192157 | 2004-06-29 | ||
| JP2004192157 | 2004-06-29 | ||
| JP2005189275A JP4879522B2 (en) | 2004-06-29 | 2005-06-29 | Display device and electronic apparatus using the same |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006048015A JP2006048015A (en) | 2006-02-16 |
| JP2006048015A5 true JP2006048015A5 (en) | 2008-05-15 |
| JP4879522B2 JP4879522B2 (en) | 2012-02-22 |
Family
ID=36026566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005189275A Expired - Fee Related JP4879522B2 (en) | 2004-06-29 | 2005-06-29 | Display device and electronic apparatus using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4879522B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5214194B2 (en) | 2007-08-10 | 2013-06-19 | 住友化学株式会社 | Organic electroluminescence device including metal-doped molybdenum oxide layer and manufacturing method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4092857B2 (en) * | 1999-06-17 | 2008-05-28 | ソニー株式会社 | Image display device |
| JP2001324958A (en) * | 2000-03-10 | 2001-11-22 | Semiconductor Energy Lab Co Ltd | Electronic device and driving method therefor |
-
2005
- 2005-06-29 JP JP2005189275A patent/JP4879522B2/en not_active Expired - Fee Related
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