JP4879522B2 - Display device and electronic apparatus using the same - Google Patents

Description

The present invention relates to a display device including a light-emitting element, a driving method thereof, and a television device.

The present invention also relates to an electronic device using a display device including a light emitting element.

In recent years, the development of display devices including light emitting elements typified by EL (Electro Luminescence) elements has been promoted, and a wide range of uses is expected by taking advantage of self-luminous type such as high image quality, wide viewing angle, thinness, and light weight. Has been.

In a display device including a light emitting element, by using a novel driving method and circuit, luminance shortage due to a decrease in duty ratio (a ratio of a light emitting period to a total period of a light emitting period and a non-light emitting period) is started. There is one that aims to improve the problem described above (for example, see Patent Document 1). The above-mentioned Patent Document 1 is characterized in that a signal is written to a plurality of different stages of pixels within one gate signal line selection period. As a result, in a pixel at a certain stage, the time from when a signal is input to when the next signal is input is set arbitrarily to some extent while ensuring the writing time to the pixel, thereby reducing the sustain (lighting) period. Set arbitrarily to achieve a high duty ratio. In addition, there is a method that performs multi-gradation display of an electro-optical device by a time gradation method without providing a reset line (see, for example, Patent Document 2).
JP 2001-324958 A JP 2002-175047 A

When the driving methods disclosed in Patent Documents 1 and 2 are employed, a display defect called ghost may occur. Ghost is a phenomenon in which, for example, when an image (here, a white box) is displayed at the center of the display screen, the same image is displayed above and below (see FIG. 15). Such a display failure called ghost occurs in a period in which the source driver outputs a video signal to the pixel and a period in which the second gate driver for erasing selects a gate line (here, the gate line in the i-th row). This is because a video signal is written to a pixel to be erased (see FIG. 16). In view of the above circumstances, it is an object of the present invention to provide a display device, a driving method thereof, and a television device that prevent a display defect called a ghost.

The present invention divides a gate control signal (GWE), which has conventionally been one, into two signals, a first gate control signal (GWE1) and a second gate control signal (GWE2). The period in which the driver outputs a video signal to the pixel and the period in which the erasing gate driver selects the gate line are set so as not to overlap. Then, by preventing the video signal from being written to the pixel for which the erasing operation is performed, the occurrence of a display defect called a ghost is prevented.

The present invention uses a pulse width control signal (PWC) in addition to one conventionally used gate control signal (GWE), so that a source driver outputs a video signal to a pixel and an erasing gate. Set so that it does not overlap with the period when the driver selects the gate line. Then, by preventing the video signal from being written to the pixel for which the erasing operation is performed, the occurrence of a display defect called a ghost is prevented.

The display device of the present invention includes a pixel region including a plurality of pixels, a source driver, a first gate driver, a second gate driver, and a control signal generation circuit. Each of the plurality of pixels includes a light emitting element, a switching transistor (first transistor) that controls input of a video signal to the pixel, and a driving transistor (second transistor) that controls light emission and non-light emission of the light emitting element. And a capacitor for holding a video signal. The source driver includes a pulse output circuit, a latch circuit, and a selection circuit that operates based on a source control signal output from the control signal generation circuit.

Each of the first gate driver and the second gate driver includes a pulse output circuit, a buffer circuit that operates based on the first gate control signal and the second gate control signal output from the control signal generation circuit, and Have

Alternatively, each of the first gate driver and the second gate driver includes a pulse output circuit, and a buffer circuit that operates based on the gate control signal and the pulse width control signal output from the control signal generation circuit.

In the display device having the above structure, the buffer circuit has at least three input nodes and one output node. Of the three input nodes, one is connected to the pulse output circuit, one is connected to the control signal generation circuit via the first gate control signal line, and the remaining one is the second gate. The control node is connected to the control signal generation circuit via the control signal line, and the output node is connected to the gate line.

Alternatively, in the display device having the above structure, one of the three input nodes of the buffer circuit is connected to the pulse output circuit, one is connected to the gate control signal line, and the remaining one is the pulse width. Connected to the control signal line, the output node is connected to the gate line.

The display device of the present invention includes a pixel region including a plurality of pixels, a source driver, a first gate driver, a second gate driver, and a circuit (corresponding to a control signal generation circuit) that generates a signal. Each of the plurality of pixels includes a light emitting element, a first transistor for controlling input of a video signal to the pixel (corresponding to a switching transistor), and a second transistor for controlling light emission and non-light emission of the light emitting element (for driving). Equivalent to a transistor) and a capacitor for holding a video signal. The source driver includes a pulse output circuit, a latch circuit, and a selection circuit that operates based on a first signal output from the circuit. Each of the first gate driver and the second gate driver includes a pulse output circuit, and a buffer circuit that operates based on the second signal and the third signal output from the signal generation circuit.

The first signal corresponds to a source control signal. The second signal and the third signal include a case where the second signal corresponds to the first gate control signal and the third signal corresponds to the second gate control signal, There are two cases where the signal corresponds to the gate control signal and the third signal corresponds to the pulse width control signal.

Each of the first gate driver and the second gate driver includes a pulse output circuit and a buffer circuit that operates based on the second signal and the third signal output from the circuit. The buffer circuit has at least three input nodes and one output node. Of the three input nodes, one is connected to the pulse output circuit, one is connected to the circuit via the first signal line (also referred to as the first control signal line), and the other one is the second. Are connected to the circuit via a signal line (also referred to as a second control signal line). The output node is connected to the gate line. Of the first signal line and the second signal line, the first signal line corresponds to the first gate control signal line, and the second signal line corresponds to the second gate control signal line. There are two cases where the first signal line corresponds to a gate control signal line and the second signal line corresponds to a pulse width control signal line.

The first gate control signal and the second gate control signal are signals having different lengths of the first period at the first potential and the second period at the second potential. The pulse width control signal is a signal in which the length of the first period at the first potential is different from the length of the second period at the second potential. One of the first potential and the second potential corresponds to the potential of the H level signal, and the other of the first potential and the second potential corresponds to the potential of the L level signal.

The display device of the present invention includes a pixel region including a plurality of pixels, a source driver, a first gate driver, a second gate driver, and a control signal generation circuit. One frame period has a writing period and a lighting period, the writing period has a plurality of gate selection periods, and each of the plurality of gate selection periods has a first sub-gate selection period and a second sub-gate selection period.

Based on the first gate control signal and the second gate control signal or the gate control signal and the pulse width control signal transmitted from the control signal generation circuit in the first sub-gate selection period, the first gate driver The buffer circuit included in the first gate driver enters the operating state, the buffer circuit included in the second gate driver enters the high impedance state, and the buffer circuit included in the first gate driver selects the first gate line. Further, based on the source control signal transmitted from the control signal generation circuit, the source driver outputs a video signal to a pixel including a transistor connected to the first gate line.

In the second sub-gate selection period, the first gate driver based on the first gate control signal and the second gate control signal or the gate control signal and the pulse width control signal transmitted from the control signal generation circuit The buffer circuit included in the second gate driver enters the high impedance state, the buffer circuit included in the second gate driver enters the operating state, and the buffer circuit included in the second gate driver selects the second gate line. Further, based on the source control signal transmitted from the control signal generation circuit, the source driver outputs an erase signal to the pixel including the transistor connected to the second gate line.

The period in which the source driver outputs the video signal and the period in which the second gate line is selected do not overlap.

Note that the high impedance state refers to a state where the output of the circuit is not electrically connected. Further, the operating state means the opposite of the high impedance state, and indicates a state where the output of the circuit is electrically connected.

According to the present invention having the above-described configuration, it is possible to prevent the occurrence of display failure called ghost.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.
(Embodiment 1)

The display device of the present invention includes a pixel region 40 in which a plurality of pixels 10 are arranged in a matrix, a first gate driver 41, a second gate driver 42, and a source driver 43 (see FIG. 1). The first gate driver 41 and the second gate driver 42 are disposed so as to face each other with the pixel region 40 interposed therebetween, or are disposed in one of the upper, lower, left, and right sides of the pixel region 40.

In addition, the display device of the present invention includes a control signal generation circuit 39 that generates a source control signal (SWE), a first control signal (Signal1), and a second control signal (Signal2).

The signal generated by the control signal generation circuit 39 will be described in detail. The first control signal (Signal1) is the first gate control signal (GWE1, GWE1B, GWE1B is the inverted signal of GWE1), and the second When the control signal (Signal2) is the second gate control signal (GWE2, GWE2B, GWE2B is an inverted signal of GWE2), the first control signal (Signal1) is the gate control signal (GWE, GWEB, GWEB is GWE). Inverted signal), and the second control signal (Signal2) is a pulse width control signal (PWC).

When the first control signal is the first gate control signal (GWE1, GWE1B) and the second control signal is the second gate control signal (GWE2, GWE2B), the control signal generation circuit 39 GWE1 is output via the first control signal line 37, GWE2 is output via the second control signal line 38, and GWE1B (inverted signal of GWE1) is output via the first control signal line 71. GWE2B (inverted signal of GWE2) is output via the second control signal line 72. Alternatively, the control signal generation circuit 39 outputs GWE1B via the first control signal line 37, outputs GWE2B via the second control signal line 38, and GWE1 via the first control signal line 71. And GWE2 is output via the second control signal line 72.

In the above two cases, the first control signal lines 37 and 71 are also called first gate control signal lines, and the second control signal lines 38 and 72 are also called second gate control signal lines. The first gate control signal is a generic name for GWE1 and GWE1B, and the second gate control signal is a generic name for GWE2 and GWE2B. The first control signal line 37 and the second control signal line 38, or the first control signal line 71 and the second control signal line 72 are provided with inverters, so that the first control signal line 37 and The same signal (that is, GWE1 or GWE1B) may be output to 71, and the same signal (that is, GWE2 or GWE2B) may be output to the second control signal lines 38 and 72.

When the first control signal is the gate control signal (GWE) and the second control signal is the pulse width control signal (PWC), the control signal generation circuit 39 sends the GWE via the first control signal line 37. , PWC is output via the second control signal line 38, GWEB (inverted signal of GWE) is output via the first control signal line 71, and via the second control signal line 72 Output PWC. Alternatively, the control signal generation circuit 39 outputs GWEB via the first control signal line 37, outputs PWC via the second control signal line 38, and GWE via the first control signal line 71. And PWC is output via the second control signal line 72.

In the above two cases, the first control signal lines 37 and 71 are also called gate control signal lines, and the second control signal lines 38 and 72 are also called pulse width control signal lines. The gate control signal is a generic name for GWE and GWEB. Note that the first control signal line 37 or 71 may be provided with an inverter to output the same signal (that is, GWE or GWEB) to the first control signal lines 37 and 71.

In the pixel 10, the source line Sx (x is a natural number, m is an integer of 2 or more, 1 ≦ x ≦ m) and the gate line Gy (y is a natural number, n is an integer of 2 or more, 1 ≦ y ≦ n) are insulated. A plurality of elements are included in a region intersecting with the body. The pixel 10 includes a light emitting element 13, a capacitor element 16, and two transistors. Of the two transistors, one is a switching transistor 11 that controls input of a video signal to the pixel 10, and the other is a driving transistor that controls lighting (light emission) and non-lighting (non-light emission) of the light emitting element 13. This is the transistor 12. Each of the switching transistor 11 and the driving transistor 12 is a field effect transistor, and has three terminals of a gate electrode, a source electrode, and a drain electrode.

The gate electrode of the switching transistor 11 is connected to the gate line Gy, one of the source electrode and the drain electrode is connected to the source line Sx, and the other is connected to the gate electrode of the driving transistor 12. One of the source electrode and the drain electrode of the driving transistor 12 is connected to the power supply line Vx (x is a natural number, 1 ≦ x ≦ m), and the other is connected to the pixel electrode of the light emitting element 13. The counter electrode of the light emitting element 13 is connected to the counter power source 18. The capacitor 16 is provided between the gate electrode and the source electrode of the driving transistor 12.

One of a source electrode (also referred to as a source and a source region) and a drain electrode (also referred to as a drain and a drain region) of the driving transistor 12 (corresponding to a node connected to the power supply line Vx) is kept at a constant potential. I'm leaning. Further, the counter electrode of the light emitting element 13 is connected to the counter power source 18 through a wiring. The counter electrode of the light emitting element 13 is kept at a constant potential.

The conductivity types of the switching transistor 11 and the driving transistor 12 are not limited and may be either N-type (N-channel type) or P-type (P-channel type). However, in the illustrated configuration, the switching transistor 11 Indicates an N type, and the driving transistor 12 is a P type. The potential of the power supply line Vx and the potential of the counter power supply 18 are not limited, but are set to different potentials so that a forward bias voltage or a reverse bias voltage is applied to the light emitting element 13.

The display device of the present invention having the above structure is characterized in that the number of transistors arranged in the pixel 10 is two. With the above feature, the number of transistors laid out in one pixel 10 is reduced, and the number of transistors is small, so that the number of wirings inevitably arranged can be reduced, so that a high aperture ratio and high definition are achieved. Realize high yield. Further, when a high aperture ratio is realized, the luminance of the light-emitting element with respect to a certain voltage can be lowered with an increase in the area that emits light. That is, the current density of the light emitting element with respect to a certain voltage can be lowered. Therefore, since the driving voltage of the display device can be reduced, the power consumption of the display device can be reduced. In addition, the reliability of the light emitting element 13 can be improved by reducing the driving voltage of the display device.

The display device of the present invention is characterized in that the driving transistor 12 is operated in a linear region. With the above characteristics, the driving voltage of the display device itself can be lowered compared with the case of operating in the saturation region, so that power consumption can be reduced.

The semiconductor constituting the switching transistor 11 and the driving transistor 12 may be any of an amorphous semiconductor (amorphous silicon), a microcrystalline semiconductor, a polycrystalline semiconductor (polysilicon), an organic semiconductor, and the like. The microcrystalline semiconductor is formed by using silane gas (SiH ₄ ) and fluorine gas (F ₂ ), by using silane gas and hydrogen gas, or after forming a thin film by using the gas mentioned above, It may be formed by irradiation.

The gate electrodes of the switching transistor 11 and the driving transistor 12 are formed of a single layer or stacked layers using a conductive material. For example, a laminated structure of tungsten (W), tungsten nitride (WN, composition ratio of tungsten (W) and nitrogen (N) is not limited), a laminated structure of molybdenum (Mo), aluminum (Al), Mo, Mo, A laminated structure of molybdenum nitride (MoN, the composition ratio of molybdenum (Mo) and nitrogen (N) is not limited) may be employed.

The conductive layer (source / drain wiring) connected to the impurity regions (source and drain electrodes) included in the switching transistor 11 and the driving transistor 12 is formed as a single layer or a stacked layer using a conductive material. For example, titanium (Ti), aluminum silicon (Al-Si, equivalent to aluminum (Al) with silicon (Si) added), Ti laminated structure, Mo, Al-Si, Mo laminated structure, MoN, Al A stacked structure of -Si and MoN may be employed. Alternatively, a material containing aluminum as a main component and containing nickel or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon may be used.

The source driver 43 includes a pulse output circuit 44, a latch circuit 45, and a selection circuit 46. The latch circuit 45 includes a first latch circuit 47 and a second latch circuit 48.

The selection circuit 46 operates based on the source control signal (SWE) output from the control signal generation circuit 39, and includes an erasing transistor 49 and an analog switch 50. The erasing transistor 49 and the analog switch 50 are provided in each column corresponding to the source line Sx. The inverter 51 is for generating an inverted signal of the source control signal, and may not be provided when an inverted signal of the source control signal is supplied from the outside. The gate electrode of the erasing transistor 49 is connected to the control signal generating circuit 39 via the source control signal line 52, one of the source electrode and the drain electrode is connected to the source line Sx, and the other is connected to the erasing power supply 53. .

The analog switch 50 is provided between the second latch circuit 48 and the source line Sx. The input node of the analog switch 50 is connected to the second latch circuit 48, and the output node is connected to the source line Sx. One of the two control nodes of the analog switch 50 is connected to the source control signal line 52, and the other is connected to the source control signal line 52 via the inverter 51.

The erasing power supply 53 supplies a potential for turning off the driving transistor 12 included in the pixel 10. When the driving transistor 12 is N-type, the potential of the erasing power supply 53 is set to L level, and the driving transistor If 12 is P-type, the potential of the erasing power supply 53 is set to H level.

The pulse output circuit 44 included in the source driver 43 corresponds to a shift register including a plurality of flip-flop circuits. The configuration of the source driver 43 is not limited to the above description, and a level shifter, a buffer, a protection circuit, and the like may be provided.

A clock signal (denoted as SCK in the drawing), a clock inversion signal (denoted as SCKB in the drawing), and a start pulse (denoted as SSP in the drawing) are input to the pulse output circuit 44, and the first signal is output in accordance with the timing of these signals. A sampling pulse is output to the latch circuit 47.

The first latch circuit 47 to which data (indicated as DATA in the drawing) is input holds the video signal from the first column to the last column in accordance with the timing at which the sampling pulse is input. When a latch pulse (denoted as SLAT in the drawing) is input, the second latch circuit 48 transfers the video signals held in the first latch circuit 47 to the second latch circuit 48 all at once.

The first gate driver 41 has a pulse output circuit 54 and a buffer circuit 55. The second gate driver 42 has a pulse output circuit 56 and a buffer circuit 57. Each of the buffer circuits 55 and 57 operates based on the first control signal (Signal 1) and the second control signal (Signal 2) output from the control signal generation circuit 39. Each of the buffer circuits 55 and 57 has at least three input nodes and one output node. Of the three input nodes, one is connected to the pulse output circuit 54 or the pulse output circuit 56, and one is connected to the control signal generation circuit 39 via the first control signal lines 37 and 71, and the remaining 1 One is connected to the control signal generating circuit 39 via the second control signal lines 38 and 72. The output node is connected to the gate line Gy. One of the buffer circuit 55 and the buffer circuit 57 is in an operating state and the other is in a high impedance state based on the first control signal and the second control signal.

The buffer circuits 55 and 57 have at least three or more input nodes. However, the buffer circuits 55 and 57 may have three or more input nodes.

The pulse output circuit 54 included in the first gate driver 41 and the pulse output circuit 56 included in the second gate driver 42 correspond to a shift register or a decoder circuit including a plurality of flip-flop circuits. If a decoder circuit is applied as the pulse output circuits 54 and 56, the gate line Gy can be selected at random. If the gate line Gy can be selected at random, it is possible to suppress the generation of a pseudo contour that occurs when the time gray scale method is applied. The configurations of the first gate driver 41 and the second gate driver 42 are not limited to the above description, and a level shifter or a buffer may be provided. Further, a protection circuit may be provided in the first gate driver 41 and the second gate driver 42.

When the pulse output circuits 54 and 56 are shift registers, the pulse output circuit 54 has a clock signal (denoted as G1CK in the drawing), a clock inversion signal (denoted as G1CKB in the drawing), and a start pulse (denoted as G1SP in the drawing). A pulse is sequentially output to the buffer circuit 55 in accordance with the timing of these signals. A clock signal (denoted as G2CK in the drawing), a clock inversion signal (denoted as G2CKB in the drawing), and a start pulse (denoted as G2SP in the drawing) are input to the pulse output circuit 56, and a buffer circuit is provided according to the timing of these signals. Sequentially output pulses to 57

Next, the operation of the display device of the present invention having the above configuration will be described with reference to the timing chart of FIG.

First, the case where the first control signal is the first gate control signal (GWE1) and the second control signal is the second gate control signal (GWE2) will be described. In addition, the periods T1 and T2 are half the gate selection period, the period T1 is a first subgate selection period, and the period T2 is a second subgate selection period. When GWE1 is at H level and GWE2 is at L level, period T3, when GWE1 is at L level and GWE2 is at H level, period T4 is set, and when both GWE1 and GWE2 are at L level, period T5 is set, and periods T3 to T5 are set. The operation in will be described.

Note that in the timing chart illustrated, the periods T1 to T4 satisfy the period T1> the period T3 and the period T2> the period T4. The period T5 is provided between the period T3 and the period T4. GWE1 has a period (corresponding to the period T3) at the H level (corresponding to one potential of the first potential and the second potential), and the L level (corresponding to the other potential of the first potential and the second potential). Corresponding period) (a period excluding the period T3 from the total period of the period T1 and the period T2). GWE2 is a signal having a different period at the H level (corresponding to the period T4) and a period at the L level (a period excluding the period T4 from the total period of the periods T1 and T2). On the other hand, SWE is a signal having the same period during H level (corresponding to period T1) and period during L level (corresponding to period T2).

In the period T3, the first gate control signal is at the H level, and the second gate control signal is at the L level. Based on the first gate control signal and the second gate control signal, one of the buffer circuit 55 and the buffer circuit 57 is in an operating state and the other is in a high impedance state. Here, the buffer circuit 55 is in an operating state. Thus, it is assumed that the buffer circuit 57 is in a high impedance state. The buffer circuit 55 in the operating state transmits an H level signal to the gate line Gj in the j-th row (j is a natural number). That is, the buffer circuit 55 selects the gate line Gj. Then, the switching transistor 11 connected to the gate line Gj is turned on.

At this time, the source control signal is at the H level, the erasing transistor 49 is turned off, and the analog switch 50 is turned on. Then, the video signal held by the source driver 43 in the second latch circuit 48 is transmitted for one row to the plurality of signal lines S1 to Sm simultaneously. That is, the source driver 43 outputs a video signal to a pixel including a transistor connected to the gate line Gj.

Then, the video signal is transmitted to the gate electrode of the driving transistor 12, and the driving transistor 12 is turned on or off according to the input video signal, and the two electrodes included in the light-emitting element 13 have different potentials or the same potential. It becomes a potential. Specifically, when the driving transistor 12 is turned on, two electrodes included in the light emitting element 13 are at different potentials, and a current flows through the light emitting element 13. On the other hand, when the driving transistor 12 is turned off, the two electrodes included in the light emitting element 13 have the same potential, and no current flows through the light emitting element 13. In this manner, the operation in which the driving transistor 12 is turned on or off in accordance with the video signal and the potentials of the two electrodes included in the light-emitting element 13 are different from each other or the same potential is referred to as a writing operation.

In the period T5, the first gate control signal is at the L level, and the second gate control signal is at the L level. At this time, the gate line Gy is at the L level, and neither the write operation nor the erase operation is performed.

In the period T4, the first gate control signal is at the L level, and the second gate control signal is at the H level. Here, it is assumed that the buffer circuit 55 included in the first gate driver 41 is in a high impedance state, and the buffer circuit 57 included in the second gate driver 42 is in an operating state. The buffer circuit 57 in the operating state transmits an H level signal to the i-th (i is a natural number) gate line Gi. That is, the buffer circuit 57 selects the i-th gate line Gi. Then, the switching transistor 11 included in the pixel 10 is turned on.

At this time, the source control signal is at L level, the erasing transistor 49 is turned on, and the analog switch 50 is turned off. Then, the plurality of signal lines S1 to Sm are electrically connected to the erasing power supply 53 through the erasing transistors 49 arranged in each column. That is, the plurality of signal lines S <b> 1 to Sm have the same potential as the erasing power supply 53. That is, the selection circuit 46 included in the source driver 43 outputs the potential of the erasing power supply 53 corresponding to the erasing signal to the pixel including the transistor connected to the gate line Gi.

Then, the potential of the erasing power supply 53 corresponding to the erasing signal is transmitted to the gate electrode of the driving transistor 12, the driving transistor 12 is turned off, and the two electrodes included in the light emitting element 13 have the same potential. That is, no current flows between both electrodes included in the light emitting element 13 and no light is emitted. An operation in which the potential of the erasing power supply 53 is transmitted to the gate electrode of the driving transistor 12, the switching transistor 11 is turned off, and the potentials of the two electrodes included in the light emitting element 13 are the same potential is an erasing operation. Called.

As described above, the gate line Gy is selected by the first gate driver 41 in the period T3 and selected by the second gate driver 42 in the period T4. That is, the gate line Gy is complementarily controlled by the first gate driver 41 and the second gate driver 42. The write operation is performed in one period T3 included in the first sub-gate selection period T1 and T4 included in the second sub-gate selection period T2, and the erase operation is performed in the other period.

According to the present invention performing the above operation, the source driver 43 outputs a video signal during a period in which the gate line Gy (i-th gate line Gi in the above embodiment) is selected by the second gate driver 42 for erasure. The period to do does not overlap. That is, there is a period (indicated by T5 in the drawing) in which the source driver 43 outputs a video signal and no gate line Gy is selected. Therefore, it is possible to prevent the occurrence of display defects called ghosts.

Next, the case where the first control signal is the gate control signal (GWE) and the second control signal is the pulse width control signal (PWC) will be described with reference to the timing chart of FIG. The periods T1 and T2 are half the gate selection period, the period T3 is when the GWE is at the H level and the PWC is at the L level, and the periods T4 and GWE are when the GWE is at the L level and the PWC is at the L level. The period T5 is the time when the PWC is at the H level or the L level, and the operation in the periods T3 to T5 will be described.

Note that in the timing chart illustrated, the periods T1 to T4 satisfy the period T1> the period T3 and the period T2> the period T4. The period T5 is provided between the period T3 and the period T4. GWE has a period (corresponding to the period T1) at the H level (corresponding to one potential of the first potential and the second potential) and an L level (corresponding to one potential of the first potential and the second potential). Corresponding period) (corresponding to the period T2). SWE is a signal having the same period during H level (corresponding to the period T1) and the period during L level (corresponding to the period T2). The PWC is a signal having a different period at the L level (corresponding to the period T3) and a period at the H level (corresponding to the period T5).

In the period T3, one of the buffer circuit 55 and the buffer circuit 57 is in an operating state and the other is in a high impedance state. Here, it is assumed that the buffer circuit 55 is in an operating state and the buffer circuit 57 is in a high impedance state. The buffer circuit 55 in the operating state transmits an H level signal to the gate line Gj in the j-th row (j is a natural number). That is, the buffer circuit 55 selects the gate line Gj. At this time, the source control signal is at the H level, and the source driver 43 outputs a video signal to the pixel including the transistor connected to the gate line Gj.

In the period T5, the gate control signal is at the H level or the L level, and the pulse width control signal is at the H level. At this time, the gate line Gy is at the L level, and neither the write operation nor the erase operation is performed.

In the period T4, it is assumed here that the buffer circuit 55 included in the first gate driver 41 is in a high impedance state and the buffer circuit 57 included in the second gate driver 42 is in an operating state. The buffer circuit 57 in the operating state transmits an H level signal to the i-th (i is a natural number) gate line Gi. That is, the buffer circuit 55 selects the i-th gate line Gi. At this time, the selection circuit 46 included in the source driver 43 outputs the potential of the erasing power supply 53 corresponding to the erasing signal to the pixel including the transistor connected to the gate line Gi.

As described above, the gate line Gy is selected by the first gate driver 41 in the period T3 and selected by the second gate driver 42 in the period T4. That is, the gate line Gy is complementarily controlled by the first gate driver 41 and the second gate driver 42. The write operation is performed in one period T3 included in the first sub-gate selection period T1 and T4 included in the second sub-gate selection period T2, and the erase operation is performed in the other period.

According to the present invention performing the above operation, the source driver 43 outputs a video signal during a period in which the gate line Gy (i-th gate line Gi in the above embodiment) is selected by the second gate driver 42 for erasure. The period to do does not overlap. That is, there is a period (indicated by T5 in the drawing) in which the source driver 43 outputs a video signal and no gate line Gy is selected. Therefore, it is possible to prevent the occurrence of display defects called ghosts.

In this way, the n-th (n is a natural number) gate line is controlled by the n-th stage output of the first gate driver 41 and the n-th stage output of the second gate driver 42. One of the first gate driver 41 and the second gate driver 42 is a gate driver that selects a pixel row in which a write operation is performed, and the other is a gate driver that selects a pixel row in which an erase operation is performed. is there.

In addition, since the light emitting element 13 can be forcibly turned off according to the present invention that performs the above operation, the duty ratio can be improved. Furthermore, although the light emitting element 13 can be forcibly turned off, it is not necessary to provide a TFT (thin film transistor) for discharging the charge of the capacitor 16, and thus a high aperture ratio is realized. When a high aperture ratio is realized, the luminance of the light-emitting element can be lowered with an increase in the area that emits light. That is, since the driving voltage can be lowered, power consumption can be reduced.

Note that the present invention is not limited to the above-described form in which the gate selection period is divided into two. The gate selection period may be divided into three or more.
(Embodiment 2)

The structure of the display device of the present invention will be described with reference to the drawings. The display device of the present invention includes a monitor circuit 64 including one or a plurality of monitor light emitting elements 66, a constant current source 67, and a buffer amplifier 68 (see FIG. 1). The light-emitting element 13 and the monitor light-emitting element 66 are provided on the same substrate and are manufactured in the same process under the same manufacturing conditions, and have the same characteristics with respect to changes in environmental temperature and changes over time. Or have approximately the same characteristics. The monitor circuit 64 including one or a plurality of monitor light emitting elements 66 may be provided in the pixel region 40 or in other regions. However, the monitor circuit 64 may be provided in an area other than the pixel area 40 so as not to affect the image display. The constant current source 67 and the buffer amplifier 68 may be provided on the same substrate 20 together with the light emitting element 13 and the monitor light emitting element 66, or may be provided on different substrates.

A constant current source 67 supplies a constant current to the monitor light emitting element 66. When the environmental temperature changes and changes with time occur in this state, the resistance value of the monitoring light emitting element 66 itself changes. Then, since the current value of the monitor light emitting element 66 is always constant, the potential difference between both electrodes of the monitor light emitting element 66 changes.

In the case of the above configuration, the potential of the electrode connected to the counter power source 18 among the two electrodes included in the monitor light emitting element 66 does not change, and the constant current source among the two electrodes included in the monitor light emitting element 66 does not change. The potential of the electrode on the side connected to 67 (herein referred to as the first electrode) changes. The changed potential of the first electrode of the monitor light emitting element 66 is input to the input terminal of the buffer amplifier 68. The buffer amplifier 68 outputs a potential from the output terminal, and the potential is applied to the first electrode of the light emitting element 13 through the driving transistor 12.

The buffer amplifier 68 is provided to prevent potential fluctuation when the potential of the first electrode of the monitor light emitting element 66 is transmitted to the first electrode of the light emitting element 13. Any circuit other than the buffer amplifier 68 may be used as long as it is a circuit that can prevent potential fluctuations, such as the buffer amplifier 68. That is, when the potential of one electrode of the monitor light emitting element 66 is transmitted to the light emitting element 13, a circuit for preventing potential fluctuation is provided between the monitor light emitting element 66 and the light emitting element 13. Such a circuit is not limited to the buffer amplifier 68 described above, and a circuit having any configuration may be used. The present invention having the above structure can improve the reliability by suppressing the fluctuation of the current value of the light emitting element due to the change of the environmental temperature or the change with time.

Note that the buffer amplifier 68 is a circuit that prevents fluctuations in potential. Such a circuit includes a circuit that outputs the same potential as the input potential, a circuit that outputs the same potential as the input potential, It can be called a circuit that outputs a potential corresponding to an input potential. In the illustrated configuration, the inverting input terminal and the output terminal of the buffer amplifier 68 are connected to each other. The input terminal of the buffer amplifier 68 is connected to the first electrode of the monitor light emitting element 66 (sometimes referred to as a second light emitting element), and the output terminal of the buffer amplifier 68 is the light emitting element 13 (with the first light emitting element). Connected to the first electrode. The second electrode of the monitoring light emitting element 66 and the second electrode of the light emitting element 13 are maintained at a constant potential.

Note that a limiter transistor connected in series to the monitoring light emitting element 66 may be provided in order to prevent an excessive current from flowing through the monitoring light emitting element 66. The limiter transistor is always turned on.

Further, when the light emitting element 13 and the monitor light emitting element 66 are operated normally, their duty ratios are different. Specifically, the duty ratio of the monitor light emitting element 66 is 100%, while the duty ratio of the light emitting element 13 is about 70% even when all white lighting is performed. Then, since the total current amount of the light emitting element 13 and the total current amount of the monitoring light emitting element 66 are different, the time-dependent change of the monitoring light emitting element 66 proceeds faster. Therefore, in order to make the total current amount of the light emitting element 13 and the monitor light emitting element 66 the same, a resistance element may be provided or a control circuit may be provided outside.

In addition, the display device of the present invention includes a power supply control circuit 63 (see FIG. 1). The power supply control circuit 63 includes a power supply circuit 61 that supplies power to the light emitting element 13 and a control circuit 62. The power supply circuit 61 is connected to the pixel electrode of the light emitting element 13 through the driving transistor 12 and the power supply line Vx. The power supply circuit 61 is connected to the counter electrode of the light emitting element 13 through a power supply line.

When the current of the light emitting element 13 flows from the pixel electrode toward the counter electrode, when the forward bias voltage is applied to the light emitting element 13 to cause the light emitting element 13 to emit light, the potential of the power supply line Vx is set to the counter power supply 18. The potential difference between the power supply line Vx and the counter power supply 18 is set so as to be higher than the first potential. On the other hand, when a reverse bias voltage is applied to the light emitting element 13, the potentials of the power supply line Vx and the counter power supply 18 are set so that the potential of the power supply line Vx is lower than the potential of the counter power supply 18. Such power supply setting is performed by supplying a predetermined signal from the control circuit 62 to the power supply circuit 61.

That is, one electrode of the light emitting element 13 is connected to the power supply line Vx (also referred to as the first power supply line) via the driving transistor 12, and the other electrode of the light emitting element 13 is connected via the second power supply line. Are connected to the counter power source 18. A power supply control circuit 63 (also simply referred to as a circuit) sets the potential of the first power supply line and the potential of the second power supply line in order to apply a forward bias voltage or a reverse bias voltage to the light emitting element 13. Control.

By applying a reverse bias voltage to the light emitting element 13 using the power supply control circuit 63, deterioration with time of the light emitting element 13 can be suppressed and reliability can be improved. In addition, the light emitting element 13 may have an initial failure in which a short-circuit portion between the anode and the cathode is generated due to adhesion of foreign matters, pinholes due to fine protrusions on the anode or cathode, and non-uniformity of the electroluminescent layer. is there. When such an initial failure occurs, lighting and non-lighting according to the signal are not performed, and almost all of the current flows through the short-circuit portion, causing a phenomenon that the entire element is extinguished, or a specific pixel is not lighted or not lighted A phenomenon occurs, and the image is not displayed well.

However, according to the configuration of the present invention, since a reverse bias can be applied to the light emitting element, a current is supplied locally only to the short-circuited portion of the anode and the cathode, and the short-circuited portion is heated. It can be insulated (increased resistance) by oxidation or carbonization. As a result, even if an initial failure occurs, the failure can be resolved and an image can be displayed favorably.

It should be noted that such initial failure insulation (high resistance) may be performed before shipment. In addition to the initial failure, a short-circuit portion between the anode and the cathode may be newly generated as time passes. Such a defect is also called a progressive defect, but according to the configuration of the present invention, a reverse bias can be periodically applied to the light emitting element, so even if a progressive defect occurs, the defect is eliminated, An image can be displayed satisfactorily. Note that there is no particular limitation on the timing at which the reverse bias voltage is applied to the light emitting element 13.
(Embodiment 3)

The configuration of the gate driver of the present invention will be described with reference to the drawings. The configurations of the first gate driver 41 and the second gate driver 42 are the same. Here, the configuration of the first gate driver 41 will be described.

The first gate driver 41 includes a pulse output circuit 54 and a buffer circuit 55 (see FIG. 4). In addition, an inverter 206 and a NAND 207 are provided between the pulse output circuit 54 and the buffer circuit 55. The pulse output circuit 54 includes a plurality of unit circuits 201, and the buffer circuit 55 also includes a plurality of unit circuits 202. The pulse output circuit 54 outputs a sampling pulse to the lower stage based on GCK, GCKB, and GSP. The buffer circuit 55 selects the gate line Gy based on the output of the pulse output circuit 54, the first control signal (Signal1), and the second control signal (Signal2).

The unit circuit 201 constituting the pulse output circuit 54 includes transistors 210 to 218, an analog switch 219, and an inverter 220 (see FIG. 5).

When the first control signal (Signal 1) is the first gate control signal and the second control signal (Signal 2) is the second gate control signal, the unit circuit 202 constituting the buffer circuit 55 is , NANDs 232 and 233, inverters 231 and 234 to 238, transistors 240 to 245, level shifters 203 and 204, and a protection circuit 205 (see FIG. 6).

When the first control signal (Signal 1) is a gate control signal and the second control signal (Signal 2) is a pulse width control signal, the unit circuit 202 constituting the buffer circuit 55 includes inverters 271 to 274 and , NAND 275, NOR 276, transistors 279, 280, level shifters 277, 278, and a protection circuit 281 (see FIG. 7).

Level shifters 203, 204, 277, and 278 are circuits for boosting the voltage. The protection circuits 205 and 281 are provided for the purpose of suppressing deterioration and destruction of the element due to static electricity. The protection circuits 205 and 281 are configured of one or more types selected from transistors, resistor elements, capacitor elements, and rectifier elements. The rectifying element is an element having a rectifying property and corresponds to a transistor or a diode in which a gate electrode and a drain electrode are connected.
(Embodiment 4)

A layout of the pixel 10 included in the display device of the present invention will be described with reference to FIG. In this layout, the conductive layer 19 corresponding to the pixel electrode of the switching transistor 11, the driving transistor 12, the capacitor 16, and the light emitting element 13 is shown.

Next, a cross-sectional structure corresponding to ABC in this layout will be described with reference to FIG. A switching transistor 11, a driving transistor 12, a light emitting element 13, and a capacitor 16 are provided over a substrate 20 having an insulating surface such as glass or quartz.

The light emitting element 13 corresponds to a stacked body of a conductive layer 19 corresponding to a pixel electrode, an electroluminescent layer 33, and a conductive layer 34 corresponding to a counter electrode. When both the conductive layers 19 and 34 have translucency, the light emitting element 13 emits light in a direction toward the conductive layer 19 and in a direction toward the conductive layer 34. That is, the light emitting element 13 performs double-sided emission. When one of the conductive layers 19 and 34 has a light-transmitting property and the other has a light-blocking property, the light-emitting element 13 emits light only in the direction toward the conductive layer 19 or in the direction toward the conductive layer 34. That is, the light emitting element 13 performs top emission or bottom emission. The structure shown in the figure shows a cross-sectional structure in the case where the light emitting element 13 performs bottom emission.

The capacitive element 16 is disposed between the gate electrode and the source electrode of the driving transistor 12 and holds the gate-source voltage of the driving transistor 12. The capacitor 16 includes conductive layers 22a and 22b (hereinafter collectively referred to as a conductive layer 22) provided in the same layer as the gate electrodes of the switching transistor 11 and the driving transistor 12, and a source / drain wiring of the driving transistor 12. The capacitor is formed by the conductive layer 26 corresponding to the above and the insulating layer between the conductive layer 22 and the conductive layer 26.

The capacitor 16 includes a conductive layer 26 corresponding to the source / drain wiring of the driving transistor 12, a conductive layer 36 provided in the same layer as the pixel electrode of the light emitting element 13, and the conductive layer 26 and the conductive layer 36. It is characterized in that a capacitor is formed by an insulating layer therebetween. Note that the conductive layer 35 is connected to the conductive layer 36 as shown in the layout of FIG.

With the above characteristics, the capacitor 16 can obtain a capacitance value sufficient to hold the gate-source voltage of the driving transistor 12. In addition, the capacitive element 16 is provided below the conductive layer constituting the power supply line, and therefore, the aperture ratio is not reduced by the arrangement of the capacitive element 16. In addition, since the gate insulating films of the switching transistor 11 and the driving transistor 12 are not used for the capacitor 16, the gate leakage current can be reduced and the power consumption can be reduced.

The conductive layers 24 to 27 corresponding to the source and drain wirings of the switching transistor 11 and the driving transistor 12 have a thickness of 500 to 2000 nm, preferably 500 to 1300 nm. Since the conductive layers 24 to 27 constitute the source line Sx and the power supply line Vx, the influence of the voltage drop can be suppressed by increasing the film thickness of the conductive layers 24 to 27 as described above. it can. If the conductive layers 24 to 27 are thickened, the wiring resistance can be reduced. Conversely, if the conductive layers 24 to 27 are excessively thick, it becomes difficult to perform pattern processing accurately or the surface irregularities are formed. Becomes a problem. That is, the thicknesses of the conductive layers 24 to 27 are preferably determined within the above range in consideration of the wiring resistance, the ease of pattern processing, and the influence of surface irregularities.

In addition, the display device of the present invention is provided on the first insulating layer 30 with insulating layers 28 and 29 (hereinafter collectively referred to as the first insulating layer 30) covering the switching transistor 11 and the driving transistor 12. The second insulating layer 31 is provided, and the conductive layer 19 corresponding to a pixel electrode is provided on the second insulating layer 31. If the second insulating layer 31 is not provided, the conductive layers 24 to 27 corresponding to the source / drain wiring and the conductive layer 19 are provided in the same layer. If it does so, the area | region which provides the conductive layer 19 will be restrict | limited except the area | region which provided the conductive layers 24-27. However, by providing the second insulating layer 31, the margin of the region where the conductive layer 19 is provided is widened, and a high aperture ratio is realized. This configuration is particularly effective in the case of top emission. When a high aperture ratio is realized, the driving voltage can be lowered and the power consumption can be reduced as the area for emitting light increases.

Note that the first insulating layer 30 and the second insulating layer 31 are formed using an inorganic material such as silicon oxide or silicon nitride, an organic material such as polyimide or acrylic, or the like. The first insulating layer 30 and the second insulating layer 31 may be formed of the same material, or may be formed of different materials. A siloxane-based material may also be used. A siloxane-based material has a skeletal structure with a bond of silicon and oxygen. An organic group containing at least hydrogen as a substituent (for example, an alkyl group or aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

Further, the partition layer (also referred to as an insulating layer or a bank) 32 may be formed using either an inorganic material or an organic material. However, since the electroluminescent layer of the light emitting element 13 is provided so as to be in contact with the partition layer 32, the partition layer 32 has a shape in which the radius of curvature continuously changes so that no pinhole or the like is generated in the electroluminescent layer. It is good to have. The partition layer 32 is preferably formed of a light-shielding material in order to clarify the boundary between pixels.
(Embodiment 5)

Examples of pixel circuits that can be applied to the display device of the present invention will be described.

In FIG. 10, the driving transistor 12 of the pixel 10 shown in FIG. 1 is deleted, and transistors 92 and 93 and a power supply line Vax (x is a natural number, 1 ≦ x ≦ l, and l is a natural number) are newly added. Provided pixel circuit). The power supply line Vax is connected to the power supply 94. In this configuration, the potential of the gate electrode of the transistor 92 is fixed by operating the transistor 92 in the saturation region by connecting the gate electrode of the transistor 92 to the power supply line Vax held at a constant potential. The transistor 93 is operated in a linear region, and a video signal including information on lighting or non-lighting of the pixel 10 is input to a gate electrode thereof. Since the value of the source-drain voltage of the transistor 93 operating in the linear region is small, a slight variation in the gate-source voltage of the transistor 93 does not affect the value of the current flowing through the light emitting element 13. Accordingly, the value of the current flowing through the light emitting element 13 is determined by the transistor 92 operating in the saturation region. The present invention having the above structure can improve the image quality by improving the luminance unevenness of the light emitting element 13 due to the characteristic variation of the transistor 92.

That is, the gate electrode (also referred to as a gate) of the transistor 92 is connected to the power supply line Vax and kept at a constant potential. One of the source and the drain of the transistor 93 is connected to the power supply line Vx and is kept at a constant potential.

Although not shown, a pixel circuit to which a current mirror circuit is applied may be used as a pixel circuit other than the above.

The display device of the present invention may use either an analog video signal or a digital video signal. However, when a digital video signal is used, it differs depending on whether the video signal uses voltage or current. That is, when the light emitting element emits light, a video signal input to the pixel includes a voltage signal and a current signal. A video signal having a voltage includes a constant voltage applied to the light emitting element and a constant current flowing through the light emitting element. There are two types of video signals that are currents: a voltage that is applied to the light emitting element is constant, and a current that flows through the light emitting element is constant. A constant voltage applied to the light emitting element is constant voltage driving, and a constant current flowing through the light emitting element is constant current driving. In constant current driving, a constant current flows regardless of the resistance change of the light emitting element. In the display device of the present invention, either constant current driving or constant voltage driving may be used, but a video signal having a voltage is used.

For the electroluminescent layer, a material that emits light from singlet excitation (hereinafter referred to as singlet excited light emitting material) or a material that emits light from triplet excitation (hereinafter referred to as triplet excited light emitting material) is used. . For example, among the light emitting elements that emit red light, the light emitting elements that emit green light, and the light emitting elements that emit blue light, a red one having a relatively short luminance half time is formed of a triplet excited light emitting material, and the other one is single. It is formed of a term excitation luminescent material. The triplet excited light-emitting material has an advantage in that the light emission efficiency is good, so that less power is required to obtain the same luminance.

Alternatively, the red and green materials may be formed of a triplet excited light emitting material, and the blue material may be formed of a singlet excited light emitting material. By forming a green light-emitting element having high human visibility with a triplet excitation light-emitting material, further reduction in power consumption can be achieved. Note that examples of triplet excited light emitting materials include those using a metal complex as a dopant, such as a metal complex having platinum as a third transition series element as a central metal, and a metal complex having iridium as a central metal. In addition, any material of a low molecular material, a medium molecular material, and a high molecular material may be used for the electroluminescent layer.

The light emitting element may have either a stacked structure in which an anode, an electroluminescent layer, and a cathode are sequentially stacked from the bottom, or a reverse stacked structure in which a cathode, an electroluminescent layer, and an anode are sequentially stacked from the bottom. An anode or a cathode included in the light-emitting element has light-transmitting indium tin oxide (ITO), ITO to which silicon oxide is added, indium zinc oxide (IZO), zinc oxide doped with gallium (Ga) ( GZO) may be used.

In addition, the light emitting element has an electroluminescent layer between the anode and the cathode, such as an anode, an electroluminescent layer, a charge generation layer,..., An electroluminescent layer, a charge generation layer,. And a charge generation layer may be laminated. Such an element is also called a tandem element. The charge generation layer is made of a metal, an inorganic semiconductor such as molybdenum oxide, or an organic compound doped with lithium.

When color display is performed using a panel including a light-emitting element, an electroluminescent layer having a different emission wavelength band is preferably provided for each pixel. Typically, red (R), green (G), and blue (B It is preferable to provide an electroluminescent layer corresponding to each color. In this case, monitor light emitting elements 66 corresponding to the respective colors of red, green, and blue may be provided to correct the power supply potential for each color. In this case, if a filter (colored layer) that transmits light in the emission wavelength band is provided on the light emitting side of the light emitting element, the color purity is improved and the mirroring of the pixel portion (reflection) is prevented. Can be achieved. In addition, when a filter is provided, it is possible to omit a circularly polarizing plate that has been conventionally required, and it is possible to eliminate loss of light emitted from the electroluminescent layer. Furthermore, a change in color tone that occurs when the pixel region is viewed obliquely can be reduced.

The electroluminescent layer can be configured to emit monochromatic or white light. In the case of using a white light emitting material, color display can be performed if a filter that transmits light of a specific wavelength is provided on the light emitting side of the light emitting element.
(Embodiment 6)

A panel mounted with a pixel region 40, a first gate driver 41, a second gate driver 42, and a source driver 43, which is an embodiment of the display device of the present invention, will be described. A pixel region 40 having a plurality of pixels including the light-emitting element 13, a first gate driver 41, a second gate driver 42, a source driver 43, and a connection film 407 are provided over the substrate 20 (see FIG. 11A). ). The connection film 407 is connected to an external circuit (IC chip).

FIG. 11B is a cross-sectional view taken along the line AB of the panel, and shows the driving transistor 12, the light emitting element 13, the capacitor 16, and the CMOS circuit 410 provided in the source driver 43 provided in the pixel region 40. .

A sealing material 408 is provided around the pixel region 40, the first gate driver 41, the second gate driver 42, and the source driver 43, and the light emitting element 13 is sealed with the sealing material 408 and the counter substrate 406. This sealing process is a process for protecting the light emitting element 13 from moisture. Here, a method of sealing with a cover material (glass, ceramics, plastic, metal, etc.) is used, but a thermosetting resin or ultraviolet light is used. A method of sealing with a curable resin or a method of sealing with a thin film having a high barrier ability such as a metal oxide or a nitride may be used. The element formed on the substrate 20 is preferably formed of a crystalline semiconductor (polysilicon) having favorable characteristics such as mobility as compared with an amorphous semiconductor, so that monolithic formation on the same surface can be achieved. Realized. Since the number of external ICs to be connected is reduced, the panel having the above configuration can be made small, light, and thin.

FIG. 12 is a cross-sectional view taken along the line C-D of the panel. The driving transistor 12, the light emitting element 13, the capacitor element 16, and the CMOS circuit 412 provided in the first gate driver 41 are provided in the pixel region 40. The CMOS circuit 411 provided in the second gate driver 42 is shown. The panel shown in the figure is characterized in that a sealing material 408 is provided so as to overlap the first gate driver 41 and the second gate driver 42. Narrowing of the frame is realized by the above feature.

11 and 12, the pixel electrode of the light-emitting element 13 has a light-transmitting property, and the counter electrode of the light-emitting element 13 has a light-shielding property. Therefore, the light emitting element 13 performs bottom emission.

As a structure different from the above, the pixel electrode of the light-emitting element 13 may have a light-shielding property, and the counter electrode of the light-emitting element 13 may have a light-transmitting property (see FIG. 13A). In this case, the light emitting element 13 performs top emission.

Further, as a structure different from the above, there are cases where both the pixel electrode of the light-emitting element 13 and the counter electrode of the light-emitting element 13 have a light-transmitting property (see FIG. 13B). In this case, the light emitting element 13 performs double-sided emission.

In the case of performing bottom emission and double emission, the conductive layer (source / drain wiring) connected to the impurity region included in the driving transistor 12 is a combination of aluminum (Al) and a material having low reflectance such as molybdenum (Mo). It is good to form it with a stick. Specifically, a laminated structure of Mo, Al—Si, Mo, a laminated structure of MoN, Al—Si, MoN, or the like may be employed. If it does so, it can prevent that the light emitted from the light emitting element reflects in source-drain wiring, and can take out light outside. The display device of the present invention may employ any of bottom emission, top emission, and dual emission.

11 and 12, an insulating layer is provided on the source / drain wiring of the driving transistor 12, and the pixel electrode of the light emitting element 13 is provided on the insulating layer. However, the present invention is not limited to this configuration, and the pixel electrode of the light-emitting element 13 is provided in the same layer as the source / drain wiring of the driving transistor 12 as in the configuration shown in FIGS. Also good. Further, in the portion where the source / drain wiring of the driving transistor 12 and the pixel electrode of the light emitting element 13 are stacked, the source / drain wiring of the driving transistor 12 is the lower layer as shown in FIG. The pixel electrode of the light emitting element 13 may be the lower layer and the source / drain wiring of the driving transistor 12 may be the upper layer as shown in FIG. 13B.

The pixel region 40 is constituted by a TFT (thin film transistor) using an amorphous semiconductor (amorphous silicon) formed on an insulating surface as a channel portion, and includes a first gate driver 41, a second gate driver 42, The source driver 43 may be constituted by an IC chip. The IC chip may be bonded onto the substrate 20 by the COG method, or may be bonded to the connection film 407 connected to the substrate 20. An amorphous semiconductor can be easily formed on a large-area substrate by using the CVD method and does not require a crystallization step, so that an inexpensive panel can be provided. At this time, if a conductive layer is formed by a droplet discharge method typified by an ink jet method, a cheaper panel can be provided.
(Embodiment 7)

As an electronic device including a pixel region including a light-emitting element, a television device (also simply referred to as a television or a television receiver), a digital camera, a digital video camera, a mobile phone device (also simply referred to as a mobile phone or a mobile phone), Examples thereof include portable information terminals such as PDAs, portable game machines, computer monitors, computers, sound reproduction apparatuses such as car audio, and image reproduction apparatuses equipped with recording media such as home game machines. A specific example thereof will be described with reference to FIG.

The portable information terminal includes a main body 9201, a display portion 9202, and the like (see FIG. 14A). The display portion 9202 can be any of those described in Embodiment Modes 1 to 6.

The digital video camera includes a display portion 9701, a display portion 9702, and the like (see FIG. 14B). The display portion 9701 can be any of those described in Embodiment Modes 1 to 6.

The portable terminal includes a main body 9101, a display portion 9102, and the like (see FIG. 14C). The display portion 9102 can be any of those described in Embodiment Modes 1 to 6.

A portable television device includes a main body 9301, a display portion 9302, and the like (see FIG. 14D). The display portion 9302 can be any of those described in Embodiment Modes 1 to 6. Such a television device can be widely applied from a small one mounted on a portable terminal such as a cellular phone to a medium-sized one that can be carried and a large one (for example, 40 inches or more). .

A portable computer includes a main body 9401, a display portion 9402, and the like (see FIG. 14E). As the display portion 9402, the display portion described in Embodiments 1 to 6 can be used.

The television device includes a main body 9501, a display portion 9502, and the like (see FIG. 14F). The display portion 9502 can be any of those described in Embodiment Modes 1 to 6.

Among the electronic devices listed above, those using a secondary battery can extend the usage time of the electronic device as much as power consumption is reduced, and can save the trouble of charging the secondary battery.

FIG. 6 illustrates a structure of a display device. The figure which shows a timing chart. The figure which shows a timing chart. The figure explaining the structure of a gate driver. The figure explaining the structure of a gate driver. The figure explaining the structure of a gate driver. The figure explaining the structure of a gate driver. FIG. 6 illustrates a structure of a display device. FIG. 6 illustrates a structure of a display device. FIG. 6 illustrates a structure of a display device. FIG. 6 illustrates a structure of a display device. FIG. 6 illustrates a structure of a display device. FIG. 6 illustrates a structure of a display device. FIG. 6 illustrates a structure of an electronic device. The figure for demonstrating the display defect called a ghost. The figure which shows a timing chart.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Pixel, 11 Switching transistor 12 Drive transistor, 13 Light emitting element 16 Capacitance element, 18 Opposite power supply 19 Conductive layer, 20 Substrate 37 1st control signal line, 38 2nd control signal line 39 Control signal generation circuit, 40 Pixel area 41 First gate driver, 42 Second gate driver 43 Source driver, 44 Pulse output circuit 45, 47, 48 Latch circuit 46 Selection circuit, 49 Erasing transistor 50 Analog switch, 51 Inverter 52 Source control signal line , 53 Erase power supply 54, 56 Pulse output circuit, 55, 57 Buffer circuit 58 Inverter, 61 Power supply circuit 62 Control circuit, 63 Power supply control circuit 64 Monitor circuit, 66 Monitor light emitting element 67 Constant current source, 68 Buffer amplifier 71 First control signal line, 72 Second control signal 92 and 93 transistor, 94 power supply

Claims (8)

A pixel region including a plurality of pixels; a source driver; a first gate driver that selects a pixel row on which a write operation is performed; a second gate driver that selects a pixel row on which an erase operation is performed; and a circuit that generates a signal. And
Each of the plurality of pixels includes a light emitting element, a first transistor, a second transistor, and a capacitor.
In the first transistor, the gate is electrically connected to the gate line, one of the source and the drain is electrically connected to the source line, and the other of the source and the drain is electrically connected to the gate of the second transistor,
In the second transistor, one of a source and a drain is electrically connected to a power supply line, and the other of the source and the drain is electrically connected to the light-emitting element,
The capacitor element has one electrode electrically connected to the gate of the second transistor and the other electrode electrically connected to one of a source and a drain of the second transistor,
The gate line is electrically connected to each of the first gate driver and the second gate driver;
The source driver outputs a video signal output by the write operation based on a source control signal output from a pulse output circuit, a latch circuit, and a circuit for generating the signal , or an erase signal output by the erase operation A circuit for selecting whether to output
Each of the first gate driver and the second gate driver operates based on a pulse output circuit and a first gate control signal and a second gate control signal output from the signal generating circuit. a buffer circuit to possess,
A display device, wherein the source driver performs the writing operation and has a period in which no pixel row is selected . In claim 1,
At least one of the first gate control signal and the second gate control signal has a length of a first period when it is a first potential and a second period when it is a second potential. A display device having different signals. A pixel region including a plurality of pixels; a source driver; a first gate driver that selects a pixel row on which a write operation is performed; a second gate driver that selects a pixel row on which an erase operation is performed; and a circuit that generates a signal. And
Each of the plurality of pixels includes a light emitting element, a first transistor, a second transistor, and a capacitor.
In the first transistor, the gate is electrically connected to the gate line, one of the source and the drain is electrically connected to the source line, and the other of the source and the drain is electrically connected to the gate of the second transistor,
In the second transistor, one of a source and a drain is electrically connected to a power supply line, and the other of the source and the drain is electrically connected to the light-emitting element,
The capacitor element has one electrode electrically connected to the gate of the second transistor and the other electrode electrically connected to one of a source and a drain of the second transistor,
The gate line is electrically connected to each of the first gate driver and the second gate driver;
The source driver outputs a video signal output by the write operation based on a source control signal output from a pulse output circuit, a latch circuit, and a circuit for generating the signal , or an erase signal output by the erase operation A circuit for selecting whether to output
Each of the first gate driver and the second gate driver, possess a pulse output circuit, a buffer circuit operating on the basis of the gate control signal and the pulse width control signal output from the circuit for generating the signal ,
A display device, wherein the source driver performs the writing operation and has a period in which no pixel row is selected . In claim 3,
At least one of the gate control signal and the pulse width control signal is a signal in which the length of the first period at the first potential is different from the length of the second period at the second potential. Characteristic display device. In any one of Claims 1 thru | or 4,
A display device, wherein a data signal is written in the first half of one horizontal period and an erase signal is written in another pixel row in the second half. In any one of Claims 1 thru | or 5 ,
The display device, wherein the second transistor operates in a linear region. 7. The pixel region according to claim 1 , wherein the pixel region, the first gate driver, the second gate driver, and the source driver are provided on the same insulating surface. Display device. An electronic apparatus using the display device according to any one of claims 1 to 7 .