JP2006024926A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, in which the dead space of a packaging area mounting the semiconductor device is reduced, as much as possible, a slit hole is formed correctly in order to miniaturize a packaging substrate using a dicing equipment having an infrared function, a lead terminal linked to an external electrode and a protective sealing mould can be dispensed by dividing a semiconductor substrate into predetermined size, and the appearance size is reduced markedly. <P>SOLUTION: A wire is provided on a first semiconductor chip 100, when the first semiconductor chip 100 and a second semiconductor chip 60 are mounted. The wire extends from a part right under the second semiconductor chip 60 to the circumference. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a first semiconductor chip and a second semiconductor chip are compactly formed.

  In general, a semiconductor device in which a transistor element is formed on a silicon substrate is mainly configured as shown in FIG. 1 is a silicon substrate, 2 is an island such as a heat sink on which the silicon substrate 1 is mounted, 3 is a lead terminal, and 4 is a resin mold for sealing.

  As shown in FIG. 21, the transistor element formed on the silicon substrate 11 has a base region formed by, for example, diffusing a P-type impurity such as boron into an N-type epitaxial layer 12 serving as a collector region in the N-type silicon substrate 11. 13 is formed, and an emitter region 14 is formed by diffusing N-type impurities such as phosphorus in the base region 13. An insulating film 15 having openings for exposing portions of the base region 13 and the emitter region 14 is formed on the surface of the silicon substrate 11, and a metal such as aluminum is deposited on the exposed base region 13 and emitter region 14. Then, the base electrode 16 and the emitter electrode 17 are formed. In the transistor having such a configuration, the silicon substrate serves as the collector electrode 18.

  As described above, the silicon substrate 1 on which the transistor elements are formed is fixedly mounted on the island 2 such as a copper-based heat dissipation plate via the brazing material 5 such as solder as shown in FIG. A base electrode and an emitter electrode of the transistor element are electrically connected to the lead terminals 3 arranged in the periphery by wires by wire bonding. The lead terminal connected to the collector electrode is formed integrally with the island, and after being electrically connected by mounting the silicon substrate on the island, transfer molding with a thermosetting resin 4 such as epoxy resin, A semiconductor device having a three-terminal structure is provided by completely covering and protecting the silicon substrate and a part of the lead terminal.

  A resin-molded semiconductor device is usually mounted on a wiring substrate such as a glass epoxy substrate, and is electrically connected to other semiconductor devices and circuit elements mounted on the mounting substrate to perform a predetermined circuit operation. Treated as a part.

  FIG. 22 is a cross-sectional view when a semiconductor device is mounted on a mounting substrate. 20 is a semiconductor device, 21 and 23 are base or emitter electrode lead terminals, 22 is a collector lead terminal, and 30 is a mounting substrate. It is.

The mounting area where the semiconductor device 20 is mounted on the mounting substrate 30 is the lead terminal 21,

22 and 23 and a region surrounded by conductive pads connected to the lead terminals. The mounting area is larger than the area of the silicon substrate (semiconductor chip) in the semiconductor device 20, and most of the mounting area is taken by the mold resin and the lead terminal as compared with the area of the semiconductor chip that actually has a function.

  Here, it is confirmed that the effective area ratio is extremely low in the resin-molded semiconductor device when the effective area ratio is considered as the ratio between the actually functioning semiconductor chip area and the mounting area. The low effective area ratio means that when the semiconductor device 20 is connected to other circuit elements on the wiring board 30, most of the mounting area becomes a dead space that is not directly related to a functioning semiconductor chip. If the effective area ratio is small, the dead space is increased on the mounting substrate 30 as described above, which hinders high-density downsizing of the mounting substrate 30.

  This problem is particularly noticeable in a semiconductor device having a small package size. For example, the maximum size of the semiconductor chip mounted on the EIAJ standard SC75A outline is 0.40 mm × 0.40 mm as shown in FIG. When this semiconductor chip is connected to a metal lead terminal with a wire and resin-molded, the overall size of the semiconductor device is 1.6 mm × 1.6 mm. The chip area of this semiconductor device is 0.16 mm, and the mounting area for mounting the semiconductor device is 2.56 mm, assuming that it is almost the same as the area of the semiconductor device. Therefore, the effective area ratio of this semiconductor device is about 6.25. Therefore, most of the mounting area is a dead space not directly related to the area of the functioning semiconductor chip.

  This problem regarding the effective area ratio is particularly noticeable in a semiconductor device having a very small package size as described above. However, in a resin-encapsulated semiconductor device in which a semiconductor chip is wire-connected by a metal lead terminal and resin-molded. Even if it exists, it becomes a problem as well.

  Wiring boards used in recent electronic devices, for example, portable information processing devices such as personal computers and electronic notebooks, 8 mm video cameras, mobile phones, cameras, liquid crystal televisions, etc. The mounting substrate used is also in the trend of high density and miniaturization.

  However, in the above-described prior art resin-encapsulated semiconductor device, as described above, since the mounting area for mounting the semiconductor device has a large dead space, there is a limit to downsizing of the mounting substrate, and downsizing of the mounting substrate. Was one of the obstacles.

  By the way, there is JP-A-3-248551 as a prior art for improving the effective area ratio. This prior art will be briefly described with reference to FIG. In this prior art, lead terminals 41, 42, and 43 connected to the base, emitter, and collector electrodes of the semiconductor chip 40 are provided in order to minimize the mounting area when the resin mold type semiconductor device is mounted on a mounting substrate or the like. It is described that the lead terminals 41, 42, 43 are formed so as to be flush with the side surface of the resin mold 44 without being led out from the side surface of the resin mold 44.

  According to this configuration, the mounting area can be reduced by an amount that does not lead out the leading end portions of the lead terminals 41, 42, and 43, and the effective area ratio can be slightly improved, but the size of the dead space is greatly improved. Not.

  In order to improve the effective area ratio, it is necessary to make the semiconductor chip area and mounting area of the semiconductor device substantially the same. In the resin mold type semiconductor device, as in this prior art, the tip of the lead terminal Even if the part is not derived, it is difficult to improve the effective area ratio due to the presence of the mold resin.

  Further, in the above semiconductor device, the lead terminal to be connected to the semiconductor chip and the mold resin are indispensable, and therefore, a process of wire connection process between the semiconductor chip and the lead terminal and an injection molding process of the mold resin are required. There is a problem that the cost and the manufacturing process are complicated, and the manufacturing cost cannot be reduced.

  In order to maximize the effective area ratio, as described above, by mounting the semiconductor chip directly on the mounting substrate, the area of the semiconductor chip and the mounting area are almost the same, and the effective area ratio is maximized.

  As one prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in JP-A-6-338504, a flip chip in which a plurality of bump electrodes 46 are formed on a semiconductor chip 45 is used as a mounting substrate. A technique for 47 face down bonding is known (see FIG. 25). In this prior art, a gate (base) electrode, a source (emitter) electrode, and a drain (collector) electrode are usually formed on the same main surface of a silicon substrate such as a MOSFET, and a current or voltage path is formed in a horizontal direction. It is mainly used for horizontal semiconductor devices that generate a relatively small amount of heat.

  However, in a vertical semiconductor device such as a transistor device where a silicon substrate is one of the electrodes and each electrode is formed on a different surface and the current path flows in the vertical direction, the above-described flip chip technology is not used. Have difficulty.

  As another prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in Japanese Patent Laid-Open No. 7-38334, a semiconductor chip 53 is formed on a conductive pattern 52 formed on a mounting substrate 51. A technique of bonding and connecting electrodes of the conductive pattern 52 and the semiconductor chip 53 arranged around the semiconductor chip 53 with a wire 54 is known (see FIG. 26). This prior art can be used for a semiconductor chip such as a transistor having a vertical structure in which the above-described silicon substrate constitutes one electrode.

  Since the wire 54 that connects the semiconductor chip 53 and the conductive pattern 52 disposed around the semiconductor chip 53 is usually a gold fine wire, the peel strength (tensile force) of the bonding joint that is bonded to the gold fine wire is increased. Therefore, it is preferable to perform bonding in a heated atmosphere of about 200 ° C. to 300 ° C. However, when a semiconductor chip is die-bonded on an insulating resin-based mounting substrate, the wiring substrate is distorted when heated to the above temperature, and a chip capacitor mounted on the mounting substrate, a chip resistor, etc. Since the solder for fixing other circuit elements is melted, wire bonding connection is performed at a heating temperature of about 100 ° C. to 150 ° C., so that there is a problem that the peel strength of the bonding junction is lowered.

  In this prior art, since the die-bonded semiconductor chip is usually covered and protected with a thermosetting resin such as an epoxy resin, the reduction in peel strength is caused by the shrinkage during the thermosetting of the epoxy resin and the joint part is peeled off. There is a problem that.

  Furthermore, conventionally, when connecting an active element such as a bipolar IC or MOSIC on a mounting substrate, a resin-molded transistor and a bipolar IC must be individually mounted. As described above, the mounting substrate Reduce the mounting area ratio.

  The present invention has been made in view of the above-described circumstances, and the present invention does not require a lead terminal connected to a semiconductor chip and a mold resin, and a semiconductor chip area and a mounting area mounted on a mounting substrate. The effective area ratio, which is the ratio of the above, is maximized, the dead space of the mounting area is minimized, and a method for manufacturing a semiconductor device with high functionality and excellent connection reliability is provided.

The present invention has been made in view of the above problems,
First, a semiconductor device in which wiring is provided on a semiconductor chip,
The problem is solved by providing wirings that are not electrically connected to the elements formed on the semiconductor chip and have exposed electrical connection portions in at least two places.

  Second, the problem is solved by providing the semiconductor chip electrically connected to the wiring on the semiconductor chip provided with the wiring.

Third, a semiconductor device in which a second semiconductor chip is provided on the first semiconductor chip,
The problem is solved by providing a wiring for electrically connecting one region to the second semiconductor element on the first semiconductor chip.

  Fourth, the other region of the wiring is solved by being electrically connected to the external connection electrode.

Fifth, a first semiconductor chip in which an IC circuit is formed in the chip;
A first wiring provided on the first semiconductor chip and electrically connected to the IC circuit;
A second wiring provided on the formation region of the IC circuit and extending by exposing the first connection region and the second connection region;
The present invention solves this by including a second semiconductor chip connected to the first connection region and disposed opposite to the surface of the first semiconductor chip on which the IC circuit is formed.

  Sixth, the second connection region is solved by being electrically connected to the external connection electrode.

Seventh, a first semiconductor chip in which an IC circuit is formed in the chip;
A first wiring provided on the first semiconductor chip and electrically connected to the IC circuit;
A second wiring provided on the formation region of the IC circuit and extending by exposing the first connection region and the second connection region;
A second semiconductor chip connected to the first connection region and disposed opposite to the surface of the first semiconductor chip on which the IC circuit is formed;
One surface of the first semiconductor chip is positioned around the second semiconductor chip, and the second wiring extends from the region where the second semiconductor chip is disposed to the one surface. It is a solution.

Eighth, a first semiconductor chip in which an IC circuit is formed in the chip;
A first wiring provided on the first semiconductor chip and electrically connected to the IC circuit;
A second wiring provided on the formation region of the IC circuit and extending by exposing the first connection region and the second connection region;
A second semiconductor chip connected to the first connection region and disposed opposite to the surface of the first semiconductor chip on which the IC circuit is formed;
One surface of the first semiconductor chip is positioned around the second semiconductor chip, and the first wiring extends from the arrangement region of the second semiconductor chip to the one surface. It solves with the feature.

  Ninthly, the semiconductor chip provided with the diffusion region is provided on the one surface, and the second connection region and the diffusion region are connected to solve the problem.

  By providing wiring for elements provided on the semiconductor chip, a semiconductor chip in which elements can be provided on the upper surface can be realized.

  Further, in a semiconductor device in which the second semiconductor chip is mounted on the first semiconductor chip, one electrode of the second semiconductor chip can be extended to another region, or one electrode of the first semiconductor chip can be extended. Can extend to another area.

  Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to FIGS.

  First, as shown in FIG. 1, for example, an N− type epitaxial layer 66 is formed on a wafer-like first semiconductor substrate 60 made of an N + type single crystal silicon substrate by an epitaxial growth technique. The predetermined region of the first semiconductor substrate 60 includes an active element formation region 61 in which a first active element such as a power MOS and a transistor is formed, and at least a first active element or an electrode of a second active element to be described later. A plurality of external connection electrodes 63, 64. . . External connection electrode regions 63A, 64A. . . (See FIG. 14). For example, the first active element region 61 and the external connection electrode regions 63A, 64A. . . Are formed as a block on the first substrate 60 in a grid pattern.

  The first active element described above is formed in the active element formation region 61. Here, it is assumed that a transistor having an N − type epitaxial layer as a collector region 66A is formed. A photoresist is formed on the first substrate 60, the photoresist on each active element formation region 61 is selectively removed, and P-type impurities such as boron (B) are selectively thermally diffused in the exposed regions. Thus, an island-shaped base region 71 having a predetermined depth is formed.

  After the base region 71 is formed, the photoresist is removed, a photoresist is formed again on the first substrate 60, and the photoresist on each active element forming region 61 (external connection electrode regions 63A, 64A,...) Is formed. Are selectively removed, and N-type impurities such as phosphorus (P) and antimony (Sb) are selectively thermally diffused in the exposed base region 71 to form an emitter region 72 of the transistor. When the emitter region 72 is formed, a ring-shaped guard ring N + -type diffusion region 73 surrounding the base region 71 is formed. When forming the N + -type emitter region 72, the N + -type diffusion is caused by the electrode regions 63A, 64A. . . The electrode regions 63A, 64A. . . Then, a high concentration diffusion layer 81 is formed.

  An insulating film 74 such as a silicon oxide film or a silicon nitride film is formed on the surface of the first semiconductor substrate 60. The insulating film 74 has a base contact hole exposing the surface of the base region 71, an emitter contact hole exposing the surface of the emitter region 72, a guard ring contact hole exposing the surface of the guard ring diffusion region 73, and an electrode serving as an external connection electrode. Regions 63A, 64A. . . The external connection contact hole is exposed.

  On the base region 71, the emitter region 72, the electrode regions 63A and 64A, and the guard ring diffusion region 73 exposed by the base contact hole, the emitter contact hole, the external connection contact hole and the guard ring contact hole, aluminum or the like is selectively formed. A base electrode 75, an emitter electrode 76, and a connection electrode 77 are formed by vapor-depositing the above metal material.

  When aluminum is used for the base electrode 75, the emitter electrode 76, and the connection electrode 77, a passivation film 74A made of an insulator such as a PSG film, SiN, or SiNx is formed on the substrate 60, and the base electrode 75, emitter The passivation film 74A on the electrode 76 and the connection electrode 77 is selectively removed to expose the surfaces of the electrodes 75, 76, and 77. Further, chromium, copper, titanium, or the like is selectively deposited by plating or vapor deposition in the exposed region to form a first barrier metal film 79, thereby preventing problems due to corrosion of the electrodes 75, 76, 77.

Next, as shown in FIG. 2, bump electrodes 121 are formed on the first barrier metal films 79. FIG. 3 is an enlarged cross section showing a region where each bump electrode 121 is formed.

In the figure, a bump electrode 121 having a height of about 30 to 50 μm is formed on the first barrier metal film 79 of each of the electrodes 75, 76 and 77. The bump electrode 121 is formed by a gold plating process. On the surface of the bump electrode 121, chromium, copper, titanium, or the like is selectively attached by plating or vapor deposition to form a second barrier metal film 122 having a thickness of several thousand angstroms. .

Further, a bonding metal is deposited on the second barrier metal 122 to form a bonding layer 123 in order to electrically bond to another substrate described later. This bonding layer 1

The metal material used for 23 has a melting point lower than the melting point of the bump electrode 121 made of gold (Au) and higher than the melting point of the solder material used for mounting on the mounting substrate described later. Used. Specifically, the melting point of gold (Au) is usually about 1064 ° C., and the melting point of the solder material used for mounting on the mounting substrate is about 170 ° C. to 190 ° C. Any material may be used as long as it has a melting point within the temperature range of both, and for example, gold tin (AuSn) having a melting point of about 370 ° C. is used.

  Each active element formation region 61 and each external connection electrode region 63A, 64A. . . Can be arranged, for example, as shown in FIG.

  Next, a second active element or the like is formed on the second semiconductor substrate 100 fixed to the first semiconductor substrate 60. For example, a wafer-like semiconductor substrate made of a single crystal P-type silicon substrate is used as the second semiconductor substrate 100, and a second active element such as a bipolar IC or MOSIC is formed on the substrate 100.

  For example, as shown in FIG. 4, a photomask having a predetermined shape is formed on a P-type second semiconductor substrate 100, and an N-type high concentration impurity such as antimony is diffused to form an island-like N + type buried collector. Region 101 is formed. After removing the photomask, an N− type epitaxial layer 102 is formed on the second substrate 100 by an epitaxial growth technique.

  Next, a mask that exposes the isolation diffusion region is formed on the epitaxial layer 102, and P + type impurities such as boron are diffused into the isolation diffusion region to form the isolation diffusion region 103. By this isolation diffusion region 103, an N-type region which becomes an active region of the transistor is surrounded by a P-type impurity. A photoresist is formed on the epitaxial layer 102, and a P-type impurity such as boron (B) is selectively thermally diffused in a region exposed by the photoresist to form an island-shaped base region 104 having a predetermined depth. .

  After the base region 104 is formed, a photoresist is formed again on the epitaxial layer 102, and N-type impurities such as phosphorus (P) and antimony (Sb) are selectively introduced into the base region 104 and the collector region exposed by the photoresist. Thermal diffusion forms the emitter region 105 and collector contact diffusion region 106 of the transistor.

  A silicon oxide film having a base contact hole exposing the surface of the base region 104, an emitter contact hole exposing the surface of the emitter region 105, and a collector contact hole exposing the surface of the collector contact diffusion region on the surface of the second semiconductor substrate 100, Alternatively, an insulating film 141 such as a silicon nitride film is formed.

  The base region 104, the emitter region 106, and the collector contact region 107 exposed by the base contact hole, the emitter contact hole, and the collector contact hole are selectively formed by a base electrode 107, an emitter electrode 108, The collector electrode 109 and, if necessary, the wiring A extending from these electrodes are arranged and formed up to a predetermined position. In the present embodiment, the collector electrode wiring 109 </ b> A is extended to a predetermined position so as to be connected to the external connection electrode of the first substrate 60.

  When aluminum is used for the base electrode 107, the emitter electrode 108, and the collector electrode 109, a passivation film 110 made of an insulator such as a PSG film, SiN, or SiNx is formed on the second substrate 100, and the base electrode 107 is formed. The passivation film 110 on the emitter electrode 108 and the collector electrode 109 or / and if necessary, on the predetermined position of the wiring A extending from the electrodes 107, 108, 109 is selectively removed, and the electrodes 107, 108 are selectively removed. 109 or / and the surface of the wiring A is exposed. Further, chromium, copper, titanium, or the like is selectively plated or deposited in the exposed region to form a first barrier metal film 111 to prevent problems due to corrosion of each electrode or the like.

  Further, in the second active element formation region of the second substrate 100, the first active element electrode formed in the active element formation region 61 of the first substrate 60 and the first substrate 60 are formed. Redundant pattern wiring 112 for connecting the external connection electrodes is formed. The pattern wiring 112 uses a general multilayer wiring technique, and is formed by, for example, selectively depositing metal on aluminum or the like, and a passivation film 113 made of an insulator such as PSG film, SiN, SiNx, or the like on the upper surface thereof. Then, the passivation film on a predetermined position of the pattern wiring is selectively removed, and the surface of the wiring 112 is exposed. Further, as described above, chromium, copper, titanium, or the like is selectively plated or deposited in the exposed region to form the first barrier metal film 114, thereby preventing problems caused by corrosion of the exposed pattern wiring 112. is doing.

  Next, as shown in FIG. 5, a dump electrode 131 is formed on each of the first barrier metal films 111 and 114. As described above, the bump electrode 131 forms the bump electrode 131 having a height of about 30 to 50 μm as shown in FIG. The metal material used for the bonding layer 133 has a melting point lower than the melting point of the bump electrode 131 made of gold (Au), and more than the melting point of the solder material used for mounting on the mounting substrate described later. High material is used. Specifically, when the melting point of gold (Au) is normally about 1064 ° C. and the melting point of the solder material used for mounting on the mounting substrate is about 170 ° C. to 190 ° C., it is used for the bonding layer 133. Any material may be used as long as it has a melting point within the temperature range of both, and for example, gold tin (AuSn) having a melting point of about 370 ° C. is used.

  In the second active element region of the second substrate 100, although not clearly shown in FIGS. 4 and 5, elements such as a plurality of transistors and diodes are formed and a bipolar IC having a predetermined function is formed.

  Next, as shown in FIGS. 6 and 7, the bump electrodes 121 and 131 formed on both the substrates 60 and 100 are bonded together, and a resin layer 78 is formed between the substrates 60 and 100. A plurality of bump electrodes 121 and 131 formed on both substrates 60 and 100 are brought into contact with each other, and bonding layers 123 and 133 formed on the bump electrodes 121 and 131 are melted to bond bump electrodes 121 and 131 made of gold bumps. Bonding is performed between the bonding layers 123 and 133 without using them as materials.

  For example, the bump electrodes 121 and 131 formed on both the substrates 60 and 100 are aligned and placed in a heated atmosphere, and only the bonding layers 123 and 133 formed on the bump electrodes 121 and 131 are melted to perform electrical bonding. Do. As described above, since the second barrier metal films 122 and 132 are interposed between the bonding layers 123 and 133 and the bump electrodes 121 and 131, the molten metal material and the bump electrodes of the bonding layers are interposed. Is prevented from eutectic with gold (Au). What is important here is that each of the bump electrodes 121 and 131 is formed on the first substrate 60 by the bonding layers 123 and 133 formed on both the barrier metals 122 and 132 in the composition state immediately after plating. The first and second active elements formed on both substrates 60 and 100 are electrically connected to the electrodes of the first active element and the connection electrode 77 formed in the external connection electrode region. It is to conduct the continuity.

  After the two substrates 60 and 100 are electrically connected, an adhesive resin layer 78 is formed between the semiconductor substrates 60 and 100 to firmly fix and support the substrates 60 and 100. As described above, both the substrates 60 and 100 are aligned so that the bump electrodes 121 and 131 formed on the both substrates 60 and 100 coincide with each other, and the bonding layer formed on the bump electrodes 121 and 131 is melted to electrically The electrodes 75, 76, 77 on the first substrate 60 are electrically connected to the electrodes and the wiring pattern on the second substrate 100, and then a predetermined pressure is applied to both the substrates 60, 100. In addition, an impregnating material composed of a liquid epoxy-based thermosetting resin is poured between the substrates 60 and 100 to perform heat treatment, and the resin material 78 is formed by curing the impregnating material to form both the substrates 60 and 100. To fix.

  If the bump electrodes 121 and 131 formed on both substrates 60 and 100 are too low, the distance between the substrates 60 and 100, that is, the thickness of the resin layer 78 becomes thin, and slit holes 80 described later are formed. In some cases, the tip of the slit hole 80 may reach the surface of the second substrate 100, and the wiring pattern 112 or the second active element may be cut, so that the distance between the substrates 60 and 100 needs to be kept sufficiently. It is necessary to consider the height of each bump electrode 121, 131.

  Next, as shown in FIG. 8, a plurality of slit holes 80 for cutting the first substrate 60 from the opposite main surface side of the first substrate 60 are formed, and the first active element formation region 61 and the external connection electrodes are formed. The regions 63A and 64A are electrically separated. The slit hole 80 is formed by using a dicing blade by a dicing apparatus.

  The reason why the slit hole 80 is formed by using the dicing apparatus is that the width and depth of dicing can be controlled with high accuracy and that the existing equipment is not required to be newly purchased. The dicing width is set according to the width of the dicing blade, and the dicing depth varies depending on the manufacturer of the dicing device. However, the current technology has an accuracy error of about 2 μ to 5 μ, and the wiring pattern 112 on the second substrate 100 is cut. Therefore, it is possible to reliably cut only the first substrate 60 and to electrically isolate the active element formation region 61 and the external connection electrode regions 63A and 64A.

  Below, the process of forming the slit hole 80 will be described.

  As shown in FIG. 9, it arrange | positions and hold | maintains so that the 1st board | substrate 60 may become the surface on the table 151 of a dicing apparatus. Thereafter, as shown in FIG. 10, infrared light emitted from the infrared lamp device 154 and transmitted to the inside of the first substrate 60 is irradiated on the surface of the first substrate 60, and reflected light is detected by a detection device 153 such as an infrared monitor. Detecting and aligning the positions of the slit hole forming regions, the plurality of slit holes 80 are formed by the dicing blade 155 as shown in FIG. If a dicing apparatus with an infrared function is used, slit holes 80 for accurately cutting the first substrate even from the back side of the first substrate 60 and slit holes 80A for dividing the semiconductor device individually are formed. In a dicing apparatus without an infrared function, it is necessary to perform dicing from the back surface side (element formation opposite surface) of the first substrate 60, and the slit holes 80 and 80A are accurately formed because alignment cannot be performed accurately. Is difficult.

  For example, in the case of a semiconductor device having an equivalent circuit including a transistor Q and a control circuit having four input terminals for controlling the transistor Q as shown in FIG. 12, the transistor Q is formed on the first substrate 60 and is controlled. The circuit is formed on the second substrate 100. At this time, it is assumed that the control circuit is composed of, for example, a bipolar IC. For example, the external connection electrodes of the semiconductor device having such an equivalent circuit are arranged as shown in FIG. The external connection electrode 62 for Vcc (collector terminal) of the transistor Q is disposed at the upper center portion, and the external connection electrode 63 for output is disposed at the lower left portion. The three-input external connection electrodes 64, 65, and 66 and the ground external connection electrode 67 of the control circuit are arranged at the remaining positions. Here, 65A. . . 67A indicates an electrode region before separation.

  More specifically, the active element formation region 61 of the first substrate 60 is the external connection electrode 62 for VCC of the semiconductor device, the external connection electrode region 63A is the external connection electrode 63 for input, and the external connection electrode region 64A. . . . Input external connection electrode 64. . . The external connection electrodes 62, 63, 64... For the respective input / output of the semiconductor device on the same plane using the same first semiconductor substrate 60. . . Will be formed.

  Accordingly, in this case, the slit hole 80 formed in the first substrate 60 includes, as shown in FIG. 14, the external connection electrode 62 for the VCC (collector terminal) of the transistor Q, the external connection electrode 63 for output, and the control. The external connection electrodes 64, 65, 66 for three inputs of the circuit and the external connection electrode 67 for grounding are partitioned and formed so as to be electrically insulated and separated (one-dot chain line region). Further, when the slit hole 80 is formed, the slit hole 80A for cutting the first substrate 60 is also formed in the region surrounding the external connection electrodes 62, 63, 64, 65, 66 and 67 surrounding one block (oblique lines). region). As described above, the slit 80A is used when the semiconductor devices are individually separated and independent.

The dicing width of the slit hole 80 formed in this step is such that the adjacent electrodes 62, 63, 64. . . For example, about 0.

Perform at 1mm width. In addition, the dicing width of the slit hole 80A for separating the semiconductor device is about 0.1 mm as in the case of the slit hole 80 because of the necessity to leave the resin layer on the side surfaces of the individually separated semiconductor devices, which will be described later. Since the slit holes 80 and 80A have substantially the same width, the slit holes 80 and 80A can be processed in the same process using the above-described dicing apparatus with an infrared function.

  As described above, the depth of the dicing (slit holes 80, 80A) is assured that the active element formation region 61, the external connection electrode regions 63A, 64A. . . In order to electrically isolate (external connection electrodes 62, 63, 64, 65, 66 and 67), the first substrate 60 is cut so that the resin layer 78 enters about 2 μ to 5 μ.

  If the thickness of the resin layer 78 is set in consideration of a dicing error of the dicing apparatus, the second active element and the wiring pattern 67 formed on the second substrate 100 in the dicing process for forming the slit holes 80 and 80A. Etc. will not break.

  As described above, the plurality of first active element formation regions 61 formed on the first substrate 60 and the external connection electrode regions 63A, 64A. . . Are electrically separated from each other by a plurality of slit holes 80 formed from the back surface side of the first substrate 60, and the external connection electrodes 62, 63, 64. . It becomes. That is, as described above, the first semiconductor substrate 60 is used and the external connection electrodes 62, 63, 64. . Will be formed.

  When the depth of the slit hole 80 becomes shallower, the external connection electrodes 62, 63, 64. . . Of the external connection electrodes 62, 63, 64. . . . As described above, the front end (bottom) of the slit hole 80 is formed so as to be in the resin layer 78 by about 2 to 6 μm. The external connection electrodes 62, 63, 64... Of the first substrate 60 electrically separated by the slit holes 80. . . Are individually independent, but are held by the resin substrate 78 with the second substrate 100.

  External connection electrode regions 64A, 63A. . . As described above, the high concentration diffusion layer 81 is formed, and the external connection electrodes 64. . . . . And the loss due to the wiring resistance connecting each electrode is reduced. The high-concentration diffusion layer 81 includes electrode regions 64A, 63A. . . When the film thickness of the epitaxial layer 66 is relatively thin, the epitaxial layer 66 is formed by the diffusion process for forming the emitter region 72 as described above.

  When the epitaxial layer 60 is relatively thick, the electrode regions 63A, 64A. . . If an N + type impurity is deposited thereon, then the epitaxial layer 60 is formed, and further a thermal diffusion process is performed so that the high concentration diffusion region 81 is grown from the first substrate 60 side. When the emitter region 72 is formed, the high concentration diffusion regions 81 and 81 come into contact with each other, and the electrode regions 63A, 64A. . . A high concentration diffusion layer 81 can be formed therein.

  In the present embodiment, since a plating layer is formed on the surface of the first substrate 60 serving as the external connection electrode, before the slit holes 80 and 80A are formed, the slit holes 80 and 80A are formed in the region as shown in FIG. Then, the first substrate 60 is subjected to a dicing process (the surface of the first substrate 60 is shaved) with a trapezoidal dicing blade using the above-described dicing apparatus. In this dicing process, the external connection electrodes 62, 63, 64. . A tapered portion 91 is formed at the edge portion. The angle of the taper portion 91 is determined by the shape of the dicing blade, and can be arbitrarily set depending on the size of the solder joint portion and the amount of solder.

  A part of the first substrate 60 is deleted and the external connection electrodes 62, 63, 64. . After the taper portion 91 is formed at the edge portion, a metal plating layer 93 such as solder is formed on the surface of the first substrate 60. The plating layer 93 is formed on the entire surface of the first substrate 60 by using a plating process such as electroplating or electroless plating. After the plating layer 93 is formed, slit holes 80 and 80A are formed as shown in FIG.

  Next, as shown in FIG. 16, after the slit holes 80 and 80A are formed in the first substrate 60, the slit holes 80 and 80A are filled with a thermosetting resin such as an epoxy resin or a thermoplastic resin for insulation. Resin layers 95 and 95A are formed. The resin layers 95 and 95A filled in the slit hole 80 ensure electrical separation of the separated external connection electrodes 62, 63 and 64, and the insulating resin layer 95A filled in the slit hole 80A. Prevents the leakage current by leaving the resin layer 95A on the side surface when the semiconductor device is divided individually.

  Further, by filling the resin layers 95, 95A into the slit holes 80, 80A, the adhesive strength between the external connection electrodes 62, 63, 64 is improved, and the state of the wafer substrates 60, 100 and the semiconductor after division Prevents adverse effects on external stress such as device stress. Since the width of the slit holes 80 and 80A is as small as several meters, the slit holes 80 and 80A can be easily filled by using an impregnating thermosetting resin.

  That is, by applying the above-described impregnating resin on the first substrate 60, the resin fills the slit holes 80 and 80A to form the resin layers 95 and 95A. At this time, the resin layers 95 and 95A also remain in a thin film state on the surface of the first substrate 60.

  Next, as shown in FIG. 17, the resin layer remaining on the back surface of the first substrate 60 is removed by polishing the back surface of the first substrate 60 using a polishing apparatus such as a back glider. The surface of the first substrate 60 (plating layer 93) is exposed. Thereafter, the resin layer adhering in the shape of the slit holes 80 and 80A is removed with a trapezoidal dicing blade using a dicing device in the region where the slit holes 80 and 80A of the first substrate 60 are formed, and the plating layer 93 is exposed. Let

  As shown in FIG. 18, when the semiconductor device of the present invention is mounted on the mounting substrate, the taper portion 91 is formed with pads (lands) formed on the mounting substrate and the external connection electrodes 62, 63, 64. Are formed in order to optimize the solder fillet shape of the solder joint portion, for example, to improve the strength against external stress of the solder joint portion due to thermal shrinkage or the like.

  After the plating layer 93 is exposed on the surface of the first substrate 60, dicing is performed at the substantially central portion of the slit hole 80A, and the substrates 60 and 100 are divided into individual semiconductor devices as shown in FIG. In this dividing step, the first substrate 60 is placed on the table of the dicing apparatus so that the first substrate 60 is on the upper side, held, aligned with the slit holes 80A for division, and dicing is performed with a dicing blade. To do.

  As described above, the resin layer 95 </ b> A can be left on the side surface of the divided semiconductor device, and a problem of leakage current leaking from the external connection electrodes 63 and 64 can be suppressed. Individually divided semiconductor devices are individually taped and wound into a reel after predetermined measurements and label printing.

  The semiconductor device manufactured by the manufacturing method described above is fixedly mounted on a pad of a conductive pattern formed on a wiring substrate such as a ceramic substrate, a glass epoxy substrate, a phenol substrate, or a metal substrate subjected to insulation treatment. A solder layer in which solder cream is pre-printed is formed on the pad, and the semiconductor device can be fixedly mounted on the pad of the wiring board by melting the solder and mounting the semiconductor device of the present invention. .

  At this time, as described above, the taper portion 91 is formed at the edge portion of each of the external connection electrodes 62, 63, 64, so that the solder fillet at the solder joint portion with the conductive pad (land) of the mounting substrate is formed. It is possible to optimize the joint strength of the solder joint portion and improve the connection reliability. Although not shown in the drawing, this fixed mounting process can be performed in the same process as the mounting process of other circuit elements mounted by solder such as a chip capacitor and a chip resistor mounted on the mounting substrate.

  Further, at this time, when the semiconductor device provided by the manufacturing method of the present invention is mounted on the wiring board, the external connection electrodes 62, 63, 64. . Are separated from each other by the interval of the slit holes 80, so that the solder fixed to the mounting substrate is adjacent to the external connection electrodes 62, 63, 64. . Will not short circuit.

  By the way, as shown in FIG. 14, in the semiconductor device of this embodiment, for example, the active element active element formation region 61 having substantially the same function as the semiconductor device described in the conventional example is 0.5 mm × 0.5 mm in size, In the semiconductor device in which the connection electrode regions 63A and 64A serving as the base and emitter electrodes have a size of 0.3 mm × 0.2 mm and the width of the slit hole 80 is 0.1 mm, the effective area ratio is as follows. That is, the element area is 0.25 mm, and the area of the semiconductor device as the mounting area is 1.28 mm, so that the effective area ratio is about 19.53%.

  Since the effective area ratio of the semiconductor device having the chip size of 0.40 mm × 0.40 mm described in the conventional example is 6.25% as described above, the effective area ratio of the semiconductor device of the present invention is about 3. It becomes 12 times larger, the dead space of the mounting area to be mounted on the mounting board can be reduced, and it can contribute to the downsizing of the mounting board.

  As described above, the first semiconductor substrate 60 on which the first active element or the like is formed and the second semiconductor substrate 100 on which the second active element connected to the first active element is separated by a predetermined distance. The first active element and the second active element are electrically connected, the second semiconductor substrate 100 is held on the table of the dicing apparatus, and the back surface side of the first semiconductor substrate 60 After aligning the substrate with infrared rays, a plurality of grooves (slit holes) 80 reaching the surface of the first semiconductor substrate 60 from the back surface side of the first semiconductor substrate 60 are formed, and the first and second By dividing the semiconductor substrates 60 and 100 into a predetermined size, a metal lead terminal connected to an external electrode and a protective sealing mold can be made unnecessary as in a conventional semiconductor device, And the external dimensions of the semiconductor device It is possible to reduce the size of the verses.

  Further, as described above, since the slit hole 80 is formed using a dicing apparatus with an infrared function, the slit hole can be formed accurately.

  In this embodiment, a transistor is formed in the active element formation region 61 of the first substrate 60. However, the present invention is not limited to this as long as it is a vertical type or a horizontal type device with a relatively small amount of heat generation. For example, a power MOSFET, IGBT, Needless to say, the present invention can be applied to a device such as an HBT.

As described above in detail, according to the method for manufacturing a semiconductor device of the present invention, the first semiconductor substrate on which the first active element or the like is formed, and the second active element connected to the first active element are provided. The formed second semiconductor substrate is disposed at a predetermined interval, the first active element and the second active element are electrically connected, and the second semiconductor substrate is placed on the table of the dicing apparatus. A plurality of grooves (slit holes) reaching the first semiconductor substrate surface from the back surface side of the first semiconductor substrate are formed after holding and aligning by irradiating the back surface side of the first semiconductor substrate with infrared rays. By dividing the first and second semiconductor substrates into a predetermined size, there is no need for a metal lead terminal connected to the external electrode and a protective sealing mold as in the conventional semiconductor device. The external dimensions of the semiconductor device. It is possible to reduce the size of the verses.

  In addition, as described above, the slit hole can be accurately formed in order to form the slit hole using a dicing apparatus with an infrared function, and the above-described miniaturized semiconductor device that suppresses defects during the manufacturing process can be obtained. Can be provided.

Sectional drawing which shows the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows a bump electrode. Sectional drawing which shows the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows the junction part of a bump electrode. Sectional drawing which shows the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of this invention. FIG. 6 is a diagram showing an equivalent circuit of a general semiconductor device. The figure which shows the back surface of the semiconductor device of this invention. The figure which shows the back surface of the semiconductor device of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of this invention. Sectional drawing which shows the conventional semiconductor device. Sectional drawing of a general transistor. Sectional drawing which mounted the conventional semiconductor device on the wiring board. The top view of the conventional semiconductor device. The top view of the conventional semiconductor device. The figure which shows the conventional semiconductor device. The figure which shows the conventional semiconductor device.

Claims (9)

A semiconductor device in which wiring is provided on a semiconductor chip,
A semiconductor device, characterized in that a wiring which is not electrically connected to an element formed in the semiconductor chip and has exposed electrical connection portions is provided in at least two places.   The semiconductor device according to claim 1, wherein a semiconductor chip electrically connected to the wiring is provided on the semiconductor chip provided with the wiring. A semiconductor device in which a second semiconductor chip is provided on the first semiconductor chip;
A semiconductor device, wherein a wiring for electrically connecting one region to the second semiconductor element is provided on the first semiconductor chip.   The semiconductor device according to claim 3, wherein another region of the wiring is electrically connected to an external connection electrode. A first semiconductor chip having an IC circuit formed in the chip;
A first wiring provided on the first semiconductor chip and electrically connected to the IC circuit;
A second wiring provided on the formation region of the IC circuit and extending by exposing the first connection region and the second connection region;
A semiconductor device comprising: a second semiconductor chip connected to the first connection region and disposed opposite to a surface of the first semiconductor chip on which an IC circuit is formed.   The semiconductor device according to claim 5, wherein the second connection region is electrically connected to an external connection electrode. A first semiconductor chip having an IC circuit formed in the chip;
A first wiring provided on the first semiconductor chip and electrically connected to the IC circuit;
A second wiring provided on the formation region of the IC circuit and extending by exposing the first connection region and the second connection region;
A second semiconductor chip connected to the first connection region and disposed opposite to the surface of the first semiconductor chip on which the IC circuit is formed;
One surface of the first semiconductor chip is located around the second semiconductor chip, and the second wiring extends from the arrangement region of the second semiconductor chip to the one surface. A featured semiconductor device. A first semiconductor chip having an IC circuit formed in the chip;
A first wiring provided on the first semiconductor chip and electrically connected to the IC circuit;
A second wiring provided on the formation region of the IC circuit and extending by exposing the first connection region and the second connection region;
A second semiconductor chip connected to the first connection region and disposed opposite to the surface of the first semiconductor chip on which the IC circuit is formed;
One surface of the first semiconductor chip is located around the second semiconductor chip, and the first wiring extends from the arrangement region of the second semiconductor chip to the one surface. A featured semiconductor device. 9. The semiconductor device according to claim 7, wherein a semiconductor chip provided with a diffusion region is provided on the one surface, and the second connection region and the diffusion region are connected.