JP2006020024A - Electronic zoom device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic zoom device whose zoom power can freely set with simple constitution while applied to an imaging device such as a television camera etc. <P>SOLUTION: In one horizontal scanning period of input image data D1, image data D3 of a plurality of lines are repeatedly outputted to a vertical filter 8, line by line, and interpolation arithmetic processing is carried out. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electronic zoom device, and can be applied to an imaging device such as a television camera. In the present invention, in one horizontal scanning period of input image data, image data of a plurality of lines is repeatedly output to a vertical filter in units of lines and subjected to interpolation calculation processing, so that a zoom magnification can be freely set with a simple configuration. To be able to.

  Conventionally, in an imaging apparatus such as a television camera, an imaging result is enlarged by an electronic zoom. In such an electronic zoom, for example, as disclosed in Japanese Patent Laid-Open No. 2000-209480, the image size is enlarged in the vertical direction and the horizontal direction via a frame memory.

  On the other hand, in Japanese Patent Laid-Open No. 5-227464, etc., the number of pixels and the number of lines related to the thinning are changed according to the magnification of the electronic zoom, by thinning out from the CCD image sensor and outputting the imaging result. There has been proposed a method of electronic zooming by changing a region where an imaging result is output, and thereby controlling driving of an image sensor.

  However, the method using the frame memory has a problem that a large-capacity memory must be used. In particular, when the resolution of the image sensor increases, the capacity of the frame memory increases accordingly.

On the other hand, in the method of electronic zooming by controlling the driving of the image sensor, the magnification of the electronic zoom is eventually limited by the number of lines and the number of pixels of the image sensor, and thus the magnification of the electronic zoom cannot be set freely. There's a problem.
JP 2000-209480 A JP-A-5-227464

  The present invention has been made in view of the above points, and an object of the present invention is to propose an electronic zoom device that can freely set the zoom magnification with a simple configuration.

  In order to solve this problem, the invention of claim 1 is applied to an electronic zoom device that outputs image data by enlarging image data at a desired zoom magnification, and has at least three or more line memories. In addition, a plurality of line memories are sequentially and cyclically selected and sequentially input image data is recorded in the line memory, and a plurality of lines of image data are simultaneously and parallelly stored from the remaining line memories of the plurality of line memories. A memory circuit that reads and outputs, a vertical filter that interpolates and outputs multiple lines of image data output from the memory circuit, and interpolates the output data of the vertical filter, and horizontally by zoom magnification A horizontal filter for outputting the enlarged output image data, and the memory circuit outputs one horizontal level of the input image data according to the zoom magnification. By repeatedly outputting multiple lines of image data line by line during the inspection period, image data enlarged in the vertical direction by the zoom magnification is output from the vertical filter, and at multiple clock cycles according to the zoom magnification. By outputting one image data, the image data expanded in the horizontal direction by the zoom magnification is output from the horizontal filter.

  According to the configuration of the first aspect, the memory circuit repeatedly outputs a plurality of lines of image data in units of lines in one horizontal scanning period of the image data in accordance with the zoom magnification, thereby enlarging the image in the vertical direction with the zoom magnification. By outputting the data from the vertical filter and outputting one image data at a plurality of clock cycles according to the zoom magnification, the image data expanded in the horizontal direction by the zoom magnification is output from the horizontal filter. By doing so, output image data can be obtained by interpolation processing relating to the number of lines and the number of pixels relating to these repeated outputs, and thus electronic zoom processing at various magnifications can be executed with a simple configuration. .

  According to the present invention, the magnification can be set freely with a simple configuration.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 1 is a block diagram illustrating an imaging apparatus according to an embodiment of the present invention. The image pickup apparatus 1 picks up an image of a desired subject using an image sensor 2 that is a solid-state image pickup device, displays image data D2 based on the image pickup result on a monitor, and records it on a recording medium.

  Here, the image sensor 2 can output an imaging result by line thinning and pixel thinning under the control of the drive circuit 3, and an imaging element such as a CMOS (Complementary Metal-Oxide Semiconductor) is applied. The image sensor 2 operates in accordance with various operation reference signals such as the pixel clock PCK, and outputs an imaging result by such line thinning and pixel thinning by the imaging signal S1. Further, the image sensor 2 outputs an imaging result with a resolution higher than the resolution of the image data D2 to be output to the monitor. In this embodiment, a VGA (Video Graphics Array) with 640 pixels × 480 lines is provided. ) Image sensor is applied.

  The drive circuit 3 outputs the imaging signal S1 with the number of pixels and the number of lines according to the resolution of the image data D2 to be output to the monitor under the control of the system controller 6 that controls the operation of the entire imaging apparatus 1. The image sensor 2 is driven.

  That is, for example, when the image data D2 to be recorded on the recording medium is 320 pixels × 240 lines by QVGA (Quarter VGA), the driving circuit 3 thins out one line with a two-line cycle, and with two-pixel cycle. A drive signal is output to the image sensor 2 so that one pixel is thinned out and the imaging signal S1 is output. Further, for example, when the image data D2 to be recorded on the recording medium is 160 pixels × 120 lines by SQVGA, 3 lines are thinned out in a 4-line cycle, and 3 pixels are thinned out in a 4-pixel cycle, and an imaging signal is obtained. A drive signal is output to the image sensor 2 so as to output S1.

  The camera signal processing circuit 4 performs an analog / digital conversion process on the imaging signal S1 output from the image sensor 2 and executes a process such as white balance adjustment, and then converts the image signal D1 into image data D1 using a luminance signal and a color difference signal. 7 is output. The camera signal processing circuit 4 operates in accordance with the pixel clock PCK output from the clock generation circuit 5 to execute these series of processes, and outputs image data D1 in synchronization with the pixel clock PCK.

  The clock generation circuit 5 generates a master clock MCK that is an operation reference signal of the imaging apparatus 1 by a reference signal generation circuit (not shown) and outputs the master clock MCK to each unit. Further, the clock generation circuit 5 divides the master clock MCK by the frequency dividing circuit 5A to generate a pixel clock PCK which is an operation reference clock for the image sensor 2, the drive circuit 3, and the camera signal processing circuit 4, and further divides the clock. The circuit 5B divides the master clock MCK to generate a rate variable clock ZCK that is an operation reference clock of the memory circuit 7 described later. The clock generation circuit 5 is configured to switch the frequency division ratios of the frequency dividing circuits 5A and 5B under the control of the clock controller 5C, and the control of the frequency division ratio by the clock controller 5C controls the overall operation of the imaging apparatus 1. Is controlled by a system controller 6.

  Thus, in this embodiment, the processing speeds of the image sensor 2 and the camera signal processing circuit 4 can be variously changed with respect to the processing speed of the memory circuit 7.

  The imaging apparatus 1 temporarily holds the image data D1 output from the camera signal processing circuit 4 in the memory circuit 7, and sequentially interpolates in the vertical direction and the horizontal direction by the vertical filter 8 and the horizontal filter 9, thereby The electronic zoom process is executed.

  That is, the vertical filter 8 performs line interpolation processing on a plurality of lines of image data output from the memory circuit 7 simultaneously in parallel, thereby generating image data of each line related to the electronic zoom processing. Specifically, for example, as shown in FIG. 2, the vertical filter 8 includes multiplication circuits 10A and 10B for weighting each tap output from the memory circuit 7, and an addition circuit 11 for adding the output data of the multiplication circuits 10A and 10B. The flip-flop circuit 12 that temporarily holds and outputs the output data of the adder circuit 11, the multiplier circuits 10A and 10B, and an interpolation circuit such as a buffer circuit provided at the output stage of the adder circuit 11 are configured. In this embodiment, the vertical filter 8 that accepts an enable control signal is applied to the flip-flop circuit 12 that outputs the interpolation result, so that the output of the processing result can be stopped at a desired timing. . The vertical filter 8 is not limited to the 2-tap interpolation circuit shown in FIG. 2, but uses a 4-tap or 8-tap interpolation circuit as shown in FIGS. 3 and 4 in comparison with FIG. For example, various configurations can be widely applied as necessary.

  Thus, the vertical filter 8 is configured such that the weighting coefficients coefA and coefB corresponding to the line interpolation ratio are set in the multiplication circuits 10A and 10B under the control of the system controller 6, thereby sampling the input image data D1 for each line. Image data of each line of the output image data D2 is sequentially generated by setting the weighting coefficients coefA and coefB according to the phase.

  The horizontal filter 9 interpolates sequentially input image data, thereby generating horizontal image data related to electronic zoom processing. Specifically, for example, as shown in FIG. 5, the horizontal filter 9 weights the flip-flop circuit 13A, which is a delay circuit corresponding to the clock cycle of the input image data, and the input image data and the output data of the flip-flop circuit 13A. Multiplier circuits 14A and 14B, an adder circuit 15 that adds the output data of the multiplier circuits 14A and 14B, a flip-flop circuit 16 that temporarily holds and outputs the output data of the adder circuit 15, and multiplier circuits 14A and 14B. It is configured by an interpolation circuit such as a buffer circuit provided at the output stage of the circuit 15. In this embodiment, the horizontal filter 9 is applied to the flip-flop circuit 13A constituting the delay circuit and the flip-flop circuit 16 that outputs the interpolation result, and receives the enable control signal, thereby interpolating at a desired timing. Can be canceled. The horizontal filter 9 is not limited to the interpolation circuit based on the 2-tap linear interpolation shown in FIG. 5, but uses a 4-tap or 8-tap interpolation circuit as shown in FIGS. 6 and 7 in comparison with FIG. For example, various configurations can be widely applied as necessary.

  In the horizontal filter 9, weighting coefficients coefA and coefB corresponding to the interpolation ratio are set in the multiplying circuits 14A and 14B under the control of the system controller 6, whereby the weighting coefficients corresponding to the sampling phase in the horizontal direction of the input image data D1. By setting coefA and coefB, each image data in the horizontal direction of the output image data D2 is sequentially generated.

  The memory circuit 7 temporarily holds the image data output from the camera signal processing circuit 4 and outputs the held image data to the vertical filter 8. Here, the memory circuit 7 has a memory capacity corresponding to the maximum horizontal sampling number of the image data D1 output from the camera signal processing circuit 4, and a plurality of line memories for recording and reproducing the image data D1. 25A to 25C, selector 26 that distributes input image data D1 to these line memories 25A to 25C, selector 27 that distributes output image data from these line memories 25A to 25C to each tap input of the vertical filter 8, and these line memories 25A to 25C The memory controller 28 controls the operations of the selectors 26 and 27.

  The memory circuit 7 sequentially selects the plurality of line memories 25A to 25C, records the sequentially input image data, and handles the remaining lines so as to correspond to the processing of the subsequent vertical filter 8 and horizontal filter 9. The stored image data is output from the memories 25A to 25C. For this reason, the memory circuit 7 is formed so as to have at least three or more line memories, and sequentially selects the plurality of line memories in a cyclic manner and records sequentially inputted image data D1 in the line memory. A plurality of lines of image data are simultaneously read out and output from the remaining line memories of the plurality of line memories. Here, in this embodiment, the line interpolation processing by the subsequent vertical filter 8 is executed by the interpolation calculation processing by two taps, so that the memory circuit 7 sets the number of line memories 25A to 25C to three. Thus, two lines of image data can be output simultaneously and in parallel from the remaining two line memories not recording the input image data D1.

  In the output of the image data, the memory circuit 7 stops recording in the line memories 25A to 25C for a predetermined number of lines, depending on the zoom magnification, thereby preventing unnecessary processing. Further, output of image data for one line to the subsequent vertical filter 8 is repeated a plurality of times during one horizontal scanning period in accordance with the zoom magnification and the line. As a result, in the image pickup apparatus 1, a plurality of lines are interpolated repeatedly by the vertical filter 8 in one horizontal scanning period, thereby performing a vertical method process in the electronic zoom process.

  Thus, as shown in FIG. 8, in VGA, one screen is formed by 480 lines × 640 pixels, whereas in CIF (Common Intermediate Format), one screen is formed by 288 lines × 352 pixels. One screen is formed by 240 lines × 320 pixels. In QCIF (Quarter CIF), one screen is formed by 144 lines × 176 pixels, and in SQVGA (Super Quarter CIF), one screen is formed by 120 lines × 160 pixels.

  Accordingly, as shown in FIG. 9, in the VGA (FIG. 9B), one horizontal scanning period by the horizontal synchronizing signal HD (FIG. 9A) corresponds to a period of about 800 pixels. The imaging result for one line by 640 pixels is output in the period for pixels. On the other hand, when outputting the imaging results by CIF and QVGA at the data transfer speed by VGA, it is possible to output the imaging results for two lines in one horizontal scanning period divided by a period of 20 pixels (see FIG. 9 (C) and (D)), the imaging results by QCIF and SQVGA can output the imaging results of 4 lines in one horizontal scanning period (FIGS. 9E and 9D). F)). Assuming that the electronic zoom process is executed by controlling the drive of the image sensor 2 as described above, a zoom magnification of 3.2 times at maximum can be secured with CIF, whereas a zoom magnification of 4 times with QVGA can be secured. In contrast, QCIF and SQVGA can secure zoom magnifications of up to 12.8 times and 16 times, respectively.

  In this embodiment, pixels are thinned out in accordance with the output image data D2, and the imaging signal S1 is output from the image sensor 2, so that the memory circuit 7 outputs 1 when the output image data D2 is output by VGA. Whereas only one line of image data can be output in the horizontal scanning period, when image data D2 is output by CIF and QVGA, respectively, one line of image data output can be repeated twice in one horizontal scanning period. When the image data D2 is output by QCIF or SQVGA, the output of one line of image data can be repeated four times in one horizontal scanning period.

  As a result, as shown in FIG. 10, the memory circuit 7 sequentially and cyclically selects the line memories 25A to 25C for each horizontal scanning period of the horizontal synchronizing signal HD (FIG. 10 (A1)) related to the input image data D1. Then, while recording the input image data D1 in the line memories 25A to 25C (FIG. 10 (B1) to (C1), (B2) to (C2)), the input image data D1 is held in the line memories 25A to 25C that are not used for recording. When outputting the image data to the vertical filter 8 and outputting the image data D2 at a double zoom magnification, the time axis compression is performed and the output of the image data in units of lines is 2 in one horizontal scanning period. Repeatedly (FIG. 10 (B1) to (C1)), the image data obtained by the two repetitions is subjected to line interpolation processing by the vertical filter 8 (FIG. 10 (E1)). . Thus, in this case, two lines of image data can be generated by the vertical filter 8 by repeating the output of the image data twice, thereby ensuring a double zoom magnification.

  On the other hand, when outputting the image data D2 with a zoom magnification of 3 times, the output of the image data in units of lines is repeated three times in one horizontal scanning period by time axis compression (FIG. 10 (B2) to (C2 )), And the image data obtained by the three repetitions are each subjected to line interpolation processing by the vertical filter 8 (FIG. 10 (E2)). Thus, in this case, three lines of image data can be generated by repeating the image data output three times, and a zoom magnification of 3 times can be secured.

  In the electronic zoom processing with a zoom magnification that does not depend on such an integer value, the memory circuit 7 determines the sampling phase of each line of the output image data D2 with respect to the input image data D1, as shown in FIG. The number of repeated outputs differs for each horizontal scanning period. For example, in electronic zoom with a zoom magnification of 1 to 2 times, one line output in such a horizontal scanning period and 2 in one horizontal scanning period. The line output is switched. In FIG. 11, reference numerals (A1) to (D1) show image data input / output processing when the zoom magnification is 1 ×, and reference (A2) is compared with the processing using the zoom magnification of 1 ×. ~ (D2) shows a case with a zoom magnification of about 1.5 times. In this case, a horizontal scanning period in which image data output in line units is repeated twice, and a horizontal scanning period in which image data output in line units is only once. Are repeated according to the zoom magnification and the sampling phase of the line related to the interpolation process.

  FIG. 12 is a schematic diagram showing the processing of the image data in the series of memory circuits 7. In the memory circuit 7, in this case, the image data of one horizontal scanning period output from the camera signal processing circuit 4 is shown. D1 is repeatedly output in units of lines in this one horizontal scanning period (FIGS. 12A to 12C).

  FIG. 13 is a characteristic curve diagram showing the number of output times of image data in units of lines that need to be repeatedly input to the vertical filter 8 according to the zoom magnification in the electronic zoom processing by line interpolation. It shows the case where each is output in the format.

  As a result, when it is attempted to secure a sufficient zoom magnification, it can be seen that image data cannot be output to the vertical filter 8 a necessary number of times only by repeated output by address control in the memory circuit 7 as described above.

  As a result, in this embodiment, when image data cannot be output to the vertical filter 8 as many times as necessary by only repeated output by address control in the memory circuit 7, switching of the frequency dividing ratio in the frequency dividing circuits 5A and 5B The processing speed of the image sensor 2 and the camera signal processing circuit 4 is reduced with respect to the processing speed of the memory circuit 7 and the image data is output to the vertical filter 8 as many times as necessary.

  That is, as shown in FIGS. 14 (A3) to (E3) in comparison with FIGS. 10 (A1) to (E2), in this embodiment, the image controller 2 and the camera are controlled by the control of the clock controller 5C by the system controller 6. The processing speed in the signal processing circuit 4 is reduced, and the length of one horizontal scanning period of the image data D1 input to the memory circuit 7 is set to twice as compared with, for example, a zoom magnification of twice. Thus, in this case, the memory circuit 7 outputs image data by repeating four lines in one horizontal scanning period thus extended, and ensures a zoom magnification of 4 times. As a result, even if the memory circuit 7 cannot repeatedly output image data during one horizontal scanning period, as shown in FIGS. 14 (A4) to (E4), the memory circuit 7 outputs 2 lines repeatedly. This can be executed, and thereby, a zoom magnification of 2 times can be secured.

  FIG. 15 is a schematic diagram showing the processing of the image data in the memory circuit 7 at the time of the rate conversion. In the memory circuit 7, in this case, one extended horizontal signal output from the camera signal processing circuit 4 is shown. The image data D1 relating to the scanning period is repeatedly output line by line in this extended one horizontal scanning period (FIGS. 15A to 15C).

  In the memory circuit 7, the operations of the line memories 25 </ b> A to 25 </ b> C are controlled by the memory controller 28 so as to correspond to the series of processes and to correspond to the processes in the horizontal filter 9 subsequent to the vertical filter 8.

  That is, the memory controller 28 selectively inputs only the effective display area used for the line interpolation process in the vertical filter 8 to the line memories 25A to 25C in the vertical direction according to the zoom magnification instructed by the host controller. Thus, processing related to a useless line is prevented. As for the horizontal direction, as shown in FIG. 16, all the input image data D1 for one line is stored in the line memories 25A to 25C, and the effective display area used for the interpolation process in the horizontal direction from the stored image data. Only selectively output from the line memories 25A to 25C, and repeatedly output in line units, thereby preventing unnecessary processing in this case (FIGS. 16A to 16D).

  Further, as shown in FIG. 17, the read address control of the line memories 25A to 25C according to the zoom magnification, the enable control of the flip-flop circuit 12 provided at the output stage of the vertical filter 8, and the delay circuit of the horizontal filter 9 are configured. By the enable control of the flip-flop circuit 16, the image data relating to the same pixel is supplied to the horizontal filter 9 for a plurality of clock cycles corresponding to the zoom magnification, and the interpolation calculation process is repeated. That is, for example, when the image data D2 is output from the line memories 25B and 25C (FIG. 17A), when the electronic zoom process is executed in the horizontal direction with the zoom magnification of 2 times, the line memories 25B and 25C are used. The stepping speed of the address counter related to the generation of the read address is reduced to ½, thereby reducing the image data output speed from the line memories 25B and 25C in accordance with the zoom magnification (FIG. 17B and ( C)). Thereby, in this case, the image data D2 relating to the same pixel is repeatedly input to the vertical filter 8 in two consecutive clock cycles, and the interpolation process is repeated in each clock cycle (FIG. 17D). In addition, by enabling control of the flip-flop circuit 12 and the flip-flop circuit 16, among the image data related to the repetition by the vertical filter 8, image data related to continuous pixels is simultaneously sent in parallel to the multiplier circuits 14 A and 14 B of the horizontal filter 9. And during the clock period corresponding to the zoom magnification, the interpolation processing is executed here (FIGS. 17E and 17F). In FIG. 17, the output data of the vertical filter 8 and the horizontal filter 9 are indicated by the display Y4 / Y5, Y5 / 6,... Of combinations of the output data Y4, Y5, Y6,. The correspondence relationship with the output data is shown. As a result, in this embodiment, image data relating to a plurality of sampling points corresponding to the zoom magnification can be generated between sampling points that are continuous in the horizontal direction of the image data D2 output from the camera signal processing circuit 4. ing.

  On the other hand, FIG. 18 is a time chart showing the write control of the line memories 25A to 25C when the data transfer speed in the image sensor 2 and the camera signal processing circuit 4 is reduced by comparison with FIG. In this case, the memory controller 28 decreases the stepping speed of the address counter related to the generation of the write address to the line memory in conjunction with the setting switching of the frequency dividing circuits 5A and 5B in the clock generation circuit 5 (FIG. 18A ) To (D) and (F)). In conjunction with this, the write enable signal is output at a predetermined cycle (FIG. 18E), and the data transfer speed is reduced in accordance with the zoom magnification by operating at the processing speed of the output image data D2. The input image data D1 is sequentially recorded in the line memory (FIGS. 18F and 18G). The image data recorded in this way is output in the same manner as described above with reference to FIG.

  Accordingly, in the image data obtained as a result of the electronic zoom processing output from the horizontal filter 9 in these manners, a plurality of lines are output during one horizontal scanning period according to the zoom magnification, and in the image sensor 2 and the camera signal processing circuit 4. It is output at a frame rate that changes according to the processing speed. The recording / monitoring system 30 acquires image data by the electronic zoom process output from the horizontal filter 9 and displays it on the monitor device. The acquired image data is data-compressed and recorded on a predetermined recording medium under the control of the system controller 6.

  The system controller 6 is a control unit that controls the overall operation of the image pickup apparatus 1 in response to an operation by a user. The system controller 6 calculates a zoom magnification in response to an operation of the zoom operator 31 and uses the calculated zoom magnification. The zoom magnification is instructed to the memory controller 28 and the clock controller 5C is instructed to control the frequency dividing circuits 5A and 5B so as to execute the electronic zoom process.

(2) Operation of Embodiment In the above configuration, in the imaging apparatus 1 (FIG. 1), after the imaging result by the image sensor 2 is converted into image data and processed by the camera signal processing circuit 4, the memory circuit 7, The vertical filter 8 and the horizontal filter 9 are sequentially processed and output to the recording system / monitor system 30 so that the imaging result can be monitored, and can be recorded and stored in a recording medium. Has been made.

  In this series of processing, the image data D1 output from the camera signal processing circuit 4 is the number of lines of image data D2 related to output to the recording system / monitor system 30 by line thinning and pixel thinning by driving the image sensor 2. Are input to the memory circuit 7 in accordance with the horizontal resolution. Further, the image data D1 input in this way is recorded in a line unit in a cyclic manner in a plurality of line memories 25A to 25C provided in the memory circuit 7, and the remaining image data D1 not used for recording the image data D1. Image data is read simultaneously and in parallel from the line memory and input to the vertical filter 8, where electronic zoom processing is executed in the vertical direction by line interpolation processing by the vertical filter 8. Further, the electronic zoom processing is executed in the horizontal direction by the interpolation processing in the subsequent horizontal filter 9.

  In this electronic zoom processing, when image data is output at a zoom magnification of 1, that is, when an image is displayed on the monitor without being enlarged by any electronic zoom, the vertical filter 8 is input simultaneously and in parallel. The interpolation coefficient is set so that one of a plurality of lines is selectively output, and the line interpolation calculation process is performed. Similarly, in the horizontal filter 9, the interpolation coefficient is selected so as to selectively output one sampled value. The image data D2 is output from the horizontal filter 9 as a result of the electronic zoom processing by one time.

  On the other hand, when the zoom magnification is 1 or more, the image data D1 is set with interpolation coefficients in the vertical filter 8 and the horizontal filter 9 in accordance with the sampling phase related to each interpolation process according to the zoom magnification. The vertical filter 8 and the horizontal filter 9 respectively perform interpolation calculation processing. In this process, for example, when the zoom magnification is less than two times, interpolation processing for two lines is performed on a specific line of the image data D2 output from the horizontal filter 9 by two consecutive lines of the image data D1. It becomes necessary to execute. When the zoom magnification is 2 times, it is necessary to execute the interpolation calculation process for two lines from the two continuous lines of the image data D1 for all the lines of the image data D2 output from the horizontal filter 9. become. When the zoom magnification exceeds 2 times and is less than 3 times, it is necessary to execute interpolation processing for two lines or three lines from two consecutive lines of the image data D1.

  In the image data D1, output to the vertical filter 8 is repeated for each line in one horizontal scanning period of the image data D1 with respect to such line interpolation processing that changes in accordance with the zoom magnification. Necessary line interpolation processing is repeated by the vertical filter 8 in accordance with the zoom magnification.

  Similarly, in the horizontal direction, when the zoom magnification is less than two times, the specific pixel of the image data D2 output from the horizontal filter 9 includes two consecutive pixels of the image data D1. It is necessary to execute an insertion calculation process. Further, when the zoom magnification is 2 times, it is necessary to execute the interpolation calculation process of 2 pixels from all the continuous 2 pixels of the image data D1 for all the pixels of the image data D2 output from the horizontal filter 9. Become. When the zoom magnification exceeds 2 times and is less than 3 times, it is necessary to execute an interpolation calculation process of 2 pixels or 3 pixels from two consecutive pixels of the image data D1.

  In the image data D1, the reading speed from the memory circuit 7 is reduced with respect to the horizontal interpolation process that changes according to the zoom magnification, and the image data of one pixel is obtained at a plurality of clock cycles of the image data D1. D1 is output to the vertical filter 8 and the flip-flop circuit in which the interpolation operation processing according to the clock cycle of the image data D1 is provided at the output stage of the vertical filter 8 and the flip-flop circuit constituting the delay circuit of the horizontal filter 9 are enabled The processing is temporarily stopped by the control, and the electronic zoom processing in the horizontal direction is executed by these.

  As a result, the imaging apparatus 1 can execute the electronic zoom process using a memory circuit including a plurality of line memories, and accordingly, the electronic zoom process can be executed with a simple configuration. Even when the magnification of the electronic zoom is set, the number of lines and the number of pixels of the image sensor 2 can be set without any limitation, so that the zoom magnification can be freely set.

  When image data output in units of lines in one horizontal scanning period is repeated in this way and there is no time allowance for repeated output in one horizontal scanning period, in this imaging apparatus 1, an image sensor 2 that is an imaging system is used. The frequency of the pixel clock PCK which is the operation reference of the camera signal processing circuit 4 is reduced, and one horizontal scanning period of the input image data D1 is expanded, thereby securing a time margin for one horizontal scanning period which is insufficient. The In this case, the image data is repeatedly output line by line from the memory circuit in this expanded one horizontal scanning period.

  As a result, the imaging apparatus 1 can execute the electronic zoom process even with a large zoom magnification, and the zoom magnification can be set more freely.

(3) Advantages of the Embodiment According to the above configuration, a plurality of lines of image data are repeatedly output to the vertical filter in units of lines in one horizontal scanning period of the input image data, and an interpolation calculation process is performed. Depending on the configuration, the zoom magnification can be freely set.

  At this time, by reducing the frequency of the pixel clock PCK, which is the operation reference of the image sensor 2 and the camera signal processing circuit 4 that are imaging systems, and enlarging one horizontal scanning period of the input image data D1, a large zoom magnification can be obtained. In addition, the electronic zoom process can be executed, and the zoom magnification can be set more freely.

  FIG. 19 is a block diagram illustrating an imaging apparatus according to the second embodiment of the present invention in comparison with FIG. In this imaging apparatus 40, a horizontal reduction filter 42 is disposed between the camera signal processing circuit 4 and the memory circuit 7, and sampling in the horizontal direction of image data output from the camera signal processing circuit 4 by the horizontal reduction filter 42 is performed. The number is reduced. Further, the horizontal reduction filter 42 intermittently stops outputting image data for each line, thereby reducing the number of lines of image data output from the camera signal processing circuit 4.

  The imaging apparatus 40 has the same configuration as that of the imaging apparatus 1 according to the first embodiment except that the pixel thinning and line thinning processes in the image sensor 2 are stopped and these processes are executed by the horizontal reduction filter 42. Is done.

  As in this embodiment, even if the processing is performed by reducing the number of lines and the number of pixels of the image data at the input stage of the memory circuit 7, the same effect as in the first embodiment can be obtained.

  FIG. 20 is a block diagram illustrating an imaging apparatus according to the third embodiment of the present invention in comparison with FIG. The imaging device 50 is provided with a FIFO memory circuit 52 at the output stage of the horizontal filter 9, and the memory circuit 52 corrects the timing of image data related to the electronic zoom processing. Specifically, in this embodiment, the memory circuit 52 outputs image data at a constant rate synchronized with the horizontal synchronizing signal and the vertical synchronizing signal.

  If the timing of the image data based on the result of the electronic zoom processing is corrected and output as in this embodiment, each sampling value of the image data can be output continuously at a constant processing speed. Image data can be processed by a general-purpose monitor system or recording system.

  In the above-described embodiment, the case where all sampling values are recorded in the line memory and processed in the horizontal direction has been described. However, the present invention is not limited to this, and only the image data in the horizontal enlargement area is selectively displayed. It may be recorded in a memory and processed.

  In the above-described embodiment, the case has been described in which when the clock frequency of the input image data D1 is reduced, the line memory is intermittently recorded by the enable control of the line memory. However, the present invention is not limited to this. The same sampling value may be repeatedly recorded in the same area.

  In the above-described embodiments, the case where the electronic zoom processing is executed by the processing by the memory circuit, the vertical filter, and the horizontal filter has been described. However, the present invention is not limited to this, and the electronic zoom method by the drive control of the image sensor is described. May be combined.

  In the above-described embodiments, the case where the imaging result is monitored and recorded on the recording medium has been described. However, the present invention is not limited to this, and can be widely applied to various video devices such as a video camera.

  The present invention can be applied to an imaging apparatus and various video devices.

It is a block diagram which shows the imaging device which concerns on the Example of this invention. It is a block diagram which shows the vertical filter of the imaging device of FIG. It is a block diagram which shows the other example of the vertical filter of the imaging device of FIG. It is a block diagram which shows the example of 8 taps of the vertical filter of the imaging device of FIG. It is a block diagram which shows the horizontal filter of the imaging device of FIG. It is a block diagram which shows the other example of the horizontal filter of the imaging device of FIG. It is a block diagram which shows the example of 8 taps of the horizontal filter of the imaging device of FIG. It is a graph which shows the relationship between the number of lines in each format, and the number of pixels. It is a time chart which shows the relationship of the pixel count concerning 1 horizontal scanning period in each format. It is a time chart with which it uses for description of the input / output of the memory circuit which concerns on the process of electronic zoom. It is a time chart used for description of processing of electronic zoom. It is a time chart with which it uses for the description which concerns on the output per line. It is a characteristic curve figure which shows the repetition frequency of the line unit in each format. 6 is a time chart for explaining input / output of a memory circuit by reducing the clock frequency of input image data. It is a time chart with which it uses for the description which concerns on the output per line when the clock frequency of input image data is reduced. 6 is a time chart for explaining a process of writing image data to a memory circuit. 6 is a time chart for explaining output of image data from a memory circuit. 6 is a time chart for explaining a process of writing image data into a memory circuit when the clock frequency of input image data is reduced. FIG. 6 is a block diagram illustrating an imaging apparatus according to a second embodiment. FIG. 9 is a block diagram illustrating an imaging apparatus according to a third embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 40, 50 ... Imaging device, 2 ... Image sensor, 4 ... Camera signal processing circuit, 5 ... Clock generation circuit, 6 ... System controller, 7 ... Memory circuit, 8 ... Vertical filter, 9 ...... Horizontal filter

Claims (2)

In an electronic zoom device that expands image data at a desired zoom magnification and outputs output image data,
A plurality of line memories having at least three or more, wherein the plurality of line memories are sequentially and cyclically selected to record the sequentially input image data in the line memory; A memory circuit for simultaneously reading out and outputting the image data of a plurality of lines from the remaining line memory; and
A vertical filter for interpolating and outputting the image data of the plurality of lines output from the memory circuit;
A horizontal filter for interpolating the output data of the vertical filter and outputting the output image data expanded in the horizontal direction by the zoom magnification;
The memory circuit includes:
According to the zoom magnification, the image data enlarged in the vertical direction by the zoom magnification is output from the vertical filter by repeatedly outputting the image data of the plurality of lines in units of lines in one horizontal scanning period of the input image data. To be output,
According to the zoom magnification, by outputting one image data at a plurality of clock cycles, image data enlarged in the horizontal direction by the zoom magnification is output from the horizontal filter. Zoom device. Having an imaging means for acquiring the input image data;
In accordance with the zoom magnification, the clock frequency of the imaging means is reduced to enlarge one horizontal scanning period of the input image data, and in one horizontal scanning period of the input image data, the line unit from the memory circuit The electronic zoom device according to claim 1, wherein the number of times image data is output is increased.

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