JP2006303693A - Electronic camera provided with function of generating reduced picture - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology of implementing resolution conversion at a high speed. <P>SOLUTION: An electronic camera includes an imaging section, a block average processing section, and a resolution conversion section. The imaging section images an object to output image data. The block average processing section captures the image data and averages the image data by each predetermined pixel block to output an average by each block. The resolution conversion section applies resolution conversion to the averages while sequentially capturing the averages outputted from the block average processing section. Particularly, the electronic camera produces a reduced picture by using a "reduction of number of pixels in the first stage" by the block average processing section and a "reduction of number of pixels in the second stage" by the resolution conversion section. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic camera having a reduced image generation function.

  In signal processing in an electronic camera, processing for reducing the number of vertical and horizontal pixels of an image is frequently performed. For example, in an electronic camera at the time of still shooting, a captured image is reduced and converted to a desired recording resolution, or a quick view image or a thumbnail image is generated. Further, in the electronic camera at the time of reproduction, processing for converting the image read from the recording medium into the monitor display resolution or the arbitrary resolution for enlarged display is performed. Further, in the electronic camera when displaying a through image, a process of converting a moving image (draft image) read out from the image sensor by line thinning into a monitor display resolution is performed.

Patent Document 1 discloses a technique for performing resolution conversion in the following two stages as such a resolution conversion technique.
[First Stage] First, the horizontal band of the input image is limited (horizontal low-pass processing). A thumbnail preparation image is generated by thinning out horizontal pixels from the processed image.
[Second Stage] Next, the vertical band of this thumbnail preparation image is limited (vertical low-pass processing). A thumbnail image is obtained by thinning out vertical pixels from the processed image.
In the above processing, horizontal and vertical low-pass processing is processing necessary to prevent moire and generate a high-quality reduced image.
JP 2003-199016 A (FIG. 2 etc.)

By the way, in the resolution conversion technique of Patent Document 1, resolution conversion is performed in two stages, horizontal and vertical.
In this case, since the horizontal low-pass process and the vertical low-pass process are performed independently, it is necessary to provide a sufficient line buffer for each low-pass process, and the circuit scale tends to increase.
In addition, since the resolution conversion is performed independently in the horizontal direction and the vertical direction, the flow of processing data tends to be complicated. For this reason, it is very difficult to perform high-speed parallel processing of these two stages in a pipeline manner.
Accordingly, an object of the present invention is to provide a technique for performing resolution conversion at high speed with a simple flow.

<< 1 >> The electronic camera of the present invention includes an imaging unit, a block average processing unit, and a resolution conversion unit.
The imaging unit images a subject and outputs image data.
The block average processing unit takes in the image data, averages it for each predetermined pixel block, and outputs an average value for each block.
The resolution conversion unit performs resolution conversion on the average value while sequentially taking in the average value output from the block average processing unit.
In particular, the electronic camera of the present invention generates a reduced image step by step by the “first stage pixel number reduction” by the block average processing unit and the “second stage pixel number reduction” by the resolution conversion unit. It is characterized by.

<< 2 >> Preferably, the block average processing unit includes a section addition unit and an average unit.
The division addition unit divides and adds the image data for each block to obtain an addition value for each block.
The averaging unit calculates the average value by averaging the addition values for each block.

<< 3 >> Preferably, the section addition unit includes a plurality of data areas in which data is added for each block. The division adding unit adds the fractional block generated by dividing the scan input of the image data into blocks and leaves it as a provisional value. Then, the division adding unit adds the remaining data of the fractional block to the provisional value of the data area at the time of subsequent scanning input.

<< 4 >> Preferably, the electronic camera includes a memory for storing image data, and a transfer unit that DMA-transfers image data from the memory for each predetermined transfer unit and supplies the data to the block average processing unit. << 5 >> Preferably, the electronic camera includes a line reduction unit that generates image data obtained by reducing the number of lines. The block average processing unit classifies the image data obtained by reducing the number of lines into pixel blocks and averages them.

<6> Preferably, the block average processing unit sets the coefficient sum of addition for each block to a power of 2, and performs a process of dividing the addition value for each block by the coefficient sum by a bit shift process.

<< 7 >> Also preferably, the block average processing unit adds an adder for each block, and a fixed-point multiplication for multiplying the addition value output from the adder by the reciprocal of the coefficient sum of the adder With a vessel.

<< 8 >> Preferably, the electronic camera includes a setting unit that obtains a coefficient sum of the adder, calculates an inverse number of the coefficient sum, and sets the multiplier in the multiplier.

<< 9 >> Also preferably, the block average processing unit captures RAW data in which a plurality of types of color components are mixedly arranged. The block average processing unit averages the same color components in the pixel block and arranges a plurality of types of color components for each block.

In the present invention, a reduced image is generated in the following two stages.
(First stage) Image data is divided into pixel blocks, and an average value is obtained for each block.
(Second stage) Resolution conversion is performed on the average value for each block, and a reduced image having a desired number of vertical and horizontal pixels is generated.

  In the first stage, the number of pixels of the image data can be reduced to the number of pixel blocks. Further, in the first stage, two-dimensional low-pass processing is also performed simultaneously by block averaging. Therefore, it is possible to omit or reduce the low-pass processing for preventing moiré, and to reduce the processing load for preventing moiré.

  Due to such advantages, in the step processing of the present invention, the flow of data is simplified, and resolution conversion can be performed at high speed.

[Description of electronic camera configuration]
FIG. 1 is a system block diagram of an electronic camera 11 in the present embodiment.
FIG. 2 is an internal block diagram of the image processing circuit 16 shown in FIG.
Hereinafter, the configuration of the electronic camera 11 will be described with reference to FIGS. 1 and 2.
A photographing lens 12 is attached to the electronic camera 11. An image sensor 13 is disposed in the image space of the photographing lens 12. The image sensor 13 can select a mode for obtaining a recorded image by reading all pixels and a draft mode for reading a draft image while thinning lines by switching the readout sequence.
The output of the image sensor 13 is input to the image processing circuit 16 via the A / D converter 14 and the interface circuit (not shown) of the image sensor 13.

The image processing circuit 16 has the following configuration.
(1) Signal processing unit 43... Performs defective pixel correction, black level clamp (OB clamp), gain adjustment, white balance adjustment, gradation conversion (gamma correction, etc.), color interpolation, color conversion or color processing. The signal processing unit 43 includes an input buffer 45 and an output buffer 46, and exchanges image data with an SDRAM (Synchronous DRAM) 35 via the picture bus 21 for high-speed transfer of image data. In the case of image data for recording by reading all pixels (still image shooting), generally processing up to white balance adjustment, that is, defective pixel correction, black level clamp (OB clamp), and gain adjustment have been processed. Are temporarily stored in the SDRAM 35 via the output buffer 46. Further, the signal processing unit 43 outputs the detection result for exposure / focus / white balance and stores it in the register 44. An MPU (Micro Processor Unit) 24 can read these detection results from the register 44 via the system bus 23 and control exposure / focus / white balance.
(2) The block average processing unit 71... Is configured to include a section addition unit 74 (including an adder) and an average unit 75.
The average unit 75 is preferably realized by a bit shifter from the viewpoint of high-speed processing described later.
Next, a fixed point multiplier is preferable as the averaging unit 75. The MPU 24 calculates the reciprocal of the coefficient sum of the pixel block and sets it in this multiplier. The multiplier obtains an average value for each block by multiplying the addition value output from the section addition unit 74 by this reciprocal by a fixed point.
A divider may be used as the averaging unit 75. The MPU 24 calculates the coefficient sum of the pixel block and sets it in this divider. The divider obtains an average value for each block by dividing the addition value output from the section addition unit 74 by this coefficient sum.
(3) Resolution converter 72... The average value for each block is sequentially fetched. The reduced image is generated by converting the resolution of the averaged image composed of the average value for each block into a predetermined number of vertical and horizontal pixels.
(4) Spatial filter 51... Performs spatial filter processing such as edge enhancement and noise removal.
(5) The color difference thinning unit 52... 4: 2: 2 is thinned out. The image data which is connected to the picture bus 21 via the output buffer 53 and whose color is thinned out is stored in the SDRAM 35.
(6) Transfer unit 73... DMA transfer of the SDRAM 35 via the picture bus 21 and the bus interface 22.

  The recording image output from the image sensor 13 is processed by the image processing circuit 16 and then input to the image compression unit 17 via the dedicated bus, or once stored in the SDRAM 35 and then the picture bus 21. To the image compression unit 17. The compressed image file generated by the image compression unit 17 is temporarily stored in the SDRAM 35 via the picture bus 21, read out via the system bus 23, and then recorded and stored in the memory card 30 via the card IF 29. Is done.

On the other hand, the draft image output from the image sensor 13 is processed by the image processing circuit 16, and then temporarily stored in the SDRAM 35 via the picture bus 21, and then read from the SDRAM 35 and input to the display unit 19. . The display unit 19 displays a moving image generated from the draft image on the liquid crystal panel 20.
Further, the picture bus 21 and the system bus 23 are connected to the SDRAM 35 and the like via the bus interface 22, and data is stored in the SDRAM 35 and data is read from the SDRAM 35 via these buses. Further, the MPU 24 and the like are connected to the system bus 23.

[Pixel block settings]
FIG. 3 is a diagram for explaining the block averaging process.
The division adding unit 74 divides the input image captured from the set image input source into pixel blocks of horizontal N pixels × vertical M pixels. In this case, by setting N ≠ M, the image aspect ratio after the block averaging process can be changed. In order to maintain the aspect ratio after block averaging, N = M may be set.

Furthermore, it is preferable that the size setting (N, M) of the pixel block is increased to a reference range size that does not cause moire in the resolution conversion unit 72 in the subsequent stage.
Further, it is preferable to select N and M of the pixel block to be a power of 2. For example, 2 × 2, 4 × 2, 4 × 4, 8 × 4, 8 × 8, etc. In these pixel blocks, the number of internal pixels NM is always a power of two. Therefore, the block average processing unit 71 can calculate the average value at high speed by simply accumulating the data in the pixel block and bit-shifting down the accumulated addition value.

  If at least one of N and M is not a power of 2, a weighting coefficient may be added to the pixel (group) in the center of the pixel block to adjust the overall coefficient sum to a power of 2. Furthermore, by setting the individual weighting coefficients of the central pixel (group) to powers of 2, respectively, it becomes possible to perform the weighting of the central pixel (group) at a high speed by bit-shifting up.

  4A to 4D are diagrams showing the weighting ratios of the pixel blocks set in this way. For example, in FIG. 4A, the value obtained by shifting up the data of the center pixel by 3 bits (8 times) and the data of surrounding 8 pixels are cumulatively added, and the cumulative added value is shifted down by 4 bits (1/16 times). )do it.

[About variable size of reduced image]
By the way, since the electronic camera 11 performs image reduction in various aspects, it is necessary to flexibly change the image reduction rate. Such a change in the reduction ratio is made possible by the MPU 24 setting the pixel block size and weighting factor in the block average processing unit 71 and finely adjusting the resolution conversion for the resolution conversion unit 72.

In this case, the block average processing unit 71 needs to design the bit width of the internal data area so that it can cope with the largest pixel block. This design will be described with a specific example.
First, the maximum imaging resolution of the electronic camera 11 is determined by design specifications. Here, it is assumed that the image is 5M pixels (2592 pixels × 1944 pixels). When this image is reduced to a quick view image (here, 640 pixels × 480 pixels), it is only necessary to reduce the image by about 1/4 in the vertical and horizontal directions. If this vertical and horizontal 1/4 times is the maximum reduction ratio per time, the maximum size of the pixel block is set to N = M = 4. When the averaging process is performed in units of 4 × 4 pixel blocks, the actual size of the image changes from “(2592 × 1944) → (648 × 486)”. The averaged image may be further reduced by the resolution conversion unit 72 in the subsequent stage to obtain a display image (640 × 480).

In this case, the reduction rate of the resolution conversion unit 72 is as follows.
640 ÷ 648 = 480 ÷ 486 = 1 / 1.0125 = 0.9876 ...
If the scaling factor of the resolution converter 72 is variable in 1% steps, “0.98” or “0.99” may be selected as the scaling factor. When the scaling factor is “0.98”, the image size is (635 × 476), and when the scaling factor is “0.99”, the image size is (641 × 481). At this time, the missing pixels may be compensated with a black level or the like. Further, it is only necessary to cut off the peripheral portion of the extra pixels.

  As is clear from this explanation, a block average of “N = M = 4” is sufficient even for an image as large as 5M pixels (2592 pixels × 1944 pixels). Even for an image as large as 15 M pixels (4760 pixels × 3360 pixels), a block average of “N = M = 7” is sufficient. Therefore, if the block average processing unit 71 corresponds to the maximum pixel block of N = 4 to 7, most of the electronic camera specifications can be satisfied.

[About the case of further reducing the image]
In the above description, it is assumed that a quick view image (640 pixels × 480 pixels) for display is created from a full resolution image. However, the electronic camera 11 must also create a smaller thumbnail image (160 pixels × 120 pixels). In order to cope with this thumbnail image, the maximum pixel block of the block average processing unit 71 must be further increased, and there is a concern that the circuit scale of the block average processing unit 71 becomes large.

In the present embodiment, this problem is solved by multistage processing of the block average processing unit 71. In general, the quick view image is displayed immediately after the still photography of the electronic camera 11, and thus is generated before the thumbnail image. Therefore, a thumbnail image is generated stepwise by performing block averaging of the quick view image generated earlier (or the averaged image before fine adjustment of the resolution) again with N = M = 4 pixel blocks. Is possible.
By such multi-stage processing of image reduction, it is possible to reduce the circuit scale while suppressing the size of the maximum pixel block of the block average processing unit 71.

[About the case where a remainder block occurs]
Next, the case where the block average processing unit 71 cannot completely divide the image data into pixel blocks and a remainder block occurs will be described. For example, when a 4M pixel image (2288 pixels × 1716 pixels) is reduced to a quick view image (640 pixels × 480 pixels), a pixel block of 3 pixels × 3 pixels is used. However, since the number of horizontal pixels is not divisible by 3, a surplus block that does not have one horizontal pixel is generated.

With respect to such a surplus block, the surplus horizontal two pixels are discarded, or one pixel is added back to complete the pixel block. In the case of discarding the remaining two pixels, it is preferable to discard one pixel at both the left and right ends from the viewpoint of maintaining the symmetry of the image.
However, it is not easy to read block data starting from the second pixel of each line from the SDRAM 35 or the like (due to address restrictions in bursty reading). For this reason, it is simpler to read from the first pixel of each line and input to the block average processing unit 71 and discard the first pixel in the line within the block average processing unit 71. The same applies when the last pixel of each line is discarded. However, for this operation, it is necessary to shift the timing of moving to the next line by one pixel when reading out pixels in the same block.

On the other hand, when the block is divided by adding one pixel, it is easier to add it to the right end. Preparing one pixel on the SDRAM 35 is a software process of the MPU 24 and is not preferable from the viewpoint of operation speed.
Therefore, in the process of inputting pixel block data, the block average processing unit 71 detects the rightmost block, and when the rightmost block is detected, the block average processing unit 71 performs folding for one pixel at the right end of each line. Preferably it is done. By such an operation, processing of the remainder block is achieved without requiring extra overhead time. Compared to the method of discarding the remainder block, this method is preferable in that the field of view is not narrowed.

  By the way, when similar residual blocks occur vertically and horizontally, the aspect ratio of the image is hardly changed by the processing of the residual blocks. However, in the above example, since the residual block does not occur in the vertical direction, the aspect ratio changes by one or two pixels. In this case, the resolution conversion unit 72 in the subsequent stage determines the vertical reduction ratio, and the horizontal reduction ratio is set to the same value as the vertical reduction ratio. Then, after the image is reduced by the resolution converter 72, the right end pixel of each line is cut off according to the number of pixels in the vertical direction, and the aspect ratio is finally adjusted. This is because the sum of the reduction ratios of the block average processing unit 71 and the resolution conversion unit 72 is exactly the same in the vertical direction and the horizontal direction, and no distortion occurs.

[About block classification of scan input]
The input image shown in FIG. 3 is a scan input divided into pixel blocks. Such scanning input repeats segment scanning in units of pixel blocks for each pixel block.
In order to block-divide a normal image scan input in this way, for example, it is possible to use a pixel extraction circuit described in Japanese Patent Application Laid-Open No. 2004-260265 by the present inventor. This pixel extraction circuit has a function of extracting a pixel block for each minimum pixel interval. However, this function is not necessary so far in the segmentation operation of the present embodiment, and this function may be omitted. In addition, the pixel extraction circuit of the above publication can also make up for the remainder block by folding pixels around the screen.
Note that the segment addition unit 74 can convert the scan data of a general image into the segment scan described above by changing the memory address order when the image data is read from the SDRAM 35.

[Support for high-speed transfer using the transfer unit 73]
By the way, when the block average processing unit 71 performs the block average processing, if the image data is input pixel by pixel, the processing becomes slow. Therefore, it is preferable that the image data of the SDRAM 35 is given to the block average processing unit 71 by bursty DMA transfer.

  In such burst transfer, the higher the number of transfer data per transfer, the faster data transfer can be realized by eliminating extra clock cycles. However, as described above, the size of the pixel block is as small as N = 5. Therefore, DMA transfer in units of the number of horizontal pixels in the pixel block is inefficient and high-speed data transfer cannot be realized.

  In order to match the DMA transfer and the pixel block, it is necessary to perform DMA transfer at a time up to the number of well-delimited data (number of words). In other words, since it is 4 bytes / word in the case of a 32-bit data bus, the number of data per burst DMA transfer is obtained by multiplying the 4 bytes and the common multiple of the number of bytes of one side (the number of horizontal pixels) listed above. It is. In this way, one unit of DMA transfer can always be terminated at a block boundary, and the number of data in one bursty DMA transfer can be increased. Therefore, high-speed data transfer is also performed in this block averaging process. Based on these conclusions, the number of data in one unit of DMA transfer is obtained for each block size (the data bus is 32 bits).

・ (2 × 2) pixel block
RGB4: 4: 4 / YCbCr4: 4: 4 image data (24 bits / pixel): 4 x 6 = 24 bytes
YCbCr4: 2: 2 image data (16 bits / pixel): 4 × 4 = 16 bytes • (3 × 3) pixel block
RGB4: 4: 4 / YCbCr4: 4: 4 image data (24 bits / pixel): 4 x 9 = 36 bytes
YCbCr4: 2: 2 image data (16 bits / pixel): 4 × 6 = 24 bytes • (4 × 4) pixel block
RGB4: 4: 4 / YCbCr4: 4: 4 image data (24 bits / pixel): 4 x 12 = 48 bytes
YCbCr4: 2: 2 image data (16 bits / pixel): 4 × 8 = 32 bytes • (5 × 5) pixel block
RGB4: 4: 4 / YCbCr4: 4: 4 image data (24 bits / pixel): 4 x 15 = 60 bytes
YCbCr4: 2: 2 image data (16 bits / pixel): 4 × 10 = 40 bytes

  Considering the characteristics of the SDRAM 35, burst transfer of about 16 words (4 × 16 = 64 bytes) is efficient. Since the numerical values listed above are all lower than this value, they may be appropriately multiplied by an integer to approach 16 words (64 bytes). In particular, when the block size is small, it is better to increase the number of transfer data in this way. By the way, when the number of data of one DMA transfer is increased in this way, the image data of a plurality of blocks are input to the block average processing unit 71 at once. Accordingly, in one DMA transfer, pixel blocks are not completely aligned, and fractional blocks are generated.

[About fractional block processing]
Here, processing of the fractional block generated by the DMA transfer of the transfer unit 73 will be described with reference to FIG. First, the division adding unit 74 secures data areas by the number of fractional blocks included in one transfer. These data areas are initialized prior to the addition operation.
The division adding unit 74 takes in data for one transfer and divides it into fractional blocks. In the example shown in FIG. 5, four fractional blocks are included per transfer, and therefore, the data is divided into four fractional blocks. The division adding unit 74 adds (weights) the data to the data area for each of these fractional blocks to obtain a provisional value. By repeating this operation up to the number of transfers in which the pixel blocks are completely aligned, the addition value for each block can be obtained.

  Note that the order of completing the addition value for each block is the order from the left pixel block in FIG. There is a time lag for the transfer cycle of one side of the block from when the added value of the previous block is output until the added value of the next block is output. Therefore, if the averaging unit 75 (bit shifter, divider, fixed point multiplier) can complete the average value calculation during this transfer cycle, the pipeline processing by the division adder 74 and the averaging unit 75 is delayed. It becomes possible to implement without.

[Utilization of input buffer 45 of signal processing unit 43]
The signal processing unit 43, which is the previous stage of the block average processing unit 71, includes an input buffer 45. By providing an image to be reduced via the input buffer 45, any one of the signal processing of the signal processing unit 43 and the block average processing unit 71 can be processed in parallel in a pipeline manner. For example, color conversion such as “RGB → YCbCr” or “YCbCr → RGB” and block averaging (LPF processing and thinning) by the block average processing unit 71 can be performed in parallel.

  If the image to be reduced is “YCbCr4: 2: 2”, such as a decompressed image of JPEG data, color conversion cannot be performed unless the color difference signals (Cb and Cr) are first interpolated. In such a case, a color difference interpolation process such as “YCbCr4: 2: 2 → YCbCr4: 4: 4” is required before the color conversion process. Since this color difference interpolation circuit may be a simple two-pixel average (returning is necessary at the right end of the image), the circuit scale does not increase so much. By performing such simple color difference interpolation first, it becomes possible to process three signal components as a set in the subsequent block averaging and resolution conversion.

[When the number of lines is reduced before block averaging]
When creating display image data (640 × 480) from full-resolution image data, it has been assumed that all image data is input to the block average processing unit 71 so far. In order not to deteriorate the image quality, full resolution input is preferable. However, when a small image such as a display image (640 × 480) is created, the full resolution input may be over-spec. Therefore, when the image quality may be somewhat sacrificed, it is preferable to reduce the processing load of the block average processing unit 71 by appropriately thinning out the lines. For example, when the block average of (5 × 5) pixels is performed, the block average of (5 × 3) pixels may be obtained by thinning out two lines. By such processing, the processing speed of the block average processing unit 71 can be increased. Since the lines in one block are thinned out, it is preferable to change the filter coefficient for the block averaging process.

[Further quick generation of quick view images]
In the above description, the case of generating full-resolution YCbCr image data prior to block averaging has been described. However, in this order, the generation of the quick view image (640 × 480) is postponed, and the quick view display is delayed accordingly.
In order to speed up the quick view display, it is preferable to generate a quick view image directly from RAW data (RGB primary color Bayer array data or the like) without waiting for generation of full resolution YCbCr image data.

FIG. 6 is a diagram for explaining the block averaging processing of the RAW data.
First, the block average processing unit 71 takes in RAW data before color interpolation processing, and performs block average processing for each color component in the pixel block. By such processing, the color interpolation processing of the high resolution image can be omitted, and an averaged image in which the RGB components are aligned for each pixel block can be directly generated (see FIG. 6 [A]). The resolution conversion unit 72 performs resolution conversion on the averaged image, so that a quick view image can be generated at high speed.

  In addition, as shown in FIG. 6B, Bayer array data can be generated once by block averaging processing for each color component. In this case, data output from the block average processing unit 71 is low-resolution RAW data. The resolution conversion unit 72 performs a simple color interpolation process and resolution conversion process on the low-resolution RAW data, so that a quick view image can be generated at high speed.

  In this case, it is preferable to arrange a block average processing unit before the color interpolation processing. This is a configuration different from the block average processing unit shown in FIG. 2, and is preferably included in the internal configuration of the signal processing unit 43.

[Supplementary items of the embodiment]
In the present embodiment, pixel blocks are set by dividing image data into rectangles and squares. However, the present invention is not limited to the shape of the pixel block. You may comprise a pixel block from the pixel group located inside circular or an ellipse. Further, in order to enhance the moire removal effect, a slight overlap area may be provided between adjacent blocks by making the pixel block size larger than the block interval. Conversely, in order to increase the definition of the image, a small gap may be provided between adjacent blocks by reducing the size of the pixel block.

  As described above, the present invention is a technique that can be used for image processing of an electronic camera.

It is a system block diagram of the electronic camera 11 in this embodiment. 2 is an internal block diagram of an image processing circuit 16. FIG. It is a figure explaining an example of a block averaging process. It is a figure which shows the weighting coefficient of a weighted average. It is a figure explaining the process of a fraction block. It is a figure explaining the block averaging process of this RAW data.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Electronic camera, 12 ... Shooting lens, 13 ... Image sensor, 16 ... Image processing circuit, 21 ... Picture bus, 22 ... Bus interface, 23 ... System bus, 24 ... MPU, 30 ... Memory card, 35 ... SDRAM, 43 ... Signal processing unit, 45 ... Input buffer, 71 ... Block average processing unit, 72 ... Resolution conversion unit, 73 ... Transfer unit, 74 ... Section addition unit, 75 ... Average unit

Claims (9)

An imaging unit for imaging a subject and outputting image data;
A block average processing unit that captures the image data, averages it for each predetermined pixel block, and outputs an average value for each block;
A resolution conversion unit that performs resolution conversion on the average value while sequentially capturing the average value output from the block average processing unit;
An electronic camera, wherein reduced images are generated step by step by “first stage pixel number reduction” by the block average processing unit and “second stage pixel number reduction” by the resolution conversion unit. The electronic camera according to claim 1,
The block average processing unit
A division addition unit that divides and adds the image data for each block, and obtains an addition value for each block;
An electronic camera comprising: an averaging unit that averages the addition values for each block to calculate the average value. The electronic camera according to claim 2,
The division adding unit includes a plurality of data areas for adding data for each block, adding a fractional block generated by dividing the scan input of the image data for each block to the data area and leaving it as a provisional value. An electronic camera, wherein the remaining data of the fractional block is added to the provisional value in the data area at the time of scanning input. The electronic camera according to any one of claims 1 to 3,
A memory for storing the image data;
An electronic camera comprising: a transfer unit that DMA-transfers the image data from the memory for each predetermined transfer unit and supplies the DMA data to the block average processing unit. The electronic camera according to any one of claims 1 to 4,
A line reduction unit that generates image data with the number of lines reduced,
The block average processing unit
An electronic camera characterized by averaging image data with the number of lines reduced into pixel blocks. The electronic camera according to any one of claims 1 to 5,
The block average processing unit sets the coefficient sum of addition for each block to a power of 2, and performs a process of dividing the addition value for each block by the coefficient sum by a bit shift process. camera. The electronic camera according to any one of claims 1 to 5,
The block average processing unit
An adder for adding the data for each block;
An electronic camera comprising: a fixed-point multiplier that multiplies an addition value output from the adder by an inverse of a coefficient sum of the adder. The electronic camera according to claim 7,
An electronic camera comprising: a setting unit that obtains a coefficient sum of the adder, calculates an inverse of the coefficient sum, and sets the coefficient sum in the multiplier. The electronic camera according to any one of claims 1 to 8,
The block average processing unit
An electronic camera characterized in that a plurality of types of color components are arranged in units of blocks by taking in RAW data including a mixture of a plurality of types of color components and averaging the data for each color component of the same type in the pixel block.

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