JP2006019459A - Epitaxial wafer for light-emitting diode - Google Patents

Epitaxial wafer for light-emitting diode Download PDF

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JP2006019459A
JP2006019459A JP2004195115A JP2004195115A JP2006019459A JP 2006019459 A JP2006019459 A JP 2006019459A JP 2004195115 A JP2004195115 A JP 2004195115A JP 2004195115 A JP2004195115 A JP 2004195115A JP 2006019459 A JP2006019459 A JP 2006019459A
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epitaxial wafer
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growth
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led
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Takashi Furuya
貴士 古屋
Daisuke Hino
大輔 日野
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an epitaxial wafer for a light-emitting diode having an irregularly roughened outermost surface at the stage of a wafer previously without a positive roughening treatment after a growth. <P>SOLUTION: The epitaxial wafer for the light-emitting diode having a double hetero structure laminates an n-type clad layer 2 composed of AlGaInP, an active layer 3, a p-type clad layer 4, and a current dispersion layer 5 composed of AlGaAs or AlGaInP on a conductive substrate 1. In such an epitaxial wafer for the light-emitting diode, a group V gas is supplied or is not supplied at a constant interval during the growth of the current dispersion layer 5 on the outermost surface, thus intentionally forming irregularities 5a to the current dispersion layer 5 as the outermost surface. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、光取り出し効率を高める為に最表面層を故意に凸凹に荒らした発光ダイオード(LED)用のエピタキシャルウェハに関するものである。   The present invention relates to an epitaxial wafer for a light emitting diode (LED) in which an outermost surface layer is intentionally roughened to increase light extraction efficiency.

従来の高輝度LED用エピタキシャルウェハは、有機金属気相成長(MOVPE)法やハイドライドVPE法といった気相成長法を用いて作製されることが多い。MOVPE法を例にとって説明する。   Conventional epitaxial wafers for high-brightness LEDs are often produced using vapor phase growth methods such as metal organic chemical vapor deposition (MOVPE) and hydride VPE methods. The MOVPE method will be described as an example.

成長は結晶基板をヒータで加熱し、そこにキャリアガスとして水素や窒素を用いてIII族原料となるトリメチルガリウム(TMG)やトリメチルアルミニウム(TMA)、トリメチルインジウム(TMI)、V族原料となるアルシン(AsH3)、ホスフィン(PH3)を供給し、熱分解反応により結晶成長させる。 In the growth, a crystal substrate is heated with a heater, and hydrogen or nitrogen is used as a carrier gas, and trimethylgallium (TMG), trimethylaluminum (TMA), trimethylindium (TMI), or trimethylindium (TMI) as a group III material, or arsine as a group V material. (AsH 3 ) and phosphine (PH 3 ) are supplied, and crystals are grown by a thermal decomposition reaction.

図3に、(AlxGa1-xyIn1-yP(0≦x≦1、0<y≦1)系のダブルヘテロ構造を持つLED用エピタキシャルウェハの断面構造を示す。 FIG. 3 shows a cross-sectional structure of an epitaxial wafer for LEDs having a double heterostructure of (Al x Ga 1 -x ) y In 1 -y P (0 ≦ x ≦ 1, 0 <y ≦ 1).

このLED用エピタキシャルウェハを製造する場合、650℃に加熱したn型GaAsからなる基板1上に、n型AlGaInPからなるn型クラッド層2、活性層3、p型AlGaInPからなるp型クラッド層4を順次に積層成長し、更に最表面に(AlxGa1-xyIn1-yP(0≦x≦1、0<y≦1)もしくはAlxGa1-xAs(0≦x<1)からなる電流分散層6を積層成長する。電流分散層6の成長終了と同時にヒータを切り温度を下げて成長は完了である。 When manufacturing this LED epitaxial wafer, an n-type cladding layer 2 made of n-type AlGaInP, an active layer 3 and a p-type cladding layer 4 made of p-type AlGaInP on a substrate 1 made of n-type GaAs heated to 650 ° C. Are sequentially stacked and (Al x Ga 1-x ) y In 1-y P (0 ≦ x ≦ 1, 0 <y ≦ 1) or Al x Ga 1-x As (0 ≦ x) The current spreading layer 6 made of <1) is grown by lamination. At the same time as the growth of the current spreading layer 6, the heater is turned off and the temperature is lowered to complete the growth.

こうして成長したLED用エピタキシャルウェハの表面は従来鏡面であり、表面平坦性も非常に良い。   The surface of the epitaxial wafer for LED thus grown is conventionally a mirror surface, and the surface flatness is very good.

このLED用エピタキシャルウェハにチップ作製プロセスを行い、n型電極、p型電極を形成し、所定寸法のチップにダイシングすると、LEDチップが完成する。完成したLEDチップの電極間に電流を流すことにより、活性層で発光する。発光した光はさまざまな方向に広がり、外部に光として取出される。   A chip manufacturing process is performed on the epitaxial wafer for LED, an n-type electrode and a p-type electrode are formed, and dicing into a chip of a predetermined size completes the LED chip. The active layer emits light by passing a current between the electrodes of the completed LED chip. The emitted light spreads in various directions and is extracted outside as light.

活性層で発光した光は、全てを外部に取出すことは困難である。それは、発光した光の中には、結晶中を伝搬する際に吸収されたり、ウェハ最表面と空気との界面で全反射してしまい外部に放出されないものがあるからである。特に、MOVPE法等の気相成長法で作製したウェハ表面は平坦性が良好な為、光の全反射が起こりやすく、光の取出し効率を低下させてしまう。そのためLEDの発光強度が低下する原因となる。   It is difficult to extract all the light emitted from the active layer to the outside. This is because some of the emitted light is absorbed when propagating through the crystal, or is totally reflected at the interface between the outermost surface of the wafer and air and is not emitted to the outside. In particular, a wafer surface produced by a vapor phase growth method such as the MOVPE method has good flatness, so that total reflection of light easily occurs and the light extraction efficiency is lowered. For this reason, the emission intensity of the LED is reduced.

LEDの発光効率は、内部量子効率と光の取出しの積(外部量子効率)に比例する。内部量子効率は、LED構造や結晶性の向上によって70%にまで達しており、既に飽和傾向である。一方、取出し効率は通常20%以下に留まっている。つまり、発光効率が低いのは、取出し効率が低いことが主な原因である。   The luminous efficiency of the LED is proportional to the product of the internal quantum efficiency and the light extraction (external quantum efficiency). The internal quantum efficiency has reached 70% due to the improvement of the LED structure and crystallinity, and already has a saturation tendency. On the other hand, the extraction efficiency usually remains below 20%. That is, the low light emission efficiency is mainly due to the low extraction efficiency.

GaAs系のLEDにおいては、そのチップの表面全体に湿式エッチングにより凹凸を付けることが提案されている(例えば、特許文献1参照)。この提案によれば、チップ表面に凹凸を付けることで、ミクロに見ると光の取り出し面にさまざまな角度を有する凹凸が形成され、これにより、有効立体角度が大きくなり、光の取出し効率が向上する。この表面凹凸化には、硝酸系のエッチング液や、弗化水素酸や、アンモニア−過酸化水素系のエッチング液が使用される。
特開2000−196141号公報(図1)
In a GaAs-based LED, it has been proposed that the entire surface of the chip is roughened by wet etching (see, for example, Patent Document 1). According to this proposal, by providing irregularities on the chip surface, irregularities with various angles are formed on the light extraction surface when viewed microscopically, thereby increasing the effective solid angle and improving the light extraction efficiency. To do. For this surface unevenness, a nitric acid-based etchant, hydrofluoric acid, or an ammonia-hydrogen peroxide-based etchant is used.
Japanese Unexamined Patent Publication No. 2000-196141 (FIG. 1)

上記したように、LEDでは、その素子表面に微細な凹凸を形成することが、光の取出し効率を高めて発光素子の光取出し効率を改善する上で有効である。   As described above, in the LED, it is effective to form fine irregularities on the element surface in order to improve the light extraction efficiency of the light emitting element by increasing the light extraction efficiency.

しかしながら、特許文献1の如くLED用エピタキシャルウェハからチップに切り出した後で、各LEDチップの表面全体を粗面化処理することは、工程数の増加を招き、コストを増大させる。従って、エピタキシャルウェハの成長後にあえて粗面化処理を行うことなく、既にウェハの段階で、LEDの表面に微細な凹凸を形成しておき、これにより光の取出し効率を高めてLEDの発光効率を改善する簡便な手段の提供が望まれる。   However, roughening the entire surface of each LED chip after cutting it out from the LED epitaxial wafer as in Patent Document 1 causes an increase in the number of steps and increases the cost. Therefore, without roughening after the growth of the epitaxial wafer, fine irregularities are already formed on the surface of the LED at the wafer stage, thereby improving the light extraction efficiency and improving the LED light emission efficiency. It is desirable to provide a simple means for improvement.

そこで、本発明の目的は、上記課題を解決し、既にウェハの段階で、凹凸に荒らされた最表面を持ち、従ってエピタキシャルウェハの成長後にあえてLEDチップの粗面化処理を行う必要のないLED用エピタキシャルウェハを提供することにある。   Accordingly, an object of the present invention is to solve the above-mentioned problems, and has an outermost surface roughened by unevenness at the stage of a wafer, and therefore there is no need to dare to roughen the LED chip after the growth of the epitaxial wafer. An epitaxial wafer is provided.

上記目的を達成するため、本発明は、次のように構成したものである。   In order to achieve the above object, the present invention is configured as follows.

請求項1の発明に係る発光ダイオード(LED)用エピタキシャルウェハは、基板上に、(AlxGa1-xyIn1-yP(0≦x≦1、0<y≦1)からなるn型クラッド層、活性層、p型クラッド層及びAlxGa1-xAs(0≦x<1)もしくは(AlxGa1-xyIn1-yP(0≦x≦1、0<y≦1)からなる電流分散層を積層したダブルへテロ構造を有する発光ダイオード(LED)用エピタキシャルウェハにおいて、最表面の電流分散層の成長中にV族ガスの供給を一定の間隔で入れたり、切ったりすることで、最表面の電流分散層に故意に凸凹を設けた構造を有することを特徴とする。 Light emitting diode (LED) epitaxial wafer according to a first aspect of the invention, on a substrate, made of (Al x Ga 1-x) y In 1-y P (0 ≦ x ≦ 1,0 <y ≦ 1) n-type cladding layer, active layer, p-type cladding layer and Al x Ga 1-x As (0 ≦ x <1) or (Al x Ga 1-x ) y In 1-y P (0 ≦ x ≦ 1, 0 In an epitaxial wafer for a light emitting diode (LED) having a double hetero structure in which current dispersion layers made of <y ≦ 1) are laminated, supply of a group V gas is inserted at regular intervals during the growth of the outermost current dispersion layer. Or having a structure in which unevenness is intentionally provided in the outermost current spreading layer by cutting or cutting.

請求項2の発明は、請求項1記載の発光ダイオード(LED)用エピタキシャルウェハにおいて、前記最表面の電流分散層に故意に設けられる凸凹が、当該電流分散層の成長中におけるV族ガス供給の入り切り間隔を5秒以上20秒以下とすることで形成されていることを特徴とする。   According to a second aspect of the present invention, in the epitaxial wafer for a light emitting diode (LED) according to the first aspect, the unevenness intentionally provided in the outermost current spreading layer is a group V gas supply during the growth of the current spreading layer. It is formed by setting the on / off interval to 5 seconds or more and 20 seconds or less.

<発明の要点>
本発明のLED用エピタキシャルウェハでは、活性層で発光した光がLEDの表面から空気中へ放出するときに表面で全反射する確率を減少させる為に、表面層である(AlxGa1-x)As(0≦x<1)もしくは(AlxGa1-xyIn1-yP(0≦x≦1、0<y≦1)からなる電流分散層の表面を故意に凸凹に荒らしている。凸凹に荒らす手段としては、チップにした後で実施する湿式のエッチングが知られている(例えば、特許文献1参照)が、本発明では、電流分散層の成長中にV族原料ガスとなるAsH3やPH3の供給を一定間隔で入れたり切ったりすることで、成長面を故意に凸凹に荒らしている。
<Key points of the invention>
The LED epitaxial wafer of the present invention is a surface layer (Al x Ga 1-x) in order to reduce the probability that light emitted from the active layer is totally reflected on the surface when emitted from the surface of the LED into the air. ) The surface of the current spreading layer made of As (0 ≦ x <1) or (Al x Ga 1−x ) y In 1-y P (0 ≦ x ≦ 1, 0 <y ≦ 1) is intentionally roughened. ing. As a means for roughening unevenness, wet etching performed after forming a chip is known (see, for example, Patent Document 1), but in the present invention, AsH that becomes a group V source gas during the growth of a current dispersion layer is known. By turning on and off the supply of 3 and PH 3 at regular intervals, the growth surface is intentionally roughened.

成長中にV族ガスの供給を切ると、成長雰囲気中のV族分圧が下がる為、成長した結晶からV族の脱離が起こり、成長面が凸凹に荒れる。但し、供給を切っている時間が長くなると成長した表面にIII族のドロップレットが発生してしまい、著しく結晶の質が悪化してしまう。結晶の質が悪くなるとデバイスにした時に輝度が低下したり、寿命が落ちる等のデバイス特性が悪くなる。   If the supply of the group V gas is cut off during the growth, the group V partial pressure in the growth atmosphere is lowered, so that the group V is detached from the grown crystal, and the growth surface becomes rough. However, if the supply is cut off for a long time, Group III droplets are generated on the grown surface, and the quality of the crystal is significantly deteriorated. If the quality of the crystal is deteriorated, the device characteristics such as the decrease in luminance and the lifespan of the device are deteriorated.

供給を切る時間と表面荒れの程度について調べたところ、5秒より短いと結晶表面は荒れることなく鏡面だった。5秒を越えると表面が凸凹に荒れだし20秒を越えると、Gaのドロップレットが発生してしまった。これより、供給を切る時間は5秒から20秒の間とする。   When the time to cut the supply and the degree of surface roughness were examined, the crystal surface was mirror-like when it was shorter than 5 seconds. When the time exceeded 5 seconds, the surface became rough, and when the time exceeded 20 seconds, Ga droplets were generated. From this, the time to cut off the supply is between 5 seconds and 20 seconds.

本発明によれば、次のような優れた効果が得られる。   According to the present invention, the following excellent effects can be obtained.

本発明のLED用エピタキシャルウェハは、ウェハの段階で、つまり最表面の電流分散層の成長中にV族ガスの供給を一定の間隔で入れたり、切ったりしながら成長することで、最表面の電流分散層に故意に凸凹を形成している。従って、本発明によれば、成長後にあえて粗面化プロセスを行うことなく、V族ガスの供給を入り切りするという簡便な方法で、ウェハ最表面を凸凹に荒らし、これにより光の取出し効率を良くして、LEDにした時の発光強度を高くすることができる。   The epitaxial wafer for LED of the present invention is grown at the wafer stage, that is, while the supply of the group V gas is turned on and off at regular intervals during the growth of the current distribution layer on the outermost surface. An irregularity is intentionally formed in the current spreading layer. Therefore, according to the present invention, the surface of the wafer is roughened by a simple method of turning on and off the supply of the group V gas without performing a roughening process after the growth, thereby improving the light extraction efficiency. Thus, the emission intensity when the LED is used can be increased.

また本発明のLED用エピタキシャルウェハは、表面が凸凹しているために、電極形成時の接触面積が増え、コンタクト抵抗が減少する。これによりLED特性の一つである順方向電圧(V)を減少させることができる。 Moreover, since the epitaxial wafer for LED of this invention has the uneven surface, the contact area at the time of electrode formation increases, and contact resistance reduces. Thereby, the forward voltage (V f ) which is one of the LED characteristics can be reduced.

以下、本発明を図示の実施の形態に基づいて説明する。   Hereinafter, the present invention will be described based on the illustrated embodiments.

図1に、本実施形態に係るLED用エピタキシャルウェハの断面構造を示す。   FIG. 1 shows a cross-sectional structure of an LED epitaxial wafer according to this embodiment.

このLED用エピタキシャルウェハは、MOVPE法を用い、導電性を有し、且つGaAsからなる基板1上に、(AlxGa1-xyIn1-yP(0≦x≦1、0<y≦1)からなるn型クラッド層2、活性層3、(AlxGa1-xyIn1-yP(0≦x≦1、0<y≦1)からなるp型クラッド層4を積層したダブルへテロ構造を有し、更にそのp型クラッド層4上に、AlxGa1-xAs(0≦x<1)もしくは(AlxGa1-xyIn1-yP(0≦x≦1、0<y≦1)からなる電流分散層5を積層した構造を有する。 This epitaxial wafer for LED uses the MOVPE method and has conductivity (Al x Ga 1 -x ) y In 1 -y P (0 ≦ x ≦ 1, 0 <) on a substrate 1 made of GaAs. n-type cladding layer 2 made of y ≦ 1), active layer 3, p-type cladding layer 4 made of (Al x Ga 1−x ) y In 1−y P (0 ≦ x ≦ 1, 0 <y ≦ 1) Further, Al x Ga 1-x As (0 ≦ x <1) or (Al x Ga 1-x ) y In 1-y P is formed on the p-type cladding layer 4. It has a structure in which a current dispersion layer 5 made of (0 ≦ x ≦ 1, 0 <y ≦ 1) is laminated.

このLED用エピタキシャルウェハを製造する場合、MOVPE法などの気相成長法により、650℃に加熱したn型GaAsからなる基板1上に、AlGaInPからなるn型クラッド層2、活性層3、AlGaInPからなるp型クラッド層4を順次に積層成長する。更に、最表面にAlGaInPもしくはAlGaAsからなる電流分散層5を積層成長するが、この最表面の電流分散層5の成長中に、V族ガスの供給を一定の間隔で入れたり、切ったりしながら成長することで、最表面の電流分散層5に故意に凸凹5aを形成する。すなわちウェハ最表面を凹凸に荒らす。   When this epitaxial wafer for LED is manufactured, an n-type cladding layer 2 made of AlGaInP, an active layer 3 and an AlGaInP are formed on a substrate 1 made of n-type GaAs heated to 650 ° C. by a vapor phase growth method such as MOVPE. The resulting p-type cladding layer 4 is sequentially stacked and grown. Further, a current spreading layer 5 made of AlGaInP or AlGaAs is laminated and grown on the outermost surface. While the current spreading layer 5 on the outermost surface is grown, the supply of the group V gas is turned on and off at regular intervals. By growing, the unevenness 5a is intentionally formed in the current distribution layer 5 on the outermost surface. That is, the top surface of the wafer is roughened.

このように、ウェハの段階で素子表面に微細な凹凸を形成したLED用エピタキシャルウェハによれば、チップにした後に粗面化処理する場合に較べ、より簡便に、素子表面に凸凹を形成して、素子最表面での全反射による光取出し効率低下の問題を解決し、光の取出し効率を高め、発光素子の発光効率を改善することができる。   In this way, according to the epitaxial wafer for LEDs in which fine irregularities are formed on the element surface at the wafer stage, it is easier to form irregularities on the element surface than in the case of roughening after forming a chip. It is possible to solve the problem of reduction in light extraction efficiency due to total reflection on the outermost surface of the element, increase the light extraction efficiency, and improve the light emission efficiency of the light emitting element.

次に、実施例を従来例と対比させて、より具体的に説明する。   Next, the embodiment will be described more specifically in comparison with the conventional example.

〔従来例〕
MOVPE法を用い、従来技術の方法で、LED用エピタキシャルウェハを成長した。成長の一例を示す。
[Conventional example]
The epitaxial wafer for LED was grown by the method of the prior art using the MOVPE method. An example of growth is shown.

基板をヒータにて650℃に加熱し、そこにキャリアガスとして水素を用いてIII族原料となるTMG、TMA、TMI、V族原料となるAsH3、PH3ドーパントとなるセレン化水素(H2Se)、ジエチル亜鉛(DEZ)を必要に応じ供給し成長を行った。 The substrate is heated to 650 ° C. with a heater, and hydrogen is used as a carrier gas therefor, TMG, TMA, TMI as Group III materials, AsH 3 as Group V materials, and hydrogen selenide as H 3 dopant (H 2 Se) and diethyl zinc (DEZ) were supplied as needed for growth.

図4に成長したLED用エピウェハの断面模式図を記す、SiドープGaAs基板7上に、SeドープGaAsバッファ層8、SeドープAlGaInPクラッド層9、アンドープAlGaInP活性層10、ZnドープAlGaInPクラッド層11を順に積層成長し、最後にZnドープAlGaAs電流分散層12を成長し、成長完了と同時にヒータを切り冷却した。成長したウェハ表面は鏡面であり、平坦性も良好だった。   FIG. 4 is a schematic cross-sectional view of the grown epitaxial wafer for LED. On a Si-doped GaAs substrate 7, a Se-doped GaAs buffer layer 8, a Se-doped AlGaInP cladding layer 9, an undoped AlGaInP active layer 10, and a Zn-doped AlGaInP cladding layer 11 are formed. Then, the Zn-doped AlGaAs current dispersion layer 12 was grown in order, and the heater was turned off and cooled simultaneously with the completion of the growth. The grown wafer surface was mirror-like and had good flatness.

〔実施例〕
次に本発明の実施例にかかるLED用エピタキシャルウェハをMOVPE法で成長した例を記す。本実施例で作製したエピタキシャルウェハの断面を図2に模式的に示す。従来例の図4とは、ZnドープAlGaInPクラッド層11の上に、上記ZnドープAlGaAs電流分散層12の代わりに、凸凹13aを有するZnドープAlGaAs電流分散層13が設けてある点で相違する。
〔Example〕
Next, an example of growing an epitaxial wafer for LED according to an embodiment of the present invention by the MOVPE method will be described. A cross section of the epitaxial wafer produced in this example is schematically shown in FIG. 4 differs from the conventional example of FIG. 4 in that a Zn-doped AlGaAs current spreading layer 13 having irregularities 13a is provided on the Zn-doped AlGaInP cladding layer 11 instead of the Zn-doped AlGaAs current spreading layer 12.

成長方法としては、p型クラッド層であるZnドープAlGaInPクラッド層11までは、従来の成長方法(図4)と同じに成長した。このZnドープAlGaInPクラッド層11の上に形成するZnドープAlGaAs電流分散層13は、その成長中に、V族原料であるAsH3の供給を10秒供給し、その後10秒供給を切る、というV族ガス供給の入り切り操作を繰り返し行うことで成長した。 As the growth method, the layers up to the Zn-doped AlGaInP cladding layer 11 which is a p-type cladding layer were grown in the same manner as the conventional growth method (FIG. 4). The Zn-doped AlGaAs current distribution layer 13 formed on the Zn-doped AlGaInP cladding layer 11 is supplied with AsH 3 as a group V material for 10 seconds during its growth, and then turns off the supply for 10 seconds. It grew by repeatedly turning on and off the group gas supply.

取り出したエピタキシャルウェハ表面を電子顕微鏡で観察したところ、表面が細かく凸凹に荒れていた。   When the surface of the taken-out epitaxial wafer was observed with an electron microscope, the surface was fine and rough.

上記した従来例と本実施例の成長方法で作成したLED用エピタキシャルウェハを、チップ作製プロセスにかけて、n型電極とp型電極を形成し、LEDチップを作成し、20mAの電流を流して発光させ、その発光強度を比較した。   The LED epitaxial wafer prepared by the growth method of the above-described conventional example and this example is subjected to a chip manufacturing process, an n-type electrode and a p-type electrode are formed, an LED chip is formed, and a current of 20 mA is applied to emit light. The emission intensity was compared.

従来例の成長方法で作製したウェハ(図4)のLEDの場合は、発光強度が100mcdだったの対し、本実施例の製造方法で作製したウェハ(図2)のLEDの場合は、発光強度が120mcdであり、本実施例のLED用エピタキシャルウェハの方が20%も輝度が向上していた。   In the case of the LED of the wafer (FIG. 4) produced by the conventional growth method, the emission intensity was 100 mcd, whereas in the case of the LED of the wafer (FIG. 2) produced by the production method of this example, the emission intensity was The brightness was improved by 20% in the LED epitaxial wafer of this example.

〔他の実施例〕
上記実施例のAsH3の供給を切ったり入れたりする間隔を、4秒、5秒、20秒、21秒としたときの成長も行い、表面状態を確認し、その後ウェハをチップ作製プロセスにかけて得られたチップの発光強度の比較を行った。
[Other Examples]
In the above example, growth was performed when the supply of AsH 3 was turned off and on for 4 seconds, 5 seconds, 20 seconds, and 21 seconds, the surface state was confirmed, and then the wafer was obtained through a chip manufacturing process. The emission intensity of the obtained chips was compared.

表面状態については、成長材料供給の入り切り間隔が4秒のウェハ(比較例1)では表面が鏡面であったが、成長材料供給の入り切り間隔が5秒、20秒のエピタキシャルウェハ(他の実施例)では表面に希望する凸凹が観察された。21秒のウェハ(比較例2)の表面には金属粒のドロップレットが発生していた。   As for the surface state, the surface of the wafer with the growth material supply on / off interval of 4 seconds (Comparative Example 1) was a mirror surface, but the growth material supply on / off interval of 5 seconds and 20 seconds with the epitaxial wafer (other examples) ), The desired irregularities were observed on the surface. Metal particle droplets were generated on the surface of the 21-second wafer (Comparative Example 2).

発光強度測定では、成長材料供給の入り切り間隔が4秒のものは102mcdであり、従来技術の成長方法のものと較べ、変化が無かった。これに対し、成長材料供給の入り切り間隔が5秒、20秒のものについては、それぞれ115mcd、122mcdと輝度が高かった。残る21秒のものは50mcdと輝度が大幅に低下していた。   In the measurement of the emission intensity, the growth material supply with the on / off interval of 4 seconds was 102 mcd, which was not changed as compared with the growth method of the prior art. On the other hand, when the growth material supply interval was 5 seconds and 20 seconds, the luminance was 115 mcd and 122 mcd, respectively. The remaining 21 seconds had 50 mcd and the brightness was greatly reduced.

本実施例によれば、成長後にあえてプロセスを行うことなく、簡便にウェハ最表面を凸凹に荒らすことができる為、これにより光の取出し効率がよくなり、LEDにした時の発光強度が高くなる。   According to the present embodiment, the wafer outermost surface can be easily roughened without being dared to perform a process after growth, so that the light extraction efficiency is improved and the light emission intensity is increased when an LED is formed. .

また本実施例を用いたエピタキシャルウェハは、表面が凸凹しているために電極形成時の接触面積が増え、コンタクト抵抗が減少する。これによりLED特性の一つである順方向電圧(V)を減少させることができる。 In addition, since the epitaxial wafer using this embodiment has an uneven surface, the contact area during electrode formation increases and the contact resistance decreases. Thereby, the forward voltage (V f ) which is one of the LED characteristics can be reduced.

〔変形例〕
上記実施例では、電流分散層の表面を凸凹に荒らす手段として、V族の供給のみを切ったが、III族、V族ともに供給を切り、V族分圧を減らすことで成長した結晶表面を荒らしながら成長してもよい。
[Modification]
In the above embodiment, as a means for roughening the surface of the current spreading layer, only the supply of the group V is cut off. However, the crystal surface grown by cutting off the supply of both the group III and group V and reducing the group V partial pressure is used. You may grow up while ruining.

本発明の実施形態にかかる発光ダイオード(LED)用エピタキシャルウェハの断面構造を示した模式図である。It is the schematic diagram which showed the cross-section of the epitaxial wafer for light emitting diodes (LED) concerning embodiment of this invention. 本発明の実施例にかかる発光ダイオード(LED)用エピタキシャルウェハの断面構造を示した模式図である。It is the schematic diagram which showed the cross-section of the epitaxial wafer for light emitting diodes (LED) concerning the Example of this invention. 従来の発光ダイオード(LED)用エピタキシャルウェハの断面構造を示した模式図である。It is the schematic diagram which showed the cross-section of the conventional epitaxial wafer for light emitting diodes (LED). 従来の他の発光ダイオード(LED)用エピタキシャルウェハの断面構造を示した模式図である。It is the schematic diagram which showed the cross-section of the other conventional epitaxial wafer for light emitting diodes (LED).

符号の説明Explanation of symbols

1 基板
2 n型クラッド層
3 活性層
4 p型クラッド層
5 電流分散層
5a 凸凹
6 電流分散層
7 SiドープGaAs基板
8 SeドープGaAsバッファ層
9 SeドープAlGaInPクラッド層
10 アンドープAlGaInP活性層
11 ZnドープAlGaInPクラッド層
12 ZnドープAlGaAs電流分散層
13 ZnドープAlGaAs電流分散層
13a 凸凹
DESCRIPTION OF SYMBOLS 1 Substrate 2 N-type cladding layer 3 Active layer 4 P-type cladding layer 5 Current dispersion layer 5a Unevenness 6 Current dispersion layer 7 Si-doped GaAs substrate 8 Se-doped GaAs buffer layer 9 Se-doped AlGaInP cladding layer 10 Undoped AlGaInP active layer 11 Zn-doped AlGaInP cladding layer 12 Zn-doped AlGaAs current spreading layer 13 Zn-doped AlGaAs current spreading layer 13 a Uneven

Claims (2)

基板上に、(AlxGa1-xyIn1-yP(0≦x≦1、0<y≦1)からなるn型クラッド層、活性層、p型クラッド層及びAlxGa1-xAs(0≦x<1)もしくは(AlxGa1-xyIn1-yP(0≦x≦1、0<y≦1)からなる電流分散層を積層したダブルへテロ構造を有する発光ダイオード用エピタキシャルウェハにおいて、
最表面の電流分散層の成長中にV族ガスの供給を一定の間隔で入れたり、切ったりすることで、最表面の電流分散層に故意に凸凹を設けたことを特徴とする発光ダイオード用エピタキシャルウェハ。
An n-type cladding layer, an active layer, a p-type cladding layer, and an Al x Ga 1 layer made of (Al x Ga 1 -x ) y In 1 -y P (0 ≦ x ≦ 1, 0 <y ≦ 1) are formed on a substrate. -x As (0 ≦ x <1) or (Al x Ga 1-x ) y In 1-y P (0 ≦ x ≦ 1, 0 <y ≦ 1) laminated double hetero structure In an epitaxial wafer for light emitting diodes having
For light-emitting diodes, wherein the outermost current spreading layer is intentionally provided with irregularities by turning on or off the supply of group V gas at regular intervals during the growth of the outermost current spreading layer Epitaxial wafer.
請求項1記載の発光ダイオード用エピタキシャルウェハにおいて、
前記最表面の電流分散層に故意に設けられる凸凹が、当該電流分散層の成長中におけるV族ガス供給の入り切り間隔を5秒以上20秒以下とすることで形成されていることを特徴とする発光ダイオード用エピタキシャルウェハ。
In the epitaxial wafer for light emitting diodes of Claim 1,
The unevenness provided intentionally in the current distribution layer on the outermost surface is formed by setting the on / off interval of the V group gas supply during the growth of the current distribution layer to be 5 seconds or more and 20 seconds or less. Epitaxial wafer for light emitting diode.
JP2004195115A 2004-07-01 2004-07-01 Epitaxial wafer for light-emitting diode Pending JP2006019459A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007273506A (en) * 2006-03-30 2007-10-18 Sumitomo Chemical Co Ltd Compound semiconductor light emitting element
US20120255360A1 (en) * 2011-04-08 2012-10-11 Tejas Testing & Inspection, Inc. Phased array ultrasonic examination system and method
CN105070800A (en) * 2015-09-10 2015-11-18 天津理工大学 AlGaInP quaternary-system LED gallium phoshpide window layer coarsening method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007273506A (en) * 2006-03-30 2007-10-18 Sumitomo Chemical Co Ltd Compound semiconductor light emitting element
WO2007119633A1 (en) * 2006-03-30 2007-10-25 Sumitomo Chemical Company, Limited Light emitting element
GB2451365A (en) * 2006-03-30 2009-01-28 Sumitomo Chemical Co Light emitting element
US8097887B2 (en) 2006-03-30 2012-01-17 Sumitomo Chemical Company, Limited Light emitting device having a monotone decreasing function
US20120255360A1 (en) * 2011-04-08 2012-10-11 Tejas Testing & Inspection, Inc. Phased array ultrasonic examination system and method
US8746070B2 (en) * 2011-04-08 2014-06-10 Tejas Testing & Inspection, Inc. Phased array ultrasonic examination system and method
CN105070800A (en) * 2015-09-10 2015-11-18 天津理工大学 AlGaInP quaternary-system LED gallium phoshpide window layer coarsening method

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