JP2006019370A - Semiconductor element mounting structure and electrooptic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element mounting structure etc., that can make the drawing around of wiring patterns easier and can reduce the size of a substrate. <P>SOLUTION: In the semiconductor element mounting structure, a semiconductor element provided with a group of bump electrodes to be face-down bonded to the substrate and the wiring pattern formed on the substrate are electrically connected to each other. The group of bump electrodes contains a first bump electrode row arranged along one side of the semiconductor element, and a second bump electrode row which is substantially linearly in-plane arranged at a prescribed distance from the facing one side of the semiconductor element. On the substrate, the first wiring pattern corresponding to the first bump electrode row and the second wiring pattern corresponding to the second bump electrode row are respectively formed. When the structure is viewed in the vertical direction, in addition, the first wiring patterns is formed in a state where the pattern is drawn out so that the pattern may intersect the one side of the semiconductor element and, at the same time, the second wiring pattern is formed in a state where the pattern is drawn out so that the pattern may intersect a plurality of sides of the element except the one side. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor element mounting structure and an electro-optical device. In particular, by using a semiconductor element including a bump electrode group including a first bump electrode array and a second bump electrode array arranged in a predetermined manner, the substrate can be reduced in size and the wiring pattern can be routed freely. The present invention relates to a semiconductor element mounting structure and an electro-optical device that can be improved.

  Conventionally, as an example of mounting a semiconductor element (semiconductor element) on a substrate by a face-down method, for example, in a liquid crystal display device, a driving semiconductor element (semiconductor chip) is anisotropy on a transparent substrate constituting a liquid crystal panel. Some are mounted on COG (Chip on Glass) using a conductive film or the like. This mounting method using an anisotropic conductive film has the advantage that it is possible to cope with fine pitch and that multiple contacts can be electrically connected together.

As a mounting structure suitable for such a mounting method, a mounting structure using a semiconductor element having a bump electrode group for face-down bonding on a mounting surface with a substrate has been proposed. The bump electrode group includes at least first bump electrode rows arranged along one side of the chip sides, and first bump electrodes arranged obliquely inward from both ends of the first bump electrode row. 2 and a third bump electrode array (see Patent Document 1).
More specifically, as shown in FIG. 11B, the bump electrode group of the driving semiconductor element is opposed to the first electrode row 651 and the first electrode row 651 arranged along the chip side. In addition to the fourth electrode row 654, second and third electrode rows 652 and 653 arranged obliquely from both ends of the first electrode row 651 toward the fourth electrode row 654 are provided. Therefore, as shown in FIG. 11A, the electrode terminals 662 and 663 on the substrate side on which the bump electrodes 652 and 653 of the second and third electrode rows are mounted are also obliquely arranged.
Therefore, since these electrode terminals are displaced from each other, when the wiring pattern drawn out from the electrode terminal is drawn out to the side opposite to the first electrode row 651, it is drawn out straight to the side. Without being bent at a right angle, the first electrode array 651 can be directly pulled out in the opposite direction. That is, it is possible to reduce useless space because there is no need to bypass the wiring pattern. In addition, since the wiring pattern can be drawn so as to follow the shortest path, the electrical resistance of the wiring pattern can be reduced. Furthermore, it is possible to draw out all the first to fourth wiring patterns 651 to 654 substantially in parallel, and when arranged in this way, even if the mounting position of the driving semiconductor element is shifted in the drawing direction of the wiring pattern, All the bump electrodes constituting the first to third bump electrode rows are located on the electrode terminals (wiring patterns).
Japanese Patent Laid-Open No. 11-297760 (Claims Fig. 4)

However, the mounting structure disclosed in Patent Document 1 eliminates the case where the wiring pattern drawn out from the vicinity of both ends of the semiconductor element is bent at a right angle by substantially expanding the lateral width of the semiconductor element, thereby reducing the length of the wiring pattern. Since the length is shortened, the semiconductor element to be used may be increased in size. Accordingly, there has been a problem that it is difficult to reduce the size of the electro-optical device by reducing the area of the protruding portion of the substrate.
In addition, although the mounting structure disclosed in Patent Document 1 can lead out all the wiring patterns as much as possible including the wiring patterns drawn from the vicinity of both ends of the semiconductor element, the pitch interval and the like are conventionally known. Thus, the degree of freedom in routing could not be improved without substantially changing.
Further, since the bump electrode group in the semiconductor element used in such a mounting structure is not substantially linear, there are many restrictions on the design of the semiconductor element, and it is difficult to manufacture such a semiconductor element. There was a case.

Therefore, the inventors of the present invention have made diligent efforts to use a semiconductor element including a bump electrode group including a first bump electrode array and a second bump electrode array that are arranged in a predetermined area, thereby overlapping the semiconductor element. The present invention has been completed by finding that such a problem can be effectively utilized and that such problems can be solved.
That is, the present invention improves the degree of freedom in routing the wiring pattern by using a semiconductor element including a bump electrode group that is arranged close to the distance between the first bump electrode array and the second bump electrode array. Another object of the present invention is to efficiently provide a semiconductor element mounting structure and an electro-optical device that can reduce the area of the protruding portion of the substrate and reduce the size of the electro-optical device.

According to the present invention, there is provided a semiconductor element mounting structure in which a semiconductor element having a bump electrode group for face-down bonding to a substrate and a wiring pattern on the substrate are electrically connected, and the bump electrode group The second bump electrode array arranged along one side of the semiconductor element and the second bump electrode arranged in a plane substantially linearly away from the side facing the one side of the semiconductor element by a predetermined distance. A bump electrode array, and the wiring pattern includes a first wiring pattern corresponding to the first bump electrode array and a second wiring pattern corresponding to the second bump electrode array, and the substrate When viewed in the vertical direction, the first wiring pattern is formed so as to intersect with one side of the semiconductor element, and the second wiring pattern intersects with a plurality of sides other than one side of the semiconductor element. I will do it Mounting structure of a semiconductor device is formed in drawer is provided, it is possible to solve the problems described above.
That is, by reducing the distance between the first bump electrode array and the second bump electrode array in the semiconductor element, the distance between the terminal of the first wiring pattern and the terminal of the second wiring pattern can be reduced. Therefore, a region overlapping with the semiconductor element in a plan view can also be effectively used as a routing region for the second wiring pattern. Therefore, when the outer dimension of the second substrate is shortened by the distance, the area of the substrate overhanging portion can be reduced, and the electro-optical device can be downsized. On the other hand, when the external dimensions of the second substrate are not changed, the wiring pattern routing area can be widened, the pitch interval of the wiring pattern can be widened, and the wiring width can be widened. Therefore, it is possible to provide an electro-optical device that can prevent occurrence of a short circuit between adjacent wiring patterns or reduce the electrical resistance of the wiring patterns.
Note that the second bump electrode row is separated from the predetermined side by a predetermined distance means that the first bump electrode row is arranged along one side of the semiconductor element, whereas the second bump electrode row is This means that the row is arranged between the side facing the one side of the semiconductor element and the first bump electrode row so as to be close to the first bump electrode row.

In constructing the semiconductor element mounting structure of the present invention, the semiconductor element has a dummy bump made of a conductive material and an electrical insulating property between the side facing the one side of the semiconductor element and the second bump electrode array. It is preferable to provide a dummy bump made of a material or one of the dummy bumps.
With this configuration, the stability of the semiconductor element can be improved, and poor connection between the semiconductor element and the terminal of the wiring pattern, disconnection of the wiring pattern by the semiconductor element, and the like can be effectively prevented.

In configuring the semiconductor element mounting structure of the present invention, the bump electrode group is preferably a metal bump or a plated bump obtained by performing metal plating on a polymer material.
With this configuration, when a metal bump is used, electrical connection can be ensured. On the other hand, in the case of a plated bump in which a metal material is plated on a polymer material, it is possible to improve the degree of freedom in arrangement and to easily cope with a narrow pitch of a wiring pattern.

Further, in configuring the semiconductor element mounting structure of the present invention, when the dummy bump is made of a conductive material when the substrate is viewed in the vertical direction, the second wiring pattern is formed so as to bypass the dummy bump. When the dummy bump is made of an electrically insulating material, it is preferable that the second wiring pattern is also formed at a position overlapping the dummy bump in plan view.
With this configuration, it is possible to effectively prevent a short circuit between the wiring patterns due to the dummy bumps.

Another aspect of the present invention is an electro-optic including a semiconductor element mounting structure in which a semiconductor element having a bump electrode group for face-down bonding to a substrate and a wiring pattern on the substrate are electrically connected. A bump electrode group of a semiconductor element is substantially separated from the first bump electrode array arranged along one side of the semiconductor element by a predetermined distance from the side facing the one side of the semiconductor element, A second bump electrode array linearly arranged in the plane, and the wiring pattern includes a first wiring pattern corresponding to the first bump electrode array and a second bump electrode array corresponding to the second bump electrode array. When the substrate is viewed in the vertical direction, the first wiring pattern is drawn out so as to intersect with one side of the semiconductor element, and the second wiring pattern is , Semiconductor An electro-optical device is formed by a drawer so as to intersect the plurality sides except one side of the element.
That is, by reducing the distance between the first bump electrode array and the second bump electrode array in the semiconductor element, the distance between the terminal of the first wiring pattern and the terminal of the second wiring pattern can be reduced. Therefore, when the outer dimension of the second substrate is shortened by the distance, the area of the substrate overhanging portion can be reduced and the electro-optical device can be reduced in size. On the other hand, if the wiring pattern routing area is widened without changing the external dimensions of the second substrate, the degree of freedom in routing the wiring pattern can be increased, the occurrence of short circuits, Can be reduced.

Hereinafter, embodiments of a semiconductor element mounting structure and an electro-optical device including the semiconductor element mounting structure of the present invention will be specifically described with reference to the drawings.
However, this embodiment shows one aspect of the present invention and does not limit the present invention, and can be arbitrarily changed within the scope of the present invention.

The present embodiment is an electro-optical device including a semiconductor element mounting structure in which a semiconductor element having a bump electrode group for face-down bonding to a substrate and a wiring pattern on the substrate are electrically connected, The bump electrode group of the semiconductor element is substantially in-plane with a predetermined distance from the first bump electrode array arranged along one side of the semiconductor element and a side facing the one side of the semiconductor element. A second wiring pattern corresponding to the first bump electrode array, and a second wiring pattern corresponding to the second bump electrode array. And when the substrate is viewed in the vertical direction, the first wiring pattern is drawn out so as to intersect with one side of the semiconductor element, and the second wiring pattern is formed on one side of the semiconductor element. An electro-optical device is formed by a drawer so as to intersect the outside of a plurality sides.
In this embodiment, an active matrix type liquid crystal display device including a TFD element (Thin Film Diode) will be described as an example of an electro-optical device including a semiconductor element mounting structure. Such a liquid crystal display device may be either a passive matrix type liquid crystal display device or an active matrix type liquid crystal display device including a TFT element (Thin Film Transistor).

1. Basic Structure of Electro-Optical Device (Liquid Crystal Display Device) First, the basic structure of the liquid crystal display device according to the present embodiment, that is, the cell structure, wiring, and the like will be specifically described with reference to FIGS. Here, FIG. 1 is a schematic perspective view of the liquid crystal display device 20, and FIG. 2 is a schematic cross-sectional view of the liquid crystal display device 20. 3A is a plan view of the first substrate 30, FIG. 3B is a plan view of the second substrate 60, and FIG. 3C is the first substrate 30 and the second substrate 30. It is a top view of the state which piled up the board | substrate 60 of this.

The liquid crystal display device 20 shown in FIGS. 1 and 2 includes a first substrate 30 having a transparent first glass substrate 31 as a base, and a second substrate 60 having a transparent second glass substrate 61 as a base. Are bonded to each other through a sealing material 23 such as an adhesive. Further, after the liquid crystal material 21 is injected into the space formed by the first substrate 30 and the second substrate 60 into the inner portion of the sealing material 23 through the opening 23a, the sealing material A cell structure sealed at 25 is provided. That is, the liquid crystal material 21 is filled between the first substrate 30 and the second substrate 60.
And although not shown in figure, this liquid crystal display device 20 can also be suitably attached with illumination apparatuses, such as a backlight and a front light, a case body, etc. as needed.

Moreover, the 1st board | substrate 30 which comprises the liquid crystal display device 20 shown by FIG.1 and FIG.2 is as an example the 1st glass substrate 31, the reflective layer 35, the colored layer 37, the light shielding layer 39, The planarizing layer 41 and the first electrode 33 are configured. A first alignment film 45 made of polyimide resin or the like is formed on the first electrode 33. Note that the electro-optical device of the present embodiment is an active matrix type liquid crystal display device including a TFD element, and the first electrode 33 means a scanning electrode.
A retardation plate (¼ wavelength plate) 47 and a polarizing plate 49 are arranged at a predetermined position on the first glass substrate 31 so that a clear image display can be recognized.

The second substrate 60 facing the first substrate 30 includes, as an example, a second glass substrate 61, wiring patterns 65, 66, and 67, a switching element 69, and a second electrode 63. It is configured. The electro-optical device according to the present embodiment is an active matrix type liquid crystal display device including a TFD element, the second electrode 63 means a pixel electrode, and the switching element 69 means a TFD element.
A second alignment film 75 made of the same polyimide resin or the like as the first alignment film 45 in the first substrate 30 is formed on the wiring pattern 65, the second electrode 63, and the like. Further, a retardation plate (¼ wavelength plate) 77 and a polarizing plate 79 are also arranged on the outer surface of the second glass substrate 61.

Then, a large number of pixels (hereinafter sometimes referred to as pixel regions) in which intersection regions between the first electrodes 33 and the second electrodes 63 formed on the respective substrates are arranged in a matrix form are configured. The arrangement of these numerous pixels constitutes the liquid crystal display area A as a whole.
In FIG. 1, the second electrode 63 and the switching element 69 corresponding to each pixel region are shown only in some pixel regions, but the other pixel regions also exist in the same manner. In the example of the electro-optical device according to this embodiment, the colored layer 37 is provided on the first glass substrate 31, but may be provided on the second glass substrate 61.

Moreover, the 2nd glass substrate 61 shown by FIG.1 and FIG.2 has the board | substrate overhang | projection part 61T extended outside the external shape of the 1st glass substrate 31, and on this board | substrate overhang | projection part 61T The wiring patterns 65, 66, and 67 are formed. The wiring patterns 65, 66, and 67 are tantalum or chromium metal material that forms the switching element 69, ITO (Indium Tin Oxide) that forms the second electrode 63, or the like. It can be formed from a transparent conductive material such as.
Of these wiring patterns, the end portions of the wiring patterns 65 and 67 serve as terminals to form the mounting region 98a of the semiconductor element (X driver) 91, and the end portions of the wiring patterns 66 and 67 A mounting region 98b of the semiconductor element (Y driver) 94 is formed as a terminal. Among these, a wiring pattern (sometimes referred to as a data line) 65 drawn toward the image display area A is electrically connected to the second electrode (pixel electrode) 63 via the switching element 69. It is connected to the.
Further, as shown in a schematic cross section in FIG. 2, the wiring pattern (leading wiring) 66 drawn toward the edge of the substrate on the image display area A side passes through the sealing material 23 containing conductive particles. It is electrically connected to the first electrode 33 on the first substrate 30. Furthermore, the wiring pattern 67 drawn toward the side opposite to the image display area A is electrically connected to the flexible substrate 93 and the connector.
In each of the mounting regions 98a and 98b, the semiconductor elements (ICs) 91 and 94 incorporating a liquid crystal driving circuit and the like are face-down so as to be electrically connected to the wiring patterns 65, 66 and 67, respectively. By mounting by so-called COG (Chip on Glass) by bonding, the semiconductor element mounting structure 100 of the present invention is configured.

2. Semiconductor Element Mounting Structure (1) Outline FIG. 4 shows a semiconductor element mounting structure 100 in the electro-optical device of this embodiment.
The semiconductor element mounting structure 100 shown in FIG. 4 is a semiconductor element mounting structure in which predetermined semiconductor elements 91, 94 and wiring patterns 65, 66, 67 on the second substrate 60 are electrically connected. Thus, the bump electrode group 120 of the semiconductor element 91 includes a predetermined first bump electrode array 121 and a second bump electrode array 122, and the wiring patterns 65, 66, and 67 are connected to the predetermined first wiring pattern 67 and When the second substrate 60 includes the second wiring patterns 65 and 66 and the second substrate 60 is viewed in the vertical direction, the first wiring pattern 67 intersects with the sides 91 a and 94 a of the semiconductor elements 91 and 94. The second wiring patterns 65 and 66 are drawn and formed so as to intersect with a plurality of sides other than one side 91a and 94a of the semiconductor elements 91 and 94. And butterflies.
In the following description, only the mounting structure of the semiconductor element (X driver) 91 for supplying a signal voltage to the second electrode 63 will be described, but the signal voltage is applied to the first electrode 33. A similar structure can be applied to the mounting structure of the semiconductor element (Y driver) 94 to be supplied.

  That is, according to the semiconductor element mounting structure of the present invention, the semiconductor element 91 is planarly overlapped by reducing the distance between the first bump electrode array 121 and the second bump electrode array 122 in the semiconductor element 91. It is possible to route the second wiring pattern 65 by effectively utilizing. More specifically, as shown in FIG. 5A, since the distance (R) between the terminal of the first wiring pattern 97 and the terminal of the second wiring pattern 65 can be reduced, the semiconductor element A region overlapping with 91 in a plane can be secured as a routing region for the second wiring pattern 65. Therefore, conventionally, the second wiring pattern 65 drawn from one side 91b of the semiconductor element 91 on the image display area A side is also drawn from two orthogonal sides 91c and 91d together with the side 91b. It will be.

At this time, as shown in FIG. 5A, the mounting position of the semiconductor element 91 is displayed as much as the distance corresponding to the distance between the terminal of the first wiring pattern 67 and the terminal of the second wiring pattern 65. It is preferable that the length of the second glass substrate 61 is made shorter by shifting to the region A side. This is because, when configured in this way, the area of the substrate overhanging portion 61T of the second glass substrate 61 can be reduced to reduce the size of the electro-optical device.
Further, as shown in FIGS. 5B and 5C, it is also preferable that the mounting position of the semiconductor element 91 is made the same as the conventional one without changing the outer dimension of the second glass substrate 61. The reason for this is that by configuring in this manner, a wide routing area of the second wiring pattern 65 can be secured, and the degree of freedom of routing of the second wiring pattern 65 can be improved. Therefore, as shown in FIG. 5B, the pitch interval (W) of the second wiring pattern 65 is widened to prevent the occurrence of a short circuit, or as shown in FIG. The electrical resistance can be reduced by increasing the width of the 65 wiring itself.
Further, as shown in FIG. 5D, the mounting position of the semiconductor element 91 is changed between the terminals of the first wiring pattern 67 and the second wiring pattern 65 without changing the external dimensions of the second glass substrate 61. It is also preferable to shift to the image display area A side by an amount corresponding to the distance that the terminal is close. This is because the degree of freedom in routing the first wiring pattern 67 can be improved by such a configuration. Therefore, as shown in FIG. 5D, the connection position between the first wiring pattern 67 and the flexible substrate 93 is selected to a desired position, for example, near the end of the second glass substrate 61. become able to.

(2) Semiconductor Element (2) -1 Overview In the semiconductor element mounting structure 100 shown in FIG. 4, the semiconductor element (X driver) 91 is connected to the second electrode (pixel electrode) 63 via the wiring pattern 65. This is a member for supplying a signal voltage. The semiconductor element (Y driver) 94 is a member for supplying a signal voltage to the first electrode (scanning electrode) 33 on the first substrate 30 via the wiring pattern 66. The semiconductor elements 91 and 94 apply a voltage to the liquid crystal material 21 in the pixel region constituted by the first electrode 33 and the second electrode 63 and apply a voltage according to each pixel. The image can be displayed by changing.
The semiconductor element does not necessarily have to be mounted with a plurality of semiconductor elements, and may be only one semiconductor element that can be controlled collectively.

  When mounting a semiconductor element, for example, wire bonding, a method of connecting a semiconductor Au bump to a substrate with an Ag paste, a method of using an anisotropic conductive film, a flip chip method of using a solder bump, a heat Various methods such as a pressure welding method using a curable resin can be employed. Above all, it can be thinned, and since it can play a role of insulating the connection part of the semiconductor element from the surroundings, it is mounted by a method using an anisotropic conductive film or a pressure welding method using a thermosetting resin. Preferably it is.

(2) -2 Bump Electrode Group Next, the bump electrode group 120 will be described with reference to FIGS. Here, FIG. 6A is a plan view seen from the mounting surface 92 side when the semiconductor element 91 is mounted on the second substrate 60, and FIG. 6B is a plan view in FIG. It is sectional drawing which looked at XX cross section of X in the arrow direction.
The semiconductor element 91 includes a first wiring pattern 67 on the second substrate 60 and a bump electrode group 120 that is electrically connected to the second wiring pattern 65. The bump electrode group 120 is substantially linearly separated from the first bump electrode array 121 arranged along one side 91a of the semiconductor element 91 by a predetermined distance from the side 91b facing the one side 91a. And a second bump electrode array 122 arranged in-plane.
Among these, the bump electrode of the first bump electrode row 121 has the other terminal connected to the terminal of the first wiring pattern 67 connected to the above-described flexible substrate 93, connector or the like, and the semiconductor element 91. Is an input terminal for inputting a signal. Further, the bump electrodes of the second bump electrode row 122 are connected to the terminals of the second wiring pattern 65 and are output terminals for outputting signals to the second electrode 63.

Here, in the semiconductor element mounting structure 100 shown in FIG. 4, one side 91 a of the semiconductor element 91 on which the first bump electrode array 121 is arranged is displayed on the liquid crystal display when mounted on the second substrate 60. This is a side 91a arranged toward the side opposite to the side where the image display area A exists in the apparatus 20.
As shown in FIGS. 6A to 6B, the first bump electrode row 121 is arranged along one side 91a of the semiconductor element 91, whereas the second bump electrode row 122 is formed. It is preferable that the semiconductor element 91 is disposed between the side 91 b facing the one side 91 a and the first bump electrode row 121 so as to approach the first bump electrode row 121.
This is because the second bump electrode row 122 is brought closer to the side 91a side of the semiconductor element 91 in which the first bump electrode row 121 is present, so that the terminals in the corresponding first wiring pattern 67 and the second This is because the distance (R) from the terminal in the wiring pattern 65 can be reduced. As a result, as described above, the area of the substrate overhanging portion 61T in the second glass substrate 61 is reduced to reduce the size of the electro-optical device, or the area of the substrate overhanging portion 61T is not changed. The degree of freedom of routing of the first wiring pattern 67 can be increased to prevent occurrence of a short circuit or to reduce electric resistance.

Further, the arrangement position of the second bump electrode row 122 is substantially linearly separated from the side 91b facing the one side 91a of the semiconductor element 91 in which the first bump electrode row 121 is arranged by a predetermined distance. If it is arranged, there is no particular limitation. That is, if the bump electrode array 122 is linear, the design restrictions of the semiconductor element 91 can be relatively relaxed.
Therefore, for example, an arrangement as shown in FIGS. Among them, as shown in FIG. 7C, the second bump electrode row 122 is arranged closer to the side 91a than the side 91b facing the side 91a where the first bump electrode row 121 is arranged. Preferably it is. This is because the electro-optical device can be downsized and the routing area of the second wiring pattern 65 can be more reliably achieved, and the semiconductor element 91 can be connected to the flexible substrate 93 or the like in the substrate overhanging portion 61T. This is because the area is not affected.

  More specifically, as shown in FIG. 7A, the second bump electrode row 122 is arranged closer to the side 91b opposite to the side 91a where the first bump electrode row 121 is arranged. In this case, the distance (R) between the first bump electrode row 121 and the second bump electrode row 122 is preferably set to a value in the range of 500 to 2,000 μm, for example. On the other hand, as shown in FIG. 7C, when the second bump electrode row 122 is arranged closer to the side 91a side where the first bump electrode row 121 is arranged than the opposite side 91b. The distance (R) between the first bump electrode row 121 and the second bump electrode row 122 is preferably set to a value in the range of 50 to 400 μm, for example.

The bump electrode group is preferably a metal bump or a plated bump obtained by performing metal plating on a polymer material.
This is because when the bump electrode is a metal bump, electrical connection between the semiconductor element and the wiring pattern can be ensured.
On the other hand, in the case of a plated bump obtained by metal plating on a polymer material, an aluminum pad required in the case of a metal bump is not necessary, and a bump electrode having a relatively small diameter can be formed. It is. Therefore, it is possible to increase the degree of freedom of arrangement of the bump electrodes and to easily cope with the narrowing of the wiring pattern. In addition, the semiconductor element can be downsized. Furthermore, since mounting can be performed without using conductive particles such as those used in anisotropic conductive films, it is possible to provide flexibility in wiring layout and bump electrode pitch.

(2) -3 Dummy Bump As shown in FIGS. 8A to 8B, a conductive material is provided between the second bump electrode row 122 and the side 91 b facing the one side 91 a of the semiconductor element 91. A dummy bump made of and / or a dummy bump made of an electrically insulating material, or one of the dummy bumps 125 is provided.
In other words, the semiconductor element 91 used in the semiconductor element mounting structure of the present invention is arranged so that the first bump electrode row 121 and the second bump electrode row 122 are arranged so as to be biased toward the predetermined side 91a. This is because if it is mounted as it is, it is not well balanced and cannot be mounted. Therefore, by providing such dummy bumps 125 at predetermined positions, it is possible to improve the balance during mounting and to improve the stability during connection.
8A is a plan view of the semiconductor element 91 provided with the dummy bumps 125 as viewed from the mounting surface side, and FIG. 8B is a cross-sectional view of the XX section of FIG. is there.

  The number of the dummy bumps 125 is not particularly limited. For example, as shown in FIGS. 8A to 8B, the first bump electrode row 121 in the semiconductor element 91 is arranged. One is preferably formed at each corner on the side 91b opposite to the side 91a. This is because the mounting state of the semiconductor element 91 can be stabilized and, as will be described later, when the dummy bump 125 made of a conductive material is formed, the second wiring pattern 65 is formed around the second wiring pattern 65. This is because it becomes relatively easy.

When the dummy bump 125 is made of a conductive material, the second wiring pattern 65 is preferably formed so as to bypass the dummy bump 125 as shown in FIG. The reason for this is that although depending on the pitch interval of the second wiring pattern 65, a short may occur between the adjacent second wiring patterns 65 due to dummy bumps.
On the other hand, when the dummy bump is made of an electrically insulating material (polymer material), as shown in FIG. 9B, the second wiring pattern 65 is also formed at a position overlapping the dummy bump 125 ′ in a plane. It is preferable. This is because the dummy bump 125 ′ made of an electrically insulating material does not cause a short circuit as described above. Therefore, the position of the dummy bump 125 ′ needs to be taken into account when forming the second wiring pattern 65. Because there is no. In such a configuration, the minimum necessary routing area can be reduced as compared with the case where the dummy bumps 125 are formed to be detoured. Therefore, the external dimensions of the second substrate 60 are reduced. , Can be smaller.

3. Application Example FIG. 10 is a schematic configuration diagram illustrating an overall configuration of an electronic apparatus including the electron optical device according to the present embodiment. This electronic apparatus has a liquid crystal panel 20 ′ constituting a part of the liquid crystal display device 20 and a control means 200 for controlling the liquid crystal panel 20 ′. In FIG. 10, the liquid crystal panel 20 ′ is conceptually divided into a panel structure 20A and a drive circuit 20B composed of a semiconductor element (semiconductor element) or the like. The control means 200 preferably includes a display information output source 201, a display processing circuit 202, a power supply circuit 203, and a timing generator 204.
The display information output source 201 includes a memory composed of a ROM (Read Only Memory), a RAM (Random Access Memory), etc., a storage unit composed of a magnetic recording disk, an optical recording disk, etc., and a tuning that outputs a digital image signal in a synchronized manner. It is preferable that the display information is supplied to the display information processing circuit 202 in the form of an image signal or the like in a predetermined format based on various clock signals generated by the timing generator 204.

The display information processing circuit 202 includes various known circuits such as a serial-parallel conversion circuit, an amplification / inversion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and executes processing of input display information. It is preferable to supply the image information to the drive circuit 20B together with the clock signal CLK. Furthermore, the drive circuit 20B preferably includes a first electrode drive circuit, a second electrode drive circuit, and an inspection circuit. Further, the power supply circuit 203 has a function of supplying a predetermined voltage to each of the above-described components.
And if it is an electronic device provided with the electro-optical device of this embodiment, the 1st bump electrode row | line | column in a semiconductor element and the 2nd bump electrode row | line | column are made to adjoin, and the area of a board | substrate overhang | projection part is reduced. An electronic device that can be reduced in size and reduced in size as a whole, or the area of the substrate overhang can be kept the same, increasing the degree of freedom of wiring pattern routing, reducing the occurrence of short circuits, and reducing electrical resistance It can be a device.

  According to the present invention, by forming a mounting structure using a specific semiconductor element, it is possible to reduce the external dimension of the substrate and to reduce the size of the electro-optical device as a whole. Further, the pitch interval of the wiring pattern can be widened to prevent occurrence of a short circuit, or the width of the wiring itself can be widened to reduce the electrical resistance. Therefore, electro-optical devices and electronic devices using liquid crystal molecules as electro-optical materials, such as mobile phones and personal computers, liquid crystal televisions, viewfinder type / direct monitor type video tape recorders, car navigation devices, pagers, etc. , Electrophoresis devices, electronic notebooks, calculators, word processors, workstations, video phones, POS terminals, electronic devices with touch panels, and devices using electron-emitting devices (FED: Field Emission Display and SCEED: Surface-Conduction Electron- Emitter Display), plasma display devices, organic and inorganic electroluminescence devices, and the like.

It is a schematic perspective view which shows the external appearance of the liquid crystal display device which concerns on this invention. It is a schematic sectional drawing which shows typically the liquid crystal display device which concerns on this invention. (A) is a top view of a 1st board | substrate, (b) is a top view of a 2nd board | substrate, (c) is in the state which piled up the 1st board | substrate and the 2nd board | substrate. It is a top view. It is a top view which shows the mounting structure of the semiconductor device which concerns on this invention. (A)-(d) is a figure provided in order to demonstrate the modification of the mounting structure of a semiconductor element, respectively. (A)-(b) is the top view and sectional drawing which respectively show the semiconductor element used for the mounting structure of the semiconductor element which concerns on this invention. (A)-(c) is a figure provided in order to demonstrate arrangement | positioning of the 1st bump electrode row | line | column and 2nd bump electrode row | line | column in a semiconductor element, respectively. (A)-(b) is the top view and sectional drawing which show the semiconductor element provided with the dummy bump, respectively. It is a figure provided in order to demonstrate the formation method of the 2nd wiring pattern. It is a block diagram which shows schematic structure of the electronic device as an application example. It is a figure provided in order to demonstrate the mounting structure of the conventional semiconductor element.

Explanation of symbols

20: electro-optical device (liquid crystal display device), 23: sealing material, 30: first substrate, 60: second substrate, 41: planarization film, 65, 65a, 65b: first wiring pattern, 91: Semiconductor element (X driver), 92: mounting surface, 94: semiconductor element (Y driver), 100: mounting structure, 120: bump electrode group, 121: first bump electrode array, 122: second bump electrode array, 125: Dummy bump

Claims (5)

A semiconductor element mounting structure in which a semiconductor element having a bump electrode group for face-down bonding to a substrate and a wiring pattern on the substrate are electrically connected,
The bump electrode group is arranged in a plane substantially linearly at a predetermined distance from a first bump electrode array arranged along one side of the semiconductor element and a side facing the one side of the semiconductor element. A second bump electrode array,
The wiring pattern includes a first wiring pattern corresponding to the first bump electrode array, and a second wiring pattern corresponding to the second bump electrode array; and
When the substrate is viewed in the vertical direction, the first wiring pattern is formed so as to intersect with one side of the semiconductor element, and the second wiring pattern is formed on one side of the semiconductor element. A mounting structure of a semiconductor element, wherein the semiconductor element mounting structure is drawn out so as to intersect with a plurality of other sides.   The semiconductor element includes a dummy bump made of a conductive material and a dummy bump made of an electrically insulating material, or one of the dummy bumps, between a side opposite to one side of the semiconductor element and the second bump electrode array. The semiconductor element mounting structure according to claim 1, further comprising:   3. The semiconductor element mounting structure according to claim 1, wherein the bump electrode group is a metal bump or a plated bump obtained by performing metal plating on a polymer material.   When the dummy bump is made of a conductive material when the substrate is viewed in the vertical direction, the second wiring pattern is formed so as to bypass the dummy bump, and the dummy bump is made of an electrically insulating material. 4. The semiconductor element mounting structure according to claim 2, wherein the second wiring pattern is also formed at a position overlapping the dummy bump in a planar manner. An electro-optical device including a semiconductor element mounting structure in which a semiconductor element including a bump electrode group for face-down bonding to a substrate and a wiring pattern on the substrate are electrically connected,
The bump electrode group of the semiconductor element is substantially linearly separated from the first bump electrode row arranged along one side of the semiconductor element by a predetermined distance from the side facing the one side of the semiconductor element. A second bump electrode array disposed in-plane,
The wiring pattern includes a first wiring pattern corresponding to the first bump electrode array, and a second wiring pattern corresponding to the second bump electrode array; and
When the substrate is viewed in the vertical direction, the first wiring pattern is formed so as to intersect with one side of the semiconductor element, and the second wiring pattern is formed on one side of the semiconductor element. An electro-optical device characterized by being drawn out so as to intersect with a plurality of other sides.

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