JP2006017897A - Electro-optical apparatus and electronic appliance - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electro-optical apparatus in which a high-quality display image can be obtained while longitudinal and lateral crosstalk can be decreased. <P>SOLUTION: A device substrate includes pixel electrodes, TFD (thin film diode) elements, data lines and dummy data lines, wherein the dummy data line is disposed between the pixel electrode and an adjacent data line not connected to the pixel electrode. The pixel electrode and the adjacent data line not connected to the pixel electrode are shielded from each other by the dummy data line and no parasitic capacitance is generated between them, which prevents fluctuation in the voltage Vlc of the pixel electrode, maintains the transmissivity of a liquid crystal to an appropriate state, and prevents longitudinal crosstalk. As the dummy data line is driven at a potential in an opposite polarity by inverting the potential of the data line, a parasitic capacitance C_b' generated between the dummy data line and the scanning line is compensated with a parasitic capacitance C_b generated between the data line and scanning line. The parasitic capacitance C_b, a spike waveform and lateral crosstalk are decreased. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electro-optical device and an electronic apparatus suitable for use in displaying various types of information.

  Conventionally, various electro-optical devices such as a liquid crystal display device, an organic electroluminescence display device, a plasma display device, and a field emission display device are known. In a liquid crystal panel called a two-terminal element type active matrix or TFD (Thin Film Diode) as an example of an electro-optical device, one of two substrates facing each other has a scanning line on one substrate and the other substrate on the other substrate. A signal line (data line) and a pixel electrode are formed on the substrate, and liquid crystal is sealed between the substrates. The other substrate is provided with an element having a nonlinear current-voltage characteristic, and the element is connected to the pixel electrode and the signal line, respectively.

  However, in such a TFD liquid crystal panel, when the level of pixels included in one line is concentrated on a specific gradation during the display of one line (scanning line) on the display screen, the signal electrode lines are all at once. The potential of changes. This potential change propagates to each pixel through the scanning line, and causes horizontal crosstalk (hereinafter referred to as “lateral crosstalk”). Here, as described above, horizontal crosstalk means that on the display image, although the same gradation is displayed in the line where the pixel level is concentrated on a specific gradation and the line where the pixel level is not, This means that the display level is different.

  Further, in such a TFD liquid crystal panel, since the interval between the pixel electrode and each signal line on both sides thereof is narrow, in particular, the parasitic capacitance generated between the pixel electrode and the adjacent signal line not connected thereto. As a result, vertical crosstalk (hereinafter referred to as “vertical crosstalk”) is generated. Here, vertical crosstalk is a color such as cyan, magenta, yellow, etc., which is a single color such as red, blue, or green, or a complementary color relationship with each color of red, blue, and green, with gray as the background color. Is displayed in a rectangular shape, the region positioned in the vertical direction of the rectangular display region is displayed brighter than the background color that should be displayed, and is displayed in a slightly colored manner.

  For this reason, such a TFD liquid crystal panel has a problem that a high-quality display image cannot be obtained when vertical crosstalk or horizontal crosstalk occurs.

  As this type of liquid crystal display device, for example, a dummy display unit is provided in addition to the main display unit, and reverse image data is displayed on the main display unit and the dummy display unit, thereby scanning the scanning lines of the dummy display unit. There is known a liquid crystal display device that reduces the occurrence of glitches generated in a linear waveform to reduce the crosstalk phenomenon and the like (see, for example, Patent Document 1).

  In addition, by adjusting the size of the auxiliary capacitance line provided in parallel to the gate line, an auxiliary capacitance voltage having a different waveform is applied so as to eliminate the contribution of parasitic capacitance to the fluctuation of the pixel potential for each auxiliary capacitance line. Therefore, a liquid crystal display device that suppresses vertical crosstalk and the like is known (see, for example, Patent Document 2).

  Further, as a driving method for this type of liquid crystal display device, for example, a driving method for a liquid crystal display device that performs lateral crosstalk correction by providing a detection terminal for detecting only a ripple component in the counter electrode waveform on the counter electrode. Is known (see, for example, Patent Document 3).

  In addition, a display device driving method that prevents the occurrence of crosstalk by a quaternary driving method (1 / 2H inversion) is known (see, for example, Patent Document 4).

Japanese Patent Laid-Open No. 6-195044 JP 2002-55656 A JP 2000-56292 A JP 2001-147671 A

  SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical device and an electronic apparatus capable of reducing vertical and horizontal crosstalk and obtaining a high-quality display image. .

  In one aspect of the present invention, an electro-optical material is interposed between a data line, a pixel electrode, a switching element connected to the data line and the pixel electrode, a substrate having a signal line, and a counter substrate having a scanning line. In the encapsulated electro-optical device, the signal line is formed between the pixel electrode and the adjacent data line not connected to the pixel electrode, and the signal line is the data line. And a driving circuit which is driven with a potential having a polarity opposite to the reference potential. In a preferred example, the pixel electrode can be formed between the data line and the signal line connected to the pixel electrode in the pixel region.

  The electro-optical device includes a data line, a pixel electrode, a switching element such as a two-terminal element connected in series to the data line, and a substrate having a signal line (referred to as a “dummy data line” in an embodiment described later); An electro-optical material is sealed between a counter substrate having scanning lines. In this electro-optical device, the signal line is formed between the pixel electrode and the adjacent data line not connected thereto. Alternatively, the pixel electrode is formed between the data line and the signal line connected to the pixel electrode in the pixel region.

  Thereby, the parasitic capacitance generated between the signal line and the scanning line and the parasitic capacitance generated between the data line and the scanning line can be offset. Therefore, it is possible to reduce the capacitance component C of the time constant RC that causes the spike waveform. As a result, the spike waveform can be reduced and lateral crosstalk can be reduced. As a result, a high-quality display image can be obtained.

  In one aspect of the electro-optical device, an interval between the pixel electrode and the data line connected to the pixel electrode is the same as an interval between the pixel electrode and the signal line adjacent to the pixel electrode. In the pixel region, the overlapping area of the data line and the scanning line is the same as the overlapping area of the signal line and the scanning line.

  According to this aspect, the interval between the pixel electrode and the data line connected to the pixel electrode is the same as the interval between the pixel electrode and the signal line adjacent to the pixel electrode. Accordingly, the parasitic capacitance generated between the pixel electrode and the signal line adjacent thereto is the same as the parasitic capacitance generated between the pixel electrode and the data line connected thereto. For this reason, the parasitic capacitances can be canceled by driving the signal lines with a potential having a polarity opposite to the potential of the data lines through the drive circuit.

  In the pixel region, the area where the data line and the scanning line overlap is the same as the area where the signal line and the scanning line overlap. Therefore, the parasitic capacitance generated between the signal line and the scanning line is the same as the parasitic capacitance generated between the data line and the scanning line. For this reason, the parasitic capacitances can be canceled by driving the signal lines with a potential having a polarity opposite to the potential of the data lines through the drive circuit. Therefore, lateral crosstalk can be reduced.

  In another aspect of the electro-optical device, a combined capacitance between the signal line and the scanning line is the same as a combined capacitance between the data line and the scanning line.

  According to this aspect, by adding a capacitance component C such as a pixel capacitance of the pixel electrode, an element capacitance of the switching element, and / or a parasitic capacitance to the signal line, among the time constant RC, the signal line and the scanning line And the combined capacitance C between the data line and the scanning line can be made the same. Thereby, the time constant RC between the scanning line and the data line can be matched with the time constant RC between the scanning line and the signal line. Note that the data line and the signal line are formed in the same direction, at substantially the same position, and with substantially the same length by the above-described configuration, so that their resistance values are substantially the same. Therefore, of the time constant RC, the resistance components R of the data line and the signal line already match. For this reason, a spike waveform (waveform rounding) generated in the potential of the scanning line due to the data line in the line selection period by driving the signal line with a potential having a polarity opposite to the potential of the data line through the driving circuit. And the spike waveform (waveform rounding) generated in the potential of the scanning line due to the signal line can be made the same size, and these spike waveforms can be almost completely canceled. Thereby, lateral crosstalk can be reduced.

  In another aspect of the electro-optical device, an area where the signal line and the scanning line overlap in the pixel region is larger than an area where the data line and the scanning line overlap.

  According to this aspect, the capacitance component is added to the signal line, for example, in the pixel region, the area where the signal line and the scanning line overlap is formed larger than the area where the data line and the scanning line overlap. By increasing the parasitic capacitance generated between the line and the scanning line, the combined capacitance between the signal line and the scanning line can be made the same as the combined capacitance between the data line and the scanning line. Therefore, lateral crosstalk can be reduced by driving the signal line through the driving circuit with a potential having a polarity opposite to the potential of the data line.

  In another aspect of the present invention, an electro-optic material is interposed between a data line, a pixel electrode, a switching element connected to the data line and the pixel electrode, a substrate having a shield line, and a counter substrate having a scanning line. In the encapsulated electro-optical device, the shield line is formed between the pixel electrode and the adjacent data line that is not connected to the pixel electrode.

  The electro-optical device includes a data line, a pixel electrode, a switching element such as a two-terminal element connected in series thereto, and a substrate having a shield line (referred to as a “dummy data line” in an embodiment described later); An electro-optical material is sealed between a counter substrate having scanning lines.

  Thereby, the pixel electrode and the adjacent data line not connected to the pixel electrode are shielded (shielded) by the shield line. Therefore, the influence of adjacent data lines can be prevented by this shield line, and no parasitic capacitance is generated between them, so that fluctuations in the voltage of the pixel electrode can be prevented. Thereby, the fluctuation | variation of the effective value applied to an electro-optical layer (for example, liquid crystal layer) can be prevented. Therefore, the transmittance of the electro-optic layer can be maintained in an appropriate state, and the occurrence of vertical crosstalk can be prevented. As a result, contrast can be improved and a high-quality display image can be obtained.

  In addition, an electronic device including the above-described liquid crystal display device can be configured.

  The best mode for carrying out the present invention will be described below with reference to the drawings. In the following embodiments, the present invention is applied to a liquid crystal display device as an example of an electro-optical device. In this embodiment, a dummy data line is provided between a pixel electrode and an adjacent data line not connected to the pixel electrode, and the dummy data line is driven with a potential having a reverse polarity obtained by inverting the potential of the data line. Thereby, vertical and horizontal crosstalk is reduced, and a high-quality display image is obtained.

[First embodiment]
(Configuration of the liquid crystal display device 100)
First, the configuration of the liquid crystal display device according to the first embodiment of the present invention will be described. FIG. 1 is a plan view schematically showing a schematic configuration of a liquid crystal display device 100 of the present invention. In FIG. 1, the configuration of electrodes and wirings of the liquid crystal display device 100 is mainly shown as a plan view. Here, the liquid crystal display device 100 of the present invention is an active matrix driving method using a TFD element, and is a transflective liquid crystal display device. FIG. 2 is a schematic cross-sectional view along the cutting line AA ′ in the liquid crystal display device 100 of FIG.

  First, the cross-sectional configuration of the liquid crystal display device 100 taken along the cutting line A-A ′ will be described with reference to FIG.

  In FIG. 2, the liquid crystal display device 100 includes an element substrate 92 and a color filter substrate 91 disposed so as to face the element substrate 92 with a frame-shaped seal member 3 interposed therebetween, and liquid crystal is sealed inside. Thus, the liquid crystal layer 4 is formed. A conductive member 7 such as a plurality of gold particles is mixed in the frame-shaped seal member 3.

  On the inner surface of the lower substrate 2, a scattering layer 9 having fine irregularities formed on the surface is formed. On the inner surface of the scattering layer 6, a reflective layer 5 having a predetermined thickness is formed for each subpixel SG. Each reflective layer 5 has a rectangular opening 20 (hereinafter also referred to as “transparent region”). Each reflective layer 5 can be formed of a thin film such as aluminum, an aluminum alloy, or a silver alloy. The opening 20 is formed so as to have an area of a predetermined ratio with respect to the total area of the sub-pixel SG for each sub-pixel SG arranged in a matrix in the vertical and horizontal directions on the inner surface of the color filter substrate 91.

  On the reflective layer 5 and between the sub-pixels SG, a black light-shielding layer BM is provided between the adjacent sub-pixels SG to prevent light from entering from one sub-pixel to the other sub-pixel. Is formed. The black light shielding layer BM can be made of a black resin material, for example, a black pigment dispersed in a resin. In the present invention, instead of this, an overlapping light shielding layer (not shown) formed by overlapping R, G, and B colored layers may be used.

  On the reflective layer 5 and the opening 20, colored layers 6R, 6G, and 6B made of any of the three colors R, G, and B are formed for each subpixel SG. A color filter is constituted by the colored layers 6R, 6G, and 6B. A pixel G indicates a region for one color pixel composed of R, G, and B sub-pixels SG. In the following description, when referring to a colored layer regardless of color, it is simply referred to as “colored layer 6”, and when referring to a colored layer by distinguishing colors, it is referred to as “colored layer 6R” or the like. Further, as shown in FIG. 2, the thickness of the colored layer 6 formed on the opening 20 is formed to be thicker than the thickness of the colored layer 6 formed on the reflective layer 5. Thus, the colored layer 6 is designed to exhibit a desired hue and brightness in the reflective display mode and the transmissive display mode, respectively.

  A protective layer 18 made of a transparent resin or the like is formed on the colored layer 6 and the black light shielding layer BM. The protective layer 18 has a function of protecting the colored layer 6 from corrosion and contamination caused by chemicals used during the manufacturing process of the color filter substrate 91 and the liquid crystal display device 100. On the surface of the protective layer 18, a transparent electrode (scanning electrode) 8 such as striped ITO (Indium-Tin Oxide) is formed. One end of the transparent electrode 8 extends into the seal member 3 and is electrically connected to the conducting member 7 in the seal member 3.

  On the other hand, the TFD element 21 and the pixel electrode 10 are formed on the inner surface of the upper substrate 1 for each subpixel. A data line 32 and a dummy data line 80 are formed on the inner surface of the upper substrate 1 and between adjacent pixel electrodes 10. The data line 32 and the dummy data line 80 extend in a direction substantially orthogonal to the extending direction of the scan electrode 8. The data line 32 and the dummy data line 80 are located above the black light shielding layer BM formed on the color filter substrate 91.

  A protective layer 17 made of transparent resin or the like is formed on the inner surfaces of the TFD element 21 and the pixel electrode 10. Scan lines 31 are formed on the left and right peripheral edge portions on the inner surfaces of the upper substrate 1 and the protective layer 17. One end of the scanning line 31 extends into the seal member 3, and the scanning line 31 is electrically connected to the conduction member 7 in the seal member 3.

  An alignment film (not shown) is formed on the inner surface of the transparent electrode 8 of the lower substrate 2 and the inner surface of the protective layer 17 of the upper substrate 1. In order to keep the thickness of the liquid crystal layer 4 uniform between these alignment films, particulate spacers (not shown) are randomly arranged. As a material for the spacer, a material mainly composed of silica or resin is preferable.

  A retardation plate (¼ wavelength plate) 11 and a polarizing plate 12 are arranged on the outer surface of the lower substrate 2, and a retardation plate (¼ wavelength plate) on the outer surface of the upper substrate 1. 13 and a polarizing plate 14 are arranged. A backlight 15 is disposed below the polarizing plate 12. The backlight 15 is preferably a point light source such as an LED (Light Emitting Diode) or a linear light source such as a cold cathode fluorescent tube.

  The transparent electrode 8 of the lower substrate 2, that is, the scanning line of the lower substrate 2, and the scanning line 31 of the upper substrate 1 are vertically connected via the conductive member 7 mixed in the seal member 3.

  Now, when reflective display is performed in the liquid crystal display device 100 of the present embodiment, the external light incident on the liquid crystal display device 100 travels along the path R shown in FIG. That is, the external light incident on the liquid crystal display device 100 is reflected by the reflective layer 5 and reaches the observer. In this case, the external light passes through the region where the colored layer 6 is formed, is reflected by the reflective layer 5 below the colored layer 6, and passes through the colored layer 6 again to have a predetermined hue. And brightness. Thus, a desired color display image is visually recognized by the observer.

  On the other hand, when transmissive display is performed, the illumination light emitted from the backlight 15 travels along the path T shown in FIG. 2 and passes through the transmissive region, that is, the colored layer 6 on the opening 20 for observation. To the person. In this case, the illumination light has a predetermined hue and brightness by passing through the colored layer 6. Thus, a desired color display image is visually recognized by the observer.

  Next, with reference to FIG. 1, FIG. 3, and FIG. 4, the configuration of the electrodes and wirings of the element substrate 92 and the color filter substrate 91 of the present invention will be described. FIG. 3 is a plan view showing a configuration of electrodes, wirings, and the like of the element substrate 92 when the element substrate 92 is observed from the front direction (that is, the lower side in FIG. 2). FIG. 4 is a plan view showing the configuration of the electrodes of the color filter substrate 91 when the color filter substrate 91 is observed from the front direction (that is, the upper side in FIG. 2). In FIG. 3, the electrodes and wirings are formed on the back side in the observation direction, but are represented by solid lines for convenience of explanation. 3 and 4, other elements other than the electrodes and wiring are not shown for convenience of explanation. In FIG. 1 and FIG. 3, the data line 32 and the dummy data line 80 are formed on the upper substrate 1, but for the sake of convenience, the data line 32 is shown as a solid line to distinguish them, while the dummy data line 80 is shown. Is indicated by a broken line.

  In FIG. 1, a region where the pixel electrode 10 of the element substrate 92 and the transparent electrode 8 of the color filter substrate 91 intersect constitute a sub-pixel SG which is the minimum unit of display. An area in which a plurality of subpixels SG are arranged in a matrix in the vertical direction and the horizontal direction of the drawing is an effective display area V (area surrounded by a two-dot chain line). In the effective display area V, images such as letters, numbers, and figures are displayed. 1 and 3, a region defined by the outer periphery of the liquid crystal display device 100 and the effective display region V is a frame region 38 that does not contribute to image display.

(Electrode and wiring configuration)
First, with reference to FIG. 3, the structure of the electrode and wiring of the element substrate 92 will be described. The element substrate 92 includes a TFD element 21, a pixel electrode 10, a plurality of scanning lines 31, a plurality of data lines 32, a plurality of dummy data lines 80, a Y driver IC 33, an X driver IC 110, and a plurality of external connection terminals 35. ing.

  On the projecting region 36 of the element substrate 92, a Y driver IC 33 and an X driver IC 110 are mounted, for example, via an ACF (Anisotropic Conductive Film). In FIG. 3, the direction from the side 92a on the projecting region 36 side of the element substrate 92 to the side 92c on the opposite side is defined as the X direction, and the direction from the side 92d to the side 92b is defined as the Y direction.

  A plurality of external connection terminals 35 are formed on the overhang region 36. Each input terminal (not shown) of the Y driver IC 33 and the X driver IC 110 is connected to the plurality of external connection terminals 35 through conductive bumps. The external connection terminal 35 is connected to a wiring board (not shown) such as a flexible printed board via ACF or solder. Thereby, for example, signals and power are supplied to the liquid crystal display device 100 from an electronic device such as a mobile phone or an information terminal.

  An output terminal (not shown) of the X driver IC 110 is connected to the plurality of data lines 32 and the plurality of dummy data lines 80 through conductive bumps. On the other hand, the output terminal (not shown) of each Y driver IC 33 is connected to the plurality of scanning lines 31 via conductive bumps. Accordingly, each Y driver IC 33 outputs a scanning signal to the plurality of scanning lines 31, and the X driver IC 110 outputs a data signal to the plurality of data lines 32 and the plurality of dummy data lines 80, respectively.

  The plurality of data lines 32 are linear wirings extending in the vertical direction on the paper surface, and are formed in the X direction from the overhang area 36 to the effective display area V. Each data line 32 is formed at a constant interval. Each data line 32 is connected to a plurality of TFD elements 21 at appropriate intervals, and each TFD element 21 is connected to a corresponding pixel electrode 10.

  The plurality of dummy data lines 80 are linear wirings extending in the vertical direction of the paper as in the case of the data lines 32, and are formed in the X direction from the extended area 36 to the effective display area V. Each dummy data line 80 is formed between the pixel electrodes 10 that form a column in the vertical direction of the paper and the adjacent data line 32 that is not connected thereto. Unlike the data line 32, each dummy data line 80 is not connected to the TFD element 21 or the pixel electrode 10. Detailed functions of the dummy data line 80 will be described later.

  The plurality of scanning lines 31 includes a main line portion 31a and a bent portion 31b that bends at substantially right angles to the main line portion 31a. Each main line portion 31 a is formed in the X direction from the overhanging region 36 in the frame region 38. Each main line portion 31a is formed substantially parallel to each data line 32 and at a predetermined interval. Each bent portion 31b extends in the Y direction to the inside of the seal member 3 located on the left and right in the frame region 38. The end portion of the bent portion 31 b is connected to the conductive member 7 in the seal member 3.

  Next, the configuration of the electrodes of the color filter substrate 91 will be described. As shown in FIG. 4, the color filter substrate 91 has stripe-shaped transparent electrodes (scanning electrodes) 8 formed in the Y direction. As shown in FIGS. 1 and 4, the left end portion or the right end portion of each transparent electrode 8 extends into the seal member 3 and is connected to the conduction member 7 in the seal member 3.

  FIG. 1 shows a state where the color filter substrate 91 and the element substrate 92 are bonded together via the seal member 3 as described above. As shown in the figure, each transparent electrode 8 of the color filter substrate 91 is orthogonal to each data line 32 of the element substrate 92 and overlaps the plurality of pixel electrodes 10 in a row in a plane. Thus, the region where the transparent electrode 8 and the pixel electrode 10 overlap constitutes the sub-pixel SG.

  Further, the transparent electrode 8 (that is, the scanning line on the color filter substrate 91 side) of the color filter substrate 91 and the scanning line 31 of the element substrate 92 alternately overlap between the left side and the right side as shown in the figure. The transparent electrode 8 and the scanning line 31 are vertically connected via the conductive member 7 in the seal member 3. That is, conduction between each scanning line of the color filter substrate 91 as the transparent electrode 8 and each scanning line 31 of the element substrate 92 is alternately realized between the left side and the right side as shown in the figure. Thereby, the transparent electrode 8 of the color filter substrate 91 is electrically connected to the Y driver ICs 33 located on the left and right sides of the paper via the scanning lines 31 of the element substrate 92.

(Drive circuit)
Next, a driving circuit of the liquid crystal display device 100 will be described. FIG. 5 schematically shows the configuration of the drive circuit of the liquid crystal display device 100. 5, the drive circuit of the liquid crystal display device 100 includes a scanning signal drive circuit 33a, a data signal drive circuit 110a, a timing signal generation circuit 51, and a conversion circuit 52. The timing signal generation circuit 51 outputs various timing signals for driving the illustrated components. These circuits are built in the X driver IC 110 and the Y driver IC 33.

  As described above, the liquid crystal display device 100 includes a plurality of scanning lines 31 extending in the row direction and a plurality of corresponding scanning electrodes 8 and a plurality of data lines extending in the column direction. 32 and a plurality of dummy data lines 80 are provided. Hereinafter, for convenience of explanation, one scanning line 31 and one corresponding scanning electrode 8 are referred to as “scanning line 85”. At each intersection of the scanning line 85 and the data line 32, the TFD element 21 and the liquid crystal layer 4 are connected in series, whereby a pixel is formed at each intersection.

  The scanning signal driving circuit 33 a applies a scanning potential VA to the scanning line 85, and the data signal driving circuit 110 a applies a signal potential VB to the data line 32. The potentials VA and VB will be described with reference to FIG. First, a scanning potential VA as shown in FIG. 6A is applied to the scanning line 85. In each line selection period T, each scanning line 85 is sequentially selected, and a potential difference of ± Vsel with respect to a certain common potential VGND, that is, any potential having a voltage is applied. This voltage Vsel is called a selection voltage. Then, after the line selection period, any potential having a voltage of ± Vhld with respect to the common potential VGND is applied. Here, when the potential at the time of selection is VGND + Vsel, the potential of VGND + Vhld is applied, and when the potential at the time of selection is VGND−Vsel, the potential of VGND−Vhld is applied. This voltage Vhld is called a holding voltage. A period in which all the scanning lines 85 are selected in a round is called a field period. In the next field period, the scanning lines 85 are sequentially selected using a selection voltage having a characteristic opposite to that of the previous field period. Go.

  On the other hand, as shown in FIG. 6B, any potential having a voltage of ± Vsig with respect to the common potential VGND is applied to the data line 32. On the other hand, a potential having a reverse polarity obtained by inverting the potential applied to the data line 32 is applied to the dummy data line 80, but the illustration is omitted here for convenience. Here, when the potential applied to the scanning line 85 selected in a certain selection period is VGND + Vsel, VGND−Vsig is used as the on potential Von and VGND + Vsig is used as the off potential Voff. Further, when the potential applied to the scanning line 85 selected in a certain selection period is VGND−Vsel, VGND + Vsig is used as the on potential Von, and VGND−Vsig is used as the off potential Voff.

  That is, the waveform of the signal potential VB in each line selection period T is set according to the gradation of each pixel in the column related to the data line 32. First, the signal potential VB is set for each line selection period T. Are divided into an ON section and an OFF section, and are set to the ON potential Von in the ON section and to the OFF potential Voff in the OFF section. That is, the signal potential VB is pulse width modulated according to the gradation value. Then, the higher the gradation to be given to the pixel (the darker the normally white mode), the larger the proportion occupied by the ON section.

  Next, the interelectrode voltage VAB of the scanning line 85 and the data line 32 is indicated by a solid line in FIG. As shown in the figure, it can be seen that the absolute value of the interelectrode voltage VAB increases during the selection period of the pixel. Further, the liquid crystal layer voltage VLC applied to the liquid crystal layer 4 is indicated by hatching in FIG. When the liquid crystal layer voltage VLC changes, the capacitance formed by the liquid crystal layer 4 must be charged and discharged, so the liquid crystal layer voltage VLC changes in a transient response to the interelectrode voltage VAB. In FIG. 6C, the voltage VNL is the difference between the interelectrode voltage VAB and the liquid crystal layer voltage VLC, that is, the terminal voltage of the nonlinear two-terminal element 21.

  An example of the signal potential VB in the present embodiment is shown in FIG. In FIG. 7A, the line selection period T includes an on section and an off section. Since the scanning potential VA is as shown in FIG. 6A, the interelectrode voltage VAB and the liquid crystal layer voltage VLC are as shown in FIG. 7B.

  The conversion circuit 52 converts the color image signals R, G, and B input from the outside into data signals DR, DG, and DB. Specifically, when the color image signals R, G, and B are supplied, the conversion circuit 52 stores the color image signals R, G, and B in a line buffer (not shown) and converts the color image signals R, G, and B into the data signals DR, The data is converted into DG and DB and supplied to the data signal driving circuit 110a. Here, the gradation values of the respective colors of the color image signals R, G, and B are values in the range of “0” to “15”, and these are the gradation values within the line selection period T according to the table of FIG. Is converted to

  The conversion circuit 52 supplies a clock signal GCP (Gray Control Pulse) to the data signal driving circuit 110a. A method for generating the clock signal GCP will be described. In the conversion circuit 52, a basic clock signal that divides each line selection period T by “256” is generated. Next, this basic clock signal is counted by an 8-bit (maximum 255) counter, and when the count result reaches a predetermined value, one pulse of the clock signal GCP is output. This “predetermined value” corresponds to the gradation values (0, 13, 26,... 255) shown in FIG. Note that the counter value at which one pulse of the clock signal GCP is output is set so as to maintain linearity according to the gradation characteristics of the liquid crystal display device 100.

  In FIG. 8, if the gradation value is “0”, the width of the ON section is also “0”, and the entire section of the line selection period is the OFF section. As the gradation value increases, the proportion of the ON period (number of basic clock signals) increases. In the gradation value 15, the on section is set to “255”, and the entire section of the line selection period is the on section.

  Next, the configuration of the data signal driving circuit 110a will be described in detail with reference to FIG. The shift register 112 in the data signal driving circuit 110a is a shift register of “m / 3” bits (m is the number of data lines 32), and each time the pixel clock XSCL is supplied, the contents of each bit are adjacent to the right side. Shift to the bit you want. As shown in FIG. 10, the pixel clock XSCL is a signal that falls in synchronization with the timing at which the data signals DR, DG, and DB of each pixel are supplied. A pulse signal DX is supplied to the leftmost bit of the shift register 112. This pulse signal DX is a one-shot pulse signal that is generated when the output of the data signals DR, DG, and DB in the line selection period T from the conversion circuit 52 is started. Therefore, the signals S1 to Sm output from each bit of the shift register 112 are signals that are sequentially set to the H level exclusively for a time equal to the period of the pixel clock XSCL.

  The register 114 latches the data signals DR, DG, and DB by three pixels in synchronization with the rising edges of the output signals S1 to Sm of the shift register 112. The latch circuit 116 simultaneously latches the data signals stored in the register 114 in synchronization with the rising edge of the latch pulse LP. The waveform converter 118 converts the latched data signal into a signal potential VB as shown in FIG. 7A and applies it to the m data lines 32. That is, the output timing of the latch pulse LP becomes the start timing of the line selection period T.

  Next, a configuration example of the waveform converting unit 118 is shown in FIG. In FIG. 11, a counter 124 is a counter provided in common for all the data lines 32, and the count value is reset to “0” when the latch pulse LP rises, and the clock signal GCP is counted. The comparator 126 compares the data signals DR, DG, DB of each pixel latched by the latch circuit 116 with the count value of the counter 124. If the count value is less than the value of the data signal, the comparator 126 compares the data signal DR, DG, DB If the value is equal to or greater than the value of the data signal, an L level comparison signal CMP is output. The switch 122 selects the ON potential Von when the corresponding comparison signal CMP is at the H level, selects the OFF potential Voff when the corresponding comparison signal CMP is at the L level, and outputs the selected potential as the signal potential VB.

  FIG. 12 shows a driving waveform in gradation display in the liquid crystal display device 100. As described above, in the liquid crystal display device 100, gradation display is performed by pulse width modulation of the drive voltage applied to the liquid crystal layer 4. An example of driving waveforms for one line (1T) in the case of white display, gray display, and black display is shown in the upper part of FIG. In this example, it is assumed that the liquid crystal display device 100 is normally white.

  The scanning line driving waveform 61 is a pulse waveform applied to the scanning line 85 and defines the scanning potential VA. The data line drive waveform 62 is a pulse waveform applied to the data line 32 and defines the signal potential VB. As understood from FIG. 5, a potential difference between the scanning line 85 and the data line 32, that is, a potential between electrodes is applied to the liquid crystal layer 4. That is, the total voltage of the scanning line driving waveform 61 and the data line driving waveform 62, that is, the interelectrode voltage shown in the combined voltage waveform shown in the lower part of FIG. In the lower part of FIG. 12, a change in the actual voltage level of the liquid crystal layer 4 (liquid crystal layer voltage level) is shown as a liquid crystal layer voltage waveform 63. Since the liquid crystal layer 4 has a delay from the voltage application to the change in the orientation of the liquid crystal molecules, a transient response corresponding to the delay occurs, and the liquid crystal layer voltage waveform 63 shown in the lower part of FIG. 12 is applied to the liquid crystal layer 4. Will be. The gradation of the liquid crystal display device 100 changes according to the liquid crystal layer voltage level. Since the liquid crystal display device 100 of this example is normally white, when the liquid crystal layer voltage level is low, white display is performed, when the liquid crystal layer voltage level is high, black is displayed, and the middle is gray display (halftone display).

  As can be understood from the upper waveform in FIG. 12, the halftone level during gray display (halftone display) is controlled by the pulse width of the data line drive waveform 62. The data line driving waveform 62 is determined by the GCP described above. Therefore, by changing GCP, the pulse width of the data line drive waveform 62 changes, and as a result, the halftone level can be changed.

(Principle of horizontal crosstalk)
Next, lateral crosstalk will be described with reference to FIGS. FIG. 13 shows an equivalent circuit of one scanning line 85 of the liquid crystal display device 100. The liquid crystal layer 4 between the scanning line 85 and the data line 32 acts as a capacitance C between both electrodes. That is, in terms of electrical characteristics, a capacity C corresponding to the number of pixels of one line is connected in parallel between the scanning line 85 and the data line 32 for one specific line. Further, the resistance R resulting from the length of the scanning line 85 is connected in series with the parallel connection of these capacitors C. Thereby, a transient response occurs in the pulse waveform applied to the liquid crystal layer 4.

  FIG. 14 shows an equivalent circuit in specific lines X and Y of the liquid crystal display device 100, and a drive waveform and a composite voltage waveform applied thereto. In FIG. 14, the liquid crystal display device 100 shows a state where lateral crosstalk has occurred. The scanning line voltage and the signal line voltage are applied to the liquid crystal display device 100 so that the areas A and C have the same gray level and the area B has a white level. However, in actuality, due to the occurrence of lateral crosstalk, the gray level on the display image differs between area A and area C, which should have the same gradation level. Even when the scanning line voltage and the signal line voltage are applied so that the area B is at the black level, the horizontal crosstalk occurs similarly to the above.

  Specifically, an equivalent circuit of the line X is shown in the upper part of FIG. Since the area A is displayed at the same gradation level, each pixel of the line X is displayed at the same gradation level. In the drive waveform A at that time, a spike-shaped waveform round (hereinafter referred to as “spike waveform” for convenience of explanation) 66 is generated due to the resistance R and the capacitance C as shown in the figure, and the combined voltage waveform A is generated. Corresponding spike waveform 68 is generated. This combined voltage waveform determines the gray level of the display pixels on the line X. The spike waveform 66 is generated in the direction in which the voltage of the scanning line 85 increases when the signal potential applied to the data line 32 rises during the line selection period, while the signal potential applied to the data line 32 rises. This occurs in a direction in which the voltage of the scanning line 85 decreases when the voltage decreases. In the example of the drive waveforms A and C shown in FIG. 14, since the signal potential applied to the data line 32 falls during the line selection period, the spike waveform 66 is in the direction in which the voltage of the scanning line 85 decreases, that is, below the page. Has arisen in the direction.

  On the other hand, for the line Y, the lower left drive waveform B is applied in the area B area, and the lower right drive waveform C is applied in the area C area. Therefore, compared with the case of the line X, the applied voltage is small in the area B where white display is performed, and as a result, the level of the spike waveform 67 generated in the drive waveform C is compared with the spike waveform 66 of the drive waveform A. Get smaller. Therefore, the spike waveform 69 in the combined voltage waveform BC of the line Y is larger than the spike waveform 68 in the combined voltage waveform A of the line X. As a result, in area C, the liquid crystal layer voltage level applied to the liquid crystal layer 4 is higher than in area A, and the display pixel becomes gray closer to black. That is, the gradations of the area C and the area A where the same gray level is to be displayed are different. The above is the principle of occurrence of lateral crosstalk.

(Generation principle of vertical crosstalk)
Next, vertical crosstalk will be described with reference to FIG. FIG. 15A is a plan view in which only a display area V in a general liquid crystal display device is enlarged, and schematically shows a state in which vertical crosstalk has occurred in the display area V. FIG.

  For the liquid crystal display device, the scanning line voltage and the data line voltage are applied so that the background area E and area F have the same gray level. In the area D, the scanning line voltage and the data line voltage are applied so that a single color or a complementary color rectangular display having a specified brightness is obtained. However, the gray level on the display image is different between the area E and the area F that should have the same gradation level due to the occurrence of vertical crosstalk. That is, the area F positioned in the vertical direction of the area D is displayed somewhat brighter than the area E, and is displayed in a slightly colored manner. Such vertical crosstalk occurs when a monochrome or complementary color rectangle is displayed against a gray background.

  Next, the principle of occurrence of this vertical crosstalk will be described with reference to FIG. FIG. 15B is a partially enlarged plan view in which one pixel (RGB three subpixels) is enlarged in a general liquid crystal display device. In FIG. 15B, “C_LCD” indicates the pixel capacitance of the pixel electrode 10, and “C_TFD” indicates the element capacitance of the TFD element 21.

  The pixel electrode 10 is usually formed at a substantially central position between the pair of data lines 32. That is, the distance between the pixel electrode 10 and the adjacent data line 32 is the same distance D1. This is due to a design reason that the aperture ratio of the pixel is increased within a range in which the pixel electrode 10 is not too close to the adjacent data lines 32. The data lines 32a, 32b, and 32c are connected to the pixel electrodes 10a, 10b, and 10c via the TFD element 21. For example, when paying attention to the pixel electrode 10b, the data line 32a is adjacent to the pixel electrode 10b, but is not connected to the pixel electrode 10b. Parasitic capacitances C_a having the same size exist between the pixel electrode 10b and two adjacent data lines 32a and 32b, respectively.

  In the liquid crystal display device, in order to display a desired image, a desired voltage is applied to each of the pixel electrodes 10a to 10c in the line selection period T. In the example of FIG. 15B, a desired voltage Vlc is applied to the pixel electrode 10b from the data line 32b via the TFD element 21.

  However, since the parasitic capacitance C_a between the pixel electrode 10b and the adjacent data line 32a exists, a voltage corresponding to the parasitic capacitance C_a is applied from the data line 32a. The potential Vlc of the electrode 10b changes from a desired potential. That is, the potential of a certain pixel electrode changes due to a parasitic capacitance between the pixel electrode and an adjacent data line. As a result, the transmittance of the pixel changes and vertical crosstalk occurs.

  Now, assume that blue is displayed in area D and gray is displayed in areas E and F in FIG. In FIG. 15B, the pixel electrode 10a corresponding to the data line 32a is a subpixel corresponding to blue, the pixel electrode 10b is a subpixel corresponding to red, and the rightmost pixel electrode 10c corresponds to green. Assume that it is a sub-pixel.

  When these three-color sub-pixels are present in area E in FIG. 15A, the area is displayed in gray, so that the voltages applied to the three data lines 32a, 32b, and 32 are substantially equal and parasitic. The influence of the capacitance C_a on the pixel electrode 10b is small.

  On the other hand, since blue is displayed in the area D, also in the area F, only the data line 32a has a low potential (potential corresponding to white), and the data lines 32b and 32c have a high potential (potential corresponding to black). Become. Therefore, in the area F, a potential difference is generated between the data line 32a and the pixel electrode 10b in the holding period, and the potential of the pixel electrode 10b is decreased by the parasitic capacitance C_a. As a result, the transmittance of the red sub-pixel formed by the pixel electrode 10b is increased, the area F becomes brighter, and appears somewhat reddish.

  When a potential having a reverse polarity (for example, a potential corresponding to black (white)) is applied to the data line 32b with respect to a potential of the data line 32a (for example, potential corresponding to white (black)), the pixel electrode 10b. The capacitance ratio of the TFD element 21 is C_LCD: C_TFD. This is because the parasitic capacitance C_a generated on the left side of the pixel electrode 10b cancels out the parasitic capacitance C_a generated on the right side of the pixel electrode 10b.

  On the other hand, when a potential of the same polarity (potential corresponding to white (black)) is applied to the data line 32b with respect to the potential of the data line 32a (potential corresponding to white (black)), the pixel electrode 10b and the TFD element The capacity ratio of 21 is C_LCD: (C_TFD + 2 · C_a). This is because each parasitic capacitance C_a generated on the left and right of the pixel electrode 10b is added to the element capacitance.

  Therefore, the difference between the pixel capacitance and the element capacitance becomes larger when potentials having opposite polarities are applied to the adjacent data lines 32. In this case, the voltage Vlc applied to the pixel electrode 10 decreases, and the effective value applied to the liquid crystal layer 4 also decreases. As described above, the effective value applied to the liquid crystal layer 4 varies depending on whether the potential applied to the adjacent data lines 32 has the same polarity or the opposite polarity, and the transmittance of the liquid crystal varies. It will be. This is the principle of occurrence of vertical crosstalk. That is, vertical crosstalk is generated when the potential of the adjacent pixel electrode changes from a desired potential due to the influence of the parasitic capacitance C_a.

[How to reduce vertical and horizontal crosstalk]
Next, a method for reducing vertical and horizontal crosstalk according to the present invention will be described with reference to FIGS. FIG. 16 is a partial enlarged plan view in which one pixel (RGB three subpixels) in the liquid crystal display device 100 is enlarged. In FIG. 16, a region surrounded by a two-dot chain line indicates a region of one subpixel SG. FIG. 17 shows an equivalent circuit diagram of each component and the like corresponding to one subpixel SG in FIG.

  As described above, the vertical crosstalk is generated because the voltage Vlc of the pixel electrode changes due to the influence of the parasitic capacitance C_a between the pixel electrode 10 and the adjacent data line 32 not connected thereto. Therefore, in order to reduce the vertical crosstalk, the parasitic capacitance C_a should be made as small as possible to reduce the influence of the parasitic capacitance C_a.

  On the other hand, horizontal crosstalk occurs because the spike waveform generated in the combined voltage waveform becomes larger due to the grayscale of pixels in a certain line being concentrated on one grayscale. Therefore, in order to reduce the transverse crosstalk, the spike waveform should be made as small as possible to reduce the influence of the spike waveform.

  Therefore, in the present invention, first, in order to reduce the vertical crosstalk, as shown in FIG. 16, a dummy data line 80 is provided between the pixel electrode 10 and the adjacent data line 32 not connected thereto. . In other words, the pixel electrode 10 is formed between the data line 32 connected to the pixel electrode 10 and the dummy data line 80 in the sub-pixel region SG. As a result, the pixel electrode 10 and the adjacent data line 32 not connected thereto are shielded (shielded) by the dummy data line 80. Therefore, no parasitic capacitance is generated between them, so that the fluctuation of the voltage Vlc of the pixel electrode 10 can be prevented. Thereby, since the fluctuation | variation of the effective value applied to the liquid crystal layer 4 can be prevented, the transmittance | permeability of a liquid crystal can be maintained in an appropriate state. Therefore, occurrence of vertical crosstalk can be prevented.

  Here, paying attention to the pixel electrode 10b, when the dummy data line 80a is provided in the position adjacent to the pixel electrode 10b in this way, a parasitic capacitance C_a is newly provided between the pixel electrode 10b and the dummy data line 80a. 'Will occur. For this reason, the voltage Vlc of the pixel electrode 10 varies due to the influence of the parasitic capacitance C_a ′ between the pixel electrode 10 and the dummy data line 80, and vertical crosstalk occurs.

  Therefore, in the present invention, the dummy data line 80 has a predetermined configuration as will be described later, and the dummy data line 80 is driven with a potential having a reverse polarity obtained by inverting the potential of the data line 32 through a driving circuit. . As a result, not only vertical crosstalk but also horizontal crosstalk can be reduced. This will be described with reference to the equivalent circuit diagram of FIG.

  First, the equivalent circuit diagram of FIG. 17 will be described with reference to FIG. In such an equivalent circuit diagram, the pixel capacitance of the pixel electrode 10 is C_LCD, the element capacitance of the TFD element 21 is C_TFD, the parasitic capacitance generated between the pixel electrode 10 and the data line 32 connected thereto is C_a, and scanning with the data line 32 is performed. When the parasitic capacitance generated between the line 85 and the line 85 is C_b, the pixel capacitance C_LCD, the element capacitance C_TFD and the parasitic capacitance C_a are connected in series with respect to the capacitance between the scanning line 85 and the data line 32. On the other hand, the parasitic capacitance C_b is connected in parallel.

  Further, in the equivalent circuit diagram, when the parasitic capacitance generated between the pixel electrode 10 and the dummy data line 80 is C_a ′ and the parasitic capacitance generated between the dummy data line 80 and the scanning line 85 is C_b ′, the scanning line With respect to the capacitance between 85 and the dummy data line 80, the pixel capacitance C_LCD and the parasitic capacitance C_a ′ are connected in series, and the parasitic capacitance C_b ′ is connected in parallel.

If it is assumed that there is no dummy data line 80 in the equivalent circuit diagram of FIG. 17, it can be considered that there is no parasitic capacitance C_a ′ and C_b ′ in the equivalent circuit diagram. At this time, the combined capacitance C_x from the data line 32 to the scanning line 85 is
C_x = {(C_TFD + C_a) * C_LCD} / (C_TFD + C_LCD + C_a) + C_b (Formula 1)
It is represented by At this time, the capacitance ratio between the pixel electrode 10 and the TFD element 21 is
C_LCD: (C_TFD + C_a) (Formula 2)
It is represented by

On the other hand, when the dummy data line 80 is present in the equivalent circuit diagram of FIG. 17 as in the present invention, and further assuming that C_a = C_a ′ and C_b = C_b ′, the synthesis from the data line 32 to the scanning line 85 is performed. The capacity C_x ′ is
C_x ′ = C_TFD * C_LCD / (C_TFD + C_LCD) (Formula 3)
It is represented by At this time, the capacitance ratio between the pixel electrode 10 and the TFD element 21 is
C_LCD: C_TFD (Formula 4)
It is represented by Note that each of the values in the above formulas 3 and 4 indicates values when the dummy data line 80 is driven with a potential having a polarity opposite to that of the data line 32.

  In other words, in Equation 3 above, the parasitic capacitance C_a and the parasitic capacitance C_a ′, and the parasitic capacitance C_b and the parasitic capacitance C_b ′ are offset, so that the combined capacitance C_x ′ is smaller than the combined capacitance C_x. Further, in the above formula 4, since the parasitic capacitance C_a and the parasitic capacitance C_a ′ are offset, the capacitance ratio of the pixel electrode 10 to the TFD element 21 is larger than that in the above formula 2.

  With such a configuration or the like, driving the dummy data line 80 with a potential having a polarity opposite to that of the data line 32 makes the pixel electrode 10 less susceptible to the parasitic capacitance C_a ′. Can be prevented. In addition, since the ratio of the pixel capacitance C_LCD to the element capacitance C_TFD can be increased, the contrast can be improved.

  Further, the parasitic capacitance C_b and the parasitic capacitance C_b ′ are canceled by driving the dummy data line 80 with a potential having a reverse polarity obtained by inverting the potential of the data line 32 in this way. Therefore, it is possible to reduce the capacitance component C of the time constant RC that causes the spike waveform. As a result, the spike waveform can be reduced and lateral crosstalk can be reduced.

  Based on the above consideration, in the present invention, the dummy D1 is set so that the distance D1 between the pixel electrode 10 and the data line 32 connected to the pixel electrode 10 and the distance D2 between the pixel electrode 10 and the dummy data line 80 are the same. The pixel electrode 80 is disposed between the pixel electrode 10 and the adjacent data line 32 not connected thereto. Thereby, the parasitic capacitance C_a and the parasitic capacitance C_a ′ can be made the same. Further, in the sub-pixel SG region, the line of the dummy data line 80 is set so that the area S1 where the data line 32 and the scanning line 85 overlap is the same as the area S2 where the dummy data line 80 and the scanning line 85 overlap. Set the width. Thereby, the parasitic capacitance C_b and the parasitic capacitance C_b ′ can be made the same. Therefore, by driving the dummy data line 80 with a reverse polarity potential obtained by inverting the potential of the data line 32 through a drive circuit, vertical and horizontal crosstalk can be reduced, and a high-quality display image can be obtained. it can.

[Second Embodiment]
Next, with reference to FIG. 18 and FIG. 19, a lateral crosstalk reduction method according to the second embodiment will be described. FIG. 18 is a partially enlarged plan view in which one pixel (RGB three subpixels) is enlarged in the liquid crystal display device of the second embodiment. FIG. 18 is a partially enlarged plan view corresponding to FIG. In FIG. 18, a region surrounded by a two-dot chain line indicates a region of one subpixel SG. FIG. 19 shows waveform diagrams of the scanning potential VA in the effective display area V, the signal potential VB1 of the data line 32, and the signal potential VB2 of the dummy data line 80. FIG. 19A shows a waveform diagram or the like when the signal potential VB1 of the data line 32 rises during the line selection period T. FIG. On the other hand, FIG. 19B shows a waveform diagram when the signal potential VB1 of the data line 32 falls during the line selection period T. The method for reducing vertical crosstalk in the second embodiment is the same as that in the first embodiment, and a description thereof will be omitted. Moreover, in 2nd Embodiment, the same code | symbol is attached | subjected about the component similar to 1st Embodiment, and the detailed description is abbreviate | omitted.

(Horizontal crosstalk reduction method)
The spike waveform that causes lateral crosstalk has a time constant RC, which is the product of a resistance component R typified by wiring resistance and a capacitance component C typified by pixel capacitance, element capacitance, and parasitic capacitance. This spike waveform is generated in the direction in which the voltage of the scanning line 85 increases (or decreases) due to the rise (or fall) of the signal potential applied to the data line 32 during the line selection period as described above. Therefore, when the signal potential having the opposite polarity obtained by inverting the signal potential is applied to the dummy data line 80 simultaneously with the rise (or fall) of the signal potential applied to the data line 32, the spike waveform is the scanning line 85. This occurs both in the direction in which the voltage increases and the direction in which the voltage on the scanning line 85 decreases. As understood with reference to FIG. 14, at this time, in one specific line (one scanning line), the time constant RC between the scanning line 85 and the data line 32, the scanning line 85 and the dummy data line. If the time constants RC between 80 are matched, the spike waveforms are canceled out. Thereby, since the fluctuation of the effective value applied to the liquid crystal layer 4 can be prevented, the transverse crosstalk can be reduced.

  By the way, in the liquid crystal display device of the second embodiment, the data line 32 is connected to the TFD element 21, the pixel electrode 10, etc., but the dummy data line 80 is not connected to them. For this reason, in one scanning line, the capacitive component C between the scanning line 85 and the data line 32 and the capacitive component C between the scanning line 85 and the dummy data line 80 do not match.

  Therefore, in the second embodiment, a predetermined capacitance component is added between the dummy data line 80 and the scanning line 85, the time constant RC between the scanning line 85 and the data line 32, and the scanning line 85 and the dummy line. The time constants RC between the data lines 80 are matched, and the dummy data line 80 is driven with a potential having a reverse polarity obtained by inverting the potential of the data line 32 through a driving circuit. As a result, the spike waveform is canceled to reduce lateral crosstalk.

  First, in order to make the time constant RC between the scanning line 85 and the data line 32 coincide with the time constant RC between the scanning line 85 and the dummy data line 80, the capacitance component C of the time constant RC is included. Need to match. Of the time constant RC, the resistance component R need not be adjusted. This is because the data line 32 and the dummy data line 80 are formed in the same direction and at substantially the same position, and their respective wiring lengths are substantially the same. That is, the resistance values as the resistance component R are almost the same.

  Therefore, in the second embodiment, a predetermined capacitance component is added between the dummy data line 80 and the scanning line 85 in order to match the capacitance components C of the time constant RC. Specifically, for example, the parasitic capacitance C_b ′ generated between the dummy data line 80 and the scanning line 85 and the combined capacitance C_x between the data line 32 and the scanning line 85 are made the same.

Here, the parasitic capacitance C_b ′ is calculated from the equation of capacitance of a general substance.
C_b ′ = ε ₀ · ε (S3 / d) (Formula 5)
It is represented by “Ε ₀ ” is the dielectric constant of the vacuum, “ε” is the relative dielectric constant of the liquid crystal layer 4, “S 3” is the overlapping area of the dummy data line 80 and the scanning line 85 (see FIG. 18), and “d” is This is a cell gap between the lower substrate and the upper substrate. Therefore, according to the above equation 5, since “ε” and “d” are constant, in order to increase the parasitic capacitance C_b ′, the overlapping area “S3” between the dummy data line 80 and the scanning line 85 is increased. do it.

  Therefore, in the present invention, as shown in FIG. 18, the area “S3” is increased by forming the dummy data line 80 wide so that the combined capacitance C_x and the parasitic capacitance C_b ′ are the same. The capacity C_b ′ is increased. Thereby, the time constant RC between the scanning line 85 and the data line and the time constant RC between the scanning line 85 and the dummy data line 80 can be made the same.

  Next, in the present invention having such a configuration, as shown in FIG. 19, the dummy data line 80 is driven with a potential having a reverse polarity obtained by inverting the potential of the data line 32 through a drive circuit.

  With this driving method, in the case where the signal potential VB1 of the data line 32 rises during the line selection period, as shown in FIG. Will fall. At this time, as indicated by a broken line area E1 in FIG. 19A, a spike waveform indicated by the broken line W1 is generated in the signal potential VA of the scanning line 85 due to the rise of the signal potential VB1 of the data line 32. At the same time, due to the fall of the signal potential VB2 of the dummy data line 80, a spike waveform indicated by a broken line W2 is generated in the signal potential VA of the scanning line 85. Here, since the time constant RC between the scanning line 85 and the data line and the time constant RC between the scanning line 85 and the dummy data line 80 are the same, the magnitudes of both spike waveforms are the same. As a result, these spike waveforms are canceled out, so that the transverse crosstalk can be almost completely eliminated. Therefore, a high-quality display image can be obtained.

  In the case where the signal potential VB1 of the data line 32 falls during the line selection period, the signal potential VB2 of the dummy data line 80 is simultaneously with the fall of the signal potential VB1 of the data line 32, as shown in FIG. Will stand up. Thus, the spike waveform is canceled out by the same principle as described above, and the transverse crosstalk can be reduced.

[Electronics]
Next, an embodiment in which the liquid crystal display device 100 according to the present invention is used as a display device of an electronic apparatus will be described. Note that the liquid crystal display device to which the second embodiment is applied can also be used as the display device of the electronic apparatus.

  FIG. 20 is a schematic configuration diagram showing the overall configuration of the present embodiment. The electronic apparatus shown here includes the liquid crystal display device 100 and a control unit 410 that controls the liquid crystal display device 100. Here, the liquid crystal display device 100 is conceptually divided into a panel structure 403 and a drive circuit 402 composed of a semiconductor IC or the like. Further, the control means 410 includes a display information output source 411, a display information processing circuit 412, a power supply circuit 413, and a timing generator 414.

  The display information output source 411 includes a memory such as a ROM (Read Only Memory) or a RAM (Random Access Memory), a storage unit such as a magnetic recording disk or an optical recording disk, and a tuning circuit that tunes and outputs a digital image signal. The display information is supplied to the display information processing circuit 412 in the form of an image signal of a predetermined format based on various clock signals generated by the timing generator 414.

  The display information processing circuit 412 includes various well-known circuits such as a serial-parallel conversion circuit, an amplification / inversion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and executes processing of input display information to obtain image information. Are supplied to the drive circuit 402 together with the clock signal CLK. The driving circuit 402 includes a scanning line driving circuit, a data line driving circuit, and an inspection circuit. The power supply circuit 413 supplies a predetermined voltage to each of the above-described components.

  Next, specific examples of electronic devices to which the liquid crystal display device 100 according to the present invention can be applied will be described with reference to FIG.

  First, an example in which the liquid crystal display device 100 according to the present invention is applied to a display unit of a portable personal computer (so-called notebook personal computer) will be described. FIG. 21A is a perspective view showing the configuration of this personal computer. As shown in the figure, the personal computer 710 includes a main body 712 having a keyboard 711 and a display 713 to which the liquid crystal display panel according to the present invention is applied.

  Next, an example in which the liquid crystal display device 100 according to the present invention is applied to a display unit of a mobile phone will be described. FIG. 21B is a perspective view showing the configuration of this mobile phone. As shown in the figure, the cellular phone 720 includes a plurality of operation buttons 721, a reception port 722, a transmission port 723, and a display unit 724 to which the liquid crystal display device 100 according to the present invention is applied.

  Electronic devices to which the liquid crystal display device 100 according to the present invention can be applied include a liquid crystal television and a viewfinder in addition to the personal computer shown in FIG. 21A and the cellular phone shown in FIG. Type / monitor direct-view type video tape recorder, car navigation device, pager, electronic notebook, calculator, word processor, workstation, videophone, POS terminal, digital still camera, etc.

  Further, the present invention is not limited to a liquid crystal display device, but also an electroluminescence device, an organic electroluminescence device, a plasma display device, an electrophoretic display device, and a device using an electron-emitting device (Field Emission Display and Surface-Conduction Electron-Emitter Display). The present invention can be similarly applied to various electro-optical devices such as the above.

[Modification]
In the above embodiment, the present invention is applied to the transflective liquid crystal display device 100. However, the present invention is not limited to this, and the present invention can also be applied to a reflective or transmissive liquid crystal display device. In the above embodiment, the present invention is applied to the normally white liquid crystal display device 100. However, the present invention is not limited to this, and the present invention can also be applied to a normally black liquid crystal display device.

  In the second embodiment, the parasitic capacitance C_b ′ generated between the dummy data line 80 and the scanning line 85 by adjusting the line width of the dummy data line 80 is reduced to the data line 32 and the scanning line 85. It was configured to be the same as the combined capacity C_x. However, the present invention is not limited to this, and by connecting a pixel electrode, a TFD element, another electrode, wiring, or the like to the dummy data line 80, a capacitance component C (pixel capacitance, element capacitance, parasitic capacitance, etc.) of the time constant RC is obtained. The parasitic capacitance C_b ′ between the dummy data line 80 and the scanning line 85 and the combined capacitance C_x between the data line 32 and the scanning line 85 may be made the same.

The top view which shows the structure of the electrode and wiring of the liquid crystal display device which concern on this embodiment. The cross-sectional structure of a liquid crystal display device is shown. The top view which shows the structure of the electrode of an element substrate, wiring, etc. FIG. The top view which shows the structure of the electrode of a color filter board | substrate. An example of a driving circuit of a liquid crystal display device is shown. Waveform diagrams of the scanning potential VA, the signal potential VB, and the interelectrode voltage VAB are shown. The waveform diagram of the signal potential VB and the interelectrode voltage VAB is shown. The graph which shows the relationship between a gradation value and the pulse width of an ON area. The circuit diagram of a data signal drive circuit is shown. 3 shows a timing chart during driving of a liquid crystal display device. The circuit diagram of a waveform conversion part is shown. The wave form diagram which shows the drive waveform example of a different gradation level. An equivalent circuit for one line of a liquid crystal display device is shown. The figure explaining the generation | occurrence | production principle of horizontal crosstalk. The figure explaining the generation | occurrence | production principle of vertical crosstalk. The figure explaining the reduction method of the vertical and horizontal crosstalk which concerns on 1st Embodiment. FIG. 3 is an equivalent circuit diagram corresponding to one pixel of the liquid crystal display device according to the first embodiment. The figure explaining the horizontal crosstalk reduction method which concerns on 2nd Embodiment. Waveform diagram illustrating the lateral crosstalk reduction method according to the second embodiment 1 is a circuit block diagram of an electronic apparatus to which a liquid crystal display device of the present invention is applied. Examples of electronic devices to which the liquid crystal display device of the present invention is applied are shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Upper substrate, 2 Lower substrate, 3 Seal member, 6 Colored layer, 7 Conductive member, 8 Scan electrode, 10 Pixel electrode, 31, 85 Scan line, 32, 32a Data line, 21 TFD element, 80 Dummy data line, 91 color filter substrate, 92 element substrate, V effective display area, 100 liquid crystal display device

Claims (7)

An electro-optical device in which an electro-optical material is sealed between a substrate having a data line, a pixel electrode, a switching element connected to the data line and the pixel electrode, and a signal line, and a counter substrate having a scanning line. There,
The signal line is formed between the pixel electrode and the adjacent data line that is not connected to the pixel electrode,
An electro-optical device comprising: a drive circuit that drives the signal line with a potential having a polarity opposite to a reference potential with respect to a potential of the data line.   The electro-optical device according to claim 1, wherein the pixel electrode is formed between the data line and the signal line connected to the pixel electrode in a pixel region. An interval between the pixel electrode and the data line connected to the pixel electrode is the same as an interval between the pixel electrode and the signal line adjacent to the pixel electrode.
3. The electro-optical device according to claim 1, wherein an area where the data line and the scanning line overlap is the same as an area where the signal line and the scanning line overlap in a pixel region.   3. The electro-optical device according to claim 1, wherein a combined capacitance between the signal line and the scanning line is the same as a combined capacitance between the data line and the scanning line.   The electro-optical device according to claim 4, wherein an area where the signal line and the scanning line overlap in a pixel region is larger than an area where the data line and the scanning line overlap. An electro-optical device in which an electro-optical material is sealed between a data line, a pixel electrode, a switching element connected to the data line and the pixel electrode, a substrate having a shield line, and a counter substrate having a scanning line. There,
The electro-optical device, wherein the shield line is formed between the pixel electrode and the adjacent data line not connected to the pixel electrode. An electronic apparatus comprising the electro-optical device according to claim 1 as a display unit.

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