CN114200724A

CN114200724A - Pixel structure

Info

Publication number: CN114200724A
Application number: CN202011024297.7A
Authority: CN
Inventors: 吴哲耀; 周凯茹; 江宜达
Original assignee: Giantplus Technology Co Ltd
Current assignee: Giantplus Technology Co Ltd
Priority date: 2020-09-02
Filing date: 2020-09-25
Publication date: 2022-03-18
Anticipated expiration: 2040-09-25
Also published as: TW202211188A; CN114200724B; TWI728909B

Abstract

The application relates to a pixel structure, which comprises a substrate, a gate line, a data line, a shielding layer, a first pixel and a second pixel. The gate line is disposed on the substrate along a first direction. The data line is arranged on the grid line along a second direction, the second direction is orthogonal to the first direction, and the data line is away from the grid line by a first distance. The shielding layer is arranged on the gate line along a second direction, and has a second distance with the gate line, wherein the second distance is greater than the first distance. The first pixel and the second pixel are arranged on the shielding layer at intervals along the second direction, and a part of the shielding layer is exposed between the first pixel and the second pixel. The pixel structure of the application has smaller data line width so as to reduce invalid disordered capacitance and realize the effect of low power consumption.

Description

Pixel structure

Technical Field

The present application relates to the field of display panels, and more particularly, to a pixel structure.

Background

With the development of science and technology, electronic products are widely used in life, and the dependence of people on the electronic products is increased. In order to use electronic products anytime and anywhere, these electronic products are gradually developed toward being light, thin, short and small so as to be convenient for users to carry with them.

For a lightweight and thin portable electronic product, a display providing a message display function is required to have a good indoor and outdoor display function, and also to reduce power consumption as much as possible to prolong a service life. Therefore, the transflective display technology is becoming an important development direction. Compared with the traditional display technology, the transflective display technology simultaneously utilizes the penetrating light from the backlight module and the reflected light from the ambient light source, so that the display uses the penetrating light of the backlight module under the condition of low light source, and reflects the display information through the ambient light under the condition of strong ambient light, thereby achieving the purpose of saving the power consumption of the panel.

At present, in a pixel structure of a transflective display device, because the electrical property of the junction of a pixel and a pixel is unstable, a data line can be placed in a gap between two adjacent pixels, so that the disturbance of liquid crystal can be reduced, and light can be prevented from being exposed from the gap. Further, in order to reliably shield the gap, the data line usually overlaps with two pixel portions. In this way, the data line is configured to have a certain width, so that the overlapping area between the data line and the gate line below the data line is increased, and the invalid capacitance generated between the data line and the gate line is also increased, so that the power consumption of the pixel structure is increased, and the pixel structure is not suitable for a low power consumption product.

Disclosure of Invention

The embodiment of the application provides a pixel structure, which solves the problem that the current pixel structure uses a data line for shading light, but generates an invalid capacitor to increase power consumption.

In order to solve the technical problem, the present application is implemented as follows:

a pixel structure is provided, which includes a substrate, a gate line, a data line, a shielding layer, a first pixel and a second pixel. The gate line is disposed on the substrate along a first direction. The data line is arranged on the grid line along a second direction, the second direction is orthogonal to the first direction, and the data line is away from the grid line by a first distance. The shielding layer is arranged on the gate line along a second direction, and has a second distance with the gate line, wherein the second distance is greater than the first distance. The first pixel and the second pixel are arranged on the shielding layer at intervals along the second direction, and a part of the shielding layer is exposed between the first pixel and the second pixel.

In the embodiment of the present application, the shielding layer in the pixel structure partially overlaps the first pixel and the second pixel, and a portion of the shielding layer is exposed between the first pixel and the second pixel, so that light does not leak from between the two pixels. Furthermore, since the distance between the shielding layer and the gate line is greater than the distance between the data line and the gate line, the ineffective capacitance is lower to achieve the power saving effect.

Drawings

FIG. 1 is a schematic diagram of a pixel structure according to an embodiment of the present application;

FIG. 2 is a cross-sectional view of a pixel structure according to an embodiment of the present application;

FIG. 3 is a control signal diagram of a pixel structure according to an embodiment of the present application; and

fig. 4 is a schematic diagram of a pixel structure according to another embodiment of the present application.

Wherein, the reference numbers:

1 pixel structure

2-pixel structure

10 base plate

11 gate line

12 data line

13 masking layer

14 first pixel

141 first sub-pixel

142 second sub-pixel

143 third sub-pixel

15 second pixel

16 first insulating layer

17 second insulating layer

18 third insulating layer

A1 first overlap region

A2 second overlap region

d1 first distance

d second distance

d3 third distance

d4 fourth distance

DR1 first direction

DR2 second direction

DR3 third Direction

Width of W1

Width of W2

Detailed Description

In order to facilitate understanding of the technical features, contents, advantages and capabilities of the invention and the achieved effects thereof, the invention is described in detail with the accompanying drawings and expression forms of embodiments, and the description drawings used in the invention are only for illustrating and assisting the description, and are not necessarily true to scale and precise configuration after the implementation of the invention, so the invention should not be read and limited in terms of the scale and configuration relationship of the attached drawings and the attached description drawings.

In the drawings, the thickness or width of elements is exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element is referred to as being "on" or "connected to" or "disposed on" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" or "disposed," can refer to a physical and/or electrical connection or arrangement. Furthermore, the use of the terms first, second and third are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or order relationship.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Please refer to fig. 1 to 2, which are schematic diagrams and cross-sectional views of a pixel structure according to an embodiment of the present application. As shown in the figure, the pixel structure 1 includes a substrate 10, a gate line 11, a data line 12, a shielding layer 13, a first pixel 14, and a second pixel 15. The gate line 11 is disposed on the substrate 10 along the first direction DR 1. The data line 12 is disposed on the gate line 11 along a second direction DR2, the second direction DR2 is orthogonal to the first direction DR1, and the data line 12 is spaced apart from the gate line 11 by a first distance d 1. The shielding layer 13 is disposed on the gate line 11 along the second direction DR2, and the shielding layer 13 is spaced apart from the gate line 11 by a second distance d2, the second distance d2 is greater than the first distance d1, that is, the shielding layer 13 is farther away from the gate line 11 than the data line 12. The first pixel 14 and the second pixel 15 are disposed on the shielding layer 13 at an interval along the second direction DR2, and a portion of the shielding layer 13 is exposed between the first pixel 14 and the second pixel 15, in other words, a gap between the first pixel 14 and the second pixel 15 is shielded by the shielding layer 13, so that light from a backlight module or other similar light sources is not leaked from the gap between the first pixel 14 and the second pixel 15, which affects display quality. The respective elements mentioned above will be explained in more detail below.

In some embodiments, the substrate 10 may be disposed on a backlight module, and the backlight module is used for providing a pixel structure light source. The Light Emitting source of the backlight module may be a Cold Cathode Fluorescent Lamp (CCFL) or a Light Emitting Diode (LED). The light emitted by the backlight module travels towards the substrate 10 and leaves the pixel structure 1 after passing through the first pixel 14 and/or the second pixel 15. Therefore, in order to allow light to pass through the entire pixel structure 1, at least a portion of the substrate 10 is transparent, or the entire substrate 10 is transparent. In some embodiments, the substrate 10 may be a glass substrate or a plastic substrate, but not limited thereto.

In some embodiments, the gate line 11 is disposed on the substrate 10. The gate line 11 may include a pure metal, a metal alloy, a metal nitride, a metal oxide, a metal oxynitride, and/or a combination thereof.

In some embodiments, the data line 12 is disposed on the gate line 11. The data line 12 may comprise pure metals, metal alloys, metal nitrides, metal oxides, metal oxynitrides, and/or combinations thereof. In addition, the data line 12 is spaced apart from the gate line 11 by a first distance d1, and the data line 12 partially overlaps the gate line 11 to form a first overlapping area a 1. In the first overlapping area a1 of the orthographic projection, the data line 12 and the gate line 11 are separated by space or dielectric to form a capacitor and store charges. However, the capacitor has no effect on the display function, i.e. the generated capacitor is an ineffective capacitor, and further increases the power consumption of the product. Specifically, the capacitance formula is C ═ epsilon x A/d, where epsilon is the dielectric constant, a is the area of overlap, and d is the distance. As can be seen from the capacitance formula, the capacitance is proportional to the overlapping area between the two thin plate conductors (i.e., the data line 12 and the gate line 11), and the capacitance is inversely proportional to the distance between the two thin plate conductors (i.e., the data line 12 and the gate line 11). That is, as the area of the first overlap area a1 between the data line 12 and the gate line 11 is smaller, the smaller the capacitance is generated. On the other hand, the farther the distance between the data line 12 and the gate line 11, the smaller the capacitance is generated.

In some embodiments, the width W1 of the data line 12 in the first direction DR1 may be between 1 μm and 20 μm. As the width W1 of the data line 12 is smaller, the first overlapping area a1 formed by the data line 12 and the gate line 11 is smaller, the generated capacitance is smaller, and the power of the pixel structure 1 is saved. In some embodiments, the first distance d1 between the data line 12 and the gate line 11 may be between 0.1 μm and 1 μm. As the first distance d1 between the data line 12 and the gate line 11 is farther, the generated capacitance is smaller, and the pixel structure 1 saves more power.

In one embodiment, the shielding layer 13 is disposed on the gate line 11, and the shielding layer 13 is opaque. The shielding layer 13 may comprise pure metals, metal alloys, metal nitrides, metal oxides, metal oxynitrides, and/or combinations thereof. In addition, the shielding layer 13 is spaced apart from the gate line 11 by a second distance d2, and the shielding layer 13 partially overlaps the gate line 11 to form a second overlapping area a 2. Specifically, the second distance d2 is greater than the first distance d1, and the second overlap region a2 is greater than the first overlap region a 1. Similar to the data line 12 and the gate line 11, the shielding layer 13 and the gate line 11 also form a capacitor and store charges. Similarly, the capacitor has no effect on the display function, i.e. the generated capacitor is an ineffective capacitor and further consumes the power of the product. However, compared to the conventional pixel structure that transmits data messages and shields light through a large-area data line, in the present application, the data messages are transmitted through a small-area data line 12 and the light is shielded by a shielding layer 13 that is farther away from the gate line 11 than the data line 12. In this way, the total capacitance of the capacitance generated by the data line 12 and the gate line 11 and the capacitance generated by the shielding layer 13 and the gate line 11 of the present application is smaller than the ineffective capacitance generated by the conventional large-area data line and gate line. That is, the present application can achieve the effect of reducing power consumption while maintaining the display function of the pixel structure 1 by the combination of the data line 12 and the shielding layer 13.

In some embodiments, the width W2 of the shielding layer 13 in the first direction DR1 may be between 5 μm and 20 μm. As the width W2 of the shielding layer 13 is smaller, the second overlapping area a2 formed by the shielding layer 13 and the gate line 11 is smaller, the generated capacitance is smaller, and the power of the pixel structure 1 is saved. However, it should be noted that the width W2 of the shielding layer 13 has a lower limit value, otherwise the shielding layer 13 cannot achieve the function of shielding light. In other words, the width W2 of the shielding layer 13 depends on the shape, size and relative distance of the first pixel 14 and the second pixel 15 disposed above. For example, when the first pixel 14 and the second pixel 15 are closer, the width W2 of the shielding layer 13 may be smaller (e.g., 5 μm). When the first pixel 14 and the second pixel 15 are spaced far apart from each other, the width W2 of the shielding layer 13 may be large (e.g., 20 μm). In some embodiments, the second distance d2 between the shielding layer 13 and the gate line 11 may be between 0.1 μm and 2 μm. As the second distance d2 between the shielding layer 13 and the gate line 11 is farther, the generated capacitance is smaller, and the pixel structure 1 saves more power.

In addition, the shielding layer 13 is spaced apart from the data line 12 by a third distance d3 in the first direction DR1 to prevent a capacitor from being formed between the shielding layer 13 and the data line 12. In some embodiments, the third distance d3 may be 0.5 μm to 5 μm. The third distance d3 may be configured according to practical situations. For example, when the shielding layer 13 is closer to the data line 12 in the first direction DR1, the third distance d3 may be 5 μm to avoid signal interference or unnecessary formation of invalid capacitors. Alternatively, when the shielding layer 13 is distant from the data line 12 in the first direction DR1, the third distance d3 may be 0.5 μm since signals do not easily interfere with each other and a capacitance is not formed.

In some embodiments, the first pixel 14 and the second pixel 15 are disposed on the shielding layer 13, and a side of the first pixel 14 close to the second pixel 15 partially overlaps the shielding layer 13, and a side of the second pixel 15 close to the first pixel 14 partially overlaps the shielding layer 13. The first pixel 14 and the second pixel 15 are electrically connected to the data line 12, respectively, for receiving the image message from the data line 12.

In some embodiments, the first pixel 14 and the second pixel 15 have a fourth distance d4 therebetween. The fourth distance d4 may be 2.5 μm to 10 μm, which is determined according to the actual use case or the fineness of the process. In other words, when the fourth distance d4 is larger, the width W2 of the shielding layer 13 between the first pixel 14 and the second pixel 15 is also larger to avoid the light from being exposed from the gap between the first pixel 14 and the second pixel 15. Conversely, when the fourth distance d4 is smaller, the width W2 of the shielding layer 13 between the first pixel 14 and the second pixel 15 may be smaller, so that the capacitance generated by the shielding layer 13 and the gate line 11 may be reduced while the light shielding property is maintained.

In some embodiments, the pixel structure 1 may further include a thin film transistor. The thin film transistor is disposed on the substrate and is used for controlling the first pixel 14 and the second pixel 15. The thin film transistor may include a gate electrode, a drain electrode, a source electrode, a channel layer, and an insulating layer. The gate may be electrically connected to the gate line 11. The gate may be formed from the same patterned conductive layer, for example: a metal layer or an alloy layer. Specifically, the gate electrode may include aluminum (aluminum), platinum (platinum), silver (silver), titanium (titanium), molybdenum (molybdenum), zinc (zinc), tin (tin), and/or a combination thereof, but not limited thereto. The drain and source electrodes may be formed of the same patterned conductive layer and may comprise the same or different materials as the gate electrode. The channel layer may be formed of the same layer of patterned semiconductor, and may be a single layer or a multi-layer structure. The channel layer may include silicon (e.g., amorphous silicon, polycrystalline silicon, single crystalline silicon), an oxide semiconductor (e.g., indium oxide (InO), gallium oxide (GaO), zinc oxide (ZnO), Indium Gallium Oxide (IGO), Indium Zinc Oxide (IZO), Indium Tin Oxide (ITO), or Indium Gallium Zinc Oxide (IGZO)), an organic semiconductor, or other semiconductor materials. The insulating layer may be a single layer or a multi-layer structure, and the insulating layer may include an inorganic material (e.g., silicon nitride, silicon oxide, silicon oxynitride), an organic material (e.g., Polyimide (PI)), polyester, polymethyl methacrylate (PMMA), polyvinyl phenol (poly (4-vinylphenol), PVP), polyvinyl alcohol (PVA), Polytetrafluoroethylene (PTFE)), but is not limited thereto.

In some embodiments, the pixel structure 1 may further include: a first insulating layer 16, a second insulating layer 17, and a third insulating layer 18. The first insulating layer 16 is disposed on the substrate 10, and the first insulating layer 16 may include silicon nitride (SiN)_x) Or materials recognized by those skilled in the art. More specifically, the thickness of the first insulating layer 16 may be 0.15 μm to 1 μm.

The second insulation layer 17 is disposed on the first insulation layer 16, and the second insulation layer 17 may include silicon nitride (SiN)_x) Or other materials recognized by those skilled in the art. More specifically, the thickness of the second insulating layer 17 may be 0.15 μm to 1 μm.

The third insulating layer 18 is disposed on the second insulating layer 17, and the third insulating layer 18 may include an organic material, silicon nitride (SiN)_x) Or other materials recognized by those skilled in the art. When the third insulating layer 18 includes an organic material, the thickness of the third insulating layer 18 may be 1 μm to 5 μm. When the third insulating layer 18 comprises silicon nitride (SiN)_x) When, the thickness of the third insulating layer 18 may be 0.15 μm to 1 μm.

Please refer to fig. 3, which is a control signal diagram of a pixel structure according to an embodiment of the present application. As shown, the data line 12 mainly transmits various image signals to the first pixel 14 and/or the second pixel 15. Since the signal itself is constantly changing, wasteful power consumption is likely to occur. As mentioned above, after the data line 12 is used with the shielding layer 13 for signal transmission and the light shielding effect is maintained, the capacitance generated by the data line 12 and the gate line 11 can be reduced. In some embodiments, the shielding layer 13 can use a simpler signal, such as an AC signal or a DC signal, to reduce the energy loss caused by the voltage transition.

Please refer to fig. 4, which is a diagram illustrating a pixel structure according to another embodiment of the present application. In the present embodiment, the same element numbers denote the same elements in fig. 1 and 4. Therefore, detailed descriptions of the same elements will be omitted. As shown, the first pixel 14 in the pixel structure 2 further includes a first sub-pixel 141, a second sub-pixel 142, and a third sub-pixel 143. Similarly, the second pixel 15 may further include: a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel. In other words, the shielding layer 13 of the present application is not limited to the pixel structure of a single large pixel, and when the pixel further includes a plurality of sub-pixels, the shielding layer 13 can also shield two sub-pixels adjacent to each other in the first direction DR1, and achieve the effects of light shielding and low power consumption. It should be noted that the number of the plurality of sub-pixels in each pixel is not limited to three, and in some embodiments, the number of the plurality of sub-pixels may be two, four or five, depending on the actual usage.

In summary, in the present embodiment, the shielding layer of the pixel structure partially overlaps the first pixel and the second pixel, and a portion of the shielding layer is exposed between the first pixel and the second pixel, so that light does not leak from between the two pixels. Furthermore, since the distance between the shielding layer and the gate line is greater than the distance between the data line and the gate line, the ineffective capacitance is lower to achieve the power saving effect.

The above-disclosed embodiments are merely examples of the present application, and are not intended to limit the scope of the present application, but rather, the present application is intended to cover all equivalent changes and modifications in the shape, structure, characteristics, and spirit of the appended claims.

Claims

1. A pixel structure, comprising:

a substrate;

a gate line disposed on the substrate along a first direction;

a data line disposed on the gate line along a second direction orthogonal to the first direction, the data line being spaced from the gate line by a first distance;

a shielding layer disposed on the gate line along the second direction, wherein the shielding layer is spaced from the gate line by a second distance greater than the first distance; and

the first pixel and the second pixel are arranged on the shielding layer at intervals along the second direction, and a part of the shielding layer is exposed between the first pixel and the second pixel.

2. The pixel structure of claim 1, wherein the data line and the gate line have a first overlapping area, the shielding layer and the gate line have a second overlapping area, and the first overlapping area is smaller than the second overlapping area.

3. The pixel structure of claim 1 wherein the first distance is 0.1 μm to 1 μm.

4. The pixel structure of claim 1 wherein the second distance is 0.1 μm to 2 μm.

5. The pixel structure of claim 1, wherein the data line is spaced apart from the shielding layer by a third distance in the first direction, the third distance being 0.5 μm to 5 μm.

6. The pixel structure of claim 1 wherein the width of the masking layer in the first direction is 5 μm to 20 μm.

7. The pixel structure of claim 1, wherein the first pixel comprises a plurality of first sub-pixels and the second pixel comprises a plurality of second sub-pixels.

8. The pixel structure of claim 1 wherein the masking layer is a metal.

9. The pixel structure of claim 1 wherein the masking layer is opaque.