JP2006013327A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable formation of an SRAM cell by adjusting resistance value of the resistor element of a gate electrode, when the size of the SRAM cell is reduced. <P>SOLUTION: In a case of manufacturing the SRAM cell, when implantation of impurity ions is performed at first time, ion implantation is performed under the condition where the ion concentration is comparatively high and acceleration voltage is low, and a source/drain diffusion layer 13 is formed. When implantation of the impurity ions is performed for the second time, ion implantation is performed under the condition where ion concentration is comparatively low and acceleration voltage is high, and the resistance value of a first polycrystalline silicon film 6 is adjusted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a semiconductor device including an SRAM cell that is improved in soft error resistance.

In a semiconductor device including a memory cell called a Full-CMOS SRAM cell (Static Random Access Memory Cell), one memory cell is composed of six MOS transistors. Each memory cell is considered to have a pattern such as a point symmetric type or a line symmetric type in plan view.
By the way, in such an SRAM cell, the occurrence of a soft error in which the memory content changes due to neutron rays or α rays incident from the outside is a problem. As a countermeasure against this soft error, it has been studied to protect the stored contents of data in the storage node by forming a resistance element between the storage node and the gate electrode of the MOS transistor.

However, the conventional SRAM cell structure has a problem that a cell area is increased by adding a resistance element as a countermeasure against a soft error, and further, the number of manufacturing steps and the manufacturing cost are increased. Therefore, a technique is known in which a region where no impurity is introduced is formed in at least a part of the polysilicon wiring portion, and the region where no impurity is introduced functions as a high resistance portion (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 5-235301

  The above-described Patent Document 1 has the following problems. That is, the polysilicon into which impurities are not introduced has a problem that when a voltage is applied, the value of the resistance element changes greatly due to the voltage change, and it is difficult to adjust the value of the resistance element. Furthermore, in recent years, the size of SRAM cells has been reduced, and it has become difficult to form resistance elements without increasing the memory cell area and the number of manufacturing steps.

  The present invention has been made to solve the above-described problems, and its purpose is to form an SRAM cell by adjusting the resistance value of the resistance element of the gate electrode wiring when the size of the SRAM cell is reduced. Another object of the present invention is to provide a method for manufacturing a semiconductor device.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a conductive layer on a semiconductor substrate via a first insulating film, a step of forming a second insulating film on the conductive layer, Removing the second insulating film formed on the conductive layer except for the non-silicide layer formation region, and implanting impurities into the semiconductor substrate from above the conductive layer with a predetermined first acceleration voltage. A step of forming a diffusion layer, a step of adjusting the resistance value of the conductive layer by ion-implanting impurities into the conductive layer with a second acceleration voltage higher than the first acceleration voltage, and non-silicide And a step of siliciding the upper portion of the conductive layer other than the layer formation region.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a conductive layer on a semiconductor substrate via a first insulating film, a step of forming a second insulating film on the conductive layer, Removing the second insulating film formed on the conductive layer except for the non-silicide layer forming region, and ionizing impurities from above the conductive layer with a predetermined first acceleration voltage and a first implantation amount. A step of implanting and forming a diffusion layer in the semiconductor substrate; and a second implantation with a second acceleration voltage condition higher than the first acceleration voltage and a lower implantation amount than the first implantation amount. The method includes a step of adjusting the resistance value of the conductive layer by ion-implanting impurities into the conductive layer in an amount, and a step of silicidizing the upper portion of the conductive layer other than the non-silicide layer formation region.

  According to the present invention, when the size of the SRAM cell is reduced, the SRAM cell can be formed by adjusting the resistance value of the resistance element of the gate electrode wiring.

Hereinafter, an embodiment in which the present invention is applied to a method for manufacturing an SRAM semiconductor memory device will be described with reference to FIGS.
FIG. 1 is a plan view schematically showing an SRAM cell formed in the SRAM semiconductor memory device, and shows the formation state of the gate electrode wiring in a plan view. FIG. 3 shows an electrical configuration of an example of the SRAM cell.

  First, the electrical configuration will be schematically described. As shown in FIG. 3, the SRAM cell M includes six MOSFETs. These six MOSFETs are composed of first and second load MOSFETs TL1 and TL2, first and second driver MOSFETs TD1 and TD2, and first and second transfer gate MOSFETs TS1 and TS2. Hereinafter, these MOSFETs TL1, TL2, TD1, TD2, TS1, and TS2 are simply referred to as transistors.

  Each of the load transistors TL1 and TL2 is configured by a p-channel MOSFET (corresponding to the MOS transistor of the present invention), and each of the driver transistors TD1 and TD2 is an n-channel MOSFET (MOS transistor of the present invention). Equivalent). Further, the transfer gate transistors TS1 and TS2 are constituted by n-channel MOSFETs (corresponding to MOS transistors).

  The inverter circuit I1 is configured such that the drains of the load transistor TL1 and the driver transistor TD1 are connected in common and the gates are connected in common. Each of these transistors TL1 and TD1 operates in a complementary manner. A common connection point of the drains of these transistors TD1 and TL1 is an output terminal node (storage node) N1.

  Further, the inverter circuit I2 is configured such that the drains of the load transistor TL2 and the driver transistor TD2 are connected in common and the gates are connected in common. These transistors TD2 and TL2 operate in a complementary manner. A common connection point of the drains of these transistors TD2 and TL2 is an output terminal node (storage node) N2.

  These inverter circuits I1 and I2 operate by applying power supply voltage Vdd applied to power supply node Nd and ground potential Vss applied to ground node Ns. In principle, these inverter circuits I1 and I2 are cross-coupled to satisfy the function as the SRAM cell M. In the present embodiment, however, the resistance element is as follows to prevent soft errors. R1 and R2 are formed.

That is, the output terminal node N1 of the inverter circuit I1 is connected to the input terminal node N3 of the inverter circuit I2 via the resistance element R2. The output terminal node N2 of the inverter circuit I2 is connected to the input terminal node N4 of the inverter circuit I1 through the resistance element R1.
The gate electrodes of the transfer gate transistors TS1 and TS2 are commonly connected to the word line WL. The source / drain node of transistor TS1 is connected between bit line BL and output terminal node N1 of inverter circuit I1, and the source / drain node of transistor TS2 is output terminal node N2 of bit line / BL and inverter circuit I2. Connected between.

<About structure>
Hereinafter, the structure (pattern layout) in the semiconductor device of the SRAM cell M will be described with reference to FIGS.
In FIG. 1, the structure of several SRAM cells M is shown. Actually, however, the number of SRAM cells M corresponding to the storage capacity is arranged in a matrix as a semiconductor memory device. 2A is a schematic cross-sectional view taken along the line AA ′ in FIG. 1, and FIG. 2B is a schematic cross-sectional view taken along the line BB ′ in FIG. Is shown.

  As shown in FIGS. 1 and 2, a shallow trench isolation element isolation region (Shallow Trench Isolation) STI is formed in the silicon semiconductor substrate 1, and an element region separated by the element isolation region STI is formed. As shown in FIG. 1, an N well Nw for forming a P channel type MOS transistor and a P well Pw for forming an N channel type MOS transistor are formed. The power supply potential Vdd is applied to the N well Nw, and the ground potential Vss is applied to the P well Pw.

  In FIG. 1, AAn indicates an active area (active region) including a source-drain channel region of an N channel type MOS transistor formed in an N well Nw. AAp represents an active area (active region) including a source-drain channel region of a P channel type MOS transistor formed in the P well Pw. In FIG. 1 and FIG. 2, GC indicates a gate electrode wiring disposed so as to be orthogonal to the active areas AAp and AAn.

As shown in FIG. 2, a spacer Sp is formed on the side wall of the gate electrode wiring GC by a silicon oxide film or a silicon nitride film, for example, and each transistor TL1, TL2, TD1, TD2, TS1, TS2, TS2 has an LDD (Lightly Doped Drain) structure is adopted.
Hereinafter, the structure will be described. As shown in FIG. 2, trenches (grooves) 2 are formed in the N well Nw and the P well Pw of the silicon semiconductor substrate 1. A first silicon oxide film 3 is formed on the entire inner surface of the trench 2. The first silicon oxide film 3 is formed in contact with the N well Nw in the trench 2. On the silicon semiconductor substrate 1, a second silicon oxide film 4 is formed as a gate insulating film (first insulating film). These first and second silicon oxide films 3 and 4 are formed so as to be coupled over the silicon semiconductor substrate 1 and the inner surface of the trench 2.

  A third silicon oxide film 5 (STI-TEOS (Tetra-Ethoxy-Silane) film) is formed as an insulating film on the first silicon oxide film 3 in the trench 2. The third silicon oxide film 5 is formed by embedding a silicon oxide film in the entire region of the trench 2 and is formed to maintain the insulation performance between the active areas AA (AAp, AAn). Has been.

A first polycrystalline silicon film 6 is formed on the first and second silicon oxide films 3 and 4 as a conductive layer. The first polycrystalline silicon film 6 is formed so as to be connected to the gate electrodes of the transistors TL1 and TD1 over the three (plurality) of active areas AAp, AAn, and AAn as shown in a plan view in FIG. ing.
A metal silicide layer (cobalt silicide layer) 7 is formed on a part of the upper portion of the first polycrystalline silicon film 6. In addition, although the embodiment silicidized with cobalt is shown, it may be silicidized with another metal (for example, tungsten or the like). As a result, the gate electrode wiring GC is constituted by the first polycrystalline silicon film 6 and the tungsten silicide layer 7. On the first polycrystalline silicon film 6, a first silicon nitride film 12 as a second insulating film is formed around the shared contact formation region SC2. The first silicon nitride film 12 is formed on the upper surface of the end portion of the divided first polycrystalline silicon film 6.

  The first silicon nitride film 12 is a film for non-silicided part of the first polycrystalline silicon film 6 and functions as an impurity implantation adjusting insulating film. By forming this film, The resistance between the contact plug P and the gate electrode wiring GC is increased (that is, the resistance element R1 is formed). Specifically, as shown in FIGS. 1 and 2A, the first silicon nitride film 12 is formed around the shared contact region SC2. The shared contact region SC2 is a contact plug P for electrically connecting the gate electrode wiring GC and the upper layer wiring (not shown) or electrically connecting the drain of the transistor TL2 and the gate electrode wiring GC. A buried formation region is shown. A region where the first silicon nitride film 12 is formed is defined as a non-silicide layer formation region.

As shown in FIG. 1, the gate electrode wiring GC is formed so as to extend in a direction perpendicular to the direction in which the active areas AAn and AAp are formed, and is divided in view of the circuit configuration in order to form the SRAM cell M. Yes. Specifically, as shown in FIG. 2, the gate electrode wiring GC is divided on the element isolation region STI.
In addition, a spacer Sp is formed in the divided portion of the gate electrode wiring GC. The spacer Sp is formed of, for example, a silicon nitride film or a silicon oxide film, and is formed on the side walls of the first polycrystalline silicon film 6 and the first silicon nitride film 12 so as to protect the gate electrode wiring GC. Yes. A second silicon nitride film 8 is formed so as to cover these gate electrode wiring GC, first silicon nitride film 12 and spacer Sp.

The second silicon nitride film 8 is formed on the tungsten silicide layer 7, the first silicon nitride film 12, and the spacer Sp. Holes Ha are formed in the first and second silicon nitride films 8 and 12 in the shared contact formation region SC2.
On the silicon nitride film 8, an interlayer insulating film 9 made of, for example, a BPSG film is formed. Further, a contact hole H is formed in the first and second silicon nitride films 8 and 12 and the interlayer insulating film 9.

  A barrier metal film 10 made of Ti (titanium) or TiN (titanium nitride) is formed in the contact hole H, and a tungsten film 11 is embedded on the barrier metal film 10. The barrier metal film 10 prevents the tungsten film 11 from contacting other films. The contact plug P is composed of the barrier metal film 10 and the tungsten film 11 and is configured to electrically connect the gate electrode wiring GC and the upper layer wiring (not shown).

  The contact plug P is formed by a so-called shared contact structure. As shown in FIGS. 1 and 2B, the gate electrode of the transistor TL1 is electrically connected to the drain region of the transistor TL2, or the upper layer wiring is formed. It is formed so as to be electrically connected to the drain region of transistor TD2 through a layer (not shown). As shown in FIG. 2B, a contact region CC for reducing contact resistance is formed in the source / drain diffusion layer SD region of the transistor TL2. The contact region CC is formed by silicidizing the upper portion of the source / drain diffusion layer SD of the transistor by a salicide process.

  As shown in FIGS. 1, 2A, and 2B, in shared contact formation region SC2, a p-type drain diffusion layer in which contact plug P is formed in N well region Nw of silicon semiconductor substrate 1 is used. The SD contact region CC and the first polycrystalline silicon film 6 are formed to be electrically conductive. Therefore, in shared contact formation region SC2, the contact region CC of drain diffusion layer SD of transistor TL2 and first polycrystalline silicon film 6 in shared contact formation region SC2 are substantially conductive.

  In addition, as shown in FIG. 1, a word line contact region CW for connection to the word line WL, a bit line contact region CB for connection to the bit lines BL, / BL, and a power supply (Vdd) contact A structure for connecting the region CD, the ground (Vss) contact region CS, and the gate electrode of the transistor TL2 to the drain regions of the transistors TL1 and TD1 is configured. In FIG. 1, the node N1 is electrically connected by an upper wiring layer (not shown) in the shared contact region SC1 and the node contact region NC1. Further, the node N2 is electrically connected by an upper wiring layer (not shown) in the shared contact region SC2 and the node contact region NC2.

<About manufacturing method>
Hereinafter, the SRAM cell manufacturing method will be described with reference to FIGS. 4 to 13, particularly focusing on the portions related to the characteristics of the manufacturing method of the present embodiment. 4 to 13 schematically show cross-sectional views along the line AA ′ in FIG. 1, and each show one manufacturing process of the main part.

First, a process for forming the structure shown in FIG. 4 will be described. A silicon oxide film (not shown) is formed on the silicon semiconductor substrate 1, and a mask material (for example, a silicon oxide film and / or a silicon nitride film: not shown) is formed thereon. Further, a resist (not shown) is patterned on the mask material so as to cover the active area AA.
Using this resist (not shown) as a mask, the mask material is removed by etching to form a hole for forming the element isolation region STI, and further, the trench 2 is formed using the resist or the remaining mask material as a mask. Further, the first silicon oxide film 3 is formed on the inner surface of the trench 2 by thinly oxidizing the inner surface of the trench 2. N well Nw and p well (not shown in FIG. 4) are formed, and the resist is removed by ashing.

  A third silicon oxide film (STI-TEOS film) 5 is buried and formed on the first silicon oxide film 3 formed on the inner surface of the trench 2. Then, the third silicon oxide film 5 is planarized using the remaining mask material as a mask, and the mask material is removed. Further, a second silicon oxide film 4 is formed as a gate insulating film by oxidizing the silicon semiconductor substrate 1. Then, an N well region Nw and a P well region Pw are formed.

  Next, as shown in FIG. 5, a first polycrystalline silicon film 6 is formed on second and third silicon oxide films 4 and 5, and a first polycrystalline silicon film 6 is formed on first polycrystalline silicon film 6. 1 silicon nitride film 12 is formed. The first silicon nitride film 12 is formed with a thickness of, for example, 400 angstroms. This film thickness is adjusted to such an extent that no void is generated between the adjacent gate electrode wirings GC when the interlayer insulating film 9 is buried and formed in a subsequent process.

  Next, a resist (not shown) is applied on the first silicon nitride film 12, and this resist is patterned by lithography. As shown in FIG. 6, a non-silicide including the shared contact formation region SC2 is formed. The first silicon nitride film 12 formed in the silicide layer formation region SL is removed so that the first silicon nitride film 12 remains in the layer formation region. Finally, the portion of the first polycrystalline silicon 6 below the remaining region of the first silicon nitride film 12 becomes a high resistance region.

Next, as shown in FIG. 7, a resist (not shown) is applied on the first polycrystalline silicon film 6 and the first silicon nitride film 12, and this resist is patterned by a lithography method. The silicon nitride film 12 and the first polycrystalline silicon film 6 are divided, and the resist is removed by ashing.
Next, as shown in FIG. 8, a silicon nitride film is formed as a spacer Sp on the side walls of the divided first polycrystalline silicon film 6 and first silicon nitride film 12.

Next, as shown in FIG. 9, a diffusion layer 13 is formed in the source / drain diffusion layer region of the silicon semiconductor substrate 1 by implanting impurities into the P well Pw and N well Nw regions. At this time, the impurity implantation amount is made smaller than the impurity implantation amount of the conventional method so as to reduce the amount of impurities implanted into the first polycrystalline silicon film 6. For example, in the conventional method, about 4.0 × 10 ¹⁵ [cm ⁻² ] of boron (B) is implanted into the source / drain diffusion layer of a P-type MOS transistor. It is 3.0 × 10 ¹⁵ [cm ⁻² ].

  At this time, it is also effective to reduce the acceleration voltage for impurity implantation. For example, when an impurity is implanted with an acceleration voltage of 5 [keV] conventionally performed at 7 [keV], the implanted impurity stays in the first silicon nitride film 12 and enters the first polycrystalline silicon film 6. Impurities are not implanted. At this time, since almost no impurities are implanted into the first polycrystalline silicon film 6 under the remaining region of the first silicon nitride film 12, the first polycrystalline silicon under the remaining region of the first silicon nitride film 12 is used. The film 6 has a higher resistance than the region where the impurity is implanted.

  Thereafter, as shown in FIG. 10, the acceleration voltage is raised and impurity implantation is performed by the second acceleration voltage to adjust the resistance value in the first polycrystalline silicon film 6. At this time, as shown in FIG. 10A, the ion concentration at the time of ion implantation takes a peak value Rp at a predetermined position in the height direction, and the first silicon nitride film 12 and the first The polycrystalline silicon film 6 is diffused and distributed in the height direction (vertical direction in the figure). At this time, as shown in FIG. It is desirable that the acceleration voltage be set in the polycrystalline silicon film 6.

In addition, it is desirable to implant impurity ions while setting the acceleration voltage to an acceleration voltage (second acceleration voltage: for example, 15 [keV]) higher than 5 [keV] (first acceleration voltage). Furthermore, the second ion implantation amount (for example, 5.0 × 10 ^{13 to} 5.0) lower than the first ion implantation amount (for example, 3.0 × 10 ¹⁵ [cm ⁻² ]), for example. × 10 ¹⁴ [cm ⁻² ] is preferable. In other words, it is desirable that the ion implantation amount at the time of impurity implantation be lower by one to two digits than the first impurity ion implantation amount.

Then, in the process of forming a large number of SRAM cells M, even if a variation in film thickness occurs during the formation of the first silicon nitride film 12, the variation in the amount of impurity implantation into the first polycrystalline silicon film 6 is small. Therefore, the resistance value change is reduced. The impurity ion implantation process may be performed twice, three times, or more as necessary if the implantation is performed in a plurality of times.
In this case, as shown in FIG. 10, when the impurity ions are implanted for the second time, the impurity ions may reach the silicon semiconductor substrate 1, but the impurity ion concentration during ion implantation is the first ion. Since it is lower than the implantation amount, even if the impurity ions reach the active area AA in the silicon semiconductor substrate 1, the short channel effect is not deteriorated, and the threshold voltage adjustment error of the transistor Tr can be almost ignored. It will be about.

  Thus, the second impurity ion implantation step does not adversely affect the characteristics of the transistor Tr. This transistor Tr is a general transistor formed on the silicon semiconductor substrate 1, and even if it is the transistors TL1, TD1, TL2, TD2, TS1, TS2 constituting the SRAM cell M, the SRAM cell M It may be a transistor or the like constituting a peripheral circuit for driving.

  And as shown in FIG. 11, by carrying out the salicide reaction of cobalt with the 1st polycrystalline silicon film 6 by carrying out the sputtering process of the metal by cobalt etc., by removing the cobalt of the part which has not reacted, A metal silicide layer 7 is formed on the first polycrystalline silicon film 6 except under the remaining region of the first silicon nitride film 12, and a silicide layer non-formed region is formed under the remaining region of the second silicon nitride film 12. Is generated.

  Then, a second silicon nitride film 8 is formed thereon as shown in FIG. 12, and an interlayer insulating film 9 made of a silicon oxide film (for example, a BPSG (Boron-phosphosilicate glass) film) is buried and formed thereon. . Then, as shown in FIG. 13, contact hole H is formed in interlayer insulating film 9 and first and second silicon nitride films 12 and 8. In FIG. 13, contact hole H is formed on so-called shared contact formation region SC2 on first polycrystalline silicon film 6 and above.

  Thereafter, a metal barrier layer 10 is formed on the inner surface of the contact hole H, and a tungsten layer 11 is embedded on the metal barrier layer 10 to form a contact plug P. At the same time, various contacts such as inter-node contacts, power supply line contacts, and ground line contacts are formed. At this time, when the contact hole H is formed in the first silicon nitride film 12 in the shared contact formation region SC2 and the contact plug P is buried, the contact plug P and the first polycrystal are formed in the portion where the metal silicide layer 7 is not formed. Since the silicon layer 6 comes into contact, the first silicon nitride film 12 and the first polycrystalline silicon film 6 in the shared contact formation region SC2 are compared with the case where they are electrically connected through the metal silicide layer. The interfacial resistance at the interface increases. The resistance value of the resistance element R1 can be adjusted by adjusting the distance between the contact plug P formation region and the metal silicide layer 7 formation region. The resistance element R1 can be configured by such a process. Further, an upper wiring layer is formed. The same applies to the resistance element R2. Through these steps, the SRAM cell M of the SRAM semiconductor memory device 1 can be formed.

  As described above, the manufacturing method of the present embodiment has the following characteristics. That is, first, when manufacturing the SRAM cell M, the element isolation region STI is formed in the silicon semiconductor substrate 1. A second silicon oxide film 4 is formed on the silicon semiconductor substrate 1 as a gate insulating film. Thereafter, a first polycrystalline silicon film 6 is formed on the second silicon oxide film 4. Thereafter, a first silicon nitride film 12 is formed on the first polycrystalline silicon film 6. Thereafter, the first silicon nitride film 12 is removed so as to leave the first silicon nitride film 12 around the region SC2 including the shared contact formation region SC2 of the first silicon nitride film 12. Further, source / drain diffusion layers SD and 13 are formed by performing the first impurity ion implantation from above the first silicon nitride film 12 with a predetermined first acceleration voltage and a first implantation amount. Then, impurities are ion-implanted into the first polycrystalline silicon film 6 under the condition that the acceleration voltage is higher than the first acceleration voltage and the second implantation amount is lower than the first implantation amount. As a result, the resistance value of the first polycrystalline silicon film 6 is adjusted. Thereafter, the upper portion of the first polycrystalline silicon film 6 except for the portion where the first silicon nitride film 12 is formed is silicided by, for example, a salicide process, thereby forming the metal silicide layer 7 and forming the gate electrode wiring GC.

  According to such a manufacturing method according to the present embodiment, the source / drain diffusion layer 13 is formed or the first multi-layer is formed by ion-implanting impurities by adjusting the acceleration voltage and the implantation amount in a plurality of times. Since the resistance value of the crystalline silicon film 6 is adjusted, the characteristics of the transistor formed on the silicon semiconductor substrate 1 can be adjusted to a desired value, and the value of the resistance element R1 of the gate electrode wiring GC can be adjusted. It becomes like this.

  Moreover, for adjusting the resistance of the first polycrystalline silicon film 6, impurity ions are implanted with a second acceleration voltage higher than the first acceleration voltage, and the ion implantation amount at that time is higher than the first implantation amount. Since the second implantation amount is low, the SRAM cell M can be formed without causing adverse effects on the characteristics such as the short channel effect and the threshold voltage of other transistors formed on the silicon semiconductor substrate 1. .

The gate electrode wiring GC is increased in resistance in accordance with the interface resistance between the contact plug P and the first polycrystalline silicon film 6 and the distance between the contact plug P and the metal silicide layer 7. Since R1 can be formed, it is possible to take measures against soft errors in the SRAM cell M.
(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.

Although the embodiment applied to the SRAM semiconductor memory device 1 is shown, any semiconductor device including the SRAM cell M can be applied to other semiconductor devices such as an SRAM embedded logic integrated circuit device.
In the embodiment, when the second ion implantation is performed, impurities are ion-implanted into the first polycrystalline silicon film 6 under the condition that the second implantation amount is lower than the first implantation amount. However, if ions are implanted at a higher acceleration voltage than at the time of the first ion implantation at the time of the second ion implantation, the first implantation is performed under the condition of the same implantation amount or a higher implantation amount with respect to the first ion implantation amount. Impurities may be ion-implanted into the polycrystalline silicon film 6.

  Although the embodiment in which the metal silicide layer 7 is formed by siliciding the upper portion of the first polycrystalline silicon film 6 as the gate electrode wiring GC is shown, an amorphous silicon film is used instead of the first polycrystalline silicon film 6. You may apply to.

The top view which shows an example of the layout of the cell array pattern in which the SRAM cell which shows one Embodiment of this invention was arranged in matrix form Schematic sectional view of the main part ((a) is a sectional view taken along the line AA ′ in FIG. 1, (b) is a sectional view taken along the line B-B ′ in FIG. 1) Equivalent circuit diagram of SRAM cell Sectional drawing which shows one manufacturing process of the principal part in FIG. 2 (the 1) Sectional drawing which shows one manufacturing process of the principal part in FIG. 2 (the 2) Sectional drawing which shows one manufacturing process of the principal part in FIG. 2 (the 3) Sectional drawing which shows one manufacturing process of the principal part in FIG. 2 (the 4) Sectional drawing which shows one manufacturing process of the principal part in FIG. 2 (the 5) Sectional drawing which shows one manufacturing process of the principal part in FIG. 2 (the 6) Sectional drawing which shows one manufacturing process of the principal part in FIG. 2 (the 7) Sectional drawing which shows one manufacturing process of the principal part in FIG. 2 (the 8) Sectional drawing which shows one manufacturing process of the principal part in FIG. 2 (the 9) Sectional drawing which shows one manufacturing process of the principal part in FIG. 2 (the 10)

Explanation of symbols

In the drawings, 1 is a silicon semiconductor substrate (semiconductor substrate), 4 is a second silicon oxide film (first insulating film), 6 is a first polycrystalline silicon film (conductive layer), and 12 is first silicon nitride. A film (second insulating film), 13 is a source / drain diffusion layer, GC is a gate electrode wiring, and Tr is a transistor.

Claims (4)

Forming a conductive layer on a semiconductor substrate via a first insulating film;
Forming a second insulating film on the conductive layer;
Removing the second insulating film formed on the conductive layer except for the non-silicide layer formation region on the conductive layer;
A step of ion-implanting impurities from above the conductive layer at a predetermined first acceleration voltage to form a diffusion layer in the semiconductor substrate;
Adjusting the resistance value of the conductive layer by ion-implanting impurities into the conductive layer with a second acceleration voltage that is higher than the first acceleration voltage;
And a step of siliciding the upper portion of the conductive layer other than the non-silicide layer formation region. Forming a conductive layer on a semiconductor substrate via a first insulating film;
Forming a second insulating film on the conductive layer;
Removing the second insulating film formed on the conductive layer except for the non-silicide layer formation region on the conductive layer;
A step of ion-implanting impurities from above the conductive layer with a predetermined first acceleration voltage and a first implantation amount to form a diffusion layer in the semiconductor substrate;
Impurities are ion-implanted into the conductive layer under a second acceleration voltage condition that is higher than the first acceleration voltage and under a second implantation amount that is lower than the first implantation amount. Adjusting the resistance value of the conductive layer by:
And a step of siliciding the upper portion of the conductive layer other than the non-silicide layer formation region.   3. The method of manufacturing a semiconductor device according to claim 1, wherein a silicon nitride film is formed as the second insulating film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein a polycrystalline silicon film is formed as the conductive layer.

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