JP2006012870A - Manufacturing method of stack via structure multilayer wiring board - Google Patents

Manufacturing method of stack via structure multilayer wiring board Download PDF

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JP2006012870A
JP2006012870A JP2004183209A JP2004183209A JP2006012870A JP 2006012870 A JP2006012870 A JP 2006012870A JP 2004183209 A JP2004183209 A JP 2004183209A JP 2004183209 A JP2004183209 A JP 2004183209A JP 2006012870 A JP2006012870 A JP 2006012870A
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plating
post
forming
wiring board
conductor circuit
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Satoshi Ishiguro
石黒智
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for improving adhesion with a lower layer conductor circuit in an interlayer connection post formed on the lower layer conductor circuit by electrolytic plating and uniforming plating height, and to provide the manufacturing method of a multilayer wiring board using the method. <P>SOLUTION: A feeding conductive thin film layer is installed on a whole face including the lower layer conductor circuit on an insulating substrate where the lower layer conductor circuit is arranged. A plating resist layer is formed on the whole face. The substrate is anode-connected in electrolyte, and voltage is applied in a state where an opening for plating-forming the post on the connected lower layer conductor circuit is formed in the resist layer. Thus, the whole feeding conductive thin film layer and a part of the lower layer conductor circuit of a part with the post formed thereon are dissolved and removed. The post is formed in metal plating liquid by depositing electrolytic plating in the opening. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明はスタックビア構造多層配線基板の製造方法に係わるものであり、複数層の配線回路を有する多層配線基板の異なる回路層の電気的接続を電解金属メッキにより形成されたポストを利用して行う多層配線板の製造方法及びその多層配線板に関するものである。 The present invention relates to a method for manufacturing a multilayer via substrate having a stacked via structure, and performs electrical connection of different circuit layers of a multilayer interconnection substrate having a plurality of layers of wiring circuits by using posts formed by electrolytic metal plating. The present invention relates to a method for manufacturing a multilayer wiring board and the multilayer wiring board.

電子機器の小型軽量薄型化が進むなかに於いて配線版基板はビルドアップ構造を採用することになったが今日の更なる高密度化要求に応える為従来のスタッガービア構造からスタックビア構造化が求められている。 As electronic devices are becoming smaller, lighter and thinner, the wiring board has adopted a build-up structure, but in order to meet today's demand for higher density, the stack via structure has been changed from the conventional staggered via structure. It has been demanded.

このスタックビア構造を実現する工法は各種提案されており例えば、図2に示す様な導体回路層202を設けた絶縁基材201に絶縁層203を形成しこれに接続用穴(ヴィアホール)204を加工しこの穴を導電性ペースト205を充填する方法もしくは図3に示す様なメッキにて充填(フィルドメッキ法)する工法がある。
この時の穴加工方法としては感光性絶縁材料を露光現像にて加工するもの、熱硬化性樹脂を形成後レーザー加工するものがあるが前者材料は未だ安定した加工が出来ず微細化が難しいこと、後者は1穴づつ加工しなくてはならず高密度化が進み加工穴数も増大するにつれ加工時間が増大すること及び高価なレーザー加工機が必要なことから量産性及びコスト面で問題が生じている。
更にペースト充填ではその電気接続信頼性が、メッキ充填ではメッキ液安定性に課題が残されており量産工法としては未だ確立されていない。
Various methods for realizing this stacked via structure have been proposed. For example, an insulating layer 203 is formed on an insulating base material 201 provided with a conductor circuit layer 202 as shown in FIG. 2, and a connection hole (via hole) 204 is formed in the insulating layer 203. There is a method of filling the hole with a conductive paste 205 or a method of filling with a plating as shown in FIG. 3 (filled plating method).
There are hole processing methods at this time, one that processes photosensitive insulating material by exposure and development, and one that laser-processes after forming a thermosetting resin, but the former material is still difficult to process and difficult to miniaturize. However, the latter has to be processed one hole at a time, and as the number of processed holes increases and the number of processed holes increases, the processing time increases and an expensive laser processing machine is required. Has occurred.
Furthermore, the electrical connection reliability remains in paste filling and the plating solution stability remains in plating filling, and the mass production method has not yet been established.

一方絶縁層を形成する前に接続用導電性突起物を形成しこれを埋設するように絶縁層を形成する工法も多く提案されている。
例えば図4に示す様な下部導体回路402もしくは下層導体回路形成用導体層上に印刷により導電性ペースト403を突起状に形成後この上に上部回路形成用導体層405付き絶縁層404を加工するもの、或いは図5に示す様な、この導電性突起物506を下層導体回路502上又は上層導体回路形成用導電層上に金属を全面メッキ504してからこの上にエッチングレジスト505を露光現像し接続用突起物を形成するものがあるが、前者はスクリーン印刷にて形成する為その微細化が難しい点で、後者は下部回路又は上部回路形成用導電層をエッチング液から保護する為エッチングバリアー層503として突起物形成用金属とは異種の金属薄膜層を予め形成しておき突起物をエッチング形成後選択的エッチング液にてエッチング除去する工程をとる為工数及びコスト的な点で課題が残ること及び更なる微細化要求に於いて突起物の径が小さくなった際の密着力の問題がある。
On the other hand, many methods have been proposed in which a conductive conductive protrusion for connection is formed before the insulating layer is formed, and the insulating layer is formed so as to be embedded.
For example, a conductive paste 403 is formed in a protruding shape by printing on a lower conductor circuit 402 or a lower conductor circuit forming conductor layer as shown in FIG. 4, and an insulating layer 404 with an upper circuit forming conductor layer 405 is processed thereon. As shown in FIG. 5, the conductive protrusions 506 are plated with metal 504 on the lower conductor circuit 502 or the upper conductor circuit forming conductive layer 504, and then the etching resist 505 is exposed and developed thereon. Some of them form connection protrusions, but the former is difficult to miniaturize because it is formed by screen printing, and the latter is an etching barrier layer to protect the lower circuit or upper circuit forming conductive layer from the etching solution. A metal thin film layer different from the projection forming metal is formed in advance as 503, and the projection is etched and then removed by selective etching. Step there is adhesion problems when the diameter of the man-hours and cost of protrusions at that challenges remain and further miniaturization request at a point is reduced for taking.

上記に説明した工法の他に導電性突起物を直接金属電解メッキで行う工法(以降電解メッキで形成された導電性突起物をポストと呼ぶ)が特開平6−314878号公報に開示されており、該工法は工程が既存技術の組み合わせで且つ簡素でありコスト的に有利且つ小径ポストが形成出来ることにて優れた工法であるが、微細化に伴うポスト小径化により密着力が不足すること及びレジスト開口部がランダムに粗密に配置される為の電流密度不均一によりポスト高さ均一性が低く絶縁層形成後の研削研磨によりポスト頭頂部を均一の高さで全て露出させるのが困難であることに問題があることが解った In addition to the above-described method, a method of conducting conductive protrusions directly by metal electrolytic plating (hereinafter, conductive protrusions formed by electrolytic plating are referred to as posts) is disclosed in JP-A-6-314878. The method is a combination of existing techniques, simple and advantageous in terms of cost, and excellent in that a small-diameter post can be formed. Post height uniformity is low due to non-uniform current density due to randomly and densely arranged resist openings, and it is difficult to expose all the tops of the post at a uniform height by grinding and polishing after forming the insulating layer. I found that there was a problem

この工法を図6を用いながら以下に説明する。
給電用導電性薄膜層602を基材601全面に形成し(図6−a)メッキレジストを回路形状に加工した後パターン電解メッキを行って下層導体回路602を形成した後(図6−b)この上にポスト形成用開口605を持ったメッキレジスト604を形成して(図6−c)、この給電用導電性薄膜層602を利用して開口部を電解銅メッキで充填してポスト606を形成する(図6−d)。その後レジストパターン及び給電用導電性薄膜層を除去し(図6−e)絶縁層607をポストを埋め込む形で形成(図6−f)、ポストの高さと同一になる様研削研磨する(図6−g)。その後絶縁層上に給電膜を設け図6−b同様上層導体回路を形成しポスト接続された多層配線板を製造する(図6−h)。
特開平6−314878号
This construction method will be described below with reference to FIG.
After the conductive thin film layer 602 for feeding is formed on the entire surface of the substrate 601 (FIG. 6A), the plating resist is processed into a circuit shape, and then pattern electroplating is performed to form the lower conductor circuit 602 (FIG. 6B). A plating resist 604 having a post forming opening 605 is formed thereon (FIG. 6C), and the opening 606 is filled with electrolytic copper plating by using the conductive thin film layer 602 for feeding. Form (FIG. 6-d). Thereafter, the resist pattern and the conductive thin film layer for power feeding are removed (FIG. 6E), and the insulating layer 607 is formed so as to embed the post (FIG. 6F), and is ground and polished so as to have the same height as the post (FIG. 6). -G). Thereafter, a power feeding film is provided on the insulating layer to form an upper conductor circuit as in FIG. 6B, and a post-connected multilayer wiring board is manufactured (FIG. 6H).
JP-A-6-314878

以上の様に電解金属メッキで形成したポストにより下層導体回路と上層導体回路を電気的に接続する工法は低コストで優れたものではあるが、微細化要求のため小径化するポストの密着力及びレジスト開口部がランダム且つ粗密に配置される為の電流密度不均一による高さバラツキに対する解決が強く望まれている。 As described above, the method of electrically connecting the lower layer conductor circuit and the upper layer conductor circuit by the post formed by electrolytic metal plating is excellent at low cost. There is a strong demand for a solution to variations in height due to non-uniform current density because the resist openings are randomly and densely arranged.

本発明は下層導体回路が形成された絶縁基材全面に給電用導電性薄膜及びその上に回路接続用ポスト形成の為の開口部を設けたメッキレジスト層が形成された状態の基材を電解質溶液中にて陽極電圧印加することでポストが電解金属メッキ形成される下層導体回路上の給電用導電性薄膜の全部及び下層導体回路の一部を溶解除去しメッキ接合面積を大きくすることで密着力を強化し且つ陽極電圧印加する際の電流密度分布を金属電解メッキ時の電流密度分布と相似にするか又は電解メッキ時の電流密度が高い部分はより高い電流密度且つ低い部分はより低い電流密度分布となる様に対向電極をレイアウトした状態で陽極電圧印加し給電用導電性薄膜層の全部及び回路導体の一部を溶解除去することで電流密度の高い部分の溶解除去量を多くし電流密度の低い部分の溶解除去量を少なくすることにより電解金属メッキにより形成されるポスト高さの均一性を良好なものとする。 The present invention relates to a substrate in a state in which a conductive thin film for feeding is formed on the entire surface of an insulating substrate on which a lower conductor circuit is formed and a plating resist layer on which an opening for forming a circuit connection post is formed is formed as an electrolyte. By applying an anode voltage in the solution, the post is electrolytically plated with metal. The entire conductive thin film for power supply on the lower conductor circuit and a part of the lower conductor circuit are dissolved and removed to increase the plating bonding area. The current density distribution when strengthening the force and applying the anode voltage is similar to the current density distribution during metal electroplating, or the higher current density during electroplating is higher and the lower current is lower current. By applying an anode voltage with the counter electrode laid out so as to obtain a density distribution and dissolving and removing all of the conductive thin film layer for power feeding and part of the circuit conductor, the amount of dissolution removal in the portion with high current density is increased. And favorable uniformity post height is formed by electroless metal plating by reducing the dissolving and removing of the lower part of the flow density.

以上説明した様に、ポスト接続する構造の多層配線板の製造方法において、メッキレジスト層にポストをメッキ形成する為の開口部を形成した状態の絶縁基材を電解質溶液中にて、電解金属メッキ時の電流密度分布が相似となるか又は電解メッキ時の電流密度が高い部分はより高く且つ低い部分はより低い電流密度分布となる様に対向陰極をレイアウトした状態で陽極電圧印加し、給電用導電性薄膜の全部及び下層回路導体の一部を溶解除去して、ポストを形成するメッキ金属と下層回路導体のメッキ接合面積を大きくし良好な密着力を得ると共に、金属電解メッキ時の電流密度分布に応じその電流密度が高い部分の下層回路導体溶解除去量は多く且つ電流密度が低い部分の下層回路導体溶解除去量は小さくすることで金属メッキによるポスト形成時の高さ均一性を良好とすることができる。
これにより高い接続信頼性を有したスタックビア構造多層配線板をフィルドメッキの様な新規技術を用いることもなく又レーザー加工機の様な高価な設備を使用することもなく製造できる。
As described above, in the method of manufacturing a multilayer wiring board having a post connection structure, an insulating base material in a state where an opening for plating a post is formed in a plating resist layer is formed by electrolytic metal plating in an electrolyte solution. The anode current is applied in a state where the counter cathode is laid out so that the current density distribution at the time is similar or the current density distribution at the time of electrolytic plating is higher and the lower current density distribution is lower. Dissolve and remove all of the conductive thin film and part of the lower circuit conductor to increase the plating bonding area between the plated metal forming the post and the lower circuit conductor to obtain good adhesion, and the current density during metal electrolytic plating Depending on the distribution, the amount of dissolution and removal of the lower layer circuit conductor in the part where the current density is high and the amount of dissolution and removal of the lower layer circuit conductor in the part where the current density is low are reduced. The height uniformity of the formation can be improved.
As a result, a stacked via structure multilayer wiring board having high connection reliability can be manufactured without using a new technique such as filled plating and without using expensive equipment such as a laser processing machine.

図1を参照しながら本発明の実施形態に付いて以下に説明する。尚、説明を簡素化する為絶縁層が1層の場合として説明する。
図面1に於いて図1−(a)はコアとなる銅張り基板の絶縁基材101に予め形成された下層導体回路102を示す。回路形成の方法は特に規定されない例えばエッチングレジストを用いたサブトラクト法でもメッキレジストを用いたセミアディティブ法でも作製出来る。
An embodiment of the present invention will be described below with reference to FIG. In order to simplify the description, the case where there is one insulating layer will be described.
In FIG. 1, FIG. 1- (a) shows a lower layer conductor circuit 102 formed in advance on an insulating base material 101 of a copper-clad substrate to be a core. The circuit formation method is not particularly defined, and can be produced by, for example, a subtract method using an etching resist or a semi-additive method using a plating resist.

図1−(b)は下層導体回路102を含む絶縁基材101全面にポストを電解金属メッキ形成させる際に給電膜となる給電用導電性薄膜層103を形成した状態を示す。この導電性薄膜層に用いられる材料は金属でも導電性有機膜でも構わないがその取り扱いから金属が好ましく、金属の場合はポスト形成金属と同種金属でも異種金属でも構わない、また下層導体回路材料と同種金属でも異種金属でも構わない。またその形成方法も無電解メッキ法でもスパッタリング法等を用ちいても或いはこの薄膜層上に若干の電解メッキを施して形成しても構わない。 FIG. 1- (b) shows a state in which a power supply conductive thin film layer 103 serving as a power supply film is formed on the entire surface of the insulating base material 101 including the lower conductor circuit 102 when a post is formed by electrolytic metal plating. The material used for the conductive thin film layer may be a metal or a conductive organic film, but a metal is preferable in terms of its handling. In the case of a metal, it may be the same kind of metal as the post-forming metal or a different kind of metal. The same kind of metal or different kind of metal may be used. The formation method may be an electroless plating method, a sputtering method, or the like, or a slight electrolytic plating on the thin film layer.

図1−(c)は給電用導電性薄膜層103上にメッキレジスト層104を形成した状態を示す。メッキレジスト材料としては特に規定されないが感光性樹脂を用いてカーテンコーター塗布やスクリーン印刷で形成する方法や又はフィルム状の感光性樹脂フィルムをロールラミネーターで熱圧着する方法等が有る。 FIG. 1- (c) shows a state in which a plating resist layer 104 is formed on the conductive thin film layer 103 for power supply. Although it does not prescribe | regulate especially as a plating resist material, there exist the method of forming by a curtain coater application | coating or screen printing using photosensitive resin, or the method of thermocompression-bonding a film-like photosensitive resin film with a roll laminator.

図1−(d)はメッキレジスト層104へポスト形成の為の開口部105を形成した状態を示す。開口方法は感光性樹脂層を露光・現像にて所定の位置に所望するポスト径に応じて形成すれば良い。現像形成後ポストキュアーの処理を施してレジストの密着力を上げたり、またはプラズマ処理等によりレジストスカムの除去やレジスト材質改変によるメッキ濡れ性の向上を行こなえばポスト形成時に一層良好な結果が得られる。 FIG. 1D shows a state in which an opening 105 for forming a post is formed in the plating resist layer 104. As the opening method, the photosensitive resin layer may be formed at a predetermined position in accordance with a desired post diameter by exposure and development. If post-curing treatment is applied after development to increase the adhesion of the resist, or removal of resist scum or improvement of plating wettability by modifying the resist material by plasma treatment, etc., better results will be obtained during post formation. It is done.

図1−(e)は上記基材に電解質溶液中にて陽極電圧印加してレジスト開口部下の給電用導電性薄膜層103の全部及び下層導体回路102の一部を溶解除去した状態を示す。これはポストの密着力を強固なものとする為ポスト形成用メッキ金属と下層導体回路とのメッキ接合面積を大きくする目的及び陽極電圧印加時の電流密度を電解メッキ時の電流密度と相似となるか或いは電解メッキ時の電流密度が高い部分はより高く、低い部分はより低い電流密度分布となる様に陽極電圧印加時の対向電極をレイアウトした状態で溶解処理することにより溶解量が電解金属メッキ時の電流密度が高い部分では多く除去
され、低い部分では少なく除去されることからポスト形成時の高さを均一化する目的で行う。
FIG. 1- (e) shows a state in which an anode voltage is applied to the base material in an electrolyte solution to dissolve and remove all of the power supply conductive thin film layer 103 and a part of the lower conductor circuit 102 under the resist opening. The purpose of this is to increase the adhesion of the post, and to increase the plating junction area between the post-forming plated metal and the lower conductor circuit, and the current density when applying an anode voltage is similar to the current density during electrolytic plating. Alternatively, the amount of dissolution can be reduced by electrolytic metal plating by performing dissolution treatment in a state where the counter electrode is laid out so that the current density distribution at the time of electrolytic plating is higher and the lower portion has a lower current density distribution. This is performed for the purpose of uniformizing the height at the time of post formation since a large amount is removed at a portion where the current density is high and a small amount is removed at a low portion.

この際電解質溶液がポスト形成用開口部内にて良好に循環される様液撹拌を行うがこの方法としてエアー撹拌やポンプ循環撹拌等あるがより効果的に行う為開口部へ直接液をノズルからポンプ加圧噴出させる噴流式撹拌方法が有効である。 At this time, liquid agitation is performed so that the electrolyte solution is circulated well within the opening for forming the post. As this method, there are air agitation and pump circulation agitation, but in order to perform it more effectively, the liquid is directly pumped from the nozzle to the opening. A jet-type stirring method for jetting pressure is effective.

また電解質溶液としては硫酸及び過酸化水素水の混合液又は塩化アンモニウムとアンモニア水又は過硫酸アンモニウム又は塩化第1鉄と塩酸又は塩化第二銅と塩酸等があるがポストを形成する為の電解金属メッキ液を用いても良い。
またその処理の為の電解装置及び槽をポスト形成用電解金属メッキ装置に組み込込むことで連続処理化し設備コスト及び加工工数を低減することも出来る。
The electrolyte solution includes a mixed solution of sulfuric acid and hydrogen peroxide solution, or ammonium chloride and ammonia water, ammonium persulfate, ferrous chloride and hydrochloric acid, or cupric chloride and hydrochloric acid. A liquid may be used.
Further, by incorporating the electrolytic apparatus and tank for the treatment into the post-forming electrolytic metal plating apparatus, it is possible to perform continuous treatment and to reduce the equipment cost and the number of processing steps.

図1−(f)電解金属メッキによりレジスト開口部に金属がポスト106として析出充填された状態を示す。この金属は前記給電用導電性薄膜層103と及び下層導体回路102と同種金属でも異種金属でも良いが、その電気導通性や液管理の容易さから銅が好ましい。 FIG. 1- (f) shows a state where metal is deposited and filled as a post 106 in the resist opening by electrolytic metal plating. This metal may be the same or different metal from the conductive thin film layer 103 for power feeding and the lower conductor circuit 102, but copper is preferred because of its electrical conductivity and ease of liquid management.

電流通電条件としては通常のメッキ用整流器を用いても良いがポストの高さ均一性をさらに良好とし且つメッキ時間を短縮させる目的でステップ制御式整流器にて、メッキ初期に於けるレジスト開口部底部乃至底部に近い部分をメッキする際は電流が入り込み難く電流密度分布が悪くなる為低電流としメッキが成長するにつれ電流が入り込みやすくなったら高電流化する方法で行っても良い。或いはパルス電流通電により高さの均一化を図っても良い。 A normal plating rectifier may be used as the current-carrying condition, but the bottom of the resist opening in the initial stage of plating is a step-controlled rectifier for the purpose of further improving post height uniformity and shortening the plating time. Alternatively, when plating the portion close to the bottom, current does not easily enter and the current density distribution deteriorates. Therefore, the current may be lowered, and if the current becomes easier to enter as the plating grows, the current may be increased. Alternatively, the height may be made uniform by applying a pulse current.

またメッキ液が硫酸銅メッキ液の場合メッキ高さの均一化を保ちながら高い電流密度でメッキ可能とする為液組成を高濃度硫酸銅、低濃度硫酸浴化すると効果的である。またこの場合浴に見合ったメッキ添加剤を選択する事でさらに効果は高まる。 When the plating solution is a copper sulfate plating solution, it is effective to use a high concentration copper sulfate or low concentration sulfuric acid bath so that the plating can be plated at a high current density while keeping the plating height uniform. In this case, the effect is further increased by selecting a plating additive suitable for the bath.

メッキ液撹拌方法としては通常のエアー撹拌でも良いが小径レジスト開口部へ効率良く金属イオンを循環させメッキ電流密度を高くしてメッキ時間を短縮する為レジスト開口部へ直接メッキ液をノズルなどからポンプ加圧噴出させる噴流撹拌を用いると効果は大きい。またこの場合ノズル形状を適切に選択すると更に効果が上がる。 As a plating solution stirring method, normal air agitation may be used, but in order to shorten the plating time by efficiently circulating metal ions to the small-diameter resist opening, the plating solution is directly pumped from the nozzle to the resist opening. The effect is great when jet agitation is used. In this case, if the nozzle shape is appropriately selected, the effect is further improved.

図1−(g)は電解金属メッキによりメッキレジスト開口部105へ金属を析出充填後メッキレジストを剥離除去した状態を示す。この除去処理は使用したレジスト樹脂組成に応じた処理液を用いれば問題無く処理可能であり、例えばアルカリ剥離型ドライフィルを用いた場合では約30〜40℃に昇温した2〜3%の水酸化ナトリウム液中に浸漬して撹拌又は振動させるかスプレーノズル噴射にて除去可能である。 FIG. 1- (g) shows a state in which the plating resist is peeled and removed after the metal is deposited and filled in the plating resist opening 105 by electrolytic metal plating. This removal treatment can be carried out without any problems if a treatment liquid corresponding to the resist resin composition used is used. For example, in the case of using an alkali peeling type dry fill, 2 to 3% of water heated to about 30 to 40 ° C. It can be removed by dipping in a sodium oxide solution and stirring or vibrating, or by spray nozzle injection.

除去が困難で残些が残り易い場合は除去液中にてノズルなどから液を直接ポンプ加圧噴出して噴流撹拌させると効果的である。この浸漬除去の場合は処理槽などの設備を電解メッキ装置に組み込むことで設備コスト及び工数を低減することが出来る。 When it is difficult to remove the residue, it is effective to pump and agitate the liquid directly from the nozzle or the like in the removal liquid and to stir the jet. In the case of this immersion removal, equipment costs and man-hours can be reduced by incorporating equipment such as a treatment tank in the electroplating apparatus.

図1−(h)は給電用導電性薄膜層103が除去されポスト106が下層導体回路102上に形成された状態を示す。除去は用いた材料に応じた除去剤を用いて処理すれば良く、例えば金属の場合ポスト形成用金属や下層導体回路と異種金属でも同種金属でも薄膜層の厚みを適正にしておけばフラッシュエッチングにて除去出来る為ポスト及び下層導体回路をダメージを与えることなく除去出来る。但し下層導体回路及が銅で薄膜層に無電解銅メッキ層を用いた場合等はフラッシュエッチング後残留した触媒層のPd等を除去する必要が生じる場合があるが、硝酸系又は塩酸系処理液にて除去可能である。 FIG. 1- (h) shows a state in which the conductive thin film layer 103 for feeding is removed and the post 106 is formed on the lower conductor circuit 102. The removal can be performed using a remover according to the material used. For example, in the case of metal, it is possible to perform flash etching if the thickness of the thin film layer is appropriate even if the metal is the same as or different from the post forming metal or the lower conductor circuit. Therefore, the post and the lower conductor circuit can be removed without causing damage. However, if the lower conductor circuit is copper and an electroless copper plating layer is used for the thin film layer, it may be necessary to remove Pd etc. of the catalyst layer remaining after flash etching. Can be removed.

図1−(i)はポストを埋め込む様に絶縁層107が形成された状態を示す。ここで用いる絶縁層は基板に要求される特性例えばTgや誘電率等を満たす材料を選べば良く、形成もその性状に応じインクタイプならカーテンコ−ターやスクリーン印刷など又シートタイプなら真空ラミネーターなどを利用すれば形成出来る。 FIG. 1- (i) shows a state in which an insulating layer 107 is formed so as to embed a post. The insulating layer used here may be selected from a material that satisfies the characteristics required for the substrate, such as Tg and dielectric constant, etc. According to the properties of the insulating layer, a curtain coater, screen printing, etc. are used for the ink type, and a vacuum laminator is used for the sheet type. If used, it can be formed.

図1−(j)は絶縁層107を研削または研磨して絶縁層の厚み及びポスト高さを均一化して平坦化されたポスト頭頂部を絶縁層表面に露出した状態を示す。これは用いた絶縁材料の硬さや粘性等に応じバフ研磨乃至ベルトサンダーなどを用いれば容易に処理出来る。 FIG. 1- (j) shows a state in which the insulating layer 107 is ground or polished to uniformize the thickness and post height of the insulating layer, and the flat top of the post is exposed on the surface of the insulating layer. This can be easily treated by using buffing or a belt sander according to the hardness and viscosity of the insulating material used.

図1−(k)は研削又は研磨により平坦化されたポスト頭頂部が露出された絶縁層上にポストにより電気接続された状態で上層導体回路108が形成された状態を示す。これは先ず絶縁層表面107を粗面化し上層回路密着力を確保してから無電解銅メッキにより表面全体に導通層を形成した後パネル銅メッキしてサブトラ法で形成しても良く或いは無電解銅メッキ後メッキレジスト形成しセミアディティブ法で形成しても良い。 FIG. 1- (k) shows a state in which the upper layer conductor circuit 108 is formed in a state where it is electrically connected by a post on the insulating layer where the post head portion flattened by grinding or polishing is exposed. This may be done by first roughening the insulating layer surface 107 to ensure the adhesion of the upper layer circuit, and then forming a conductive layer over the entire surface by electroless copper plating, and then plating the panel copper and forming it by the sub-tra method. A plating resist may be formed after copper plating and formed by a semi-additive method.

以降はソルダーレジスト形成や端子処理等通常のプリント配線基板製造工程を実施することで製品化される。 Thereafter, it is commercialized by carrying out normal printed wiring board manufacturing processes such as solder resist formation and terminal processing.

以上の説明した実施の形態にて下層回路と上層回路がポストにより電気接続されたスタックビア構造の多層配線基板が製造される。 In the embodiment described above, a multilayer wiring board having a stacked via structure in which a lower layer circuit and an upper layer circuit are electrically connected by a post is manufactured.

340×406mmサイズの市販銅張り積層板(板厚0.4mmt、銅箔厚18μmt)と携帯電話試作パターンを用いて下層導体回路を形成した後給電用導電性薄膜として無電解銅メッキを厚さ0.3〜0.4μmt形成し、この上に厚み60μmのドライフィルムをラミネートして露光・現像処理にて90μmφのレジスト開口部を形成した。この時の開口部レイアウトは試作パターンに従い面付け数は6製品、開口部数は8,300個/製品面で、最短開口部間は300μm、最遠開口部間は32mmで粗密さはかなり大きいものとなった。
この基材を陽極電圧印加すること無しに、通常パネルメッキ用硫酸銅メッキにて表ー1に示す条件で最大ポスト高さがドライフィルムを越えないようにメッキした。

表ー1 電解銅メッキ条件

Figure 2006012870

メッキ後ドライフィルムを35℃の3%水酸化ナトリウム液へ浸漬除去し、次いで無電解銅膜を濃硫酸40cc/L及び30%過酸化水素水5cc/Lの混合液中にて浸漬して剥離除去しポスト高さ及び密着力を測定した。結果は表ー2へ示す如く高さ均一性及び密着力ともに実用に耐えるものではなかった。また、高さ測定は開口部粗密の中から均等に割り振りn=25ポスト測定したが、やはりポスト高さは開口部が密になっている部分が大きく、粗の部分が小さかった。密着力測定は高さ30〜50μmt内にある20のポストで測定したが高さによる影響は無かった、バラツキはむしろ開口部の下地銅回路表面の活性化のバラツキによると推測した。

表ー2 測定結果
Figure 2006012870
After forming a lower layer conductor circuit using a commercially available copper-clad laminate (plate thickness: 0.4 mmt, copper foil thickness: 18 μm) of 340 × 406 mm size and mobile phone prototype pattern, electroless copper plating is thick as a conductive thin film for power feeding A dry film having a thickness of 60 μm was laminated thereon, and a resist opening of 90 μmφ was formed by exposure / development processing. The layout of the openings at this time is 6 products, the number of openings is 8,300 per product according to the prototype pattern, the distance between the shortest openings is 300 μm, the distance between the farthest openings is 32 mm, and the density is quite large It became.
Without applying an anode voltage, this base material was plated by copper sulfate plating for panel plating so that the maximum post height did not exceed the dry film under the conditions shown in Table-1.

Table-1 Electrolytic copper plating conditions
Figure 2006012870

After plating, the dry film is dipped and removed in a 3% sodium hydroxide solution at 35 ° C., and then the electroless copper film is dipped in a mixed solution of concentrated sulfuric acid 40 cc / L and 30% hydrogen peroxide 5 cc / L and peeled off. After removal, the post height and adhesion were measured. As a result, as shown in Table-2, the height uniformity and the adhesion were not practical. In addition, the height measurement was evenly distributed from the density of the opening, and n = 25 posts were measured, but the post height was large in the area where the opening was dense and small in the coarse area. The adhesion force was measured with 20 posts within a height of 30 to 50 μm, but there was no effect due to the height. It was estimated that the variation was rather due to the variation in activation of the surface of the underlying copper circuit in the opening.

Table-2 Measurement results
Figure 2006012870

実施例ー1と同様にして作製したレジスト開口部が形成された基材を表ー3に示す条件にて陽極電圧印加した後実施例ー1と同条件で電解銅メッキして高さと密着力を同一場所ポストに付いて測定した結果、高さ及び密着力とも大幅に改善された。
ポスト密着力の値ばかりでなくバラツキも小さくなっているのは陽極電圧印加により回路導体表面が溶解除去されて表面の活性が均一化された為と考えられる。

表ー3 陽極電圧印加条件

Figure 2006012870

表ー4 測定結果
Figure 2006012870

A substrate with a resist opening formed in the same manner as in Example-1 was applied with an anodic voltage under the conditions shown in Table 3, and then electrolytic copper plating was performed under the same conditions as in Example-1 to obtain height and adhesion. As a result of measuring with the same place post, both the height and the adhesion were greatly improved.
The reason why the variation as well as the value of the post-adhesion force is small is considered to be that the surface of the circuit conductor was dissolved and removed by applying the anode voltage, and the surface activity was made uniform.

Table-3 Anode voltage application conditions
Figure 2006012870

Table 4 Measurement results
Figure 2006012870

実施例ー1と同様にして作製したレジスト開口部が形成された基材を表
ー5に示す様に撹拌を噴流撹拌にて陽極電圧印加した後電解銅メッキを液組成の変更と撹拌を噴流撹拌としてメッキし、高さと密着力を同一場所ポストに付いて測定した。
結果は表ー6の如く、高さバラツキは電流密度を上げたにもかかわらず改善された。
これは撹拌効果が上がった為と銅イオン濃度が上がった為レジスト開口部内の銅イオン濃度の交換率が上がった効果と考えられる。

表ー5 陽極電圧印加条件

Figure 2006012870

表ー6 電解銅メッキ条件
Figure 2006012870

表ー7 測定結果
Figure 2006012870
As shown in Table 5, the substrate having the resist openings formed in the same manner as in Example 1 was applied with an anodic voltage by jet stirring and then the electrolytic copper plating was changed in liquid composition and the jet was jetted. Plating as agitation, height and adhesion were measured on the same place post.
As a result, as shown in Table-6, the height variation was improved despite increasing the current density.
This is considered to be an effect of increasing the exchange rate of the copper ion concentration in the resist opening due to the increased stirring effect and the increased copper ion concentration.

Table-5 Anode voltage application conditions
Figure 2006012870

Table-6 Electrolytic copper plating conditions
Figure 2006012870

Table-7 Measurement results
Figure 2006012870

ここでの噴流条件は、陽極電圧印加及び電解銅メッキに於いて構造は共通で、図7へ示す如く塩ビパイプ(VP25)702をピッチ150mmにて液供給配管(VP50塩ビパイプ)701から垂直に高さ500mmで立て液流接続させ、このパイプにピッチ50mmにて液噴出用ノズルを設け、これに液圧2.5kg/cm のポンプ加圧にて吐出させた。また、この噴流液が基材のレジスト開口部に均一に当たる様電気導通接続された基材704をストローク150mm、サイクル20回/分にて左右に揺動させた。 The jet conditions here are the same for anode voltage application and electrolytic copper plating. As shown in FIG. 7, a PVC pipe (VP25) 702 is vertically arranged from a liquid supply pipe (VP50 PVC pipe) 701 at a pitch of 150 mm. A vertical liquid flow connection was made at a height of 500 mm, and a liquid ejection nozzle was provided on this pipe at a pitch of 50 mm, and this was discharged by pump pressurization at a hydraulic pressure of 2.5 kg / cm 2 . Further, the base material 704 that was electrically connected so that the jet liquid uniformly hits the resist openings of the base material was swung left and right at a stroke of 150 mm and a cycle of 20 times / minute.

は本発明によるスタックビア構造ポスト接続型多層配線板の製造方法を説明した図面。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a method for manufacturing a stacked via structure post connection type multilayer wiring board according to the present invention; 回路接続用穴を加工し導電性ペースト充填する工法を示した説明図Explanatory drawing showing the method of processing circuit connection holes and filling with conductive paste 絶縁層に穴(VIA)を加工しフィルドメッキで充填する工法の説明図Explanatory drawing of the method of processing holes (VIA) in the insulating layer and filling with filled plating 下層回路上に導電性ペーストを印刷して突起形成し銅箔付き絶縁層をプレス積層 する工法の説明図Explanatory drawing of a method of printing a conductive paste on the lower layer circuit to form protrusions and press laminate an insulating layer with copper foil 下層回路上に異種金属層形成後全面メッキしエッチングにてポスト形成する方法 の説明図Explanatory drawing of the method of post forming by etching after forming different metal layers on the lower layer circuit and plating the entire surface 基材上に導電膜を形成し下層導体回路を形成後メッキレジストへ開口部を設け電 解メッキにてポスト形成する方法の説明図Explanatory drawing of the method of forming the conductive film on the base material and forming the lower layer conductor circuit, then providing an opening in the plating resist and post-forming by electroplating は本発明の実施例に使用した噴流撹拌構造を概説した図面。BRIEF DESCRIPTION OF THE DRAWINGS These are the drawings which outlined the jet stirring structure used in the Example of this invention.

符号の説明Explanation of symbols

101、201、301、401、501,601 絶縁基材
102,202,302,402,502,602 下層導体回路
103、503 給電用導電性薄膜層
104、604 メッキレジスト
105、605 レジスト開口部
106、606 金属メッキポスト
107、203、303,404,506,607 絶縁層
108、206,306、406、507、608 上層導体回路
204 接続用穴(VIA)
205 導電性ペースト
305 穴埋めメッキ層
403 導電性突起
701 液供給配管
702 塩ビパイプ
703 液噴出用ノズル
704 電気導通接続された基材
101, 201, 301, 401, 501, 601 Insulating base material 102, 202, 302, 402, 502, 602 Lower conductive circuit 103, 503 Conductive thin film layer 104, 604 Plating resist 105, 605 Resist opening 106, 606 Metal plating posts 107, 203, 303, 404, 506, 607 Insulating layer 108, 206, 306, 406, 507, 608 Upper layer conductor circuit 204 Connection hole (VIA)
205 conductive paste
305 Hole-filled plating layer 403 Conductive protrusion 701 Liquid supply pipe 702 PVC pipe 703 Liquid ejection nozzle 704 Substrate electrically connected

Claims (8)

下層導体回路が設けられた絶縁基材上へ下層回路を含む全面に給電用導電性薄膜層を設けた後、全面にメッキレジスト層を形成して、接続したい下層回路部分上にポストをメッキ形成する為の開口を該レジスト層に形成した状態で電解質溶液中にて該基材を陽極接続し電圧を印加することでポスト形成される部分の給電用導電性薄膜層全部及び下層導体回路の一部を溶解除去処理した後、金属メッキ液中にて該開口部に金属メッキを析出させることでポストを形成することを特徴とする多層配線基板の製造方法。
After a conductive thin film layer for feeding is formed on the entire surface including the lower layer circuit on the insulating base material provided with the lower layer conductor circuit, a plating resist layer is formed on the entire surface, and a post is plated on the lower circuit portion to be connected In the state in which the opening for forming is formed in the resist layer, the base material is anode-connected in the electrolyte solution and a voltage is applied to the post-formed portion of the conductive thin film layer for feeding and one of the lower conductor circuits. A method for producing a multilayer wiring board, comprising: forming a post by depositing metal plating in the opening in a metal plating solution after dissolving and removing the portion.
メッキレジスト層にポストをメッキ形成する為の開口部を形成した状態の絶縁基材を電解質溶液中にて、電解金属メッキ時の電流密度分布が相似となるか又は電解メッキ時の電流密度が高い部分はより高く且つ低い部分はより低い電流密度分布となる様に対向陰極をレイアウトした状態で陽極電圧印加し、給電用導電性薄膜の全部及び下層導体回路の一部を溶解除去して、ポストを形成するメッキ金属と下層導体回路のメッキ接合面積を大きくし良好な密着力を得ると共に、金属電解メッキ時の電流密度分布に応じその電流密度が高い部分の下層導体回路溶解除去量は多く且つ電流密度が低い部分の下層導体回路溶解除去量は小さくすることで金属メッキによるポスト形成時の高さ均一性を良好とすることを特徴とする多層配線基板の製造方法。
Insulating base material in which an opening for forming a post on the plating resist layer is formed in an electrolyte solution, the current density distribution during electrolytic metal plating is similar or the current density during electrolytic plating is high An anode voltage is applied in a state where the counter cathode is laid out so that the portion is higher and the lower portion has a lower current density distribution, and all of the conductive thin film for feeding and a part of the lower conductor circuit are dissolved and removed, Increase the plating bonding area between the plated metal and the lower conductor circuit to form a good adhesion, and according to the current density distribution at the time of metal electrolytic plating, the lower conductor circuit dissolved and removed in the portion where the current density is high and A method of manufacturing a multilayer wiring board characterized in that the height uniformity at the time of post formation by metal plating is improved by reducing the amount of the lower conductor circuit dissolved and removed in the portion where the current density is low .
ポスト形成用電解金属メッキ時のメッキ液が硫酸銅メッキ浴でその液組成が硫酸銅濃度が50g/L〜200g/Lの範囲、硫酸濃度が50g/L〜200g/Lの範囲、塩素濃度が30mg/L〜70mg/Lの範囲にあることを特徴とする多層配線基板製造方法。
The plating solution at the time of electrolytic metal plating for post formation is a copper sulfate plating bath, and the composition of the solution is such that the copper sulfate concentration ranges from 50 g / L to 200 g / L, the sulfuric acid concentration ranges from 50 g / L to 200 g / L, and the chlorine concentration is A method for producing a multilayer wiring board, which is in a range of 30 mg / L to 70 mg / L.
前記ポストを形成する為の電解金属メッキ電源にステップ的に電流を制御出来る電源又はパルス電源を使用することを特徴とする多層配線基板製造方法。
A method of manufacturing a multilayer wiring board, wherein a power source capable of controlling current stepwise or a pulse power source is used as an electrolytic metal plating power source for forming the post.
前記陽極電圧印加処理する為の電解装置及び槽をポスト形成用電解金属メッキ装置に組み込むことで連続的処理を可能として設備コスト及び加工工数を低減することを特徴とする請求項1、請求項2のいずれかに記載した多層配線基板製造方法。


3. An electrolysis apparatus and a tank for applying an anode voltage are incorporated in a post-forming electrolytic metal plating apparatus to enable continuous treatment, thereby reducing equipment costs and processing man-hours. The multilayer wiring board manufacturing method described in any of the above.


前記陽極電圧印加処理及びポスト形成用電解金属メッキ処理に於いて処理液撹拌方法として液をエアー撹拌するか又はポンプ循環撹拌させるか又は絶縁基材のポスト形成用メッキレジスト層開口部へ直接液をポンプ加圧噴出して撹拌させることを特徴とする請求項1〜請求項5のいずれかに記載した多層配線基板の製造方法。
In the anode voltage application process and post-forming electrolytic metal plating process, as a processing liquid stirring method, the liquid is air-stirred or pump-circulated and stirred, or the liquid is directly applied to the post-forming plating resist layer opening of the insulating substrate. 6. The method for producing a multilayer wiring board according to claim 1, wherein the pump is jetted and stirred.
前記陽極電圧印加処理に於ける電解質溶液に、硫酸及び塩酸又は硫酸及び過酸化水素水又は塩化アンモニウムとアンモニア水又は過硫酸アンモニウム又は塩化第1鉄と塩酸又は塩化第二銅と塩酸又はポストを形成する為の金属メッキ液の内のいずれかを含む溶液であることを特徴とする請求項1、請求項2のいずれかに記載した多層配線基板製造方法。
Sulfuric acid and hydrochloric acid or sulfuric acid and hydrogen peroxide water or ammonium chloride and ammonia water or ammonium persulfate or ferrous chloride and hydrochloric acid or cupric chloride and hydrochloric acid or posts are formed in the electrolyte solution in the anode voltage application treatment. 3. The method for producing a multilayer wiring board according to claim 1, wherein the solution contains any one of the metal plating solutions.
前記ポスト形成用電解金属メッキ終了後の処理であるメッキレジスト除去処理及び給電用導電性薄膜層除去処理及び給電用導電性薄膜層に無電解銅メッキを使用した際に残留する触媒層のPd除去処理の一部又は全部をポスト形成用電解金属メッキ装置に組み込むことで連続処理を可能とし設備コスト及び加工工数を低減することを特徴とする請求項1〜請求項7のいずれかに記載した多層配線基板の製造方法。
Plating resist removal treatment, power supply conductive thin film layer removal treatment, and Pd removal of the catalyst layer remaining when electroless copper plating is used for the power supply conductive thin film layer, which are treatments after the post-forming electrolytic metal plating is completed The multilayer according to any one of claims 1 to 7, wherein a part or all of the treatment is incorporated into an electrolytic metal plating apparatus for forming a post, thereby enabling continuous treatment and reducing equipment cost and processing man-hours. A method for manufacturing a wiring board.
JP2004183209A 2004-06-22 2004-06-22 Manufacturing method of stack via structure multilayer wiring board Pending JP2006012870A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007221125A (en) * 2006-02-13 2007-08-30 Sanmina-Sci Corp Method and process for embedding conductive element in dielectric layer
US9832871B2 (en) 2013-05-21 2017-11-28 Murata Manufacturing Co, Ltd. Module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007221125A (en) * 2006-02-13 2007-08-30 Sanmina-Sci Corp Method and process for embedding conductive element in dielectric layer
KR101062095B1 (en) * 2006-02-13 2011-09-02 산미나-에스씨아이 코포레이션 How to embed conductive elements in a dielectric layer
US9832871B2 (en) 2013-05-21 2017-11-28 Murata Manufacturing Co, Ltd. Module

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