JP2006012381A - Signal processing method, reproduced signal processing circuit, and optical disk device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct inter-code interference with good accuracy in a signal reproduced from an optical disk. <P>SOLUTION: The reproduced signal is delayed according to two or more different delay time by a delaying part 101 to produce two or more delayed signals Tap2 to Tap5, and size relations between the signal level of Tap3 and two slice level signals are obtained by a coefficient selection circuit 102, and based on the result, a group of coefficients are selected by a coefficient setting circuit 103. Then, the reproduced signal and two or more delayed signals are multiplied by the group of coefficients by multiplication parts 104, and multiplication signals mux1 to mux5 are added by an adder. In this case, since a proper coefficient group according to a mark is selected by the coefficient setting circuit 103, a waveform equalization signal Seq turns into a signal of which the waveform is equalized according to the mark. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a signal processing method, a reproduction signal processing circuit, and an optical disc apparatus, and more particularly to a signal processing method, a reproduction signal processing circuit for processing a reproduction signal from an optical disc, and an optical disc apparatus including the reproduction signal processing circuit.

  In recent years, with the advancement of digital technology and the improvement of data compression technology, CD (compact disc), CD as a medium for recording information such as music, movies, photos and computer software (hereinafter also referred to as “content”) An optical disc such as a DVD (digital versatile disc) that can record data equivalent to about 7 times the data on a disc having the same diameter as a CD has been attracting attention. The optical disk device to be used has become widespread.

  In this optical disk apparatus, laser light is emitted from a light source, information is recorded by forming a minute spot on the recording surface of the optical disk on which spiral or concentric tracks are formed, and based on the reflected light from the recording surface Information is reproduced.

  In an optical disc, information is recorded by the lengths and combinations of marks and spaces having different reflectivities. In this case, the information is converted (binarized) into a combination of two types of numerical values (binary) of 0 and 1, and written on the optical disc. Hereinafter, such a recording method is referred to as a binary recording method.

  By the way, the information amount of the content tends to increase year by year, and further increase of the information amount that can be recorded on one optical disk is expected. As means for increasing the amount of information that can be recorded on an optical disc, (1) reducing the size of the mark (higher recording density), (2) converting the information into a combination of three or more numerical values, etc. It is done. However, any of these may cause intersymbol interference at the time of reproduction, and may deteriorate the signal quality of the reproduction signal. In the following, converting information into a combination of three or more numerical values is referred to as multi-value conversion, multi-value data is referred to as multi-value data, and the number of multi-value data is referred to as multi-value data. . A recording method for recording information with multiple values is called a multi-value recording method.

  Accordingly, various apparatuses for processing the reproduction signal have been devised (see, for example, Patent Document 1 and Patent Document 2). The waveform equalizer disclosed in Patent Document 1 corresponds to the binary recording method, and the waveform equalization characteristics are switched between a mark reproduction signal and a space reproduction signal. That is, the waveform equalization characteristics for the mark reproduction signal are set to be the same regardless of the length of the mark. The information recording / reproducing apparatus disclosed in Patent Document 2 corresponds to the multi-value recording method, and corrects the waveform equalization characteristic in the demodulation circuit based on the reproduction signal of the calibration information recorded on the information recording medium. Yes.

  However, in the binary recording method, if the size of the mark is further reduced in the future, the intersymbol interference will show nonlinearity. In the waveform equalizer disclosed in Patent Document 1, the waveform equalization characteristic is marked. Therefore, the influence of intersymbol interference remains and it may be difficult to obtain a reproduction signal having a required signal quality. Further, in the multi-level recording method, if the mark interval becomes further narrower in the future, the intersymbol interference will show non-linearity, and in the information recording / reproducing apparatus disclosed in Patent Document 2, the influence of the intersymbol interference remains. Therefore, it may be difficult to obtain a reproduction signal having a required signal quality.

Japanese Patent Laid-Open No. 2003-85764 JP 2002-319138 A

  The present invention has been made under such circumstances, and a first object thereof is to provide a signal processing method and a reproduction signal processing circuit capable of accurately correcting intersymbol interference in a reproduction signal of an optical disk. is there.

  A second object of the present invention is to provide an optical disc apparatus capable of accurately reproducing information recorded on the optical disc.

  The invention according to claim 1 is a signal processing method for processing a reproduction signal from an optical disc, wherein at least one of a plurality of delay signals obtained by delaying the reproduction signal according to a plurality of delay times that are different by a predetermined time. A signal processing method including a step of determining a plurality of multiplication coefficients to be multiplied by the reproduction signal and the plurality of delay signals based on a signal level of a delay signal corresponding to a predetermined delay time set in advance.

  According to this, at the time of processing a reproduction signal from the optical disc, at least a predetermined delay time set in advance among a plurality of delay signals obtained by delaying the reproduction signal according to a plurality of delay times that differ by a predetermined time. A plurality of multiplication coefficients to be multiplied by the reproduction signal and the plurality of delay signals are determined based on the signal level of the delay signal corresponding to. In this case, a plurality of appropriate multiplication coefficients corresponding to the marks formed on the optical disc are determined, and signal processing corresponding to the marks can be performed. Therefore, as a result, it is possible to accurately correct the intersymbol interference in the reproduction signal of the optical disc.

  In this case, as in the signal processing method according to claim 2, in the determining step, the magnitude relationship between the signal level of the delay signal corresponding to the specific delay time and at least one predetermined determination level is set. Based on this, the plurality of multiplication coefficients may be determined.

  In this case, a plurality of levels can be set as the determination level as in the signal processing method according to claim 3.

  4. Each of the signal processing methods according to claim 2 and claim 3, wherein, as in the signal processing method according to claim 4, the delay signal corresponding to a delay time shorter by one step than the specific delay time and the specific delay The method may further include the step of setting the at least one determination level based on a signal level of at least one of the delay signals corresponding to a delay time longer by one step than the time.

  In the signal processing method according to claim 1, as in the signal processing method according to claim 5, in the determining step, the signal level of the delay signal corresponding to the specific delay time and the specific delay time are determined. A plurality of multiplication factors based on a signal level of a delay signal corresponding to a delay time shorter by one stage than a signal level of a delay signal corresponding to a delay time longer by one stage than the specific delay time Can be determined.

  In this case, as in the signal processing method according to claim 6, in the determining step, the signal level is multiplied by a plurality of preset values, and based on a sum signal obtained by adding the values, A plurality of multiplication factors may be determined.

  In this case, as in the signal processing method according to claim 7, in the determining step, the plurality of multiplications are performed based on a magnitude relationship between a signal level of the summed signal and at least one predetermined determination level. The coefficient can be determined.

  In this case, as in the signal processing method according to the eighth aspect, a plurality of levels can be set as the determination level.

  In each of the signal processing methods according to claims 6 to 8, as in the signal processing method according to claim 9, in the determining step, the plurality of multiplication coefficients are determined based on a history of the summed signals. Can be.

  The signal processing method according to any one of claims 1 to 9, wherein, as in the signal processing method according to claim 10, the reproduction signal is a reproduction signal of information multi-valued into three or more values. Can do.

  In each of the signal processing methods according to the first to tenth aspects, as in the signal processing method according to the eleventh aspect, each of the plurality of delay times may be an integral multiple of the period of the reproduction clock. it can.

  According to a twelfth aspect of the present invention, there is provided a reproduction signal processing circuit for processing a reproduction signal from an optical disc, wherein the reproduction signal is delayed according to a plurality of delay times that are different from each other by a predetermined time. A delay circuit that generates a plurality of corresponding delay signals; a plurality of multiplication coefficients are determined based on at least a signal level of the delay signal corresponding to a specific delay time set in advance among the plurality of delay signals. A determination circuit; a multiplication circuit that multiplies the reproduction signal and the plurality of delay signals by the plurality of multiplication coefficients to generate a plurality of multiplication signals; and adds the plurality of multiplication signals to generate an addition signal. A reproduction signal processing circuit comprising: an addition circuit;

  According to this, the reproduction signal is delayed by the delay circuit in accordance with a plurality of delay times that differ by a certain time, and a plurality of delay signals respectively corresponding to the plurality of delay times are generated. When the plurality of multiplication coefficients are determined by the determination circuit based on at least the signal level of the delay signal corresponding to a predetermined delay time set in advance among the plurality of delay signals, reproduction is performed by the multiplication circuit. A plurality of multiplication signals are generated by multiplying the signal and the plurality of delayed signals by a plurality of multiplication coefficients, respectively. Further, the plurality of multiplication signals are added by the adding circuit. In this case, since a plurality of appropriate multiplication coefficients corresponding to the mark are determined by the determination circuit, the addition signal is a signal processed according to the mark. Therefore, as a result, it is possible to accurately correct the intersymbol interference in the reproduction signal of the optical disc.

  In this case, as in the reproduction signal processing circuit according to claim 13, the determination circuit has a magnitude relationship between a signal level of the delay signal corresponding to the specific delay time and at least one determination level set in advance. The plurality of multiplication coefficients can be determined according to the above.

  In this case, as in the reproduction signal processing circuit according to the fourteenth aspect, a plurality of determination levels can be set.

  15. Each reproduction signal processing circuit according to claim 13 and 14, as in the reproduction signal processing circuit according to claim 15, the delay signal corresponding to a delay time shorter by one step than the specific delay time; and The information processing apparatus may further include a setting circuit that sets the determination level in accordance with at least one signal level of a delay signal corresponding to a delay time longer by one step than a specific delay time.

  13. The reproduction signal processing circuit according to claim 12, wherein, as in the reproduction signal processing circuit according to claim 16, the determination circuit includes a signal level of a delay signal corresponding to the specific delay time, and the specific delay. The plurality of multiplications based on a signal level of a delay signal corresponding to a delay time shorter by one step than time and a signal level of a delay signal corresponding to a delay time longer by one step than the specific delay time The coefficient can be determined.

  In this case, as in the reproduced signal processing circuit according to claim 17, the determination circuit multiplies each signal level by a plurality of preset values, and adds the values to each other, based on a sum signal obtained by adding them. A plurality of multiplication factors may be determined.

  In this case, as in the reproduction signal processing circuit according to claim 18, the determination circuit is configured to perform the plurality of multiplications based on a magnitude relationship between a signal level of the sum signal and at least one predetermined determination level. The coefficient can be determined.

  In this case, as in the reproduction signal processing circuit according to the nineteenth aspect, a plurality of determination levels can be set.

  20. In each reproduction signal processing circuit according to any one of claims 17 to 19, as in the reproduction signal processing circuit according to claim 20, the determination circuit determines the plurality of multiplication coefficients based on a history of the sum signal. You can do that.

  In each reproduction signal processing circuit according to any one of claims 12 to 20, as in the reproduction signal processing circuit according to claim 21, the difference between the addition signal and a preset target value is minimized. A correction circuit for correcting at least one of the plurality of multiplication coefficients may be further provided.

  In each reproduction signal processing circuit according to any one of claims 12 to 21, as in the reproduction signal processing circuit according to claim 22, the reproduction signal is a reproduction signal of information multi-valued into three or more values. can do.

  23. In each reproduction signal processing circuit according to any one of claims 12 to 22, as in the reproduction signal processing circuit according to claim 23, each of the plurality of delay times is an integral multiple of the period of the reproduction clock. be able to.

  According to a twenty-fourth aspect of the present invention, there is provided an optical disc apparatus for irradiating light onto a recording surface of an optical disc and performing at least reproduction of information recording, reproduction, and erasing, and adjusting a waveform of a reproduction signal from the optical disc An optical disc apparatus comprising: a reproduction signal processing circuit according to any one of claims 12 to 23; and a processing device that reproduces the information based on an output signal of the reproduction signal processing circuit.

  According to this, since the reproduction signal processing circuit according to any one of claims 12 to 23 is provided, it is possible to accurately reproduce information recorded on the optical disc.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a schematic configuration of an optical disc apparatus 20 according to an embodiment of the present invention.

  An optical disk device 20 shown in FIG. 1 includes a spindle motor 22 for rotating the optical disk 15, an optical pickup device 23, a seek motor 21 for driving the optical pickup device 23 in the sledge direction, a laser control circuit 24, An encoder 25, a drive control circuit 26, a reproduction signal processing circuit 28, a buffer RAM 34, a buffer manager 37, an interface 38, a flash memory 39, a CPU 40, a RAM 41, and the like are provided. Note that the arrows in FIG. 1 indicate the flow of typical signals and information, and do not represent the entire connection relationship of each block. Further, the optical disk device 20 corresponds to the multi-value recording method, and the record data is multi-valued to 6 values (0 to 5) as an example. That is, the multi-value number is 6. Further, as an example, it is assumed that a phase change information recording medium is used as the optical disc 15.

  In the multi-value recording method, as shown in FIG. 2 as an example, a track is virtually divided into a plurality of areas (hereinafter referred to as “cells”) for each predetermined length (here, S) in the tangential direction of the track. Is divided). One multi-value data is stored in one cell. When the value of the multi-value data is 1 to 5, a recording mark having an area corresponding to the value is formed at the center of the cell. When the value of the multi-value data is 0, no recording mark is formed. Note that the cell cycle when the optical disk 15 is rotating in accordance with the reproduction speed is Tcell (see FIG. 2).

  In the portion where the recording mark is formed, the reflectance of the laser beam decreases as the area of the recording mark increases. Therefore, the reproduction signal generated from the laser beam reflected by the recording surface of the optical disc and subjected to waveform equalization processing is As shown in FIG. 2, when the value of the multilevel data is 0, the maximum level (L0) is set, and when the value of the multilevel data is 5, the minimum level (L5) is set. Note that the signal levels when the multi-value data is 1 to 4 are L1 to L4.

  The optical pickup device 23 irradiates the recording surface on which the spiral or concentric tracks of the optical disk 15 rotated by the spindle motor 22 are irradiated with laser light and receives reflected light from the recording surface. It is a device. As shown in FIG. 3 as an example, the optical pickup device 23 includes a light source unit 51, a coupling lens 52, a beam splitter 54, an objective lens 60, a detection lens 58, a light receiver PD, an I / V amplifier 62, and an objective. A drive system 61 for driving the lens 60 is provided.

  The light source unit 51 includes a semiconductor laser LD as a light source that emits laser light. In the present embodiment, the maximum intensity emission direction of the laser light emitted from the light source unit 51 is the + X direction. A coupling lens 52 is disposed on the + X side of the light source unit 51, and the light beam emitted from the light source unit 51 is made to be substantially parallel light.

  The beam splitter 54 is disposed on the + X side of the coupling lens 52, transmits the light beam from the coupling lens 52 as it is, and branches the light beam (return light beam) reflected by the optical disk 15 in the -Z direction. An objective lens 60 is disposed on the + X side of the beam splitter 54, and the light beam transmitted through the beam splitter 54 is condensed on the recording surface of the optical disk 15.

  The detection lens 58 is disposed on the −Z side of the beam splitter 54 and condenses the returned light beam branched in the −Z direction by the beam splitter 54 on the light receiving surface of the light receiver PD. The light receiving surface of the light receiver PD is composed of a plurality of light receiving regions. Each light receiving region generates a signal corresponding to the amount of received light by photoelectric conversion.

  The I / V amplifier 62 converts a signal from each light receiving region of the light receiver PD into a voltage signal, amplifies the signal with a predetermined gain, and outputs the amplified signal to the reproduction signal processing circuit 28.

  The drive system 61 slightly drives the objective lens 60 in the tracking direction, which is a direction perpendicular to the tangential direction of the track, and a focusing actuator for slightly driving the objective lens 60 in the focus direction that is the optical axis direction of the objective lens 60. And a tracking actuator.

  Returning to FIG. 1, the reproduction signal processing circuit 28 includes a servo signal detection circuit 28b, a wobble signal detection circuit 28c, an RF signal detection circuit 28d, a decoder 28e, a clock signal generation circuit 28f, a demodulation circuit 28g, and a waveform equalization circuit 28h. Etc.

  The servo signal detection circuit 28b detects servo signals such as a focus error signal and a track error signal based on the output signal of the I / V amplifier 62. The servo signal detected here is output to the drive control circuit 26.

  The wobble signal detection circuit 28 c detects the wobble signal based on the output signal of the I / V amplifier 62. The wobble signal detected here is output to the clock signal generation circuit 28f and the demodulation circuit 28g.

  The RF signal detection circuit 28d detects an RF signal based on the output signal of the I / V amplifier 62. The RF signal detected here is output to the clock signal generation circuit 28f and the waveform equalization circuit 28h.

  The clock signal generation circuit 28f generates a reproduction clock signal based on the RF signal, and generates a demodulation clock signal and a recording clock signal based on the wobble signal. The reproduction clock signal is supplied to the waveform equalization circuit 28h and the decoder 28e, the demodulation clock signal is supplied to the demodulation circuit 28g, and the recording clock signal is supplied to the encoder 25 and the like. The period of the reproduction clock signal is the same as the cell period Tcell or 1 / integer thereof.

  The waveform equalization circuit 28h performs waveform equalization processing on the RF signal. Details of the waveform equalizing circuit 28h will be described later.

  The decoder 28e performs a decoding process and an error detection process on the output signal (waveform equalization signal) of the waveform equalization circuit 28h. When an error is detected, the decoder 28e performs an error correction process. The data is stored in the buffer RAM 34 via the manager 37. Here, since the waveform equalization circuit 28h performs waveform equalization processing on the RF signal, the intersymbol interference component included in the RF signal is accurately corrected, and stable and accurate reproduction data can be obtained. Can do. The RF signal includes address data, and the decoder 28e outputs the extracted address data to the CPU 40.

  The demodulation circuit 28g demodulates the modulation unit of the wobble signal and acquires address data or media parameters. Each data obtained here is supplied to the CPU 40.

  The drive control circuit 26 generates a drive signal for the tracking actuator for correcting the positional deviation of the objective lens 60 with respect to the tracking direction based on the track error signal from the reproduction signal processing circuit 28, and generates a focus error signal. Based on this, a driving signal for the focusing actuator for correcting the focus shift of the objective lens 60 is generated. The drive signals for the actuators generated here are output to the optical pickup device 23. Thereby, tracking control and focus control are performed. The drive control circuit 26 generates a drive signal for driving the seek motor 21 and a drive signal for driving the spindle motor 22 based on an instruction from the CPU 40. The drive signal of each motor is output to the seek motor 21 and the spindle motor 22, respectively.

  The buffer RAM 34 temporarily stores data to be recorded on the optical disc 15 (recording data), data reproduced from the optical disc 15 (reproduction data), and the like. Data input / output to / from the buffer RAM 34 is managed by the buffer manager 37.

  The encoder 25 takes out the recording data stored in the buffer RAM 34 through the buffer manager 37 based on an instruction from the CPU 40, modulates the data, adds an error correction code, and the like, and writes a signal to the optical disc 15. Is generated. The write signal generated here is output to the laser control circuit 24.

  The laser control circuit 24 controls the light emission power of the semiconductor laser LD. For example, at the time of recording, a drive signal for the semiconductor laser LD is generated based on the write signal, recording conditions, light emission characteristics of the semiconductor laser LD, and the like.

  The interface 38 is a bidirectional communication interface with a host device 90 (for example, a personal computer), and is a standard interface such as ATAPI (AT Attachment Packet Interface), SCSI (Small Computer System Interface), and USB (Universal Serial Bus). It is compliant.

  The flash memory 39 includes a program area and a data area. In the program area of the flash memory 39, various programs described in codes readable by the CPU 40 are stored. The data area stores recording conditions such as recording power and recording strategy, light emission characteristics of the semiconductor laser LD, and coefficient information (to be described later) used in the waveform equalization circuit 28h.

  The CPU 40 controls the operation of each unit in accordance with a program stored in the program area of the flash memory 39 and stores data necessary for control in the RAM 41 and the buffer RAM 34.

  Here, the waveform equalization circuit 28h will be described. As shown in FIG. 4 as an example, the waveform equalization circuit 28h includes a delay unit 101 composed of a plurality of delay elements, a coefficient selection circuit 102, a coefficient setting circuit 103, a multiplier unit 104 composed of a plurality of multipliers, and an addition. A device 105 is provided.

  In the present embodiment, the delay unit 101 includes four delay elements (101a, 101b, 101c, and 101d) as an example. Each delay element has substantially the same signal delay characteristic and is arranged in series. The delay element 101a delays the output signal (reproduction signal) of the RF signal detection circuit 28d by time Tcell, and the delay element 101b delays the output signal of the delay element 101a by time Tcell. The delay element 101c delays the output signal of the delay element 101b by time Tcell, and the delay element 101d delays the output signal of the delay element 101c by time Tcell. That is, the delay unit 101 is a so-called analog delay line. In the following, for convenience, the output signal of the RF signal detection circuit 28d is Tap1, the output signal (delay signal) of the delay element 101a is Tap2, the output signal (delay signal) of the delay element 101b is Tap3, and the output signal of the delay element 101c. The (delay signal) is called Tap4, and the output signal (delay signal) of the delay element 101d is called Tap5. Tap1 to Tap5 are also collectively referred to as Tap signals. That is, Tap1 is also referred to as the first Tap signal, Tap2 as the second Tap signal, Tap3 as the third Tap signal, Tap4 as the fourth Tap signal, and Tap5 as the fifth Tap signal.

  The coefficient selection circuit 102 includes a comparison unit cmp and a decoder 113 as shown in FIG. 5 as an example. The comparison unit cmp has two comparators (111, 112). The comparator 111 compares Tap3 with the slice level signal SL1 (determination level) and outputs the comparison result. The comparator 112 compares Tap3 with the slice level signal SL2 (> SL1) (determination level) and outputs the comparison result. Here, the comparator 111 is set to output 0 (low level) when Tap3 <SL1, and to output 1 (high level) when Tap3 ≧ SL1. The comparator 112 is set to output 0 (low level) when Tap3 <SL2, and to output 1 (high level) when Tap3 ≧ SL2. That is, in the present embodiment, Tap3 has a magnitude relationship with two slice level signals (determination levels). Note that the slice level signal SL1 and the slice level signal SL2 are set in advance by experiments, simulations, or the like in consideration of nonlinearity of intersymbol interference.

  Here, the intersymbol interference in the multilevel recording method will be described.

  As an example, as shown in FIG. 6, when multi-value data “0” “0” “5” “0” “0” is reproduced, reproduction corresponding to the second and fourth multi-value data “0” is performed. The signal level is detected smaller than L0, and the reproduction signal level corresponding to the multilevel data “5” is detected larger than L5. Since the spot diameter of the light spot at the time of reproduction is larger than the length of the cell, the reproduction signal level corresponding to the second and fourth multi-value data “0” corresponds to the multi-value data “5”. This is because the reproduction signal level affects the reproduction signal level corresponding to the multilevel data “5”, and the reproduction signal levels corresponding to the second and fourth multilevel data “0”. Such a change in the reproduction signal level due to the influence of adjacent cells is called intersymbol interference.

  At this time, if the amount of intersymbol interference is proportional to the size of the recording mark, the intersymbol interference is said to be linear. However, in the multi-level recording method, when the mark shape is different between the small recording mark and the large recording mark, or the light intensity distribution of the light spot is complicated, the amount of intersymbol interference is not proportional to the size of the recording mark. There is. In this case, the intersymbol interference is non-linear.

  Specifically, the nonlinearity of the mark shape and intersymbol interference will be described. Here, as an example, as shown in FIG. 7, when multi-value data “0” “0” “x” “0” “0” is reproduced, “x” exerted on the fourth “0” Think about the impact. The recording mark changes in length in the tangential direction (time axis direction) of the track according to the multi-value data. However, as the recording mark becomes smaller, the length in the direction perpendicular to the tangential direction also changes. The reproduction signal level corresponding to “0” is smaller than half when x = 3 (point B in FIG. 7) and when x = 5 (point A in FIG. 7). That is, the change sensitivity of the intersymbol interference amount for a large recording mark is higher than the change sensitivity of the intersymbol interference amount for a small recording mark. In FIG. 7, for convenience of comparison, a recording mark for multilevel data “1”, a recording mark for multilevel data “3”, and a recording mark for multilevel data “5” are included in one cell. Overlaid.

  In this case, the relationship between the reproduction signal level corresponding to the cell center and the intersymbol interference amount in the adjacent cell (hereinafter also referred to as “center level-interference amount relationship” for convenience) is shown in FIG. 8 as an example. Moreover, it becomes a convex curve.

  Therefore, in this embodiment, the center level-interference amount relationship is divided into three regions (region 1, region 2, and region 3) as shown in FIG. -Interference amount relationship is linear, that is, intersymbol interference is linear. Accordingly, the waveform equalization circuit 28h has three waveform equalization characteristics (first characteristic, second characteristic, and third characteristic). The signal level at the boundary between the region 1 and the region 2 is the slice level signal SL1, and the signal level at the boundary between the region 2 and the region 3 is the slice level signal SL2.

  Therefore, if the output signal of the comparator 111 and the output signal of the comparator 112 are both 0, the decoder 113 uses the signal for selecting the waveform equalization characteristic (first characteristic) corresponding to the region 1 as the selection signal ksel. If the output signal of the comparator 111 is 1 and the output signal of the comparator 112 is 0, a signal for selecting the waveform equalization characteristic (second characteristic) corresponding to the region 2 is output as the selection signal ksel. If the output signal of the comparator 111 and the output signal of the comparator 112 are both 1, a signal for selecting the waveform equalization characteristic (third characteristic) corresponding to the region 3 is output as the selection signal ksel.

  The coefficient setting circuit 103 has five selectors (121, 122, 123, 124, 125) and five registers (126a, 126b, 126c, 126d, 126e) as shown in FIG. 10 as an example. Yes. The register 126a has three coefficient information (1A, 1B, 1C), the register 126b has three coefficient information (2A, 2B, 2C), the register 126c has three coefficient information (3A, 3B, 3C), and the register 126d. Stores three coefficient information (4A, 4B, 4C), and register 126e stores three coefficient information (5A, 5B, 5C). Here, 1A, 2A, 3A, 4A, and 5A are coefficient information corresponding to the first characteristic, respectively, and these coefficient information is also referred to as a first coefficient group. 1B, 2B, 3B, 4B, and 5B are coefficient information corresponding to the second characteristic, and these coefficient information is also referred to as a second coefficient group. 1C, 2C, 3C, 4C, and 5C are coefficient information corresponding to the third characteristic, and these coefficient information is also referred to as a third coefficient group. Each coefficient group is acquired in advance by simulation or experiment and stored in the data area of the flash memory 39. In the initialization process when the power is turned on, the CPU 40 transfers the data from the data area of the flash memory 39 to each register.

  The selector 121 selects one of the three pieces of coefficient information (1A, 1B, 1C) according to the selection signal ksel, and outputs it as a coefficient signal k1. The selector 122 selects any one of the three pieces of coefficient information (2A, 2B, 2C) according to the selection signal ksel and outputs it as a coefficient signal k2. The selector 123 selects one of the three pieces of coefficient information (3A, 3B, 3C) according to the selection signal ksel and outputs it as a coefficient signal k3. The selector 124 selects any one of the three pieces of coefficient information (4A, 4B, 4C) according to the selection signal ksel and outputs it as a coefficient signal k4. The selector 125 selects any one of the three pieces of coefficient information (5A, 5B, 5C) according to the selection signal ksel and outputs it as a coefficient signal k5. That is, the selection signal ksel is a signal that designates one of the three coefficient groups. The coefficient signal k2 and the coefficient signal k4 are negative signals.

  Returning to FIG. 4, the multiplication unit 104 includes five multipliers (104a, 104b, 104c, 104d, and 104e). The multiplier 104a multiplies Tap1 by k1 and outputs the multiplication signal mux1. The multiplier 104b multiplies Tap2 by k2 and outputs it as a multiplication signal mux2. The multiplier 104c multiplies Tap3 by k3, and outputs the multiplication signal mux3. The multiplier 104d multiplies Tap4 by k4, and outputs the multiplication signal mux4. The multiplier 104e multiplies Tap5 by k5 and outputs the multiplication signal mux5. As each multiplier, a variable gain amplifier whose gain changes according to the coefficient signal can be used. The coefficient signals k1 to k5 are also collectively referred to as Tap coefficients.

  The adder 105 adds the multiplication signals to generate a waveform equalization signal Seq. This waveform equalization signal Seq is output to the decoder 28e.

  As a result, the reproduction signals of the multi-value data “0”, “0”, “5”, “0”, “0”, as shown in FIG. The reproduction signal level corresponding to is substantially L0, and the reproduction signal level corresponding to the multilevel data “5” is almost L5. That is, the intersymbol interference is corrected.

  Here, optical resolution characteristics (Modulation Transfer Function, hereinafter referred to as “MTF”) will be described (see FIG. 12). As the size of the recording mark decreases, the frequency of the reproduction signal increases. When the size of the recording mark becomes smaller than the spot diameter of the light spot and the frequency exceeds the threshold value Fp, the amplitude of the reproduction signal is attenuated when waveform equalization processing is not performed. Although the frequency band in the multi-value recording method exceeds the threshold value Fp, the threshold value is shifted from Fp to the high frequency side Fp ′ by the waveform equalization process, so that attenuation of amplitude can be suppressed. Even in the multi-level recording method, when the same recording mark continues, the frequency may be lower than the threshold value Fp.

  Regenerated signal waveform (eye pattern) before waveform equalization of multi-value data “0” “0” “x” “0” “0” and multi-value data “5” “5” “x” “5” A reproduction signal waveform (eye pattern) before waveform equalization of “5” is shown in FIG. 13 as an example. In the reproduction signal of the multi-value data “0” “0” “x” “0” “0”, the amplitude becomes maximum when x = 5, and the multi-value data “5” “5” “x” “5” The reproduction signal “5” has the maximum amplitude when x = 0. However, in the multi-value recording method, since the size of each recording mark is smaller than the spot diameter of the light spot, single recording such as “x” in “0” “0” “x” “0” “0” is performed. In the mark (hereinafter referred to as “isolated wave” for convenience), even if x = 5, the maximum amplitude (L0−L5) is not reached. The reproduction signal level corresponding to x = 1 and x = 2 in the reproduction signal of the multi-value data “0” “0” “x” “0” “0” is present even though the recording mark exists. The reproduction signal level corresponding to x = 0 in the reproduction signal of the multi-value data “5” “5” “x” “5” “5” is higher. Such a situation is also corrected by the waveform equalization circuit 28h.

《Playback processing》
Next, processing when the optical disc apparatus 20 receives a reproduction request command from the host apparatus 90 will be briefly described with reference to FIG. The flowchart in FIG. 14 corresponds to a series of processing algorithms executed by the CPU 40.

  When the reproduction request command is received from the host device 90, the start address of the program corresponding to the flowchart of FIG. 14 is set in the program counter of the CPU 40, and the reproduction process is started.

  In the first step 301, a signal for driving the spindle motor 22 based on the reproduction speed is output to the drive control circuit 26, and the reproduction signal processing circuit 28 is notified that the reproduction request command has been received from the host device 90. .

  In the next step 303, when it is confirmed that the rotation of the optical disk 15 has reached a predetermined speed, servo-on is set for the drive control device 26. Thereby, tracking control and focus control are performed as described above. Note that tracking control and focus control are performed as needed until the reproduction process is completed.

  In the next step 305, the reproduction start address is extracted from the reproduction request command, and the drive control circuit 26 is instructed so that a light spot is formed before the reproduction start address. Thereby, a seek operation is performed. If the seek operation is unnecessary, the process here is skipped.

  In the next step 307, reproduction is permitted. Thus, as described above, the reproduction data is acquired by the RF signal detection circuit 28d, the waveform equalization circuit 28h, and the decoder 28e, temporarily stored in the buffer RAM 34, and then output to the host device 90 for each sector.

  In the next step 309, it is determined whether or not the reproduction is finished. If the reproduction has not ended, the determination here is denied, and after waiting for a certain time, it is determined again whether the reproduction has ended. On the other hand, if the reproduction is finished, the determination here is affirmed and the process is finished.

  As is clear from the above description, in the optical disc apparatus 20 according to the present embodiment, a delay circuit is configured by the delay unit 101, a determination circuit is configured by the coefficient selection circuit 102 and the coefficient setting circuit 103, and a multiplication unit 104 is configured. A multiplication circuit is configured, and an adder 105 is configured by the adder 105. The processing device is configured by the CPU 40 and a program executed by the CPU 40. Note that at least a part of the processing device realized by the processing according to the program by the CPU 40 may be configured by hardware, or all may be configured by hardware.

  In the processing by the reproduction signal processing circuit 28, the signal processing method according to the present invention is implemented.

  As described above, according to the optical disc device 20 according to the present embodiment, the reproduction signal from the optical disc via the optical pickup device 23 is delayed by a delay unit 101 (delay circuit) at a plurality of different delay times. Accordingly, a plurality of delay signals Tap2 to Tap5 corresponding to a plurality of delay times are generated. Then, the coefficient selection circuit 102 (part of the determination circuit) acquires the magnitude relationship between the signal level of Tap3 (delay signal corresponding to a specific delay time) and the two slice level signals (determination levels), Based on the result, a coefficient group (a plurality of multiplication coefficients) is selected by the coefficient setting circuit 103 (part of the determination circuit). The coefficient group selected here is multiplied by the reproduction signal and the plurality of delay signals in the multiplication unit 104 (multiplication circuit). Multiplication signals mux1 to mux5 output from the multiplication unit 104 are added by an adder 105 (adder circuit) and supplied to the decoder 28e as a waveform equalization signal Seq to obtain reproduction data. In this case, since the appropriate coefficient group corresponding to the mark is selected (determined) by the coefficient setting circuit 103, the waveform equalization signal Seq is a signal that is waveform equalized according to the mark. Therefore, as a result, it is possible to accurately correct the intersymbol interference in the reproduction signal of the optical disc. Then, information recorded on the optical disc can be accurately reproduced.

  In the above embodiment, the case where the delay unit 101 of the waveform equalization circuit 28h includes four delay elements is described. However, the present invention is not limited to this. For example, the delay unit 101 may include two delay elements or six delay elements. good. The number of delay elements may be adjusted according to the size of the cell with respect to the spot diameter of the light spot. In the multi-value recording method, it is preferable that the number of delay elements is an even number.

  In the above embodiment, the case where the waveform equalization circuit 28h is configured by an analog circuit has been described. For example, when it is necessary to change the delay time according to the reproduction speed or to switch the multiplication coefficient at high speed, You may comprise with a digital circuit. In this case, an A / D converter is provided before the waveform equalization circuit. It is desirable that the sampling rate in the A / D converter is 10 times or more the delay time, and sampling data is filtered to remove sampling noise. A signal equivalent to the output signal of the delay element can be obtained by extracting the discretized signal by the A / D converter at the same period as the delay time. If sampling by the A / D converter is performed in the same cycle as the delay time, it is not necessary to extract the data and the data can be used as it is. There is. In addition, it is preferable to remove transmission line noise using a filter or the like in advance regardless of the sampling rate.

  In the above embodiment, the case where the delay elements constituting the delay unit 101 of the waveform equalization circuit 28h are arranged in series has been described. However, as an example, the delay elements having different delay times as shown in FIG. (101a ′, 101b ′, 101c ′, 101d ′) may be arranged in parallel. In this case, the delay time of the delay element 101a 'is Tcell, the delay time of the delay element 101b' is 2Tcell, the delay time of the delay element 101c 'is 3Tcell, and the delay time of the delay element 101d' is 4Tcell. Thus, for example, when distortion occurs in the signal every time it passes through the delay element, it is possible to prevent accumulation of distortion that occurs when the delay elements are arranged in series.

  Moreover, although the said embodiment demonstrated the case where a center level-interference amount relationship was divided | segmented into three area | regions, it is not limited to this. As the number of regions increases, the accuracy of correcting intersymbol interference improves. However, if the number of regions is about half the number of multi-values, intersymbol interference can be corrected with sufficient accuracy. When the non-linearity is biased toward the small recording mark side or the large recording mark side, the number of areas may be two or three regardless of the number of multi-values.

  In the above-described embodiment, Tap3 has been described with respect to a case where a magnitude relationship between two slice level signals (determination levels) is acquired. However, the present invention is not limited to this. For example, when the number of regions is 2, Tap3 may be acquired with a magnitude relationship with one slice level signal (determination level). In short, a signal for specifying a region may be output to the coefficient setting circuit 103.

  In the above embodiment, the case where the clock signal generation circuit 28f generates the demodulation and recording clock signals from the wobble signal has been described. For example, a clock extraction mark (for example, a clock mark) is included in the recorded information. May be included, each clock signal may be generated based on the mark.

  In the above-described embodiment, the case where the length of the recording mark in the tangential direction (time axis direction) of the track changes according to the multi-value data has been described. However, the present invention is not limited to this. For example, as shown in FIG. 16 as an example, the length of the recording mark in the direction orthogonal to the tangential direction of the track may be changed according to the multi-value data. In this case, since the length in the tangential direction also changes as the recording mark becomes smaller, when the multi-value data “0” “0” “x” “0” “0” is reproduced, The reproduction signal level corresponding to “0” is greater than half when x = 3 (point D in FIG. 16) and when x = 5 (point C in FIG. 16). That is, the change sensitivity of the intersymbol interference amount for a large recording mark is lower than the change sensitivity of the intersymbol interference amount for a small recording mark. In such a case, the center level-interference amount relationship is an upwardly convex curve as shown in FIG. 17 as an example. Also in this case, it is possible to divide into three regions as in the above embodiment, and to make the intersymbol interference linear in each region. In FIG. 16, for convenience, a recording mark for multilevel data “1”, a recording mark for multilevel data “3”, and a recording mark for multilevel data “5” are shown superimposed in one cell. ing.

  For example, as shown in FIG. 18, when the recording mark is circular and the diameter changes according to the multi-value data, the multi-value data “0” “0” “x” “0”. When “0” is reproduced, the reproduction signal level corresponding to the fourth “0” is the same as when x = 3 (point F in FIG. 18) and when x = 5 (point E in FIG. 18). When x = 1 (point G in FIG. 18), it is about half that when x = 3 (point F in FIG. 18). In such a case, the center level-interference amount relationship is a straight line as shown in FIG. 19 as an example. That is, the intersymbol interference is linear. In FIG. 19, for convenience, a recording mark for multilevel data “1”, a recording mark for multilevel data “3”, and a recording mark for multilevel data “5” are shown superimposed in one cell. ing.

  In the above-described embodiment, the case where each of the slice level signal SL1 and the slice level signal SL2 in the coefficient selection circuit 102 is a fixed value has been described. However, the present invention is not limited to this, and for example, at least one of adjacent recording marks You may set according to.

  In order to simplify the explanation, the center level-interference amount relationship is divided into two regions (region A and region B), and the slice level signal (SL) indicating the boundary between region A and region B is the maximum amplitude. It is assumed that it is set to 1/2. In this case, for example, when the multi-value data “x” “x” “2” “x” “x” is reproduced, the multi-value data “x” is displayed as shown in FIG. 20A when x = 0. “2” is recognized as region A, and correct waveform equalization processing is performed. However, when x = 5, the multi-value data “2” is recognized as the region B as shown in FIG. 20B, and correct waveform equalization processing is not performed. Such a phenomenon becomes more remarkable as the multi-value number is larger.

  In such a case, instead of the coefficient selection circuit 102, a coefficient selection circuit 102 'using Tap2, Tap3, and Tap4 as input signals may be used as shown in FIG. 21 as an example. The coefficient selection circuit 102 ′ has a slice level setting circuit 130 in addition to the two comparators (111, 112) and the decoder 113 that constitute the coefficient selection circuit 102. The slice level setting circuit 130 includes two comparators (131, 132), a decoder 133, two registers (136a, 136b), and two selectors (134, 135).

  Three slice level information (SL1A, SL1B, SL1C) is stored in the register 136a, and three slice level information (SL2A, SL2B, SL2C) is stored in the register 136b. These slice level information is acquired in advance by simulation or experiment and stored in the data area of the flash memory 39. In the initialization process when the power is turned on, the CPU 40 transfers the data from the data area of the flash memory 39 to each register.

  The comparator 131 compares Tap2 with a preset slice level signal SL3 and outputs the comparison result. The comparator 132 compares Tap4 with a preset slice level signal SL4 and outputs the comparison result. Here, the comparator 131 is set to output 0 (low level) when Tap2 <SL3, and output 1 (high level) when Tap2 ≧ SL3. The comparator 132 is set to output 0 (low level) when Tap4 <SL4 and 1 (high level) when Tap4 ≧ SL4. Note that SL3 and SL4 may simply be at a level that is 1/2 of the maximum amplitude, but at least one of SL3 and SL4 may be slightly shifted from the level that is 1/2 of the maximum amplitude depending on the characteristics of the nonlinearity. . Of course, at least one of SL3 and SL4 may be variable.

  The decoder 133 generates a signal SLsel for selecting SL1 and SL2 based on the output signal of the comparator 131 and the output signal of the comparator 132. The selector 134 selects one of the three slice level signals (SL1A, SL1B, SL1C) according to the signal SLsel and outputs it as the slice level signal SL1. The selector 135 selects one of the three signals (SL2A, SL2B, SL2C) according to the signal SLsel and outputs it as the slice level signal SL2. Note that the number of options in each selector need not be three.

  The comparator 111 compares Tap3 and SL1 in the same manner as the coefficient selection circuit 102, and outputs the comparison result. Similar to the coefficient selection circuit 102, the comparator 112 compares Tap3 and SL2, and outputs the comparison result. Similarly to the coefficient selection circuit 102, the decoder 113 selects the waveform equalization characteristic (first characteristic) corresponding to the region 1 if the output signal of the comparator 111 and the output signal of the comparator 112 are both 0. If the output signal of the comparator 111 is 1 and the output signal of the comparator 112 is 0, a signal for selecting a waveform equalization characteristic (second characteristic) corresponding to the region 2 is output. If the output signal of the comparator 111 and the output signal of the comparator 112 are both 1 as a selection signal ksel, a signal for selecting a waveform equalization characteristic (third characteristic) corresponding to the region 3 is selected as the selection signal ksel. Output.

  For example, when the shape of the recording mark has a very large asymmetry with respect to the tangential direction of the track, SL1 and SL2 may be set using either Tap2 or Tap4.

  In the above embodiment, the case where each coefficient group in the coefficient setting circuit 103 is stored in the data area of the flash memory 39 has been described, but information on each coefficient group may be recorded on the optical disc. In this case, it is necessary to record on the optical disc so that information on each coefficient group can be acquired from the reproduction signal without performing waveform equalization processing. For example, in the case of a recordable optical disc, information regarding each coefficient group may be added to the wobble signal.

  In addition, when the optimal waveform equalization characteristics are expected to vary due to changes in light spots over time, variations, recording conditions, and the like, options (coefficient information) in each selector in the coefficient setting circuit 103 can be corrected. You may do it. A waveform equalization circuit (28h ') corresponding to this correction will be described. As shown in FIG. 22, the waveform equalizing circuit 28h 'is obtained by adding an error detecting circuit 106 and a coefficient updating circuit 107 to the waveform equalizing circuit 28h.

  Here, it is assumed that an area in which recorded information is known (hereinafter referred to as “correction information area”) is provided on the optical disc 15. Note that ID information indicating that the correction information area is the correction information area is recorded at the head of the correction information area. Therefore, as shown in FIG. 23, an A / D converter (ADC) 28j and a correction information area detection circuit 28k are newly provided. The A / D converter 28j converts the reproduction signal into digital data. The correction information area detection circuit 28k monitors whether or not the ID information is included in the output signal of the A / D converter, and outputs the correction signal to the waveform equalization circuit 28h 'when the ID information is detected. In the waveform equalization circuit 28h ', the correction signal is supplied to the error detection circuit 106 as shown in FIG.

  Processing during operation of the waveform equalization circuit 28h 'will be described with reference to the flowchart of FIG.

  In the first step 401, coefficient information stored in each register of the coefficient setting circuit 103 is initialized. Note that this processing may be skipped if it has already been initialized.

  In the next step 403, it is determined whether or not the reproduction process has been completed. If the reproduction process has not ended, the determination here is denied and the routine proceeds to step 405.

  In step 405, it is determined whether there is a correction signal. If there is a correction signal, the determination here is affirmed and the routine proceeds to step 407.

  In step 407, 1 is set to the flag st as information indicating that there is a correction signal.

  In the next step 411, the coefficient selection circuit 102 outputs the selection signal ksel.

  In the next step 413, the coefficient setting circuit 103 outputs a coefficient signal based on the selection signal ksel.

  In the next step 415, the adder 105 generates a waveform equalization signal Seq.

  In the next step 417, it is determined whether or not the flag st is 0. If the flag st is not 0, the determination here is denied and the routine proceeds to step 419.

  In this step 419, the error detection circuit 106 compares the waveform equalization signal Seq output from the adder 105 with the target value Starget set from the CPU 40, and the deviation of the waveform equalization signal Seq from the target value Starget is shifted. Output as an error signal. As the target value Starget, an ideal signal level of information recorded in the correction information area, for example, a level obtained by equally dividing the maximum amplitude by the number of levels is used.

  In the next step 421, the coefficient update circuit 107 calculates new coefficient information based on the following equation (1), and the coefficient information stored in each register of the coefficient setting circuit 103 is updated. Here, the error signal is e (n), the i-th Tap signal is Xi (n), the coefficient signal input to the i-th multiplier is Ci (n), and A is a constant. Then, the process returns to step 403. n is the number of repetitions.

  Ci (n + 1) = Ci (n) + A * e (n) * Xi (n) (1)

  If there is no correction signal in step 405, the determination in step 405 is denied, and the process proceeds to step 409. In step 409, 0 is set to the flag st as information indicating that there is no correction signal. Then, the process proceeds to step 411.

  If the flag st is 0 in step 417, the determination in step 417 is affirmed and the process returns to step 403.

  In step 403, if the reproduction process has been completed, the determination in step 403 is affirmed and a standby state is entered. If there is a reproduction request in this standby state, the waveform equalization circuit 28 h ′ enters an operating state, and the process proceeds to step 403.

  In step 419, if the error signal is equal to or smaller than a predetermined value, the coefficient information need not be updated. In step 421, information (for example, a flag) indicating that convergence is confirmed when the coefficient information converges may be set. Furthermore, user data is not reproduced until the coefficient information converges.

  In this case, as shown in FIG. 25 as an example, a memory 28m and a changeover switch 28n for holding a correction signal may be provided. When detecting the ID information, the correction information area detection circuit 28k outputs a correction signal to the memory 28m, the changeover switch 28n, and the waveform equalization circuit 28h '. When the memory 28m receives the correction signal, the memory 28m stores the output signal of the A / D converter. As a result, the reproduction signal in the correction information area is stored in the memory 28m. Then, the memory 28m outputs the stored reproduction signal in response to a request from the waveform equalization circuit 28h '. When the changeover switch 28n receives the correction signal, the changeover switch 28n switches the signal line so that the output signal of the memory 28m is supplied to the waveform equalization circuit 28h '. As a result, the reproduction signal in the correction information area is supplied from the memory 28m to the waveform equalization circuit 28h '. Accordingly, the number of times the correction information area is reproduced can be reduced, and the time required for the correction process can be shortened.

  As the correction information area, an area in which address information is recorded or an area in which synchronization information is recorded may be used.

  In addition, the slice level signal can be optimized based on the same concept. In this case, as shown in FIG. 26, instead of the coefficient update circuit 107 in the waveform equalization circuit 28h ′, a waveform equalization circuit 28h ″ provided with a slice level update circuit 108 and an arithmetic circuit 109 is used. Then, the slice level update circuit 108 updates the slice level signal in the coefficient selection circuit 102 (see FIG. 27). The optimization process of the slice level signal SL1 in the waveform equalization circuit 28h ″ will be described with reference to the flowchart of FIG. I will explain. Here, as an example, the slice level signal SL1 is changed from D1 to (D1 + mΔd) in increments of Δd. Further, it is assumed that the coefficient information is not changed. This optimization process is started by a correction signal.

  In the first step 501, the slice level update circuit 108 sets the initial value D1 to the slice level signal SL1.

  In the next step 503, the initial value 0 is set to the counter i.

  In the next step 505, the selection signal ksel is output by the coefficient selection circuit 102.

  In the next step 507, the coefficient setting circuit 103 outputs a coefficient signal based on the selection signal ksel.

  In next step 509, the waveform equalization signal Seq is generated by the adder / subtractor 105.

  In the next step 511, the error detection circuit 106 compares the waveform equalization signal Seq output from the adder / subtractor 105 with the target value Starget set by the CPU 40, and the deviation of the waveform equalization signal Seq from the target value Starget. Is detected as an error. This error is stored in the memory (not shown) of the arithmetic circuit 109 in association with the slice level signal SL1.

  In the next step 513, it is determined whether or not the value of the counter i is greater than or equal to m. If the value of the counter i is less than m, the determination here is denied and the routine proceeds to step 515.

  In this step 515, 1 is added to the value of the counter i.

  In the next step 517, Δd is added to the slice level signal SL1, and the process returns to step 505.

  Thereafter, the processes and determinations in steps 505 to 517 are repeated until the determination in step 513 is affirmed.

  When the value of the counter i becomes m, the determination in step 513 is affirmed, and the routine proceeds to step 519.

  In step 519, the arithmetic circuit 109 acquires a relationship (for example, an approximate expression) between the slice level signal SL1 and the error.

  In the next step 521, the arithmetic circuit 109 calculates the slice level signal corresponding to the minimum value of the error as the optimum slice level signal from the relationship between the slice level signal SL1 and the error.

  In the next step 523, the arithmetic circuit 109 updates the slice level signal SL1 in the coefficient selection circuit 102 to the optimum slice level signal. Then, the process ends.

  Note that the slice level signal SL2 can be similarly optimized.

  In the above embodiment, the case where information is recorded by the multi-value recording method has been described. However, the present invention is not limited to this, and even when information is recorded by the binary recording method. good. Even in the binary recording system, when the mark size is reduced, the intersymbol interference exhibits nonlinearity (see FIG. 29). In FIG. 29, the downward convex waveform is a reproduction signal when a 3T to 7T mark is inserted into a long space, and the upward convex waveform is a reproduction signal when a 3T to 7T space is inserted into a long mark. It is. According to this, the amplitude is small at 3T (mark, space) and 4T (mark, space) and does not reach the maximum amplitude.

  By the way, since the intersymbol interference occurs optically, the intersymbol interference is not necessarily symmetrical with respect to the tangential direction of the track due to the complexity of the intensity distribution of the light spot, the anisotropy of the recording mark shape, the tilt of the optical disk with respect to the objective lens, Instead, the Tap2 coefficient information and Tap4 coefficient information are generally different from each other when Tap3 is used as a reference. Therefore, for example, if the shape of the recording mark is significantly distorted with reference to the cell center, the value of the coefficient information on one side (Tap2 or Tap3) may be almost zero. In this case, the coefficient selection circuit 102 may use the output signal of the delay element that has the greatest influence on the output after waveform equalization, instead of using Tap3. For example, an output signal of a delay element corresponding to coefficient information having the largest absolute value may be used.

  Further, in the above embodiment, instead of the waveform equalization circuit 28h, as shown in FIG. 30 as an example, a coefficient selection circuit 102a that performs coefficient selection using the output signal of the RF signal detection circuit 28d instead of Tap3. A waveform equalizing circuit 28ha provided with the above may be used. The waveform equalizing circuit 28ha will be described in detail below. In the waveform equalizing circuit 28ha shown in FIG. 30, a delay element 100 is further arranged in front of the delay element 101a.

  As shown in FIG. 31 as an example, the coefficient selection circuit 102 a has substantially the same signal delay characteristics as the delay elements constituting the delay unit 101 in the coefficient selection circuit 102 (see FIG. 5) in the above embodiment. One delay element (114a, 114b, 114c), three multipliers (115a, 115b, 115c), a coefficient setting circuit 116, an adder 117, and a memory (storage circuit) 118 are added. is there. Note that the number of delay elements may be adjusted according to the size of the cell with respect to the spot diameter of the light spot.

  Here, the output signal of the RF signal detection circuit 28d is input to the delay element 114a, the output signal of the delay element 114a is input to the multiplier 115a and the delay element 114b, and the output signal of the delay element 114b is delayed from the multiplier 115b. The signal is input to the element 114c and the output signal of the delay element 114c is input to the multiplier 115c.

  The coefficient setting circuit 116 outputs three coefficient signals (ka1, ka2, ka3). This coefficient signal is a signal having a value (level) suitable for roughly removing the intersymbol interference component determined by the size of the laser beam focused on the recording surface of the optical disc 15 and the cell length, It is obtained in advance by theoretical calculation, simulation and experiment. At this time, it is preferable to consider variations in characteristics of the optical disc. The coefficient signal may be a predetermined value (for example, a design value) as an initial value, and may be corrected according to the correction result when the coefficient signal in the coefficient setting circuit 103 is corrected. By the way, the value (level) of the coefficient signal may be positive or negative.

  Multiplier 115a multiplies the output signal of delay element 114a and coefficient signal ka1, multiplier 115b multiplies the output signal of delay element 114b and coefficient signal ka2, and multiplier 115c outputs the output signal of delay element 114c and the coefficient. Multiply by signal ka3. Thereby, the output signal of the delay element is amplified or attenuated.

  The adder 117 outputs a sum signal obtained by adding the output signal of the multiplier 115a, the output signal of the multiplier 115b, and the output signal of the multiplier 115c.

  The memory 118 holds a sum signal that is an output signal of the adder 117, that is, an addition result. The memory 118 outputs the stored content (addition result) to the comparator 111 and the comparator 112 at a timing necessary for the processing of the coefficient setting circuit 103. The comparator 111 compares the addition result with the slice level signal SL1, and outputs the comparison result. The comparator 112 compares the addition result with the slice level signal SL2, and outputs the comparison result. Here, the comparator 111 is set to output 0 (low level) when the addition result <SL1, and to output 1 (high level) when the addition result ≧ SL1. Further, the comparator 112 is set to output 0 (low level) when the addition result <SL2, and to output 1 (high level) when the addition result ≧ SL2. The comparison unit cmp acquires a magnitude relationship with two slice level signals (determination levels). For example, when the number of regions is 2, the comparison unit cmp has one slice level signal (determination level). What is necessary is just to acquire the magnitude relationship with. In short, a signal for specifying a region may be output to the coefficient setting circuit 103.

  The decoder 113 outputs the selection signal ksel as in the above embodiment.

  The delay element 100 is provided to correct a time lag between the Tap signal input to the multiplier 104 and the Tap coefficient. Therefore, for example, when the influence of Tap3 is large, when the delay amount by the processing in the coefficient selection circuit 102a and the coefficient setting circuit 103 is 3 Tcell, the delay amount in the delay element 100 is set to Tcell. Note that the output timing of the memory 118 may be delayed instead of using the delay element 100. Further, when the influence of Tap3 is great, if Tap3 input to the multiplier 104c is slower than k3, a delay element is provided in front of the coefficient selection circuit 102a instead of the delay element 100. Incidentally, when the influence of Tap3 is large, the delay element 100 is naturally unnecessary if there is no time lag between Tap3 and k3 input to the multiplier 104c.

  In the following, for convenience, a circuit including each delay element, each multiplier, and an adder 117 in the coefficient selection circuit 102a is also referred to as a first signal processing circuit, and includes a delay unit 101, a multiplication unit 104, and an adder 105. The circuit is also referred to as a second signal processing circuit.

  Here, advantages of using the first signal processing circuit will be described. To simplify the explanation, the center level-interference amount relationship is divided into two regions (region A and region B), and the slice level signal (SL) indicating the boundary between region A and region B is the maximum amplitude. It is assumed that it is set to 1/2. A signal level greater than SL is determined as region A. When the reproduction signal is used as it is for condition determination without using the first signal processing circuit, for example, when multi-value data “x” “x” “2” “x” “x” is reproduced, x = 0 Multi-value data “2” is recognized as region A (see FIG. 20A), and correct waveform equalization processing is performed. However, when x = 5, multi-value data “2” is region B is recognized (see FIG. 20B), and correct waveform equalization processing is not performed. Such a phenomenon becomes more remarkable as the multi-value number is larger. In such a case, if the intersymbol interference component is roughly removed from the preceding and succeeding data with a simple circuit using a preset coefficient signal, erroneous recognition can be prevented. Of course, if accuracy is to be pursued in the removal of intersymbol interference components, the first signal processing circuit requires a circuit configuration similar to that of the second signal processing circuit, but unlike the second signal processing circuit. Since it does not lead to a direct continuous data determination error, the first signal processing circuit can fix the coefficient signal and simplify the configuration. If the coefficient signal of the second signal processing circuit is sequentially reflected in the coefficient signal of the first signal processing circuit, the accuracy can be further improved.

  In this case, delay elements (101a ', 101b', 101c ', 101d') having different delay times may be arranged in parallel as shown in FIG. 32 as an example. In this case, the delay time of the delay element 101a 'is Tcell, the delay time of the delay element 101b' is 2Tcell, the delay time of the delay element 101c 'is 3Tcell, and the delay time of the delay element 101d' is 4Tcell. Thus, for example, when distortion occurs in the signal every time it passes through the delay element, it is possible to prevent accumulation of distortion that occurs when the delay elements are arranged in series.

  Further, as shown in FIG. 33 as an example, three addition results (Sn−1, Sn, Sn + 1) obtained from the adder 117 in time series from the memory 118 are output, and the comparator 111 The comparison result between the addition result Sn and the slice level signal SL1 is output, and the newly provided comparator 119a outputs the comparison result between the addition result Sn-1 and the new slice level signal SL3, and is newly provided. The comparator 119b may output a comparison result between the addition result Sn + 1 and the new slice level signal SL4. That is, the history of the sum signal may be used. Here, the level of the target cell is determined by the comparator 111, the level of the cell in front of the target cell is determined by the comparator 119a, and the level of the cell behind the target cell is determined by the comparator 119b. For example, if SL1 = SL3 = SL4 and the level is set to ½ of the maximum amplitude, if Sn-1 <SL3 and Sn + 1 <SL4, the marks in the front and rear cells are It corresponds to the case where both are large, and at this time, it is found that the nonlinearity of intersymbol interference appears remarkably. Here, a total of four waveforms are equalized from the level determination result of the target cell (size relationship with SL1 (2 conditions)) and the mark size in the front and rear cells (size determination (2 conditions)). Characteristics are required. Therefore, the decoder 113 outputs a selection signal ksel corresponding to the comparison result of each comparator. That is, in this case, each register constituting the coefficient setting circuit 103 needs to store four pieces of coefficient information so that the selector can select from them. In the above description, the data of the three cells before and after are used for the condition determination. However, the present invention is not limited to this. The determination may be made with two cells using either the target cell or the front and rear. In addition, when the intersymbol interference is very large, the determination may be performed by the front and rear cells.

  As an example, as shown in FIG. 34, the options (coefficient information) in each selector in the coefficient setting circuit 103 may be corrected.

  As an example, as shown in FIG. 35, optimization of a slice level signal can also be performed. In this case, as shown in FIG. 36 as an example, the slice level update circuit 108 updates the slice level signal in the coefficient selection circuit 102a.

  When the delay element 110 is unnecessary, as shown in FIG. 37 as an example, the coefficient selection circuit 102a inputs the output signal of the delay element 101a to the multiplier 115a instead of the output signal of the delay element 114a. Alternatively, the output signal of the delay element 101b may be input to the multiplier 115b instead of the output signal of the delay element 114b, and the output signal of the delay element 101c may be input to the multiplier 115c instead of the output signal of the delay element 114c. Thereby, the number of parts can be reduced.

  When information is recorded by the binary recording method, the delay time in each delay element is the same as one cycle of the reproduction clock, but for example 1.5 cycles or 2 in consideration of the modulation method. It may be a period.

  Further, in the above embodiment, the case where the phase change type information recording medium is used as the optical disc 15 has been described. In this case, any of a DVD type, a CD type and a next generation information recording medium corresponding to light having a wavelength of about 405 nm may be used.

  In the above embodiment, the case where the optical pickup device includes one semiconductor laser has been described. However, the present invention is not limited thereto, and for example, a plurality of semiconductor lasers that emit light beams having different wavelengths may be included. In this case, for example, at least one of a semiconductor laser that emits a light beam with a wavelength of about 405 nm, a semiconductor laser that emits a light beam with a wavelength of about 660 nm, and a semiconductor laser that emits a light beam with a wavelength of about 780 nm may be included. . That is, the optical disk apparatus may be an optical disk apparatus that supports a plurality of types of optical disks that conform to different standards. At this time, the multi-level recording method may be used for at least one of the plurality of types of optical discs.

1 is a block diagram showing a configuration of an optical disc device according to an embodiment of the present invention. It is a figure for demonstrating multi-value information. It is a figure for demonstrating the optical pick-up apparatus of FIG. It is a figure for demonstrating the waveform equalization circuit of FIG. FIG. 5 is a diagram for explaining a coefficient selection circuit in FIG. 4. It is FIG. (1) for demonstrating intersymbol interference. It is a figure for demonstrating the relationship between the shape of a recording mark, and intersymbol interference. It is a figure for demonstrating the nonlinearity of intersymbol interference. It is a figure for demonstrating the area | region division | segmentation of the nonlinearity of FIG. FIG. 5 is a diagram for explaining the coefficient setting circuit of FIG. 4. It is a figure for demonstrating the effect of waveform equalization. It is a figure for demonstrating an optical resolution characteristic. It is an eye pattern before waveform equalization. It is a flowchart for demonstrating reproduction | regeneration processing. It is a figure for demonstrating the modification of the waveform equalization circuit of FIG. It is a figure for demonstrating the interference between codes | symbols in the recording mark of a shape different from the recording mark of FIG. It is a figure for demonstrating the nonlinearity of the intersymbol interference in FIG. It is FIG. (1) for demonstrating the case where intersymbol interference shows linearity. It is FIG. (2) for demonstrating the case where intersymbol interference shows linearity. 20A and 20B are diagrams for explaining the relationship between the slice level signal and the multilevel data. It is a figure for demonstrating the coefficient selection circuit which can set a slice level signal. It is a figure for demonstrating the waveform equalization circuit which can correct | amend coefficient information. It is a figure for demonstrating the correction signal in FIG. It is a flowchart for demonstrating the correction process of coefficient information. It is a figure for demonstrating the modification of FIG. It is a figure for demonstrating the waveform equalization circuit which can optimize a slice level signal. It is a figure for demonstrating the coefficient selection circuit of FIG. It is a flowchart for demonstrating the optimization process of a slice level signal. It is a figure for demonstrating the interference between codes | symbols in a binary recording system. It is a figure for demonstrating the modification of FIG. It is a figure for demonstrating the coefficient selection circuit in FIG. It is a figure for demonstrating the modification of FIG. FIG. 31 is a diagram for explaining a modification of the coefficient selection circuit in FIG. 30. It is a figure for demonstrating the modification of FIG. It is a figure for demonstrating the modification of FIG. It is a figure for demonstrating the coefficient selection circuit in FIG. It is a figure for demonstrating the modification of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 15 ... Optical disk, 20 ... Optical disk apparatus, 28 ... Reproduction signal processing circuit, 40 ... CPU (processing device), 101 ... Delay part (delay circuit), 102 ... Coefficient selection circuit (part of decision circuit), 103 ... Coefficient setting Circuit (part of decision circuit) 104... Multiplier (multiplier circuit) 105... Adder (adder circuit) 106. Error detection circuit (part of correction circuit) 107. Part), 130... Slice level setting circuit (setting circuit).

Claims (24)

A signal processing method for processing a reproduction signal from an optical disc,
The reproduction signal is based on a signal level of a delay signal corresponding to at least a predetermined delay time among a plurality of delay signals obtained by delaying the reproduction signal according to a plurality of delay times that are different by a predetermined time. And a signal processing method including determining a plurality of multiplication coefficients to be multiplied by the plurality of delayed signals.   In the determining step, the plurality of multiplication coefficients are determined based on a magnitude relationship between a signal level of the delay signal corresponding to the specific delay time and at least one predetermined determination level. The signal processing method according to claim 1.   The signal processing method according to claim 2, wherein a plurality of levels are set as the determination level.   Based on the signal level of at least one of the delay signal corresponding to a delay time shorter by one step than the specific delay time and the delay signal corresponding to a delay time longer by one step than the specific delay time, The signal processing method according to claim 2, further comprising a step of setting the at least one determination level.   In the determining step, the signal level of the delay signal corresponding to the specific delay time, the signal level of the delay signal corresponding to a delay time shorter by one step than the specific delay time, and the specific delay time 2. The signal processing method according to claim 1, wherein the plurality of multiplication coefficients are determined based on a signal level of a delay signal corresponding to a delay time longer by one stage.   6. The determining step includes multiplying each signal level by a plurality of preset values, and determining the plurality of multiplication coefficients based on a sum signal obtained by adding the values. A signal processing method according to claim 1.   7. The determination unit according to claim 6, wherein, in the determining step, the plurality of multiplication coefficients are determined based on a magnitude relationship between a signal level of the sum signal and at least one predetermined determination level. Signal processing method.   The signal processing method according to claim 7, wherein a plurality of determination levels are set.   9. The signal processing method according to claim 6, wherein, in the determining step, the plurality of multiplication coefficients are determined based on a history of the sum signal.   The signal processing method according to claim 1, wherein the reproduction signal is a reproduction signal of information multi-valued into three or more values.   The signal processing method according to claim 1, wherein each of the plurality of delay times is an integral multiple of a period of a reproduction clock. A reproduction signal processing circuit for processing a reproduction signal from an optical disc,
A delay circuit that delays the reproduction signal according to a plurality of delay times that differ by a certain time period, and generates a plurality of delay signals respectively corresponding to the plurality of delay times;
A determination circuit that determines a plurality of multiplication coefficients based on at least a signal level of a delay signal corresponding to a predetermined delay time set in advance among the plurality of delay signals;
A multiplication circuit for multiplying the reproduction signal and the plurality of delayed signals by the plurality of multiplication coefficients respectively to generate a plurality of multiplication signals;
A reproduction signal processing circuit comprising: an addition circuit for adding the plurality of multiplication signals to generate an addition signal.   The determination circuit determines the plurality of multiplication coefficients according to a magnitude relationship between a signal level of a delay signal corresponding to the specific delay time and at least one determination level set in advance. Item 13. A reproduction signal processing circuit according to Item 12.   The reproduction signal processing circuit according to claim 13, wherein a plurality of determination levels are set.   The determination level according to at least one signal level of a delay signal corresponding to a delay time shorter by one step than the specific delay time and a delay signal corresponding to a delay time longer by one step than the specific delay time The reproduction signal processing circuit according to claim 13, further comprising a setting circuit for setting.   The determination circuit includes: a signal level of a delay signal corresponding to the specific delay time; a signal level of a delay signal corresponding to a delay time shorter by one stage than the specific delay time; 13. The reproduction signal processing circuit according to claim 12, wherein the plurality of multiplication coefficients are determined based on a signal level of a delay signal corresponding to a delay time longer by one stage.   17. The determination circuit according to claim 16, wherein the determination circuit multiplies each of the signal levels by a plurality of preset values, and determines the plurality of multiplication coefficients based on a sum signal obtained by adding the values. Reproduction signal processing circuit.   The reproduction signal according to claim 17, wherein the determination circuit determines the plurality of multiplication coefficients based on a magnitude relationship between a signal level of the sum signal and at least one determination level set in advance. Processing circuit.   19. The reproduction signal processing circuit according to claim 18, wherein a plurality of levels are set as the determination level.   The reproduction signal processing circuit according to any one of claims 17 to 19, wherein the determination circuit determines the plurality of multiplication coefficients based on a history of the sum signal.   The correction circuit for correcting at least one of the plurality of multiplication coefficients so as to minimize a difference between the addition signal and a preset target value. The reproduction signal processing circuit according to any one of 20.   The reproduction signal processing circuit according to any one of claims 12 to 21, wherein the reproduction signal is a reproduction signal of information multi-valued into three or more values.   23. The reproduction signal processing circuit according to claim 12, wherein each of the plurality of delay times is an integral multiple of a period of a reproduction clock. An optical disc apparatus that irradiates light onto a recording surface of an optical disc and performs at least reproduction among recording, reproduction, and erasure of information,
The reproduction signal processing circuit according to any one of claims 12 to 23, which processes a reproduction signal from the optical disc;
A processing device for reproducing the information based on an output signal of the reproduction signal processing circuit.