JP2006244660A - Signal processing method, signal processing circuit and optical disk - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify the constitution of a circuit without lowering decoding accuracy. <P>SOLUTION: In a signal processing circuit of the present invention, when performing the decoding processing of a signal which is to be obtained by reproducing an information recording medium by using a PRML method in which a plurality of predicted values are used, coefficients (y0, y+, y-) proportional to the predicted values are multiplied by differences among constants (y0/2, y+/2, y-/2) proportional to the predicted values and digital values of the signal for every predicted values (y0, y+, y-), and branch metrics (Λ0, Λ+, Λ-) are calculated based on the calculated results and a pass metric is generated based on the branch metrics corresponding respectively to the plurality of predicted values and an optimum pass is selected based on the generated pass metric and the history information of the pass metric and decoded signal is generated based on the selected pass. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a signal processing method, a signal processing circuit, and an optical disc apparatus, and more specifically, a signal processing method and signal processing circuit for processing a signal obtained by reproducing an information recording medium, and an optical disc apparatus including the signal processing circuit. About.

  In recent years, with the advancement of digital technology and the improvement of data compression technology, CD (compact disc), CD as a medium for recording information such as music, movies, photos and computer software (hereinafter also referred to as “content”) An optical disc such as a DVD (digital versatile disc) that can record data equivalent to about 7 times the data on a disc having the same diameter as a CD has been attracting attention. The optical disk device to be used has become widespread.

  In this optical disk apparatus, laser light is emitted from a light source, information is recorded by forming a minute spot on the recording surface of the optical disk on which spiral or concentric tracks are formed, and based on the reflected light from the recording surface Information is reproduced.

  Recently, when information is reproduced, signal processing called PRML (Partial Response Maximum Likelihood) has been used (see, for example, Patent Documents 1 to 4). The frequency characteristic of the recording and reproduction system has a partial response characteristic. In the PRML method, a reproduction signal read from an information recording medium is decoded using a Viterbi algorithm which is a kind of maximum likelihood decoding, and a data series is reproduced.

  However, the devices disclosed in Patent Literature 1 to Patent Literature 4 have a large circuit scale for performing PRML signal processing, which is one of the factors that hinder downsizing and cost reduction of the device.

Japanese Patent No. 2877109 JP 2002-324339 A JP 2002-352436 A JP 2004-265478 A

  The present invention has been made under such circumstances, and a first object of the present invention is to provide a signal processing method capable of simplifying arithmetic processing without degrading decoding accuracy.

  A second object of the present invention is to provide a signal processing circuit that can be reduced in size and cost without reducing the decoding accuracy.

  A third object of the present invention is to provide an optical disc apparatus capable of accurately reproducing information recorded on an optical disc.

  The invention according to claim 1 is a signal processing method for decoding a signal obtained by reproducing an information recording medium by a PRML method using a plurality of predicted values, wherein each predicted value is proportional to the predicted value. The signal processing method includes a step of multiplying the difference between the calculated constant and the digital value of the reproduced signal by a coefficient proportional to the predicted value, and calculating a branch metric based on the multiplication result.

  According to this, for each predicted value, the difference between the constant proportional to the predicted value and the digital value of the signal is multiplied by the coefficient proportional to the predicted value, and the branch metric is calculated based on the multiplication result. In this case, since one of the multiplications is a fixed value when calculating the branch metric, the calculation process can be simplified as compared with the conventional multiplication of values that change. This simplification does not affect the decoding result. Therefore, the arithmetic processing can be simplified without reducing the signal decoding accuracy.

  In this case, as in the signal processing method according to claim 2, in the calculation step, an addition result obtained by adding a preset value to the multiplication result can be calculated as the branch metric. .

  In each of the signal processing methods according to claim 1 and 2, as in the signal processing method according to claim 3, the plurality of predicted values include a first predicted value, a second predicted value, and a third predicted value. The second predicted value is 0, the first predicted value and the third predicted value are different in sign and have the same absolute value, and the second predicted value is the same as the second predicted value. The proportional constant and coefficient are both 0, and the constant and coefficient proportional to the first predicted value and the third predicted value may be a constant and coefficient proportional to the absolute value, respectively.

  The invention according to claim 4 is a signal processing circuit for decoding a signal obtained by reproducing an information recording medium using a plurality of predicted values, and for each predicted value, a constant proportional to the predicted value and A branch metric calculation circuit for multiplying a difference from the digital value of the signal by a coefficient proportional to the prediction value and calculating a branch metric based on the multiplication result; and the branch metrics corresponding to the plurality of prediction values, respectively. A path metric calculation circuit that generates a path metric based on the path metric and selects an optimum path based on the generated path metric and path metric history information; and a generation circuit that generates a decoded signal based on the selection result And a signal processing circuit.

  According to this, for each predicted value, the branch metric arithmetic circuit multiplies the difference between the constant proportional to the predicted value and the digital value of the signal by the coefficient proportional to the predicted value, and the branch metric based on the multiplication result. Is calculated. Then, a path metric calculation circuit generates a path metric based on the branch metrics corresponding to the plurality of predicted values, and selects an optimal path based on the generated path metric and path metric history information. A decoding signal is generated by the generation circuit based on the selection result. In this case, in the branch metric arithmetic circuit, since one of the multiplications is a fixed value, the circuit configuration can be simplified as compared with the conventional multiplication of values that change. This simplification does not affect the selection result in the path metric calculation circuit. Therefore, it is possible to reduce the size and cost without reducing the decoding accuracy of the signal.

  In this case, as in the signal processing circuit according to claim 5, the branch metric calculation circuit can set an addition result obtained by adding a preset value to the multiplication result as the branch metric. .

  In each of the signal processing circuits according to claim 4 and 5, as in the signal processing circuit according to claim 6, the plurality of predicted values are a first predicted value, a second predicted value, and a third predicted value. The second predicted value is 0, the first predicted value and the third predicted value are different in sign and have the same absolute value, and the second predicted value. The constant and the coefficient proportional to the value are both 0, and the constant and the coefficient proportional to the first predicted value and the second predicted value may be a constant and a coefficient proportional to the absolute value, respectively. .

  In each of the signal processing circuits according to claims 4 to 6, as in the signal processing circuit according to claim 7, the path metric calculation circuit is further preset with a path metric value calculated at the time of the selection. The correction can be made to be within the range.

  In each of the signal processing circuits according to claims 4 to 6, as in the signal processing circuit according to claim 8, the path metric calculation circuit further sets a path metric value calculated at the time of the selection in advance. When it is out of the range, the branch metric calculation circuit is notified to that effect, and the branch metric calculation circuit can further correct the branch metric when the notification is received.

  According to a ninth aspect of the present invention, there is provided an optical disc apparatus that irradiates light onto a recording surface of an optical disc and performs at least reproduction of information recording, reproduction, and erasing, and an optical pickup device; 9. An optical disc apparatus comprising: a signal processing circuit according to claim 4 that processes a signal from the optical disc obtained in this manner; and a control device that controls the optical pickup device and the signal processing circuit. It is.

  According to this, since the signal processing circuit according to any one of claims 4 to 8 is provided, information recorded on the optical disc can be reproduced with high accuracy.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a schematic configuration of an optical disc apparatus 20 according to an embodiment of the present invention.

  An optical disk device 20 shown in FIG. 1 includes a spindle motor 22 for rotating the optical disk 15, an optical pickup device 23, a seek motor 21 for driving the optical pickup device 23 in the sledge direction, a laser control circuit 24, An encoder 25, a drive control circuit 26, a reproduction signal processing circuit 28, a buffer RAM 34, a buffer manager 37, an interface 38, a flash memory 39, a CPU 40, a RAM 41, and the like are provided. Note that the arrows in FIG. 1 indicate the flow of typical signals and information, and do not represent the entire connection relationship of each block. In the present embodiment, an information recording medium that conforms to the DVD standard is used for the optical disc 15 as an example.

  The optical pickup device 23 is a device for irradiating the recording surface of the optical disk 15 on which spiral or concentric tracks are formed with laser light and receiving reflected light from the recording surface. The optical pickup device 23 includes a semiconductor laser as a light source, an optical system that guides a light beam emitted from the semiconductor laser to a recording surface of the optical disc 15 and guides a return light beam reflected by the recording surface to a predetermined light receiving position. The light receiving device is arranged at the light receiving position and receives the return light beam, and includes a drive system (focusing actuator and tracking actuator) (both not shown). Then, a signal corresponding to the amount of received light is output from the light receiver to the reproduction signal processing circuit 28.

  The reproduction signal processing circuit 28 includes an I / V amplifier 28a, a servo signal detection circuit 28b, a wobble signal detection circuit 28c, an RF signal detection circuit 28d, a decoder 28e, and the like.

  The I / V amplifier 28a converts the output signal of the light receiver constituting the optical pickup device 23 into a voltage signal and amplifies it with a predetermined gain.

  The servo signal detection circuit 28b detects servo signals such as a focus error signal and a track error signal based on the output signal of the I / V amplifier 28a. The servo signal detected here is output to the drive control circuit 26.

  The wobble signal detection circuit 28c detects a wobble signal based on the output signal of the I / V amplifier 28a. The RF signal detection circuit 28d detects an RF signal based on the output signal of the I / V amplifier 28a.

  The decoder 28e extracts address information and a synchronization signal from the wobble signal. The address information extracted here is output to the CPU 40, and the synchronization signal is output to the encoder 25 and the like.

  The decoder 28e performs a decoding process and an error detection process on the RF signal. When an error is detected, the decoder 28e performs an error correction process, and then stores the reproduced data in the buffer RAM 34 via the buffer manager 37. To do. Here, as shown in FIG. 2 as an example, an equalization circuit e1 that performs equalization processing on an RF signal and an output signal s (t) (see FIG. 3A) of the equalization circuit e1 are sampled. An ADC circuit e2 for converting to a digital value, a decoding circuit e3 for generating a decoded signal o (t) from an output signal p (t) of the ADC circuit e2 (see FIG. 3B), and the like. Details of the decoding circuit e3 will be described later.

  The drive control circuit 26 generates a drive signal for the tracking actuator for correcting the displacement of the objective lens 60 in the tracking direction based on the track error signal from the reproduction signal processing circuit 28. The drive control circuit 26 also generates a driving signal for the focusing actuator for correcting the focus shift of the objective lens 60 based on the focus error signal from the reproduction signal processing circuit 28. The drive signals for the actuators generated here are output to the optical pickup device 23. Thereby, tracking control and focus control are performed. Furthermore, the drive control circuit 26 generates a drive signal for driving the seek motor 21 and a drive signal for driving the spindle motor 22 based on an instruction from the CPU 40. The drive signal of each motor is output to the seek motor 21 and the spindle motor 22, respectively.

  The buffer RAM 34 temporarily stores data to be recorded on the optical disc 15 (recording data), data reproduced from the optical disc 15 (reproduction data), and the like. Data input / output to / from the buffer RAM 34 is managed by the buffer manager 37.

  The encoder 25 takes out the recording data stored in the buffer RAM 34 through the buffer manager 37 based on an instruction from the CPU 40, modulates the data, adds an error correction code, and the like, and writes a signal to the optical disc 15. Is generated. The write signal generated here is output to the laser control circuit 24.

  The laser control circuit 24 controls the light emission power of the semiconductor laser. For example, during recording, a laser control circuit 24 generates a drive signal for the semiconductor laser based on the write signal, the recording conditions, the light emission characteristics of the semiconductor laser, and the like.

  The interface 38 is a bidirectional communication interface with a host device 90 (for example, a personal computer), and is a standard interface such as ATAPI (AT Attachment Packet Interface), SCSI (Small Computer System Interface), and USB (Universal Serial Bus). It is compliant.

  The flash memory 39 stores various programs written in codes readable by the CPU 40, recording conditions including recording power and recording strategy information, and light emission characteristics of the semiconductor laser.

  The CPU 40 controls the operation of each unit in accordance with the program stored in the flash memory 39 and stores data necessary for control in the RAM 41 and the buffer RAM 34.

  Here, the PRML will be described. PRML considers the frequency characteristics of recording and reproduction systems having partial response characteristics, and performs a decoding process using a Viterbi algorithm, which is a type of maximum likelihood decoding, on a reproduction signal read from an information recording medium. It is something to regenerate.

  Here, for the sake of easy understanding, the simplest PR (1, 1) channel among various partial response characteristics will be described. A state transition diagram of this PR (1, 1) channel is shown in FIG. That is, if the input is 1 in state S0, y0 is output and the state transitions to state S1. If the input is 0 in state S0, y- is output and the state does not change. On the other hand, if the input is 0 in state S1, y0 is output and the state transitions to state S0. If the input is 1 in state S1, y + is output and the state does not change. As an example, as shown in FIG. 3B, the PR (1, 1) channel is applied when the reproduction signal after AD conversion is one of three reference values (y-, y0, y +). Is done.

  The branch metrics (λ− (t), λ0 (t), λ + (t)) at time t are calculated by the following equations (1) to (3).

λ− (t) = [p (t) − y−] ² …… (1)
λ0 (t) = [p (t) −y0] ² …… (2)
λ + (t) = [p (t) −y +] ² …… (3)

  Further, the path metrics (L0 (t), L1 (t)) at time t are calculated by the following equations (4) and (5). Note that min [A, B] is a function representing the minimum value of A and B.

L0 (t) = min [L0 (t-1) + λ- (t), L1 (t-1) + λ0 (t)] (4)
L1 (t) = min [L0 (t-1) + λ0 (t), L1 (t-1) + λ + (t)] (5)

  By the way, the decoding result in the Viterbi algorithm is determined by the selection result of the minimum path in the path metric calculation. Therefore, even if the same value is added to or subtracted from all path metrics at the same time, there is no change in the relative magnitude relationship between the path metrics, so there is no difference in the history information of the path selection signal, and the decoding results are the same. It becomes. The same is true when the same value is added to or subtracted from all branch metrics at the same time.

  When the above formulas (1) to (3) are expanded, the following formulas (6) to (8) are obtained.

λ- (t) ＝ p (t) ² −2 ・ p (t) ・ y- ＋ (y-) ² …… （6）
λ0 (t) ＝ p (t) ² −2 ・ p (t) ・ y0 + (y0) ² ...... (7)
λ + (t) ＝ p (t) ² −2 ・ p (t) ・ y + ＋ (y +) ² …… （8）

  Substituting the above expressions (6) to (8) into the above expressions (4) and (5), the following expressions (9) and (10) are obtained.

L0 (t) = min [L0 (t-1) + [y- − p (t)] ² , L1 (t-1) + [y0 − p (t)] ² ]
= Min [L0 (t-1) + p (t) ² − 2 • p (t) • y- + (y-) ² ,
L1 (t-1) + p (t) 2 - 2 · p (t) · y0 + (y0) 2] ...... (9)
L1 (t) = min [L0 (t-1) + [y0 − p (t)] ² , L1 (t-1) + [y + − p (t)] ² ]
= Min [L0 (t-1) + p (t) ² − 2 • p (t) • y0 + (y0) ² ,
L1 (t-1) + p (t) 2 - 2 · p (t) · y + + (y +) 2] ...... (10)

As shown in the above equations (9) and (10), the two path metrics have a common term p (t) ² . p (t) ² is a value that changes at each time t, but is a term that is common to both path metrics at the same time. Even if the p (t) ² is subtracted from both path metrics at the same time, the relative magnitude relationship between the path metrics does not change. Further, p (t) ² is a term that exists in common to all three branch metrics. Therefore, as shown in the following formulas (11) to (13), the path metric calculation is performed using the value obtained by subtracting p (t) ² from all the branch metrics, and the decoding result is obtained even if the Viterbi decoding is performed. Are the same.

λ- (t) − p (t) ² = (y-) ² −2 ・ y- ・ p (t)
= Y- ・ [y- −2 ・ p (t)] (11)
λ0 (t) − p (t) ² = (y0) ² −2 ・ y0 ・ p (t)
= Y0 ・ [y0−2 ・ p (t)] (12)
λ + (t) − p (t) ² = (y +) ² −2 ・ y + ・ p (t)
= Y + ・ [y + − 2 ・ p (t)] (13)

  Furthermore, even if all the branch metrics are multiplied by a constant positive value, the relative magnitude relationship between the path metrics is not changed, and the decoding result is the same. Therefore, in this embodiment, the following equations (14) to (16) are obtained by multiplying the above equations (11) to (13) by ½.

(λ- (t) −p (t) ² ) / 2 = y− · [y- / 2−p (t)] (14)
(λ0 (t) − p (t) ² ) / 2 = y0 · [y0 / 2 − p (t)] (15)
(λ + (t) −p (t) ² ) / 2 = y + · [y + / 2−p (t)] (16)

  Therefore, in this specification, the left sides of the above equations (14) to (16) are Λ− (t), Λ0 (t), and Λ + (t), respectively, and these are newly defined as branch metrics (next) (See formulas (17) to (19)).

Λ- (t) = y- · [y- / 2-p (t)] (17)
Λ0 (t) = y0 · [y0 / 2 − p (t)] (18)
Λ + (t) = y + · [y + / 2−p (t)] (19)

  Next, the decoding circuit e3 will be described.

  As shown in FIG. 5 as an example, the decryption circuit e3 includes a branch metric calculation circuit 11, a path metric calculation circuit 13, and a path memory 18 as a generation circuit.

  The branch metric calculation circuit 11 uses the output signal p of the ADC circuit e2 and the three predicted values (y−, y0, y +) to newly define the branch metrics (Λ− (t), Λ0 (t), Λ + (t)) is calculated. Here, as shown in FIG. 6 as an example, there are provided three subtracters (111, 112, 113), three coefficient units (114, 115, 116), three registers (117, 118, 119), and the like. ing.

  In the subtractor 111, a difference signal between the output signal p (t) of the ADC circuit e2 and 1/2 of the predicted value y + is generated. The subtractor 112 generates a difference signal between the output signal p (t) of the ADC circuit e2 and 1/2 of the predicted value y0. In the subtractor 112, a difference signal between the output signal p (t) of the ADC circuit e2 and 1/2 of the predicted value y− is generated.

  The coefficient unit 114 multiplies the output signal of the subtractor 111 by the predicted value y +. The multiplication result in the coefficient unit 114 is output to the register 117.

  The coefficient unit 115 multiplies the output signal of the subtractor 112 by the predicted value y0. The multiplication result in the coefficient unit 115 is output to the register 118.

  The coefficient unit 116 multiplies the output signal of the subtractor 113 by the predicted value y−. The multiplication result in coefficient unit 116 is output to register 119.

That is, the branch metric calculation circuit 11 performs the calculations of the above equations (17) to (19), and the calculation result is the branch metric (Λ− (t), Λ0 (t), Λ + (t )) Is output as y- ² .

  The path metric calculation circuit 13 selects a minimum one of the integrated values of branch metrics corresponding to each of a plurality of paths input to each state at a certain time based on the path of the trellis diagram. A trellis diagram corresponding to the state transition diagram of FIG. 4 is shown in FIG.

  Here, as shown in FIG. 8 as an example, the path metric calculation circuit 13 includes four adders (131, 132, 133, 134), two selectors (136, 137), and two comparators (135, 138) and two registers (139, 140).

  The adder 131 generates an addition signal of the branch metric Λ + (t) and the path metric L1 at the previous time. The adder 132 generates an addition signal of the branch metric Λ0 (t) and the path metric L0 at the previous time. The adder 133 generates an addition signal of the branch metric Λ0 (t) and the path metric L1 at the previous time. The adder 134 generates an addition signal of the branch metric Λ- (t) and the path metric L0 at the previous time.

  The comparator 135 compares the output signal of the adder 131 and the output signal of the adder 132, and outputs a comparison result. The comparator 138 compares the output signal of the adder 133 and the output signal of the adder 134, and outputs a comparison result. The output signal of the comparator 135 is output to the path memory 18 as the path selection signal SEL1. The output signal of the comparator 138 is output to the path memory 18 as the path selection signal SEL0.

  The selector 136 selects the smaller one of the output signal of the adder 131 and the output signal of the adder 132 based on the output signal of the comparator 135 and sets it as a new path metric L1. This new path metric L1 is stored in the register 139.

  The selector 137 selects the smaller one of the output signal of the adder 133 and the output signal of the adder 134 based on the output signal of the comparator 138 and sets it as a new path metric L0. The new path metric L0 is stored in the register 140.

  That is, in the path metric calculation circuit 13, Λ- (t) instead of λ- (t) in the above equations (4) and (5), Λ0 (t), λ + (t) instead of λ0 (t) ) Instead of Λ + (t) is performed, and path metrics (L0 (t), L1 (t)) at time t are obtained.

  The path memory 18 stores a history of path selection signals, and estimates and outputs the most likely value. Here, as shown in FIG. 9 as an example, the path memory 18 stores a plurality of selectors 151 that select one of two input signals in accordance with the path selection signal SEL1, and selection results from the selectors 151, respectively. A plurality of registers 152, a plurality of selectors 161 for selecting one of two input signals according to the path selection signal SEL0, a plurality of registers 162 for storing the selection results of the selectors 161, respectively. . That is, the output of the register connected to the previous stage is transmitted to the subsequent stage according to the structure of the trellis diagram according to the path selection signal. In each selector in the first stage, 0 and 1 are two input signals. If the number of stages in the path memory is sufficiently long, the detection values in the respective states are merged at a certain point, and the same value is obtained in the final stage. This value is the decoded signal o (t).

  A decoded signal o (t) corresponding to the output signal p (t) of the ADC circuit e2 shown in FIG. 3B is shown in FIG. Decoded with high accuracy. The output timing of o (t) is delayed from the generation timing of p (t) by the signal processing time (assumed to be k) in the composite circuit e3. The delay time k here increases as the number of register stages in the path memory 18 increases.

  As is clear from the above description, in the optical disk device 20 according to the present embodiment, a signal processing circuit is configured by the decoding circuit e3. Further, the control device is configured by the CPU 40 and a program executed by the CPU 40. Note that at least a part of the control device realized by processing according to the program by the CPU 40 may be configured by hardware, or all may be configured by hardware.

  In the present embodiment, the signal processing method of the present invention is implemented in the decoding circuit e3.

  As described above, according to the decoding circuit 28e according to the present embodiment, the branch metric calculation circuit 11 has a circuit configuration that can obtain the same Viterbi decoding result as before without performing the square calculation. This eliminates the need for a multiplier for square calculation, and can simplify the circuit compared to the conventional branch metric calculation circuit (see FIG. 11). Since the coefficient unit is a circuit that always multiplies a constant value (fixed value), the circuit scale is small compared to a multiplier for square calculation.

  In addition, according to the optical disc apparatus 20 according to the present embodiment, since the decoded signal can be obtained with high accuracy by the decoding circuit 28e, information recorded on the optical disc can be reproduced with high accuracy.

<< Modification 1 >>
In the above embodiment, when the following equations (20) and (21) are satisfied, the branch metric calculation circuit 11A shown in FIG. 12 is replaced with the branch metric calculation circuit 11 in the above embodiment. It may be used.

y0 = 0 (20)
y- = -y + (21)

  Substituting this relationship into the above equations (17) to (19) yields the following equations (22) to (24).

[Lambda]-(t) = y +. [Y + / 2 + p (t)] (22)
Λ0 (t) = 0 (23)
Λ + (t) = y + · [y + / 2−p (t)] (24)

  Furthermore, even if all the branch metrics are multiplied by a constant positive value, the relative magnitude relationship between the path metrics is not changed, and the decoding result is the same. Therefore, the values (Λ − ′ (t), Λ0 ′ (t), Λ obtained by the following expressions (25) to (27) obtained by multiplying the expressions (22) to (24) by 1 / y + respectively. + ′ (T)) can be newly defined as a branch metric.

Λ-´ (t) = y + / 2 + p (t) (25)
Λ0 ′ (t) = 0 (26)
λ + ´ (t) = y + / 2 − p (t) (27)

  The branch metric calculation circuit 11A realizes the calculations of the above formulas (25) to (27). This eliminates the need for the subtractor 112, the three coefficient units (114, 115, 116), and the register 118 in the branch metric arithmetic circuit 11, and can further reduce the size and cost.

  In this case, a path metric calculation circuit 13A shown in FIG. 13 can be used instead of the path metric calculation circuit 13 in the above embodiment. That is, the adders 132 and 133 in the path metric calculation circuit 13 are not necessary, and the path metric calculation circuit can be downsized.

<< Modification 2 >>
Even if a constant value is added to the above equations (25) to (27), the relative magnitude relationship between the path metrics is not changed, and the decoding result is the same. Therefore, values (Λ − ″ (t), Λ0 ″ (t), Λ + obtained by the following equations (28) to (30) obtained by adding a constant value k to the above equations (25) to (27). ″ (T)) can be newly defined as a branch metric.

Λ-″ (t) = y + / 2 + p (t) + k (28)
Λ0 ″ (t) = k ...... (29)
Λ + ″ (t) = y + / 2−p (t) + k (30)

  The branch metric calculation circuit 11B shown in FIG. 14 realizes the calculations of the above expressions (28) to (30).

  By the way, if the maximum value of the absolute value of the amplitude of p (t) is set to pmax, the branch metric value is always positive if the value of k is set so that the condition shown by the following equation (31) is satisfied. Value.

k> pmax−y + / 2 (31)

  As a result, there is no need to distinguish between positive and negative values, and the circuit can be further simplified, so that the branch metric calculation circuit and path metric calculation circuit can be further reduced in size and cost.

<< Modification 3 >>
Further, in place of the path metric calculation circuit 13 in the above embodiment, a path metric calculation circuit 13B shown in FIG. 15 may be used.

  The path metric calculation circuit 13B is obtained by adding a normalization control circuit 141 and two subtracters (142, 143) to the path metric calculation circuit 13.

  The normalization control circuit 141 outputs a normalization signal to the two subtracters (142, 143) when one of the two path metrics L0 and L1 is equal to or greater than a predetermined threshold value. When the normalization signal is output, the subtractor 142 subtracts a predetermined correction value from the path metric L1, and outputs a normalized path metric L11. When the normalized signal is output, the subtracter 143 subtracts a predetermined correction value from the path metric L0, and outputs a normalized path metric L10.

  As shown in FIG. 16, the normalization control circuit 141 receives only the upper 2 bits of the two path metrics L0 and L1 when the bit width of the path metric is 8 bits. The normalization control circuit 141 is composed of an AND gate and an OR gate, and a normalization signal is output when either the upper 2 bits of L0 or the upper 2 bits of L1 is “11”. . In other words, when either L0 or L1 is greater than or equal to “192” in decimal notation (“1100 0000” in binary notation), a normalized signal is output. When the normalized signal is output, “01” is subtracted from the upper 2 bits of L0 and L1 in binary notation, and becomes the upper 2 bits of the branch metrics L10 and L11 after normalization. The lower 6 bits of L0 and L1 become the lower 6 bits of L10 and L11 as they are. In other words, “64” in decimal notation (“0100 0000” in binary notation) is subtracted from L0 and L1. That is, in the third modification, when one of the two path metrics L0 and L1 is equal to or greater than the predetermined threshold “192”, the predetermined correction value “64” is subtracted from the path metrics L0 and L1 to obtain the normal value. Path metrics L10 and L11.

  Thereby, it is possible to prevent an overflow of the path metric value due to repeated integration. Specifically, if the threshold is made smaller than the maximum value that can be processed by the path metric arithmetic circuit minus the maximum value of the branch metric, the value obtained by adding the branch metric after normalization is processed. It is below the maximum possible value, and overflow can be prevented. Further, in the third modification, normalization processing is performed with the same clock as when a branch metric equal to or greater than the threshold is detected. However, when there is a delay from threshold detection to normalization, the threshold is further increased according to the delay amount. By setting low, overflow can be prevented. The correction value is set to be smaller than a value obtained by subtracting the maximum value difference between values that can be taken by the path metrics from the threshold value. By doing so, the minimum one of the plurality of path metrics can prevent underflow due to overcorrection.

  Thus, path metric overflow can be prevented with an extremely simple circuit. For this reason, even if an overflow prevention function is added, it is possible to reduce the size and speed as compared with the conventional case.

<< Modification 4 >>
Further, instead of the branch metric calculation circuit 11 in the above embodiment, a branch metric calculation circuit 11C shown in FIG. 17 is used, and in place of the path metric calculation circuit 13 in the above embodiment, a path metric shown in FIG. An arithmetic circuit 13C may be used. Here, the normalization process is performed by the branch metric calculation circuit 11C. When the normalized signal is input, the subtracter (120, 121, 122) of the branch metric calculation circuit 11C subtracts a predetermined correction value from the branch metric to obtain a normalized branch metric. Even when the normalization is performed by the branch metric calculation circuit, the integration amount in the path metric calculation unit is limited, so that the overflow of the path metric can be prevented as in the third modification. In addition, when normalization is performed by a branch metric arithmetic circuit, a delay occurs between the threshold detection and normalization due to the delay caused by the presence of each register, but as described above, the threshold is set low according to the delay amount By doing so, overflow can be prevented.

  Furthermore, the path metric calculation needs to repeat the addition-comparison-select operation processing loop every clock, and the path metric calculation circuit is required to have high speed. Here, since the normalization processing is not performed in the arithmetic processing loop but is performed by the branch metric arithmetic circuit, circuit operation at a higher speed than that of the third modification is possible. As shown in FIG. 19, a normalization function may be added to the branch metric calculation circuit 11B.

  Further, in the above embodiment and each modification, the case of the PR (1, 1) channel has been described, but the present invention is not limited to this. Many other types of PR channels have been proposed, and different numbers of prediction values and path metrics are used, but the present invention is also effective for them.

  In the above-described embodiment, the case where the optical disk apparatus is compatible with a disk compliant with the DVD standard has been described. However, the present invention is not limited to this. For example, the next generation corresponding to a CD and light having a wavelength of about 405 nm. The information recording medium may be used.

  In the above embodiment, the case where the optical pickup device includes one semiconductor laser has been described. However, the present invention is not limited thereto, and for example, a plurality of semiconductor lasers that emit laser beams having different wavelengths may be included. In this case, for example, at least one of a semiconductor laser that emits laser light having a wavelength of about 405 nm, a semiconductor laser that emits laser light having a wavelength of about 660 nm, and a semiconductor laser that emits laser light having a wavelength of about 780 nm is included. May be. That is, the optical disk apparatus may be an optical disk apparatus that supports a plurality of types of optical disks that conform to different standards.

  As described above, the signal processing method of the present invention is suitable for simplifying the arithmetic processing without reducing the decoding accuracy. The reproduction signal processing circuit of the present invention is suitable for downsizing and cost reduction without reducing the decoding accuracy. Also, the optical disk device of the present invention is suitable for accurately reproducing information recorded on the optical disk.

1 is a block diagram showing a configuration of an optical disc device according to an embodiment of the present invention. It is a figure for demonstrating a part of decoder in FIG. FIG. 3A is a waveform diagram for explaining the output signal of the equalization circuit, and FIG. 3B is a sampling chart for explaining the output signal of the ADC circuit. It is a state transition diagram of the PR (1, 1) channel. It is a figure for demonstrating the decoding circuit in FIG. It is a figure for demonstrating the branch metric calculation circuit in FIG. FIG. 5 is a trellis diagram corresponding to the state transition diagram of FIG. 4. It is a figure for demonstrating the path metric calculation circuit in FIG. FIG. 6 is a diagram for explaining a path memory in FIG. 5. It is a figure for demonstrating the decoded signal output from a decoding circuit. It is a figure for demonstrating the conventional branch metric calculation circuit. FIG. 10 is a diagram for explaining a branch metric calculation circuit in Modification 1; FIG. 11 is a diagram for explaining a path metric calculation circuit in Modification 1; FIG. 10 is a diagram for explaining a branch metric calculation circuit in Modification 2; FIG. 10 is a diagram for explaining a path metric calculation circuit in Modification 3. It is a figure for demonstrating the normalization control circuit in FIG. It is a figure for demonstrating the branch metric calculation circuit in the modification 4. It is a figure for demonstrating the path metric calculation circuit in the modification 4. It is a figure for demonstrating the branch metric calculation circuit by which the normalization control function was added to the branch metric calculation circuit of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Branch metric calculation circuit, 13 ... Path metric calculation circuit, 15 ... Optical disk (information recording medium), 18 ... Path memory (generation circuit), 20 ... Optical disk apparatus, 23 ... Optical pick-up apparatus, 40 ... CPU (control apparatus) E3... Decoding circuit (signal processing circuit).

Claims (9)

A signal processing method for decoding a signal obtained by reproducing an information recording medium by a PRML method using a plurality of predicted values,
Signal processing including a step of multiplying a difference between a constant proportional to a predicted value and a digital value of the signal for each predicted value by a coefficient proportional to the predicted value and calculating a branch metric based on the multiplication result Method.   The signal processing method according to claim 1, wherein in the step of calculating, an addition result obtained by adding a preset value to the multiplication result is calculated as the branch metric. The plurality of predicted values include a first predicted value, a second predicted value, and a third predicted value,
The second predicted value is 0, the first predicted value and the third predicted value have different signs, and the absolute values are equal to each other,
The constant and coefficient proportional to the second predicted value are both 0,
3. The signal processing method according to claim 1, wherein the constant and the coefficient proportional to the first predicted value and the third predicted value are a constant and a coefficient proportional to the absolute value, respectively. A signal processing circuit for decoding a signal obtained by reproducing an information recording medium using a plurality of predicted values,
A branch metric computation circuit that multiplies the difference between a constant proportional to the prediction value and the digital value of the signal for each prediction value by a coefficient proportional to the prediction value and calculates a branch metric based on the multiplication result; ;
A path metric calculation circuit that generates a path metric based on the branch metrics corresponding to the plurality of predicted values, and selects an optimal path based on the generated path metric and path metric history information;
And a generation circuit that generates a decoded signal based on the selection result.   5. The signal processing circuit according to claim 4, wherein the branch metric calculation circuit uses the addition result obtained by adding a preset value to the multiplication result as the branch metric. The plurality of predicted values include a first predicted value, a second predicted value, and a third predicted value,
The second predicted value is 0, the first predicted value and the third predicted value are different in sign and have the same absolute value,
The constant and coefficient proportional to the second predicted value are both 0,
6. The signal processing circuit according to claim 4, wherein the constant and the coefficient proportional to the first predicted value and the second predicted value are a constant and a coefficient proportional to the absolute value, respectively.   The path metric calculation circuit further corrects the path metric value calculated at the time of the selection to be within a preset range. Signal processing circuit. The path metric calculation circuit further notifies the branch metric calculation circuit when the value of the path metric calculated at the time of selection is outside a preset range,
The signal processing circuit according to claim 4, wherein the branch metric calculation circuit further corrects the branch metric upon receiving the notification. An optical disc apparatus that irradiates light onto a recording surface of an optical disc and performs at least reproduction among recording, reproduction, and erasure of information,
An optical pickup device;
The signal processing circuit according to any one of claims 4 to 8, which processes a signal from the optical disc acquired through the optical pickup device;
An optical disc apparatus comprising: the optical pickup device; and a control device that controls the signal processing circuit.

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