JP2011165245A - Decoding device, reproducing device, and decoding method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve stable decoding operation in combination of adaptive equalization processing and adaptive Viterbi processing. <P>SOLUTION: The decoding device performs adaptive equalization in which frequency characteristic of partial response equalization adaptively follows the frequency characteristic of an input signal, and adaptive Viterbi decoding in which the identification point of the maximum likelihood decoding adaptively follows an input signal characteristic. At this time, while using the value of the identification point adaptively controlled by adaptive Viterbi decoding as an equalization target of adaptive equalization, at least the equalization target of adaptive equalization for one or both of the minimum and maximum levels of the input signal is fixed or substantially fixed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a decoding apparatus, a reproducing apparatus, and a decoding method in a system that performs recording and reproduction using PRML decoding (Partial Response Maximum Likelihood (PRML)).

Japanese Patent No. 324349

  In a high-density magnetic recording / reproducing apparatus and optical recording / reproducing apparatus, PRML decoding is generally used for binarization decoding of an information signal read from a recording medium. The PRML decoding device includes a partial response equalization circuit and a maximum likelihood decoding circuit.

In the partial response equalization circuit, adaptive equalization is generally used in which the equalization characteristic is adaptively controlled so as to approach the ideal partial response in order to follow variations in recording characteristics and fluctuations in the reproduction state.
However, the transmission path for magnetic recording / reproduction and optical recording / reproduction is not completely regarded as an ideal partial response transmission path, and there is a drawback that deviation from the ideal value occurs even with adaptive equalization.

In the maximum likelihood decoding circuit, a Viterbi algorithm for determining a most probable decoded data string from a likelihood history for decoded data at each sample time is generally used, and is also called a Viterbi decoding circuit.
Also corrects deviations (equalization errors) where the transmission path is not an ideal partial response transmission path, vertical asymmetry (asymmetry) of the RF waveform due to nonlinearity, and distortion components that can occur in both optical and electrical systems. Therefore, an adaptive Viterbi circuit that adaptively controls the discrimination point of the input stage of the Viterbi decoding circuit according to input data is also used in the high-density recording / reproducing circuit.
An example of the configuration of the adaptive Viterbi circuit is described in Patent Document 1 described above. Here, the PR class having an intersymbol interference length of 2 or 3 is described. However, the update method of the discrimination point (amplitude reference level) can be generalized even when the intersymbol interference length becomes 4 or 5. It is.

Here, consider the combined use of an adaptive equalization circuit and an adaptive Viterbi circuit. In this case, the adaptive equalization target value in the adaptive equalization circuit is replaced with the amplitude reference level (identification point) cABC (A, B, C is 0 or 1) controlled by the adaptive Viterbi circuit, and the equalization error is reduced. It is most desirable to calculate. This is because the smaller the equalization error (the error between the equalization circuit output and the target value) is less affected by asymmetry and the like, and the convergence of adaptive equalization is stabilized.
However, if the equalization target of the adaptive equalization circuit and the identification point of the adaptive Viterbi circuit are linked together and both are adaptively operated at the same time, both controls interfere, and each control is in a state different from the characteristic that should be converged. There are cases where it falls.

This will be described with reference to FIGS. In each figure, the horizontal axis is the time axis, and the values of the equalized reproduction signal (dots are the respective reproduction signal values), the change in the reference level (identification point) of the Viterbi circuit, and the change in the target value of the adaptive equalization circuit Show.
This is a case of PR (1, 2, 2, 1), and 10 values and 6 states are obtained. Each identification point has a predetermined value as an initial value corresponding to c1111, c0111 (c1110), c0110, c1100 (c0011), c1001, c0001 (c1000), and c0000 from the maximum amplitude value side.
FIG. 9 shows a case where the Viterbi decoding circuit side does not perform adaptive control for the discrimination point. That is, the reference level is not updated and the initial value is maintained. In accordance with this, the equalization target in the adaptive equalization circuit does not change. In this case, there is no problem with the equalized reproduction signal.
FIG. 10 shows a case where the Viterbi decoding circuit side performs adaptive control for the discrimination point and the discrimination point (reference level) is updated. However, the equalization target in the adaptive equalization circuit is fixed. In this case, there is no problem with the equalized reproduction signal.
FIG. 11 shows a case where the equalization target of the adaptive equalization circuit and the identification point of the adaptive Viterbi circuit are linked as described above, and both are adaptively operated simultaneously. The Viterbi decoding circuit side performs adaptive control for the discrimination point, and the discrimination point (reference level) is updated. Further, the reference level at which the equalization target in the adaptive equalization circuit is also updated is used.
In this case, both controls interfere. That is, as shown in FIG. 11, the reference level and the equalization target of the reproduction signal maximum point (c1111) and the minimum point (c0000) deviate monotonously from the original values, and the amplitude of the equalized reproduction signal increases with time. The phenomenon of becoming smaller is occurring.

Unless such interference can be avoided, it is difficult to operate the adaptive equalization circuit and the adaptive Viterbi circuit simultaneously.
As one method for avoiding this drawback, it is effective to greatly reduce the control band of either the discrimination point or the equalization target. However, reducing the bandwidth of adaptive control that should be followed quickly does not meet the original purpose of adaptive control and leads to deterioration in reading performance.

  SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to solve interference between an adaptive equalization circuit and an adaptive Viterbi circuit, operate both more effectively, and as a result, improve reading performance and margin.

  A decoding apparatus according to the present invention is a Viterbi decoding circuit that performs maximum likelihood decoding on an input signal and outputs decoded data, and an adaptive Viterbi decoding circuit that adaptively tracks an identification point of maximum likelihood decoding to input signal characteristics; An equalization circuit that performs partial response equalization on an input signal to the adaptive Viterbi decoding circuit, and performs adaptive equalization processing that adaptively follows the frequency characteristics of the partial response equalization to the frequency characteristics of the input signal. , Using the value of the discrimination point adaptively controlled by the adaptive Viterbi decoding circuit as an equalization target for adaptive equalization, and equalization target for adaptive equalization for one or both of the minimum level and the maximum level of the input signal Includes an adaptive equalization circuit that is fixed or substantially fixed.

In addition, the adaptive Viterbi decoding circuit stops or substantially stops the adaptive control for one or both of the identification points corresponding to the minimum level and the maximum level of the input signal as the identification point, so that the adaptation etc. The equalization target of adaptive equalization for one or both of the minimum level and the maximum level of the input signal in the equalization circuit is fixed or substantially fixed.
In particular, the adaptive Viterbi decoding circuit stops or substantially stops adaptive control only for the identification point corresponding to the minimum level of the input signal as the identification point, so that the adaptive equalization circuit Only the equalization target for adaptive equalization with respect to the minimum level is fixed or substantially fixed.
Alternatively, the adaptive equalization circuit does not use the value of the discrimination point in the adaptive Viterbi decoding circuit for the equalization target of adaptive equalization for one or both of the minimum level and the maximum level of the input signal. The adaptive equalization target for one or both of the minimum level and the maximum level of the input signal in the adaptive equalization circuit is fixed.
In particular, the adaptive equalization circuit does not use the value of the discrimination point in the adaptive Viterbi decoding circuit only for the equalization target of adaptive equalization with respect to the minimum level of the input signal, so that the input in the adaptive equalization circuit Only the equalization target for adaptive equalization for the minimum level of the signal is fixed.
The reproducing apparatus of the present invention includes an information reading unit that reads an information signal from a recording medium, and a decoding unit that performs a decoding process on the information signal read by the information reading unit. The decoding unit is configured as the decoding device.

  The decoding method of the present invention performs partial response equalization for an input signal, and adaptive equalization processing for adaptively tracking the frequency characteristics of the partial response equalization to the frequency characteristics of the input signal, and the partial response equalization. A maximum likelihood decoding is performed on the input signal to output decoded data, and an adaptive Viterbi decoding process for adaptively tracking the identification point of the maximum likelihood decoding to the input signal characteristics is performed. In the adaptive equalization process, the value of the discrimination point adaptively controlled in the adaptive Viterbi decoding process is used as an equalization target for adaptive equalization, and one or both of the minimum level and the maximum level of the input signal are used. The equalization target for adaptive equalization is fixed or substantially fixed.

  That is, according to the present invention, the adaptive equalization circuit and the adaptive Viterbi decoding circuit are used in combination, and the adaptive equalization target value in the adaptive equalization circuit is determined as an identification point (Viterbi decoding amplitude reference) that is adaptively controlled by the adaptive Viterbi decoding circuit. Basically, the equalization error is calculated by replacing the level. In addition, an equalization target for adaptive equalization for at least one or both of the minimum level and the maximum level of the input signal is fixed or substantially fixed. Substantially fixed means that the degree of freedom of adaptive control is considerably limited and is in a state close to fixing.

  As one specific method, when each discrimination point in the adaptive Viterbi decoding circuit is used as an equalization target of the adaptive equalization circuit, one of the minimum level and the maximum level of the input signal on the adaptive Viterbi decoding circuit side or The adaptive control is stopped or substantially stopped at the discrimination points for both. As a result, for example, the discrimination point at the minimum level and the equalization target are both fixed or nearly fixed. That is, for example, the adaptive control of the minimum level discrimination point and the equalization target is stopped, or the control gain is significantly lowered to lower the adaptive control band, thereby reducing the degree of freedom of application control.

As another method, each discrimination point in the adaptive Viterbi decoding circuit is used as an equalization target of the adaptive equalization circuit. For the equalization target for one or both of the minimum level and the maximum level of the input signal, , Fixed without using the Viterbi decoding identification point. That is, in this case, as an equalization target for adaptive equalization, for example, only the minimum level equalization target does not reflect the discrimination point, and the initial value is used as it is.
As described above, in the adaptive equalization, by limiting the degree of freedom of the equalization target of the minimum level or the maximum level of the input signal, a situation in which the signal amplitude after the equalization changes with time is avoided.

  According to the present invention, the adaptive equalization circuit and the adaptive Viterbi decoding circuit are used in combination, and the adaptive equalization target value in the adaptive equalization circuit is set to the identification point (the amplitude of the Viterbi decoding amplitude that is adaptively controlled by the adaptive Viterbi decoding circuit). When the equalization error is calculated instead of the reference level, adverse effects due to interference between the adaptive control loops can be avoided. Therefore, frequency characteristics can be optimized with adaptive equalization, and equalization error correction and asymmetry correction can be performed with adaptive Viterbi decoding. Can be secured.

1 is a block diagram of a disk drive device according to an embodiment of the present invention. It is a block diagram of the decoding part of embodiment. It is a block diagram of the adaptive equalization circuit of an embodiment. It is a block diagram of the adaptive Viterbi decoder of an embodiment. It is explanatory drawing of the state transition in the case of PR (1, x, x, 1). It is a trellis diagram in the case of PR (1, x, x, 1). It is a wave form chart in the case of the 1st method of an embodiment. It is a wave form diagram in the case of the 2nd method of embodiment. It is a wave form diagram when an identification point and an equalization target are fixed. FIG. 6 is a waveform diagram when the equalization target is fixed. It is a wave form diagram at the time of performing adaptive control of an identification point and an equalization target.

Hereinafter, embodiments of the present invention will be described in the following order. In the embodiment, an example in which the decoding device of the present invention is mounted on a disk drive device for an optical disk will be described.
[1. PRML overview]
[2. Disk drive device]
[3. Configuration of decoding unit and adaptive control]

[1. PRML overview]

In the embodiment, the partial response characteristic is set to PR (1, x, x, 1) in the PRML (Partial-Response Maximum-Likelihood) system that performs recording / playback in the partial response system and performs maximum likelihood decoding such as Viterbi decoding. ) And a run length limited code such as an RLL (1, 7) code is used and the minimum run length is limited to 1 as an example.
It should be noted that x in PR (1, x, x, 1) is selected according to the optical characteristics such as “2” and “3”. Hereinafter, for example, the case of PR (1, 2, 2, 1) will be considered.

First, the PRML decoding method will be briefly described.
The PRML decoding method is a method for detecting a partial response sequence that minimizes the Euclidean distance of a reproduction signal, and is a technique that combines a process of partial response and a process of maximum likelihood detection.
The partial response sequence is obtained by performing weighted addition defined by the target response to the bit sequence. In the optical disk system, PR (1, 2, 2, 1) is often used, and this returns a value obtained by adding a weight of 1, 2, 2, 1 to the bit sequence as a partial response value.
The partial response is a process of returning an output longer than 1 bit with respect to a 1-bit input, and the reproduced signal is sequentially converted into 1, 2, 2, A process obtained as a signal obtained by multiplying by 1 is expressed as PR (1, 2, 2, 1).
In the maximum likelihood detection, a distance called Euclidean distance is defined between two signals, and the distance between an actual signal and an expected signal from an assumed bit sequence is examined. This is a method of detecting a bit sequence such that is closest. Here, the Euclidean distance is a distance defined as a distance obtained by adding the square of the amplitude difference between two signals at the same time over the entire time. Further, Viterbi detection, which will be described later, is used to search for a bit sequence that minimizes this distance.
In the partial response maximum likelihood detection combining these, the signal obtained from the bit information of the recording medium is adjusted by a filter called an equalizer so that it becomes a partial response process, and the resulting reproduced signal is assumed to be a bit sequence. The Euclidean distance with the partial response is checked, and a bit sequence having the closest distance is detected.

In order to search for a bit sequence in which the Euclidean distance is actually minimized, the above-described algorithm based on Viterbi detection is effective.
Viterbi detection uses a Viterbi detector consisting of a plurality of states configured in units of continuous bits of a predetermined length and branches represented by transitions between them, and all possible bit sequences are used. A desired bit sequence is efficiently detected from the inside.
In an actual circuit, for each state, a register that stores a partial response sequence and a Euclidean distance (path metric) of the signal up to that state called a path metric register, and a state called a path memory register. There are two registers for storing the bit sequence flow (path memory) up to the end, and for each branch, the partial response sequence at that bit called the branch metric unit and the Euclidean distance of the signal are calculated. Arithmetic units are provided.

FIG. 5 shows a state transition (state transition) in the case of PR (1, x, x, 1).
When the data bit string is bkε {0, 1}, the PR output dk of this system has a state transition as shown in FIG. 5, and dk is output when transitioning from each state to the next state.
In FIG. 5, ST000 to ST111 indicate respective states, and Cxxxx indicates an output. These outputs Cxxxx represent outputs obtained at the time of state transition.
For example, considering the state ST000, if the input bk = 0, the state ST000 is maintained and the output is C0000. If the input bk = 1 in the state ST000, the process proceeds to the state ST001. The output upon transition from state ST000 to state ST001 is C0001.
Considering from the state ST001, the input bk can only be bk = 1 from the run length limitation, and if the input bk = 1, the process proceeds to the state ST011. The output upon transition from state ST001 to state ST011 is C0011.
These state transitions and output values are as follows.
C1111: ST111 → ST111
C1110: ST111 → ST110, C0111: ST011 → ST111
C0110: ST011 → ST110
C1100: ST110 → ST100, C0011: ST001 → ST011
C1001: ST100 → ST001
C1000: ST100 → ST000, C0001: ST000 → ST001
C0000: ST000 → ST000

In Viterbi detection, various bit sequences can be associated in a one-to-one relationship by one of the paths that pass through the state. Further, the Euclidean distance between the partial response sequence passing through these paths and the actual signal is obtained by sequentially adding the above-described branch metrics in the branches, that is, the transitions between the states constituting the above paths. Can be obtained.
Further, in order to select a path that minimizes the above Euclidean distance, paths having smaller path metrics are sequentially selected while comparing the magnitudes of path metrics of two or less branches that are reached in each state. This can be achieved. By transferring this selection information to the path memory register, information representing the path reaching each state in a bit sequence is stored. The value of the path memory register is converged to a bit series that finally minimizes the Euclidean distance while being sequentially updated, and the result is output. In this way, it is possible to efficiently search for a bit sequence that generates a partial response sequence having the closest Euclidean distance to the reproduction signal.

FIG. 6 shows a trellis diagram in the case of PR (1, x, x, 1).
As shown in this trellis diagram, state transitions at each time point (k, k−1...) Are defined. That is, the bit at each time point can be determined by determining the most probable path.

[2. Disk drive device]

As a technique for recording / reproducing digital data, for example, there is a data recording technique using an optical disc as a recording medium, such as a CD (Compact Disc) and a DVD (Digital Versatile Disc).
As optical disks, known as CDs, CD-ROMs, DVD-ROMs, etc., read-only types in which information is recorded by embossed pits, CD-Rs, CD-RWs, DVD-Rs, DVDs, etc. There are types in which user data can be recorded as is known in RW, DVD + RW, DVD-RAM, and the like. In the recordable type, data can be recorded by using a magneto-optical recording method, a phase change recording method, a dye film change recording method, or the like. The dye film change recording method is also called a write-once recording method, and can be recorded only once and cannot be rewritten. On the other hand, the magneto-optical recording method and the phase change recording method can rewrite data and are used for various purposes such as recording of various content data such as music, video, games, application programs and the like.
In recent years, a high-density optical disk called a Blu-ray Disc (registered trademark) has been developed, and the capacity has been significantly increased.

It is assumed that the disk drive device according to the present embodiment can perform reproduction and recording corresponding to a reproduction-only disk or a recordable disk (a write-once disk or a rewritable disk) corresponding to a Blu-ray disk.
In the case of a recordable disc, recording / reproduction of a phase change mark (phase change mark) or a dye change mark is performed under a combination of a laser having a wavelength of 405 nm (so-called blue laser) and an objective lens having an NA of 0.85. Then, recording / reproduction is performed with a data block of 64 KB (kilobytes) as one recording / reproducing unit (RUB) at a track pitch of 0.32 μm and a linear density of 0.12 μm / bit.
For the ROM disk, reproduction-only data is recorded by embossed pits having a depth of about λ / 4. Similarly, the track pitch is 0.32 μm and the linear density is 0.12 μm / bit. A 64 KB data block is handled as one reproduction unit (RUB).

The RUB, which is a recording / playback unit, is a total of 498 frames generated by adding a link area of one frame before and after, for example, an ECC block (cluster) of 156 symbols × 496 frames.
In the case of a recordable disc, a groove (groove) is formed on the disc by meandering (wobbling), and this wobbling groove is used as a recording / reproducing track. Groove wobbling includes so-called ADIP (Address in Pregroove) data. In other words, the address on the disk can be obtained by detecting the wobbling information of the groove.

In the case of a recordable disc, a recording mark by a phase change mark is recorded on a track formed by a wobbling groove, and the phase change mark is an RLL (1, 7) PP modulation method (RLL; Run Length Limited, PP). : Parity preserve / Prohibit rmtr (repeated minimum transition runlength)), etc., with linear densities of 0.12 μm / bit and 0.08 μm / ch bit.
When the channel clock period is “T”, the mark length is 2T to 8T.
In the case of a read-only disc, no groove is formed, but similarly data modulated by the RLL (1, 7) PP modulation method is recorded as an embossed pit row.

A disk drive apparatus capable of recording / reproducing corresponding to such a disk is shown in FIG.
The disc 90 is, for example, the above-described Blu-ray disc type read-only disc or recordable disc.
When the disk 90 is loaded into the disk drive device, it is loaded on a turntable (not shown), and is rotationally driven by the spindle motor 2 at a constant linear velocity (CLV) during recording / reproducing operations.
During reproduction, information of marks (pits) recorded on tracks on the disk 90 is read by the optical pickup (optical head) 1.
When the disk 90 is a recordable disk, user data is recorded as a phase change mark or a dye change mark on a track on the disk 90 by the optical pickup 1 at the time of data recording.
On the disc 90, for example, physical information of the disc is recorded as reproduction-only management information by embossed pits or wobbling grooves. Reading of these information is also performed by the pickup 1. Further, the ADIP information embedded as wobbling of the groove track on the disk 90 is also read from the recordable disk 90 by the optical pickup 1.

In the pickup 1, a laser diode serving as a laser light source, a photodetector for detecting reflected light, an objective lens serving as an output end of the laser light, and a laser recording light are irradiated onto the disk recording surface via the objective lens. An optical system or the like for guiding the reflected light to the photodetector is formed. The laser diode outputs, for example, a so-called blue laser having a wavelength of 405 nm. The NA by the optical system is 0.85.
In the pickup 1, the objective lens is held so as to be movable in the tracking direction and the focus direction by a biaxial mechanism.
The entire pickup 1 can be moved in the disk radial direction by the thread mechanism 3.
The laser diode in the pickup 1 is driven to emit laser light by a drive signal (drive current) from the laser driver 13.

Reflected light information from the disk 90 is detected by a photo detector, converted into an electrical signal corresponding to the amount of received light, and supplied to the matrix circuit 4.
The matrix circuit 4 includes a current-voltage conversion circuit, a matrix calculation / amplification circuit, and the like corresponding to output currents from a plurality of light receiving elements as photodetectors, and generates necessary signals by matrix calculation processing.
For example, an RF signal (reproduction data signal) corresponding to reproduction data, a focus error signal for servo control, a tracking error signal, and the like are generated.
Further, a push-pull signal is generated as a signal related to groove wobbling, that is, a signal for detecting wobbling.
The reproduction data signal (RF signal) output from the matrix circuit 4 is supplied to the decoding unit 5, the focus error signal and tracking error signal are supplied to the optical block servo circuit 11, and the push-pull signal is supplied to the wobble signal processing circuit 15. .

The decoding unit 5 performs binarization processing of the reproduction data signal and supplies the obtained binary data string to the subsequent frame sync detection / synchronization protection circuit 6.
Therefore, the decoding unit 5 performs an A / D conversion process on the RF signal, a reproduction clock generation process using a PLL, a PR (Partial Response) equalization process, and a Viterbi decoding (maximum likelihood decoding) process. That is, a binary data string is obtained by a partial response maximum likelihood decoding process (PRML detection method: Partial Response Maximum Likelihood detection method). The decoded binary data string is supplied to the frame sync detection / synchronization protection circuit 6.

  For the binary data string output from the decoding unit 5, the frame sync detection / synchronization protection circuit 6 performs frame sync detection and synchronization protection processing for stable frame sync detection.

The encode / decode unit 7 performs demodulation of reproduction data during reproduction and modulation processing of recording data during recording. That is, data demodulation, deinterleaving, ECC decoding, address decoding, etc. are performed during reproduction, and ECC encoding, interleaving, data modulation, etc. are performed during recording.
At the time of reproduction, a binary data string decoded by the decoding unit 5 and a demodulation timing signal based on frame sync detection by the frame sync detection / synchronization protection circuit 6 are supplied to the encode / decode unit 7. The encode / decode unit 7 performs demodulation processing on the binary data string at the timing indicated by the demodulation timing signal based on frame sync detection, and obtains reproduction data from the disk 90. That is, the reproduction data from the disk 90 is obtained by performing demodulation processing on the data recorded on the disk 90 after RLL (1, 7) PP modulation and ECC decoding processing for error correction.
The data decoded to the reproduction data by the encoding / decoding unit 7 is transferred to the host interface 8 and transferred to the host device 100 based on an instruction from the system controller 10. The host device 100 is, for example, a computer device or an AV (Audio-Visual) system device.

If the disc 90 is a recordable disc, ADIP information processing is performed during recording / reproduction.
That is, the push-pull signal output from the matrix circuit 4 as a signal related to groove wobbling is converted into wobble data digitized by the wobble signal processing circuit 15. A clock synchronized with the push-pull signal is generated by the PLL process.
The wobble data is MSK demodulated and STW demodulated by the ADIP demodulating circuit 16, demodulated into a data stream constituting an ADIP address, and supplied to the address decoder 9.
The address decoder 9 decodes the supplied data, obtains an address value, and supplies it to the system controller 10.

At the time of recording, recording data is transferred from the host device 100, and the recording data is supplied to the encoding / decoding unit 7 via the host interface 8.
In this case, the encoding / decoding unit 7 performs error correction code addition (ECC encoding), interleaving, sub-code addition, and the like as recording data encoding processing. Further, RLL (1-7) PP modulation is performed on the data subjected to these processes.

The recording data processed by the encoding / decoding unit 7 is subjected to a recording compensation process in the write strategy unit 14 as a recording compensation process. Fine adjustment of the optimum recording power for the characteristics of the recording layer, the spot shape of the laser beam, the recording linear velocity, etc. The laser drive pulse is subjected to waveform adjustment and the like, and is supplied to the laser driver 13.
Then, the laser driver 13 gives the laser drive pulse subjected to the recording compensation process to the laser diode in the pickup 1 to execute the laser emission driving. As a result, a mark corresponding to the recording data is formed on the disk 90.
The laser driver 13 includes a so-called APC circuit (Auto Power Control), and the laser output is not dependent on temperature or the like while monitoring the laser output power by the output of the laser power monitoring detector provided in the pickup 1. Control to be constant. The target value of the laser output at the time of recording and reproduction is given from the system controller 10, and the laser output level is controlled to be the target value at the time of recording and reproduction.

The optical block servo circuit 11 generates various servo drive signals for focus, tracking, and thread from the focus error signal and tracking error signal from the matrix circuit 4 and executes the servo operation.
That is, a focus drive signal and a tracking drive signal are generated according to the focus error signal and tracking error signal, and the biaxial driver 18 drives the focus coil and tracking coil of the biaxial mechanism in the pickup 1. As a result, the pickup 1, the matrix circuit 4, the optical block servo circuit 11, the biaxial driver 18, the tracking servo loop and the focus servo loop by the biaxial mechanism are formed.
The optical block servo circuit 11 turns off the tracking servo loop in response to a track jump command from the system controller 10 and outputs a jump drive signal to execute a track jump operation.
The optical block servo circuit 11 generates a thread drive signal based on a thread error signal obtained as a low frequency component of the tracking error signal, access execution control from the system controller 10, and the like. To drive. Although not shown, the thread mechanism 3 includes a mechanism including a main shaft that holds the pickup 1, a thread motor, a transmission gear, and the like, and a required slide of the pickup 1 by driving the thread motor in accordance with a thread drive signal. Movement is performed.

The spindle servo circuit 12 performs control to rotate the spindle motor 2 at CLV.
The spindle servo circuit 12 obtains the clock generated by the PLL processing for the wobble signal as the current rotational speed information of the spindle motor 2, and compares it with predetermined CLV reference speed information to generate a spindle error signal. .
Further, at the time of data reproduction, the reproduction clock generated by the PLL in the decoding unit 5 becomes the current rotation speed information of the spindle motor 2, so that the spindle error signal is compared with the predetermined CLV reference speed information. Can also be generated.
The spindle servo circuit 12 outputs a spindle drive signal generated according to the spindle error signal, and causes the spindle driver 17 to execute CLV rotation of the spindle motor 2.
Further, the spindle servo circuit 12 generates a spindle drive signal in response to a spindle kick / brake control signal from the system controller 10, and also executes operations such as starting, stopping, acceleration, and deceleration of the spindle motor 2.

Various operations of the servo system and the recording / reproducing system as described above are controlled by a system controller 10 formed by a microcomputer.
The system controller 10 executes various processes in accordance with commands from the host device 100 given via the host interface 8.
For example, when a write command (write command) is issued from the host device 100, the system controller 10 first moves the pickup 1 to an address to be written. Then, the encoding / decoding unit 7 causes the encoding process to be performed on the data (for example, video data, audio data, etc.) transferred from the host device 100 as described above. Recording is executed by the laser driver 13 driving to emit laser light according to the data encoded as described above.

Further, for example, when a read command for requesting transfer of certain data recorded on the disk 90 is supplied from the host device 100, the system controller 10 first performs seek operation control for the instructed address. That is, a command is issued to the optical block servo circuit 11, and the access operation of the pickup 1 targeting the address specified by the seek command is executed.
Thereafter, operation control necessary for transferring the data in the designated data section to the host device 100 is performed. That is, the data is read from the disk 90, the reproduction processing in the decoding unit 5, the frame sync detection / synchronization protection circuit 6, and the encoding / decoding unit 7 is executed, and the requested data is transferred.

Although the example of FIG. 1 has been described as a disk drive device connected to the host device 100, the disk drive device may not be connected to other devices. In this case, an operation unit and a display unit are provided, and the configuration of the interface part for data input / output is different from that in FIG. That is, it is only necessary that recording and reproduction are performed in accordance with a user operation and a terminal unit for inputting / outputting various data is formed.
Of course, various other examples of the configuration of the disk drive device are conceivable. For example, an example of a read-only device can be considered.

[3. Configuration of decoding unit and adaptive control]

FIG. 2 shows a configuration example of the decoding unit 5. The decoding unit 5 includes an A / D converter 53, a PLL circuit 54, an adaptive equalization circuit 51, and an adaptive Viterbi decoder 52.
The A / D converter 53 converts the reproduction data signal supplied from the matrix circuit 4 into digital data.
The PLL circuit 54 generates a reproduction clock clk by PLL processing using, for example, the output of the A / D converter 53 and supplies it to each unit.
The reproduction data signal converted into digital data is subjected to PR equalization processing by the adaptive equalization circuit 51, further Viterbi-decoded by the adaptive Viterbi decoder 52, and output as a decoded binary data string.
In the case of this example, the adaptive equalization circuit 51 has a function of adaptively following the frequency characteristic of the partial response equalization to the frequency characteristic of the input reproduction data signal.
The adaptive Viterbi decoder 52 has a function of adaptively following the identification point of maximum likelihood decoding to the characteristics of the input signal, that is, the frequency characteristics and asymmetry of the signal equalized by the adaptive equalization circuit 51. .

A configuration example of the adaptive equalization circuit 51 is shown in FIG. In this example, the adaptive equalization circuit 51 has a configuration of an adaptive transversal filter (hereinafter, LMS-TVF) of the least square method (LMS).
The adaptive equalization circuit 51 includes delay units 61-1 to 61-n, multipliers 62-1 to 62-n, and an adder 63.
The reproduction signal (output of the A / D converter 53 in FIG. 2) input from the terminal 60 is branched into seven signals delayed by one channel clock by the delay units 61-1 to 61-n.
Next, the seven branched signals are amplified with different coefficients by the multipliers 62-1 to 62-n, respectively.
The signals amplified by the multipliers 62-1 to 62-n are added by the adder 63, and the output thereof is output as an equalized signal from the terminal 64 to the adaptive Viterbi decoder 52 in the subsequent stage.

Here, the coefficients of the multipliers 62-1 to 62-n are coefficients that minimize the equalization error with respect to the adaptive equalization target of the equalized signal. This coefficient is adaptively controlled by the LMS algorithm.
For adaptive control of the multiplication coefficient, delay units 65 and 66, a multiplier 68, a subtractor 69, and an LMS calculation unit 67 are provided as shown in the figure.

As the reference data for adaptive equalization, a binary data string as an output of the adaptive Viterbi decoder 52 at the subsequent stage is used.
In the multiplier 68, an impulse response according to PR (1, 2, 2, 1) is convoluted with the Viterbi decoder output.
The delay unit 65 delays the equalized output by the Viterbi decoder output and the convolution processing time and supplies the delayed output to the subtracter 69. The subtractor 69 obtains a difference between the delayed equalization output and the output of the multiplier 68. This is input to the LMS calculation unit 67 as an equalization error.
An input signal from the input terminal 60 is also input to the LMS calculation unit 67 after being given a delay corresponding to the processing time by the delay unit 66.
The LMS calculation unit 67 uses these input signals to set and control the coefficients of the multipliers 62-1 to 62-n that minimize the equalization error with respect to the adaptive equalization target.

Here, in this case, the identification point (Viterbi reference level) used in the subsequent adaptive Viterbi decoder 52 is used as the value as the adaptive equalization target. This Viterbi reference level itself is also adaptively controlled by the subsequent adaptive Viterbi decoder 52.
In a normal adaptive equalization circuit, the adaptive equalization target is a fixed value, but in this example, the equalization target changes with the reference level that is adaptively controlled by the adaptive Viterbi decoder 52.
Considering the combined use of the adaptive equalization circuit 51 and the adaptive Viterbi decoder 52 as in this example, the adaptive equalization target value in the adaptive equalization circuit 51 is set to the amplitude reference level (adaptive control controlled by the adaptive Viterbi decoder 52). It is most desirable to calculate the equalization error instead of the identification point. This is because the smaller the equalization error (the error between the equalization circuit output and the target value) is less affected by asymmetry and the like, and the convergence of adaptive equalization is stabilized.
On the other hand, it will be described with reference to FIG. 11 that the control loop in the adaptive equalization circuit 51 and the control loop in the adaptive Viterbi decoder 52 interfere with each other in this way, resulting in a problem of amplitude fluctuation. However, in this example, the problem is avoided by limiting a part of the adaptive control as described later.

Next, FIG. 4 shows the configuration of the adaptive Viterbi decoder 52.
The adaptive Viterbi decoder 52 includes a reference level holding unit 80, a reference level update unit 81, a branch metric calculator (BMC) 82, an add / compare / select (ACS) 83, a metric storage unit ( An MMU (Metric Memory Unit) and a path memory unit (PMU: Path Memory Unit) 85 are included.

The reference level holding unit 80 holds initial values of amplitude reference levels c0000 to c1111 that are identification points.
The reference level update unit 81 generates amplitude reference levels c′0000 to c′1111 that adaptively update the amplitude reference level serving as an identification point, and supplies the amplitude reference levels to the branch metric calculation unit 82.

The branch metric calculation unit 82 calculates a relative value of the Euclidean distance between the reproduction signal z [k + m] and the amplitude reference level c′0000 to c′1111 to obtain the branch metric bm. This may be calculated over m clocks. If the branch metrics of the 10-value 6-state Viterbi decoding are bm0000 to bm1111, the following results.
bm0000 _k = (Z _k −c′0000) ²
bm0001 _k = (Z _k −c′0001) ²
bm0011 _k = (Z _k −c′0011) ²
bm0110 _k = (Z _k −c′0110) ²
bm0111 _k = (Z _k −c′0111) ²
bm1000 _k = (Z _k −c′1000) ²
bm1001 _k = (Z _k −c′1001) ²
bm1100 _k = (Z _k −c′1100) ²
bm1110 _k = (Z _k −c′1110) ²
bm1111 _k = (Z _k −c′1111) ²

The addition / comparison / selection unit 83 generates path metrics m000 [k] to m111 [k] by adding the branch metrics along the path reaching the six states.
The path metrics m000 [k] to m111 [k] are transmitted to the metric storage unit 84.
The metric storage unit 84 is a circuit for processing so that the path metric does not overflow, and once latches the path metrics m000 [k] to m111 [k], and the latched path metrics m000 [k−1] to m111. [K−1] is transmitted to the addition / comparison / selection unit 83.

The addition / comparison / selection unit 83 generates path metrics m000 [k] to m111 [k] from the path metrics m000 [k−1] to m111 [k−1] and the branch metrics bm000 to bm111 as follows. Will do. Note that min {A, B} means that the smaller one of A and B is selected.
m000 [k] = min {m000 [k−1] + bm0000 _k , m100 [k−1] + bm1000 _k }
m001 [k] = min {m000 [k−1] + bm0001 _k , m100 [k−1] + bm1001 _k }
m011 [k] = m001 [k−1] + bm0011 _k
m100 [k] = m110 [k−1] + bm1100 _k
m110 [k] = min {m111 [k−1] + bm1110 _k , m011 [k−1] + bm0110 _k }
m111 [k] = min {m111 [k−1] + bm1111 _k , m011 [k−1] + bm0111 _k }

Then, the addition / comparison / selection unit 83 creates selection information s000, s001, s110, and s111 having values of “0” or “1” to select the smallest path metric, and stores it in the path memory unit 85. Output.
The path memory unit 85 receives the selection information s000, s001, s110, and s111, stores the identification result that becomes the history of the path metric for each of the six states, sequentially updates the identification result dec [k−n ] Is output.
That is, the maximum likelihood path among the paths as shown in the trellis diagram of FIG. 6 is determined from the selection information s000 to s111, and as a result, the decoded value “0” or “1” at the time point kn is output.
Further, the path memory unit 85 outputs the identification results pm000 [k] to pm000 [k−1] at each time point to the reference level update unit 81.

The reference level updating unit 81 adaptively updates the amplitude reference levels c0000 to c1111 by a combination of the amplitude reference levels c0000 to c1111 and the identification results pm000 [k] to pm000 [k−1]. ˜c′1111 is generated and given to the branch metric calculator 82.
For example, when pm000 [n] = 0, pm000 [n-1] = 0, pm0000 [n-2] = 0, and pm000 [n-3] = 1, c0001 is changed to c'0001 as follows. Update.
c′0001 = α · z [k−n + 2] + (1−α) · c0001
Α is a correction coefficient.

When generalized, the reference value cABCD (where A, B, C, and D are 0 or 1 respectively) is updated to the reference value c′ABCD as follows.
When uABCD is a logical expression of (pm000 [n] = A), (pm000 [n-1] = B), (pm0000 [n-2] = C), (pm000 [n-3] = D),
c′ABCD = α · (uABCD · z [k−n + 2] +! uABCD · cABCD) + (1−α) · cABCD

In other words, each reference value can be shown individually as follows.
c′0000 = α · (u0000 · z [k−n + 2] +! u0000 · c0000) + (1−α) · c0000
c′0001 = α · (u0001 · z [k−n + 2] +! u0001 · c0001) + (1−α) · c0001
c′0011 = α · (u0011 · z [k−n + 2] +! u0011 · c0011) + (1−α) · c0011
c′0110 = α · (u0110 · z [k−n + 2] +! u0110 · c0110) + (1−α) · c0110
c′0111 = α · (u0111 · z [k−n + 2] +! u0111 · c0111) + (1−α) · c0111
c′1000 = α · (u1000 · z [k−n + 2] +! u1000 · c1000) + (1−α) · c1000
c′1001 = α · (u1001 · z [k−n + 2] +! u1001 · c1001) + (1−α) · c1001
c′1100 = α · (u1100 · z [k−n + 2] +! u1100 · c1100) + (1−α) · c1100
c′1110 = α · (u1110 · z [k−n + 2] +! u1110 · c1110) + (1−α) · c1110
c′1111 = α · (u1111 · z [k−n + 2] +! u1111 · c1111) + (1−α) · c1111

The updated reference levels c′0000 to c′1111 are supplied to the branch metric calculation unit 82 as described above.
Further, in the case of this example, the updated reference levels c′0000 to c′1111 are supplied to the adaptive equalization circuit 51 as an adaptive equalization target.

Here, in the case of the present embodiment, the following technique (first technique) is adopted, and thereby adverse effects caused by interference between the adaptive control loop of the adaptive equalization circuit 51 and the adaptive control loop of the adaptive Viterbi decoder 52. To prevent.
That is, only for the reference level c′0000, the value of the coefficient α is remarkably reduced or α = 0.
For example, when α = 0, the above formula is
c'0000 = 1.c0000 = c0000
It becomes.
That is, for only the reference level c′0000, the adaptive update control is stopped, and the value of the reference level c0000 as the initial value is always used. In other words, only the reference level c′0000 is fixed.
FIG. 7 shows the equalized reproduction signal, reference level, and adaptive equalization target when α = 0. 7 and FIG. 8 to be described later, the horizontal axis is the time axis as in FIGS. 9 to 11 described above, the value of the equalized reproduction signal, the change in the reference level of the adaptive Viterbi decoder 52, and the adaptive equalization circuit. 51 shows a change in the target value.
As shown in the figure, the reference levels c′1111 to c0001 are updated according to time, but c′0000 is fixed.
Since the value of c′0000 to c′1111 is used as the adaptive equalization target in the adaptive equalization circuit 51, the level corresponding to c′1111 to c′0001 is also updated according to time. However, the equalization target (corresponding to a value of c′0000) for the minimum level of the input signal is fixed.

In this manner, by limiting the adaptive control so that the control as c′0000 is stopped and the reference level is fixed, the amplitude of the equalized reproduction signal is reduced as can be seen from FIG. It will be eliminated.
That is, in the present embodiment, the adaptive equalization circuit 51 and the adaptive Viterbi decoder 52 are used in combination, and the adaptive equalization target value in the adaptive equalization circuit 51 is adaptively controlled by an identification point (c ′ 0000-c′1111) to calculate the equalization error. At this time, the adaptive Viterbi decoder 52 equalizes the minimum level of the input signal in the adaptive equalization circuit 51 by stopping the adaptive control for the discrimination point (c0000) corresponding to the minimum level of the input signal as the discrimination point. The target is fixed. As a result, it is possible to avoid adverse effects due to interference between the adaptive control loops. Therefore, frequency characteristics can be optimized with adaptive equalization, and equalization error correction and asymmetry correction can be performed with adaptive Viterbi decoding. Can be secured.

For the reference level c′0000, in addition to setting the value of the coefficient α to 0, the value of the coefficient α may be significantly reduced. That is, the update control band of the reference level c′0000 is lowered, and the degree of change of the reference level c′0000 is remarkably suppressed. In other words, the adaptive control is substantially stopped for the reference level c′0000.
Even if it does in this way, the same effect can be acquired.

  In addition, whether the coefficient α is set to 0 or a remarkably small value, a configuration for storing the coefficient α for the reference level c′0000 is provided in the reference level update unit 81 as a configuration. That's fine. For this reason, there is an advantage that the present embodiment can be realized with a minimum circuit addition.

It is also conceivable to apply not the reference level c′0000 but the reference level c′1111 corresponding to the maximum level of the input signal.
For example, α = 0 for c′1111
c′1111 = 1 · c1111 = c1111
And
Alternatively, the value of α is significantly lowered for c′1111.
That is, only the reference level c′1111 is set to stop adaptive control, or the update control band is lowered, and the degree of change of the reference level c′1111 is remarkably suppressed to make the adaptive control substantially stop. As a result, the equalization target for the maximum level of the input signal in the adaptive equalization circuit 51 is fixed or substantially fixed.
Even in this case, it is possible to avoid an adverse effect (decrease in the equalized signal amplitude) due to mutual control loop interference, and the same effect as described above can be obtained.

Furthermore, it may be applied to both the reference levels c′0000 and c′1111.
That is, α = 0 for c′0000 and c′1111
c'0000 = 1.c0000 = c0000
c′1111 = 1 · c1111 = c1111
And
Alternatively, the value of α is significantly reduced for both c′0000 and c′1111.
That is, for both the reference levels c′0000 and c′1111, the adaptive control is stopped, or the update control band is lowered, and the degree of change of the reference levels c′0000 and c′1111 is remarkably suppressed and the adaptive control is omitted. Set to the stopped state. Thereby, the equalization target for the minimum level and the maximum level of the input signal in the adaptive equalization circuit 51 is fixed or substantially fixed.
Even in this case, it is possible to avoid an adverse effect (decrease in the equalized signal amplitude) due to mutual control loop interference, and the same effect as described above can be obtained.
However, limiting the adaptive control for both c′0000 and c′1111 in this way may cause the degree of inhibition of the degree of freedom of adaptive control to be too large, and it may be difficult to obtain the effect of adaptive control. It should be noted that.

Next, a second method as the present embodiment will be described.
In the first method described above, the updated reference levels c′0000 to c′1111 obtained by the reference level update unit 81 are supplied to the adaptive equalization circuit 51 as equalization targets.
On the other hand, as a second method, the reference level update unit 81 in the adaptive Viterbi decoder 52 normally performs adaptive control for the reference levels c′0000 to c′1111. However, only the reference level c′0000 is not supplied to the adaptive equalization circuit 51.
In the LMS calculation unit 67 of the adaptive equalization circuit 51, the reference levels c′0001 to c′1111 supplied from the adaptive Viterbi decoder 52 are used as equalization targets according to each level. For the equalization target of adaptive equalization with respect to the level, the value (c′0000) of the discrimination point in the adaptive Viterbi decoder 52 is not used. That is, the LMS calculation unit 67 of the adaptive equalization circuit 51 uses a fixed value only for the equalization target for adaptive equalization with respect to the minimum level of the input signal.

FIG. 8 shows the equalized reproduction signal, reference level, and adaptive equalization target in this case.
As shown in the figure, c′1111 to c0000 are updated according to time as reference levels.
As the adaptive equalization target in the adaptive equalization circuit 51, c′0001 to c′1111 are used as they are, but the equalization target for adaptive equalization with respect to the minimum level of the input signal is a fixed value.

In this way, by using a fixed value without using c′0000 in the adaptive equalization circuit 51, the amplitude of the equalized reproduction signal is reduced as can be seen from comparison with FIG. Is resolved.
In other words, the adaptive equalization circuit 51 and the adaptive Viterbi decoder 52 are used in combination, and the adaptive equalization target value in the adaptive equalization circuit 51 uses an identification point that is adaptively controlled by the adaptive Viterbi decoder 52. The equalization target for adaptive equalization for the minimum signal level is a fixed value. Thereby, it is possible to avoid an adverse effect due to interference of the adaptive control loops of each other. Therefore, frequency characteristics can be optimized with adaptive equalization, and equalization error correction and asymmetry correction can be performed with adaptive Viterbi decoding. Can be secured.
In particular, in this case, the adaptive Viterbi decoder 52 side performs normal adaptive control for all the discrimination points and the adaptive control is not limited, so that the effect of the adaptive control of the discrimination points can be maximized. In addition, since there is no structural change on the adaptive Viterbi decoder 52 side, the ease of implementation is high.

As a modification of the second method, the adaptive equalization circuit 51 may set only the equalization target for adaptive equalization with respect to the maximum level of the input signal to a fixed value.
Furthermore, the equalization target for adaptive equalization for both the minimum level and the maximum level of the input signal in the adaptive equalization circuit 51 may be a fixed value.

Although the embodiments have been described above, the present invention is not limited to the examples given in the embodiments. For example, various configurations of the adaptive equalization circuit 51 and the adaptive Viterbi decoder 52 are conceivable.
Further, although the example in which the target response is PR (1, 2, 2, 1) has been described, other cases such as PR (1, 3, 3, 1), PR (1, 2, 1), etc. Is applicable. That is, the same effect can be obtained in the case of PR (1, x, 1), PR (1, x, x, 1), PR (1, x, y, x, 1), and the like.

  1 Optical pickup, 4 Matrix circuit, 5 Decoding unit, 6 Frame sync detection / synchronization protection circuit, 7 Encoding / decoding unit, 10 System controller, 51 Adaptive equalization circuit, 52 Adaptive Viterbi decoder, 67 LMS operation unit, 80 Reference level Holding unit, 81 Reference level update unit, 82 Branch metric calculation unit, 83 Addition / comparison / selection unit, 84 Metric storage unit, 85 path memory unit

Claims (7)

A Viterbi decoding circuit that performs maximum likelihood decoding on an input signal and outputs decoded data, wherein an adaptive Viterbi decoding circuit that adaptively tracks an identification point of maximum likelihood decoding to an input signal characteristic;
An equalization circuit that performs partial response equalization on an input signal to the adaptive Viterbi decoding circuit, and performs adaptive equalization processing that adaptively follows the frequency characteristic of the partial response equalization to the frequency characteristic of the input signal, The identification point value adaptively controlled by the adaptive Viterbi decoding circuit is used as an equalization target for adaptive equalization, and the equalization target for adaptive equalization for one or both of the minimum level and the maximum level of the input signal is An adaptive equalization circuit that is fixed or substantially fixed;
A decoding device comprising: The adaptive Viterbi decoding circuit stops or substantially stops adaptive control for one or both of the identification points corresponding to the minimum level and the maximum level of the input signal as the identification point,
The decoding apparatus according to claim 1, wherein an equalization target for adaptive equalization for one or both of the minimum level and the maximum level of the input signal in the adaptive equalization circuit is fixed or substantially fixed. The adaptive Viterbi decoding circuit stops or substantially stops adaptive control only for the identification point corresponding to the minimum level of the input signal as the identification point,
The decoding apparatus according to claim 2, wherein the adaptive equalization circuit is configured such that only an equalization target for adaptive equalization with respect to a minimum level of an input signal is fixed or substantially fixed.   The adaptive equalization circuit does not use the value of the discrimination point in the adaptive Viterbi decoding circuit for the equalization target of adaptive equalization with respect to one or both of the minimum level and the maximum level of the input signal. The decoding apparatus according to claim 1, wherein an equalization target of adaptive equalization for one or both of the minimum level and the maximum level of the input signal in the equalization circuit is fixed.   The adaptive equalization circuit does not use the value of the discrimination point in the adaptive Viterbi decoding circuit for only the equalization target of adaptive equalization with respect to the minimum level of the input signal, thereby minimizing the input signal in the adaptive equalization circuit. 5. The decoding apparatus according to claim 4, wherein only an equalization target for adaptive equalization with respect to a level is fixed. An information reading unit for reading an information signal from the recording medium;
A decoding unit that performs a decoding process on the information signal read by the information reading unit;
With
The decoding unit
A Viterbi decoding circuit that performs maximum likelihood decoding on an input signal and outputs decoded data, wherein an adaptive Viterbi decoding circuit that adaptively tracks an identification point of maximum likelihood decoding to an input signal characteristic;
An equalization circuit that performs partial response equalization on an input signal to the adaptive Viterbi decoding circuit, and performs adaptive equalization processing that adaptively follows the frequency characteristic of the partial response equalization to the frequency characteristic of the input signal, The identification point value adaptively controlled by the adaptive Viterbi decoding circuit is used as an equalization target for adaptive equalization, and the equalization target for adaptive equalization for one or both of the minimum level and the maximum level of the input signal is A reproduction apparatus having an adaptive equalization circuit that is fixed or substantially fixed. An adaptive equalization process that performs partial response equalization on the input signal and adaptively follows the frequency characteristics of the partial response equalization to the frequency characteristics of the input signal;
Adaptive Viterbi decoding processing that performs maximum likelihood decoding on the partial response equalized input signal and outputs decoded data, and adaptively tracks the identification point of maximum likelihood decoding to the input signal characteristics;
Is performed,
In the adaptive equalization process, the value of the discrimination point adaptively controlled in the adaptive Viterbi decoding process is used as an equalization target for adaptive equalization, and adaptation to one or both of the minimum level and the maximum level of the input signal is performed. A decoding method in which the equalization target of equalization is fixed or substantially fixed.

Images