JP2006012363A - Strobe signal delay device and semiconductor device equipped with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate delay to a flip flop of a strobe signal corrected by a delay element and its variation in an interface part of a data reception device for use in a DLL. <P>SOLUTION: In a delay device, a delay element having a variable delay value and a delay control circuit for controlling delay of the delay element are provided, and an output of the delay element and an output of a minimum delay element which has a delay value being a minimum delay unit of the delay element are connected to a phase comparator, and the delay element and the minimum delay element have a common input, and the strobe signal or a reference clock is selected as the common input, and the delay control circuit can be controlled by a comparison result of the phase comparator, and the output of the delay element can be used as a clock of a plurality of data latches. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a strobe signal delay control device using a DLL (Delay Locked Loop).

  In the case of a high-speed data interface in a semiconductor device, in order to synchronize a clock or strobe signal with data, a mechanism for capturing data at a constant timing is required regardless of fluctuations in voltage or temperature. One means for realizing this is to use a DLL (Delay Locked Loop) circuit.

  The above DLL circuit will be further described. As a data interface method between devices, a method of transmitting and receiving data in synchronization with the clock using a single clock whose phase is controlled between devices, or a device that transmits data outputs a strobe signal and data to output the data. There is a method of taking in the strobe and data received by the receiving device. Examples of the latter include data interfaces such as ultra DMA, DDR (double data rate) -SDRAM, and DDRII-SDRAM in a hard disk. Among these, for Ultra DMA, for example, even in Ultra DMA 100, since the strobe signal has a maximum frequency of 50 MHz, there is no particular difficulty in designing an ASIC having a hard disk interface. However, in the case of DDR-SDRAM, data must be received in synchronization with a high-speed strobe signal such as 400 MHz or 266 MHz, and the timing specification of the strobe signal and data is strict. If not used, an appropriate data interface is difficult. Furthermore, in the case of a DDRII-SDRAM, since the data must be received at a period of 400 MHz or more, the above difficult point becomes more remarkable.

  As a known technique for solving the above problem, a technique using a DLL is known. FIG. 8 shows an example of part of the configuration of a device that receives data using this technique. FIG. 9 shows data input timings according to the configuration shown in FIG.

  In the DLL circuit 104, the delay control circuit 110 compares the set value of the delay element 106 in the DLL for one cycle of the input clock with the phase of the clock that has passed through the delay element 106. calculate. From the calculated delay setting value of the delay element 106 and the gear ratio setting value (given from the external 134), the delay setting value calculation circuit 112 calculates the delay setting value of the delay element 126 that delays the strobe signal. If the gear ratio set value is 45%, the strobe signal delay element 126 is set to a delay value of 45% of the clock period. Here, it is assumed that the delay element 106 and the strobe signal delay element 126 in the DLL 104 are delay elements having the same configuration. These delay elements 106 and 126 are provided with a delay value even if the delay setting is 0%. Therefore, the minimum delay element 118 has the same delay value as the delay values of the delay elements 106 and 126 when the delay setting is 0%. In FIG. 9, “td” is a delay value by the strobe delay element.

  FIG. 10A shows the ideal timing of the strobe delay in the device configuration shown in FIG. TDD indicates a delay from the input of a plurality of data signals to the flip-flop 120 via the minimum delay element 118. TD1 is a strobe delay value. Since the delay value of the delay element 126 is determined by selecting a small delay unit, jitter exists. J1 indicates the jitter.

In ASIC design, it is necessary that the TDD be constant among a plurality of data signals. Therefore, as shown in FIG. 8, the flip-flop 120 is arranged in the vicinity of the minimum delay element 118, and is designed so that there is no TDD difference between the data lines. On the other hand, the strobe signal corrected by the delay element 126 is designed so that the skew from the delay element 126 to each flip-flop 120 is reduced by using clock tree synthesis after output, but the problem here is that In other words, the distance from the delay element 126 to the flip-flop 120 is increased. Furthermore, the delay from the delay element 126 to the flip-flop 120 also has a problem that the fluctuation is large due to fluctuations in temperature and voltage. “TC” shown in FIG. 10B corresponds to a delay value from the delay element 126 to the flip-flop 120, and “J2” corresponds to a variation amount of the delay value. Therefore, the margin becomes “M1A” and “M1B” in the effective data window TDW at the ideal timing in FIG. 10A, whereas in the actual ASIC design, the margin is (see FIG. 10B). “M2A” and “M2B” are obtained, and the balance and margin for the data window are reduced as is apparent from the figure.
Micron Design Line “DDR SRAM Functionality and Controller Read Data Capture”.

  An object of the present invention is to eliminate TC and J2 in FIG. That is, an object of the present invention is to eliminate the delay value until the flip-prop of the strobe signal corrected by the delay element and its fluctuation amount in the interface portion of the data receiving device using the DLL.

The present invention has been made to achieve the above object. The delay device according to claim 1 according to the present invention includes:
A delay element having a variable delay value and a delay control circuit for controlling a delay of the delay element;
The output of the delay element and the output of the minimum delay element having the delay value of the minimum delay unit of the delay element are connected to the phase comparator,
The input of the delay element and the input of the minimum delay element are common, and either the strobe signal or the reference clock is selected as the common input,
The delay device can control the delay control circuit based on the comparison result of the phase comparator. In the delay device,
The output of the delay element can be used as a clock for a plurality of data latches.

The delay device according to claim 2 according to the present invention includes:
When the reference clock is selected as the input of the delay element and the input of the minimum delay element,
One input of the phase comparator is a signal that starts from a reference clock input and passes through a clock line for at least a plurality of data latches and a delay element whose delay value is variable,
Another input of the phase comparator is a signal passing through the minimum delay element having a delay value of at least the minimum delay unit of the delay element from the starting point,
The delay control circuit determines the delay value of the delay element using the comparison result of the phase comparator,
The strobe signal is connected to a clock of the data latch through the delay element and the clock line when a strobe signal is selected as an input of the delay element and an input of the minimum delay element. The delay device described.

The delay device according to claim 3 according to the present invention includes:
3. The delay device according to claim 1, wherein a plurality of signals passing through a delay element having at least the same delay value as the minimum delay element are respectively connected to inputs of a plurality of data latches. is there.

The delay device according to claim 4 according to the present invention includes:
4. The delay device according to claim 3, wherein a signal passing through a delay element having the same delay value as the minimum delay element is input to a plurality of data latches.

A semiconductor device according to claim 5 of the present invention is
A semiconductor device comprising the delay device according to claim 1 or 2.
From the delay element output to the clock inputs of the multiple data latches connected to the clock line, and to the input of the phase comparator connected to the clock line, a plurality of wiring delay skews are reduced. A semiconductor device having a structure in which a data latch and a phase comparator are arranged.

According to a sixth aspect of the present invention, there is provided a semiconductor device.
6. The semiconductor device according to claim 5, wherein clock tree synthesis is used in the clock line so that wiring delay skew is reduced.

The delay device according to claim 7 according to the present invention includes:
With a pulse generator,
3. The delay device according to claim 1, wherein a pulse signal indicating one cycle of the reference clock is input from the pulse generator instead of the reference clock.

A semiconductor device according to an eighth aspect of the present invention includes:
A pair of the delay devices according to claim 1 or 2 is provided, and a pair of the delay devices is input with a signal obtained by inverting the strobe signal instead of the strobe signal.

The semiconductor device according to claim 9 according to the present invention includes:
The data latch input connected to the clock line of one delay device of the two pairs of delay devices is connected to the common signal with the input of the data latch connected to the clock line of the other delay device. The semiconductor device according to claim 8.

According to a tenth aspect of the present invention, there is provided a semiconductor device.
The external clock synchronized with the period of two adjacent rising or falling signals of the strobe signal is input, and a clock obtained by multiplying the external clock is input as a reference clock. It is a semiconductor device.

According to the eleventh aspect of the present invention, there is provided a semiconductor device.
The strobe signal is connected to the strobe signal of the DDR-SDRAM, and the corresponding data bus of 4 or 8 DDR-SDRAMs is connected to the input of the data latch through a minimum delay element. 8. The semiconductor device according to 8.

The delay device according to claim 12 according to the present invention includes:
The reference clock is selected as an input when the correction mode signal is active, and the delay control circuit determines the delay value of the delay element according to the output of the phase comparator. It is a delay device.

According to a thirteenth aspect of the present invention, there is provided a semiconductor device.
12. The semiconductor device according to claim 11, wherein the correction mode signal of the delay device is activated in synchronization with a refresh cycle of the DDR-SDRAM.

  By using the present invention, it is possible to eliminate the delay value until the flip-prop of the strobe signal corrected by the delay element and its fluctuation amount in the interface portion of the data receiving device using the DLL.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.

<< First Embodiment >>
FIG. 1 is a schematic circuit diagram of an interface unit 2 of a data receiving device including a DLL according to a first preferred embodiment of the present invention. FIG. 2 shows a simple circuit example of the delay element 42 of FIG. In FIG. 2, one of the buffers 52 constitutes a minimum delay unit. Even if the minimum delay unit is selected by the selection circuit 50 (that is, even if the lowest signal of the selection circuit 50 in FIG. 2 is selected), a delay due to the selection circuit or the like is always added. It is desirable that the delay value at this time is equal to the delay value of the minimum delay element 40. When the minimum unit is selected as the delay element, the minimum delay element 40 has a large delay difference in the comparison result of the phase comparator 46 (even if the delay element 42 has the minimum unit delay, the minimum delay element 40 exceeds the desired value). This is a circuit for preventing a delay).

  In FIG. 3, when the input of the delay element 42 is a reference clock, the phase comparator input 1 indicates an input by a line passing through the minimum delay element 40, and “tD_min” in FIG. 3 indicates the delay value by the minimum delay element 40. Show. Further, the phase comparator input 2 indicates an input by a line passing through the delay element 42 and the clock line. Here, in the initial state of the phase comparator input 2, the delay setting of the delay element 42 is set to the minimum or close to the minimum. The timing at that time is shown in the phase comparator input 2 (a) of FIG. When the initial setting of the delay value of the delay element 42 is minimum (that is, when the delay value of the minimum delay element 40 is set), the delay of the clock line is added to the timing difference from the phase comparator input 1. Arises from being done. The delay control circuit 44 controls to increase the delay unit of the delay element 42 with respect to the initial state. Then, the phase comparator input changes from “phase comparator input 2 (b)” to “phase comparator input 2 (c)”.

  The delay control circuit 44 controls to reduce the delay value when it becomes later than the edge of the phase comparator input 1 as in the timing of the phase comparator input 2 (c) shown in FIG. Thereafter, the delay control circuit 44 controls the increase / decrease of the delay value of the delay element 42 so that the edges of the two inputs (phase comparator input 1 and phase comparator input 2) are approximated. At this time, tD_lock in FIG. 3 indicates a delay time passing through the delay element and the clock line in FIG. 1 and coincides with one cycle of the reference clock. If the delay from the delay element output of FIG. 1 to the phase comparator input and the input of each flip-flop is equal, the delay element input to the clock input of the flip-flop (20a, 20b) is equal to the period of the reference clock. Will be controlled as such.

  The delay value of the delay element 42 is controlled by selecting the reference clock by the multiplex 38 when the correction mode signal of FIG. When the correction mode signal is inactive, the strobe signal is selected, and the strobe signal reaches the clock of the flip-flop (20a, 20b) after a delay time of one cycle of the reference clock.

  As shown in FIG. 4, when there is valid data in the middle of each strobe edge, if the strobe signal is synchronized with the bus clock and the reference clock corresponds to the quadruple clock in FIG. , 20b) is input with a signal delayed by 90 degrees of the strobe. At this time, it is possible to capture data at an intermediate point in the effective range of data.

  The minimum delay elements (18a, 18b) added before the flip-flops (20a, 20b) of the data delay device (21a, 21b) of FIG. 1 add tD_min of FIG. 4 as a data delay, and strobe of tcyc It complements that delay is added appropriately. In the data delay device (21a, 21b) of FIG. 1, the output of the minimum delay element (18a, 18b) is connected to one flip-flop (20a, 20b), but as shown in FIG. (20-1, 20-2, 20-3, 20-4) may be connected. When a plurality of flip-flops are connected, the subsequent circuit (in the case of FIG. 5, a circuit that captures data of D0OUT0 to D0OUT3) can easily capture data.

<< Second Embodiment >>
FIG. 6 is a schematic circuit diagram of the interface unit 2 of the data receiving device including the DLL according to the second preferred embodiment of the present invention. The strobe delay device 36 does not input a reference clock, but gives a pulse corresponding to the reference clock period by the pulse generator 49 of FIG. May be.

<< Third Embodiment >>
FIG. 7 is a schematic circuit diagram of the interface unit 2 of the data receiving device including the DLL according to the third preferred embodiment of the present invention. The strobe signal 22 input to the semiconductor device is input to the strobe delay device 36 via an IO buffer or other buffer. There are cases where the quality (delay, slope of the signal) differs between the rise and fall of the strobe signal. By using the strobe signals corrected through different delay devices for the data latched at the rising edge of the strobe and the data latched at the falling edge, it is possible to prevent the delay value from being different depending on the edge.

1 is a schematic circuit diagram of an interface unit of a data receiving device including a DLL according to a preferred first embodiment of the present invention. 2 is a simple circuit example of the delay element in FIG. 1. It is an example of a reference clock and a phase comparator input. It is an example of a reference clock, a bus clock, data, a strobe, and a corrected strobe. It is an example of a circuit connected to a plurality of flip-flops. It is a schematic circuit diagram of the interface part of the data receiving device provided with DLL which is suitable 2nd Embodiment based on this invention. It is a schematic circuit diagram of the interface part of the data reception device provided with DLL which is suitable 3rd Embodiment based on this invention. It is a part of example of a structure of the data receiving device using DLL which is a well-known technique. 9 is an example of data input timing according to the device configuration shown in FIG. 8. FIG. 8 shows an ideal timing example (a) of the strobe delay in the device configuration shown in FIG.

Explanation of symbols

18, 18a, 18b ... minimum delay elements 21, 21a, 21b ... data delay devices, 36 ... strobe delay devices, 38 ... multiplexes, 40 ... minimum delay devices, 42. Delay element, 46... Phase comparator.

Claims (13)

A delay element having a variable delay value and a delay control circuit for controlling a delay of the delay element;
The output of the delay element and the output of the minimum delay element having the delay value of the minimum delay unit of the delay element are connected to the phase comparator,
The input of the delay element and the input of the minimum delay element are common, and either the strobe signal or the reference clock is selected as the common input,
In the delay device capable of controlling the delay control circuit according to the comparison result of the phase comparator,
A delay device characterized in that the output of the delay element can be used as a clock for a plurality of data latches. When the reference clock is selected as the input of the delay element and the input of the minimum delay element,
One input of the phase comparator is a signal that starts from a reference clock input and passes through a clock line for at least a plurality of data latches and a delay element whose delay value is variable,
Another input of the phase comparator is a signal passing through the minimum delay element having a delay value of at least the minimum delay unit of the delay element from the starting point,
The delay control circuit determines the delay value of the delay element using the comparison result of the phase comparator,
The strobe signal is connected to a clock of the data latch through the delay element and the clock line when a strobe signal is selected as an input of the delay element and an input of the minimum delay element. The delay device described.   3. The delay device according to claim 1, wherein a plurality of signals passing through a delay element having at least the same delay value as the minimum delay element are respectively connected to inputs of a plurality of data latches.   4. The delay device according to claim 3, wherein a signal passing through a delay element having the same delay value as the minimum delay element is input to a plurality of data latches. In a semiconductor device provided with the delay device according to claim 1 or 2,
From the delay element output to the clock inputs of the multiple data latches connected to the clock line, and to the input of the phase comparator connected to the clock line, a plurality of wiring delay skews are reduced. A semiconductor device having a structure in which a data latch and a phase comparator are arranged.   6. The semiconductor device according to claim 5, wherein clock tree synthesis is used in the clock line and the wiring delay skew is reduced. With a pulse generator,
3. The delay device according to claim 1, wherein a pulse signal indicating one cycle of the reference clock is input from the pulse generator instead of the reference clock.   3. A semiconductor device comprising two pairs of the delay devices according to claim 1 or 2, wherein a signal obtained by inverting the strobe signal is input to a pair of the delay devices instead of the strobe signal.   The data latch input connected to the clock line of one delay device of the two pairs of delay devices is connected to the common signal with the input of the data latch connected to the clock line of the other delay device. The semiconductor device according to claim 8.   9. The external clock synchronized with the period of two adjacent rising or falling signals of the strobe signal is input, and a clock obtained by multiplying the external clock is input as a reference clock. Semiconductor device.   The strobe signal is connected to the strobe signal of the DDR-SDRAM, and the corresponding data bus of 4 or 8 DDR-SDRAMs is connected to the input of the data latch via a minimum delay element. 8. The semiconductor device according to 8.   The reference clock is selected as an input when the correction mode signal is active, and the delay control circuit determines the delay value of the delay element according to the output of the phase comparator. Delay device. 12. The semiconductor device according to claim 11, wherein the correction mode signal of the delay device is activated in synchronization with a refresh cycle of the DDR-SDRAM.

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