KR20140083367A - Delay lock loop and latency control circuit including the same - Google Patents

Delay lock loop and latency control circuit including the same Download PDF

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KR20140083367A
KR20140083367A KR1020120153040A KR20120153040A KR20140083367A KR 20140083367 A KR20140083367 A KR 20140083367A KR 1020120153040 A KR1020120153040 A KR 1020120153040A KR 20120153040 A KR20120153040 A KR 20120153040A KR 20140083367 A KR20140083367 A KR 20140083367A
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South Korea
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delay
value
clock
signal
comparison
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KR1020120153040A
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Korean (ko)
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정진일
서영석
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에스케이하이닉스 주식회사
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Publication of KR20140083367A publication Critical patent/KR20140083367A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects

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Abstract

The present invention provides a delay locked loop for preventing an overlock and a latency adjustment error caused by an overlock, the delay locked loop comprising: a delay unit for delaying a reference clock to generate an output clock; A replica delay unit for delaying the output clock by a modeled delay value to generate a feedback clock; A phase comparator for comparing the phase of the feedback clock with the comparison clock; Wherein the phase comparator adjusts the delay value of the delay unit in response to a comparison result of the phase comparator, and when the delay value of the delay unit does not reach the minimum value, transfers the reference clock to the comparison clock, And transmitting a frequency-divided clock obtained by dividing the frequency of the reference clock by N, to the comparison clock.

Description

TECHNICAL FIELD [0001] The present invention relates to a delay locked loop (hereinafter referred to as " delay locked loop "

The present invention relates to a delay locked loop and latency control circuit for preventing errors due to overlock and overlock.

Circuit elements such as a DDR SDRAM (Double Data Rate Synchronous DRAM) perform various signals and data transmission in synchronization with a clock used in an external system. At this time, the internal clock used in the circuit element is synchronized with the external clock at the time of inputting, but is not synchronized with the external clock when it is output to the outside of the device while passing through various components in the element. Therefore, in order to transmit signals and data stably, the internal clock and the external clock must be accurately synchronized in the external system by compensating the internal clock for the time that the data is held on the bus in the circuit element. A delayed locked loop is used to perform this role.

A brief description of how the delay locked loop adjusts the phase of the internal clock is as follows. The delay locked loop generates an internal clock by delaying the external clock through the variable delay unit. Also, the internal clock is delayed by the replica delay unit modeling the delay value of the path through the signal in the circuit to generate the feedback clock. Finally, the delay value of the variable delay unit is adjusted until the phase of the feedback clock becomes equal to the phase of the external clock. When the phase of the feedback clock is equal to the phase of the external clock, the delay value of the variable delay unit is maintained (delay locked state). Then, when the phase of the feedback clock is different from that of the external clock due to a change in the power supply voltage, . In the delay locked state, the phase of the variable delay part is different from the external clock by N (natural number) * tCK (1 clock cycle) - tREP (replica delay delay value) have.

1 is a diagram for explaining a problem that may occur in a delay locked loop due to a drop in power supply voltage. 'RCK' is a reference clock (RCK), which is a clock signal input to the delay locked loop, and 'FCK' is a feedback clock (FCK), which is a clock signal output from the replica delay unit. The delay locked loop adjusts the delay value of the variable delay unit (not shown in FIG. 1) of the delay locked loop to synchronize the reference clock (RCK) and the feedback clock (FCK).

First, a method of controlling the delay value of the variable delay unit by sensing the phase of the reference clock signal RCK and the feedback clock signal FCK will be described. The delay locked loop samples the logical value of the reference clock (RCK) at the rising edge of the feedback clock (FCK). When the logic value of the reference clock signal RCK is 'high' at the rising edge of the feedback clock FCK, it is determined that the phase of the reference clock signal RCK precedes the feedback clock signal FCK, thereby reducing the delay value of the variable delay unit. When the logic value of the reference clock signal RCK is 'low' at the rising edge of the feedback clock FCK, it is determined that the phase of the reference clock signal RCK is lower than the feedback clock signal FCK and the delay value of the variable delay unit is increased .

The first waveform diagram 110 shows the waveforms of the reference clock RCK and the feedback clock FCK before the delay value of the variable delay unit reaches the minimum value. When the power supply voltage falls and the phase of the feedback clock FCK is delayed, the delay locked loop senses this and decreases the delay value of the variable delay unit 111.

The second waveform diagram 120 shows the waveforms of the reference clock RCK and the feedback clock FCK after the delay value of the variable delay unit reaches the minimum value. When the power supply voltage continues to fall in the first waveform diagram 110, the delay value of the variable delay unit continues to decrease. When the power supply voltage continuously reaches the minimum value of the delay value of the variable delay unit, the delay value does not decrease any more, and the reference clock RCK and the feedback clock FCK) is distorted (121).

The third waveform diagram 130 shows the waveforms of the reference clock signal RCK and the feedback clock signal FCK when an overlock phenomenon occurs. When the power supply voltage further decreases in the second waveform diagram 120, the phases of the reference clock RCK and the feedback clock FCK are further distorted. When the phase of the feedback clock FCK is continuously delayed and the phase of the rising edge R of the feedback clock FCK becomes lower than the phase of the falling edge F of the reference clock RCK, the delay locked loop outputs the feedback clock FCK Is higher than the reference clock signal RCK and increases the delay value of the variable delay unit and is delayed fixed again when the phases of the reference clock signal RCK and the feedback clock signal FCK become equal to each other.

The phase of the feedback clock FCK in the delay locked state of the first waveform diagram 110 and the phase of the feedback clock FCK of the third waveform diagram 130 are the same, The phase of the feedback clock FCK is one clock later than the phase of the feedback clock FCK of the first waveform diagram 110. [ As described above, the delay locked state in which the phase of the feedback clock FCK is delayed by one clock phase relative to the phase in which the phase of the feedback clock FCK is originally delay locked is referred to as an overlock state, and there is a problem in adjusting the latency due to overlock.

On the other hand, although the semiconductor device operates independently, it usually operates by exchanging data (signals) with surrounding semiconductor devices. In order for two or more semiconductor devices to exchange signals and operate with each other, when one semiconductor device requests an operation to another semiconductor device, the requested semiconductor device requires a certain waiting time to perform an operation corresponding to the request, Latency is called latency.

For example, if a memory controller issues a read command to memory, the memory delivers the stored data to the memory controller. However, it is impossible to transfer data to the memory controller as soon as the memory receives the read command. This is because it takes time to prepare and call the data stored in the memory internally. Therefore, when the latency is set, the memory transfers data to the memory controller after a predetermined latency from the point of time when the read command is applied from the memory controller.

The memory includes a latency adjusting circuit for delaying the data by a predetermined delay value in order to output the called data in response to the read command at a time point when the latency has elapsed from the application time of the read command. The latency control circuit not only delays the data exactly as latency but also delays the data taking into account the delay value that occurs as the data travels through the memory path. For example, if the latency has a value of A and the delay value of the internal path of the memory has a value of B, the latency adjusting circuit delays the data by A-B. For reference, the delay value occurring when the data passes through the path in the memory includes the delay value of the variable delay portion of the delay locked loop.

Based on the above, the problems that may occur when controlling latency will be described.

Let X be the latency value, and Y be the delay value experienced by the data in the memory during normal delay and fixation. In this case, the delay value experienced by the data in the memory in the overlock state is (Y + 1) * tCK. tCK represents the time corresponding to one clock cycle. The delay value of the latency control circuit is determined in a general delay locked state. At this time, the delay value of the latency control circuit becomes XY, and the data is output after the latency has passed after the read command is applied. However, if an overlock occurs due to a drop in the power supply voltage, the delay value of the latency control circuit is still XY, but the delay value experienced by the data in the memory is (Y + 1) * tCK due to overlock, (X + 1) * tCK. That is, if an overlock occurs in the delay locked loop, the output timing of the data becomes incorrect.

The present invention provides a delay locked loop in which an overlock is prevented by preventing a delay value of a variable delay unit from increasing when a delay value of a variable delay unit of a delay locked loop reaches a minimum value.

The present invention also provides a latency control circuit that prevents latency errors caused by overlock by preventing overlock of the delay locked loop.

A delay locked loop according to the present invention includes: a delay unit for delaying a reference clock to generate an output clock; A replica delay unit for delaying the output clock by a modeled delay value to generate a feedback clock; A phase comparator for comparing the phase of the feedback clock with the comparison clock; Wherein the phase comparator adjusts the delay value of the delay unit in response to a comparison result of the phase comparator, and when the delay value of the delay unit does not reach the minimum value, transfers the reference clock to the comparison clock, And transmitting a frequency-divided clock obtained by dividing the frequency of the reference clock by N, to the comparison clock.

According to another aspect of the present invention, there is provided a delay locked loop including: a delay unit delaying a reference clock to generate an output clock; A replica delay unit for delaying the output clock by a modeled delay value to generate a feedback clock; A phase comparator for comparing the phase of the reference clock with the phase of the feedback clock; And a controller for adjusting a delay value of the delay unit in response to a comparison result of the phase comparator and maintaining the delay value of the delay unit after the delay value of the delay unit reaches a minimum value.

Also, the latency control circuit according to the present invention generates an output clock by delaying a reference clock with a delay value adjusted in response to a comparison result of a phase of a comparison clock and a feedback clock. When the delay value does not reach a minimum value, A delay locked loop for delivering a divided clock obtained by dividing the frequency of the reference clock by N when the clock reaches the comparison clock and the delay value reaches the minimum value, to the comparison clock; A path information generator for generating path information corresponding to a delay value of a path through which the input signal passes through the integrated circuit, the delay value of the path including a delay value equal to the delay value of the delay locked loop; And a delay unit for delaying the input signal using the latency value of the input signal and the path information.

Further, the latency adjusting circuit according to the present invention includes: a delay locked loop for delaying a reference clock to generate an output clock, wherein the delay locked loop maintains a delay value of the delay unit at a minimum value; A path information generator for generating path information corresponding to a delay value of a path through which the input signal passes through the integrated circuit, the delay value of the path including a delay value equal to the delay value of the delay locked loop; And a delay unit for delaying the input signal using the latency value of the input signal and the path information.

The present invention prevents the delay value of the variable delay unit from increasing when the delay value of the variable delay unit of the delay locked loop reaches the minimum value, thereby preventing overlock.

The technique also avoids over-locking of the delay locked loop, thereby preventing the latency adjusting circuit from delaying the signal to a false delay value.

1 is a diagram for explaining a problem that may occur in a delay locked loop due to a drop in power supply voltage,
2 is a configuration diagram of a delay locked loop according to an embodiment of the present invention;
3 is a configuration diagram of the divided clock generation unit 241 and the control signal generation unit 243 according to the present invention,
4 is a configuration diagram of a delay locked loop according to another embodiment of the present invention;
FIG. 5 illustrates a latency control circuit 520 and its periphery according to an embodiment of the present invention.
FIG. 6 is a diagram of an embodiment of the path information generation unit 522 of FIG. 5; FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

2 is a configuration diagram of a delay locked loop according to an embodiment of the present invention.

2, the delay locked loop includes a delay unit 210 for delaying a reference clock signal RCK to generate an output clock signal OCK, a delay unit 210 for delaying the output clock signal OCK by a delayed model value, A phase comparator 230 for comparing phases of the comparison clock CCK with the feedback clock FCK and a phase comparator 230. The phase comparator 230 compares the phase of the feedback clock FCK with the phase of the feedback clock FCK, The reference clock RCK is transferred to the comparison clock CCK when the delay value of the delay unit 210 does not reach the minimum value and the delay value of the delay unit 210 is shifted to the minimum value And a control unit 240 for transmitting the divided clock DCK divided by N times the frequency of the reference clock RCK to the comparison clock CCK.

The operation of the delay locked loop will be described with reference to FIG.

The delay unit 210 delays the reference clock signal RCK to generate an output clock signal OCK. The delay value of the delay unit 110 is adjusted by the control unit 240. The delay unit 210 includes a plurality of delay units (not shown in FIG. 2). The delay unit 210 delays the reference clock signal RCK by using activated delay units of the plurality of delay units, . The number of delay units activated among the plurality of delay units is controlled by the control unit 240. The delay unit 210 activates the minimum signal MIN when the delay value of the delay unit 210 reaches the minimum value.

The replica delay unit 220 generates the feedback clock FCK by delaying the output clock OCK. The replica delay unit 220 outputs a delay value modeled by delay elements modeled in the integrated circuit until the clock signal input to the integrated circuit is transferred to the reference clock RCK input to the delay locked loop, Has a delay value equal to the sum of the delay values output from the delay locked loop and modeled by the delay elements passing through the integrated circuit.

The phase comparator 230 compares the phases of the comparison clock CCK and the feedback clock FCK to generate a comparison signal COMP corresponding to the phase comparison result. The phase comparator 230 generates the comparison signal COMP having the first value (high) when the phase of the comparison clock CCK is ahead of the phase of the feedback clock FCK. And conversely generates the comparison signal COMP having the second value (low) when the phase of the comparison clock CCK is lower than the phase of the feedback clock FCK. Here, a method of comparing the phases is to sample the logical value of the comparison clock CCK at the rising edge of the feedback clock FCK, and when the logical value of the comparison clock CCK is at the high level at the rising edge of the feedback clock FCK, The phase of the comparison clock CCK is higher than the feedback clock FCK and the phase of the comparison clock CCK is lower than the feedback clock CCK when the logic value of the comparison clock CCK is low at the rising edge of the feedback clock FCK. Clock (FCK).

The control unit 240 adjusts the delay value of the delay unit 210 according to the comparison result of the phase comparator 230 and selects the reference clock RCK when the delay value of the delay unit 240 does not reach the minimum value And transmits the divided clock DCK to the comparison clock CCK when the delay value of the delay unit 240 reaches the minimum value and selects the divided clock DCK by dividing the frequency of the reference clock RCK by N do. The control unit 240 deactivates the divided clock DCK when the delay value of the delay unit 210 does not reach the minimum value and outputs the divided clock DCK when the delay value of the delay unit 210 reaches the minimum value Activate. When the delay value of the delay unit 210 does not reach the minimum value, the divided clock DCK is not used, so that the divided clock DCK is inactivated to reduce the consumed power. Note that the frequency of the frequency dividing clock DCK is 1 / N of the frequency of the reference clock RCK and the frequency of the frequency dividing clock DCK is N times the frequency of the reference clock RCK.

In more detail, the control unit 240 generates the control signal CONT in response to the minimum signal MIN and the comparison signal COMP. The control unit 240 generates the control signal CONT having the same logical value as the comparison signal COMP when the minimum signal MIN is inactivated. The control unit 240 determines that the rising edge of the understanding feedback clock FCK is lower than the comparison clock CCK by a change in the delay value of the delay unit 210 from the time when the minimum signal MIN is activated when the minimum signal MIN is activated, (High) until reaching the next edge (rising edge or falling edge) of the control signal CONT. When the minimum signal MIN is activated, the divided clock DCK is transferred to the comparison clock CCK, so that the high or low interval of the comparison clock CCK is increased N times as compared with the case where the minimum signal MIN is inactivated. Accordingly, the interval in which the control signal CONT has the first value can be increased as the frequency division ratio is increased. For reference, the delay unit 210 decreases the delay value in response to the control signal CONT having the first value, and increases the delay value in response to the control signal CONT having the second value.

The control unit 240 selects one of the divided clock generating unit 241, reference clock RCK and divided clock DCK for dividing the reference clock signal RCK by N to generate the divided clock signal DCK And a control signal generator 243 for generating a control signal CONT in response to the minimum signal MIN and the comparison signal COMP.

The dividing clock generating unit 241 divides the reference clock signal RCK by N to generate a divided clock signal DCK and deactivates the dividing clock signal DCK when the minimum signal MIN is inactive. Activates the dividing clock (DCK) when enabled. The configuration and operation of the divided clock generation section 241 will be described later in the description of FIG.

The clock selection unit 242 selects the reference clock signal RCK when the minimum signal MIN is inactive and transmits the reference clock signal RCK to the comparison clock signal CCK. When the minimum signal MIN is activated, the clock selection unit 242 selects the divided clock signal DCK To the comparison clock (CCK). Therefore, when the minimum signal MIN is inactivated, the comparison signal COMP corresponds to a result of comparing the phases of the reference clock signal RCK and the feedback clock signal FCK. When the minimum signal MIN is activated, Corresponds to a result obtained by comparing the phases of the divided clock DCK and the feedback clock FCK.

The control signal generator 243 generates a control signal CONT having the same value as the comparison signal COMP when the minimum signal MIN is inactivated and outputs the control signal CONT to the delay unit 210 when the minimum signal MIN is activated. The control signal CONT having the first value is generated until the rising edge of the feedback clock FCK reaches the next edge of the comparison clock CCK. The configuration and operation of the control signal generator 243 will be described later in the description of FIG.

Hereinafter, with reference to the above description, it is assumed that (1) the delay value of the delay unit 210 does not reach the minimum value, and (2) the case where the delay value of the delay unit 210 reaches the minimum value, The operation will be described.

(1) When the delay value of the delay unit 210 does not reach the minimum value

The controller 240 transmits the reference clock signal RCK to the comparison clock signal CCK in response to the inactivated minimum signal MIN. The control unit 240 generates the control signal CONT having the first value (high) when the phase of the comparison clock CCK is ahead of the phase of the feedback clock FCK in response to the comparison signal COMP, The delay value of the delay unit 210 decreases in response to the signal CONT. Conversely, when the phase of the comparison clock CCK is lower than the phase of the feedback clock FCK, the control unit 240 generates the control signal CONT having the second value (low), and in response to the control signal CONT, The delay value of the delay unit 210 increases.

(2) When the delay value of the delay unit 210 reaches the minimum value

When the power supply voltage continues to fall, the phase of the feedback clock FCK is delayed, and the delay value of the delay unit 210 of the delay locked loop continues to decrease to reach the minimum value. The control unit 240 activates the dividing clock DCK and transfers the dividing clock DCK to the comparison clock CCK. The control unit 240 generates the control signal CONT having the first value (high) regardless of the logic value of the comparison signal COMP. The logic value of the control signal CONT is maintained until the rising edge of the feedback clock FCK passes the rising edge or the falling edge of the comparison clock CCK due to the change of the power supply voltage from the time when the minimum signal MIN is activated, And is maintained at the first value. The delay value of the delay unit 210 must be decreased in response to the control signal CONT having the first value but is kept at the minimum value without decreasing since it has already reached the minimum value.

In the case of the conventional delay locked loop, when the supply voltage continues to decrease after the delay value of the delay unit reaches the minimum value and the rising edge of the feedback clock FCK passes the rising edge of the reference clock RCK, And an overlock occurs. At this time, the margin at which no overlock occurs is 1/2 * tRCK (tRCK: one cycle of the reference clock (RCK)). That is, if the phase of the feedback clock FCK is delayed by 1/2 * tRCK after the delay value of the delay unit reaches the minimum value, unconditional overlock occurs. However, in the case of the delay locked loop according to the present invention, since the comparison clock CCK is transmitted with the dividing clock DCK, the high or low interval of the comparison clock CCK is set to be higher than the high or low interval of the reference clock RCK It is long. Therefore, the margin at which no overlock occurs is 1/2 * N * tRCK, i.e. N times the conventional delay locked loop.

The delay locked loop according to the present invention is configured such that the logic value of the control signal CONT is maintained at a first value that decreases the delay value of the delay unit 210 when the delay value of the delay unit 210 reaches the minimum value, Was increased N times. Therefore, the possibility of overlock is reduced due to the drop of the power supply voltage.

3 is a configuration diagram of the divided clock generation unit 241 and the control signal generation unit 243 according to the present invention.

3, the divided clock generating unit 241 includes an AND gate, an inverter INV and a D flip-flop DFF1. The control signal generating unit 243 includes a D flip-flop DFF2 ) And XNOR gate (XNOR).

The D flip flops DFF1 and DFF2 include an input terminal D, an output terminal Q, an enable terminal EN and a set terminal S or a reset terminal RS. When the enable terminal EN is inactivated (low), a value input to the input terminal D is stored in the D flip flops DFF1 and DFF2. When the enable terminal EN is activated And the value stored in the D flip flops DFF1 and DFF2 is output to the output terminal Q. [ When the reset terminal RS is activated (low), the value output to the output terminal Q of the D flip-flop DFF1 becomes low, and when the set terminal S is activated (low), the D flip- The output terminal Q becomes high.

The divided clock generation unit 241 and the control signal generation unit 243 will be described with reference to FIG.

First, the operation of the divided clock generation unit 241 will be described.

The AND gate AND receives the minimum signal MIN and the reference clock RCK and generates a signal input to the enable terminal EN of the D flip-flop DFF1. When the minimum signal MIN is inactivated (low), the signal input to the enable terminal EN of the D flip-flop DFF1 is inactivated and the signal input to the reset terminal RS of the D flip-flop DFF1 is Activated (low). Therefore, a low is outputted to the output terminal Q of the D flip-flop DFF1, and the divided clock DCK is maintained in a deactivated state.

When the minimum signal MIN is activated (high), the signal input to the enable terminal EN of the D flip-flop DFF1 becomes equal to the reference clock RCK and the reset terminal RS of the flip- (High). Therefore, the value output to the output terminal Q of the D flip-flop DFF1 is toggled for each rising edge of the reference clock signal RCK. A divided clock DCK obtained by dividing the reference clock signal RCK by two is generated at the output terminal Q of the D flip flop DFF1. Here, the starting value of the frequency dividing clock DCK may be either low or high depending on when the delay value of the delay unit 210 reaches the minimum value. The configuration of the divided clock generation unit 241 is not limited to the example shown in FIG. 3, and the division ratio may be a value other than 2.

Next, the operation of the control signal generator 243 will be described.

The XNOR gate XNOR generates the control signal CONT in response to the signal output to the output terminal Q of the D flip-flop DFF2 and the comparison signal COMP. When the minimum signal MIN is inactivated (low), the enable terminal EN of the flip-flop DFF2 is inactivated (low) and the set terminal S is activated (low). HIGH is outputted to the output terminal Q of the D flip-flop DFF2. The XNOR gate XNOR lowers the control signal CONT when the comparison signal COMP is low and makes the control signal CONT high when the comparison signal COMP is high. That is, when the minimum signal MIN is inactivated, the comparison signal COMP and the control signal CONT have the same value.

When the minimum signal MIN is activated (high), the enable terminal EN of the flip-flop DFF2 is activated (high) and the set terminal S is deactivated (high). When the minimum signal MIN is activated (high), the value of the comparison signal COMP input to the input terminal D is stored in the D flip flop DFF2 while the minimum signal MIN is inactivated. The value stored in the D flip-flop DFF2 is outputted to the output terminal of the DFF2. Therefore, if the value of the comparison signal COMP is high just before the minimum signal MIN is activated, the value output to the output terminal Q of the D flip-flop DFF2 after the minimum signal MIN is activated is high, If the value of the comparison signal COMP is low immediately before the minimum signal MIN is activated, the value output to the output terminal Q of the D flip-flop DFF2 after the minimum signal MIN is activated is low. The value of the comparison signal COMP after the activation of the minimum signal MIN is equal to the value of the comparison signal COMP just before the minimum signal MIN is activated. Therefore, the control signal CONT, which is the output of the XNOR gate XNOR, becomes high (first value) regardless of the value of the comparison signal COMP immediately before the minimum signal MIN is activated. This value is maintained until the logical value of the comparison signal COMP is changed.

4 is a configuration diagram of a delay locked loop according to another embodiment of the present invention.

4, the delay locked loop includes a delay unit 410 for delaying the reference clock signal RCK to generate an output clock signal OCK, a delay unit 450 for delaying the output clock signal OCK by a delayed model value, A phase comparator 430 for comparing phases of the reference clock signal RCK and the feedback clock signal FCK and a phase comparator 430 for comparing the reference clock signal RCK with the feedback clock signal FCK, And a controller 440 for adjusting the delay value of the delay unit 410 and maintaining the delay value of the delay unit 410 after the delay value of the delay unit 410 reaches the minimum value.

The delay locked loop will be described with reference to FIG.

The configuration and operation of the delay unit 410, the replica delay unit 420 and the phase comparator 430 in the delay locked loop of FIG. 4 are the same as those of the delay locked loop of FIG. 2, ), And the phase comparator 230 are similar to the configuration and operation of the phase comparator 230. Hereinafter, the delay locked loop of FIG. 4 will be described focusing on the configuration and operation of the control unit 440. FIG.

The phase comparator 430 compares the phase of the reference clock signal RCK with the phase of the feedback clock signal FCK to generate a comparison signal COMP corresponding to the phase comparison result. And generates the comparison signal COMP having the first value (high) when the phase of the reference clock signal RCK is ahead of the phase of the feedback clock signal FCK. On the other hand, when the phase of the reference clock signal RCK is lower than the phase of the feedback clock signal FCK, a comparison signal COMP having a second value (low) is generated. The method of comparing the phases is the same as described above in the description of FIG.

The control unit 440 controls the delay value of the delay unit 410 according to the comparison result of the phase comparator 430. When the delay value of the delay unit 410 does not reach the minimum value, The delay value of the delay unit 410 is increased or decreased according to the comparison result and the delay value of the delay unit 410 is maintained at the minimum value when the delay value of the delay unit 410 reaches the minimum value.

In more detail, the controller 440 generates the control signal CONT in response to the minimum signal MIN and the comparison signal COMP. The control unit 440 generates the control signal CONT having the same logical value as the comparison signal COMP when the minimum signal MIN is inactivated. The controller 440 also generates a control signal CONT having a first value (high) when the minimum signal MIN is activated. That is, the control unit 440 maintains the value of the control signal CONT at the first value regardless of the value of the comparison signal COMP when the minimum signal MIN is activated. That is, after the delay value of the delay unit 410 reaches the minimum value, when the power supply voltage falls and the rising edge of the feedback clock FCK passes the polling edge of the reference clock RCK and the value of the comparison signal COMP becomes the second value (Low), the value of the control signal CONT is maintained at the first value, so that the delay value of the delay unit 410 does not increase. The delay value of the delay unit 410 is decreased in response to the first control signal CONT but remains at the minimum value since it has already reached the minimum value. The control unit 440 which performs this operation may include an OR gate that receives the minimum signal MIN and the comparison signal COMP and outputs the control signal CONT.

Hereinafter, with reference to the above description, it is assumed that (1) the delay value of the delay unit 410 does not reach the minimum value, and (2) the case where the delay value of the delay unit 410 reaches the minimum value, The operation will be described.

(1) When the delay value of the delay unit 410 does not reach the minimum value

The control unit 440 generates the control signal CONT having the first value (high) when the phase of the reference clock signal RCK is ahead of the phase of the feedback clock signal FCK in response to the comparison signal COMP, The delay value of the delay unit 410 decreases in response to the control command CONT. On the contrary, when the phase of the reference clock signal RCK is lower than the phase of the feedback clock signal FCK, the control unit 440 generates the control signal CONT having the second value (low) The delay value of the portion 410 increases.

(2) When the delay value of the delay unit 410 reaches the minimum value

When the power supply voltage continues to fall, the phase of the feedback clock FCK is delayed, and the delay value of the delay unit 410 of the delay locked loop continues to decrease to reach the minimum value. The control unit 440 generates the control signal CONT having the first value (high) regardless of the logical value of the comparison signal COMP in response to the activated minimum signal MIN. The logic value of the control signal CONT is maintained at the first value from the time when the minimum signal MIN is activated until the delay locked loop is initialized. The delay value of the delay unit 410 must be decreased in response to the control signal CONT having the first value but remains at the minimum value since it has already reached the minimum value.

As described above, in the conventional delay locked loop, the possibility of occurrence of overlock increases as the period of the reference clock signal RCK is shortened. However, the delay locked loop according to the present invention maintains the delay value of the delay unit 410 at the minimum value even if the phase of the feedback clock FCK is delayed according to the power supply voltage when the delay unit 410 reaches the minimum value Do not overlock.

5 is a diagram showing a latency control circuit 520 and a peripheral portion thereof according to an embodiment of the present invention. The latency adjusting circuit includes the delay locked loop shown in Fig. 2 or the delay locked loop shown in Fig.

5, the input signal IN input to the input pad 501 represents a signal input to the integrated circuit, and the target circuit 540 must perform an operation of X corresponding to the input signal IN Circuit. Delay A 510 represents the delay experienced in the integrated circuit until the input signal IN arrives at the latency control circuit 520 and Delay B 530 represents the delay experienced by the input signal IN ) Until it reaches the target circuit 540. [ The target circuit 540 may be an output pad (not shown in FIG. 5) for inputting and outputting a signal.

Assume that the latency between the input signal IN and its corresponding X operation is N. In this case, the target circuit 540 must perform an operation X after N clocks after the input signal IN is applied to the input pad 501. [ Therefore, the input signal IN input to the input pad 501 must reach the target circuit 540 after exactly N clocks. The latency adjusting circuit 520 adjusts the delay value of the input signal IN so that the input signal IN can reach the target circuit 540 at an accurate timing.

5, the latency adjusting circuit 520 delays the reference clock signal RCK by a delay value adjusted in response to a result of comparing the phases of the comparison clock signal CCK and the feedback clock signal FCK, (OCK). When the delay value does not reach the minimum value, the reference clock (RCK) is transmitted to the comparison clock (CCK). When the delay value reaches the minimum value, the frequency of the reference clock (RCK) A delay locked loop 521 for transmitting the clock DCK to the comparison clock CCK, a delay value of the path through which the input signal IN passes in the integrated circuit (the delay value of the path is delayed in the delay locked loop 521) (LATENCY <0: A>) of the input signal IN and the path information (PATH <0: A>) of the path information <0: A>) to delay the input signal IN.

Hereinafter, the latency control circuit 520 will be described with reference to FIG. 2 and FIG.

The target circuit 540 represents a circuit that performs an operation indicated by the input signal IN in response to the input signal IN. The target circuit 540 performs an operation of X indicated by the input signal IN input to the input pad 501 at a point of time after the input signal IN has been set by the latency value set from the time when the input signal IN is input to the input pad 501 do.

The delay locked loop 521 delays the reference clock signal RCK to generate an output clock signal OCK. The reference clock signal RCK is a clock signal delayed in the integrated circuit until the clock signal input to the clock input pad (not shown in FIG. 5) reaches the delay locked loop 521. The operation of the delay locked loop 521 is the same as described above in the description of FIG. 2, and the delay locked loop 521 generates the control signal CONT.

The path information generating unit 522 generates path information (PATH <0: A>) when the delay fixing operation of the delay locked loop 521 is completed. The path information generation unit 522 obtains the delay value of the path through which the input signal IN passes in the integrated circuit, and outputs the result as path information (PATH <0: A>). Here, the delay value of the path through which the input signal IN passes through the integrated circuit is the delay A 510 and the input signal IN_CON, which the input signal IN experiences until the input signal IN is input to the latency control circuit 520, (530) experienced from the target circuit (520) to the target circuit (540). The delay value is adjusted by the control signal CONT of the delay locked loop 521 to the delay A 510 or the delay B 530 and the delay value of the delay locked loop 521 Delay C (DEL_C) is included. In FIG. 5, the case where the delay C (DEL_C) is included in the delay A 510 is shown. The path information PATH < 0: A > is a value obtained by quantizing the delay value of the delay A 510 and the delay value of the delay B 530 in clock units (based on the reference clock RCK). The detailed configuration and operation of the path information generation unit 522 will be described later in the description of FIG.

The delay unit 523 receives the delay information (DELAY <0: A>) generated by subtracting the value of the path information (PATH <0: A>) from the latency (LATENCY < IN). That is, latency (LATENCY <0: A>) - path information (PATH <0: A>) = delay information (DELAY <0: A>). The bits of each information (PATH <0: A>, LATENCY <0: A>, DELAY <0: A>) may vary depending on the design. The delay unit 523 includes a simple subtracting circuit which takes the path information PATH <0: A> from the value of the latency LATENCY <0: A> to generate the delay information DELAY < circuit. The delay unit 523 delays the input signal IN by a delay value corresponding to the delay information DELAY < 0: A >, and outputs the delayed signal. In more detail, the delay unit 523 delays the input signal IN by a clock corresponding to the value of the delay information DELAY <0: A>. For example, if the delay information DELAY <0: A> indicates '4', the input signal IN is delayed by 4 clocks and output.

Hereinafter, the overall operation of the latency control circuit 520 will be described with reference to the above description.

The delay locked loop 521 performs a delay locked operation to adjust the delay value of the delay unit 210 of the delay locked loop 521 so that the reference clock RCK and the feedback clock FCK are synchronized. At this time, the delay value of the delay C (DEL_C) included in the delay A 510 is also adjusted to have the same value as the delay value of the delay unit 210 by the control signal CONT. After completion of the delay fixing operation, the path information generating unit 521 generates a path information generating unit 521 that corresponds to the sum of the delay values of the delay A 510 and the delay B 530 that the input signal IN experiences in the integrated circuit in addition to the latency adjusting circuit 520 (PATH < 0: A >). Here, the delay value of the delay A 510 includes the delay value of the delay C (DEL_C). The value of the generated path information (PATH <0: A>) is K. If the value of the latency LATENCY <0: A> is N, the value of the delay information DELAY <0: A> becomes NK and the latency adjusting circuit 520 delays the input signal IN by NK clock Output.

 In the above situation, if the power supply voltage falls and the overlock occurs in the conventional case, the input signal IN is the sum of the delay values of the delay A 510 and the delay B 530 experienced in the integrated circuit in addition to the latency control circuit 520 Is increased to K + 1. This is because the delay value of delay C (DEL_C) increases by one clock before it becomes overlocked. However, since the latency control circuit 520 delays the input signal IN by using NK which is a value of the delay information DELAY <0: A> generated before the overlock occurs, the input signal IN is delayed by the target circuit 540, The time point when the input signal IN is input to the input pad 501 is a time point after the (N + 1) -th clock has passed.

However, in the present invention, no overlock occurs even if the power supply voltage falls. Therefore, the sum of the delay values of the delay A 510 and the delay B 530 is maintained at a value corresponding to K based on the clock. Therefore, even if the power supply voltage falls, the input signal IN arrives at the target circuit 540 after N clocks have elapsed from the time when the input signal IN is input to the input pad 501.

The above description applies equally to the case where the latency adjusting circuit 520 of FIG. 5 includes the delay locked loop of FIG.

FIG. 6 is a diagram of an embodiment of the path information generator 522 of FIG.

6, the path information generator 522 has a delay value equal to that of the path through which the input signal IN passes in the integrated circuit, and delays the start signal ST to generate the end signal END (PATH <0: A>) by counting the reference clock (RCK) from the activation end of the start signal (ST) to the activation end of the end signal (END) And a generating unit 620.

The termination signal generator 610 adjusts the delay value in response to the control signal CONT generated in the D flip flops 611 and 614 and the delay locked loop 521 and adjusts the delay value of the delay locked loop 521 A delay unit 612 having a delay value equal to the phase difference between the clock (RCK) and the output clock (OCK)), and a replica having a delay value modeled as a delay experienced by the input signal IN in the integrated circuit And a delay unit 613. 5, the delay value of the replica delay unit 613 is equal to a value obtained by subtracting the delay value of the delay C (DEL_C) from the delay value of the delay A 510 and the delay value of the delay B 520 Lt; / RTI &gt; The D flip flops 611 and 614 are provided in order to enable a more accurate operation by synchronizing the passing signals (ST and the output signal of the replica delay unit 613) with the reference clock (RCK) It is not a component. The start signal ST and the end signal END are generated by a delay equal to a delay value equal to the delay experienced by the input signal IN in the integrated circuit (delay value of delay A 510 + delay value of delay B 530) .

The information generation unit 620 includes a counter 621 and a code storage unit 622. The counter 621 counts the reference clock signal RCK input in response to the activation of the start signal ST and outputs a code CNT <0: A>. The code storage unit 622 stores the code CNT < 0: A > in response to the activation point of the end signal END. Since the counting of the code CNT <0: A> is started by the start signal ST and the storing of the code CNT <0: A> is by the ending signal END, The number of reference clocks RCK corresponding to the delay value of the end signal generator 610 is stored. The code (CNT <0: A>) stored in the code storage unit 622 is directly output as the path information PATH <2: 0>.

The start signal ST is a signal for starting the operation of generating the path information PATH <0: A>. When the start signal ST is activated, the path information PATH <0: A> is generated. The start signal ST can be activated after the delay fixing operation of the delay locked loop 521 is completed. Generating such a start signal ST can be easily performed by a person having ordinary skill in the art, so that a detailed description thereof will be omitted.

In the above example, the case where the activation level of the specific signal is high (or low) and the deactivation level is low (or high) has been described, but it may vary depending on the design.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

Claims (19)

A delay unit for delaying a reference clock to generate an output clock;
A replica delay unit for delaying the output clock by a modeled delay value to generate a feedback clock;
A phase comparator for comparing the phase of the feedback clock with the comparison clock;
Wherein the phase comparator adjusts the delay value of the delay unit in response to a comparison result of the phase comparator, and when the delay value of the delay unit does not reach the minimum value, transfers the reference clock to the comparison clock, A control unit for transmitting a frequency-divided clock obtained by dividing the frequency of the reference clock by N to the comparison clock,
/ RTI &gt;
The method according to claim 1,
The control unit
And deactivates the frequency dividing clock when the delay value of the delay unit does not reach the minimum value and activates the frequency dividing clock when the delay value of the delay unit reaches the minimum value.
The method according to claim 1,
The control unit
A divided clock generating unit that divides the reference clock by N to generate a divided clock;
A clock selector for selecting one of the reference clock and the divided clock and transmitting the same to the comparison clock; And
And a control signal generator for generating a control signal in response to a comparison signal corresponding to a comparison result of the phase comparator and a minimum signal activated when the delay value of the delay unit reaches the minimum value,
/ RTI &gt;
The method of claim 3,
The divided clock generating unit
And deactivates the frequency dividing clock when the minimum signal is inactive and activates the frequency dividing clock when the minimum signal is activated.
The method of claim 3,
The clock selector
Wherein the reference clock is selected and transmitted to the comparison clock when the minimum signal is inactivated, and the selected clock is transmitted to the comparison clock when the minimum signal is activated.
The method of claim 3,
The phase comparator
And generating a comparison signal having a first value when the phase of the comparison clock is ahead of the feedback clock and outputting the comparison result having a second value obtained by inverting the first value when the phase of the comparison clock is behind the feedback clock, A delay locked loop that produces a signal.
The method according to claim 6,
The control signal generator
Generating the control signal having the same value as the comparison signal when the minimum signal is deactivated and generating the control signal having the first value until the rising edge of the feedback clock reaches the next edge of the comparison clock when the minimum signal is activated, Value of said control signal.
8. The method of claim 7,
The delay unit
Wherein the delay value decreases in response to the control signal having the first value and the delay value increases in response to the control signal having the second value.
A delay unit for delaying a reference clock to generate an output clock;
A replica delay unit for delaying the output clock by a modeled delay value to generate a feedback clock;
A phase comparator for comparing the phase of the reference clock with the phase of the feedback clock; And
And a controller for controlling the delay value of the delay unit in response to the comparison result of the phase comparator unit and maintaining the delay value of the delay unit after the delay value of the delay unit reaches the minimum value,
/ RTI &gt;
10. The method of claim 9,
The control unit
And generates a control signal in response to a comparison signal corresponding to a comparison result of the phase comparator and a minimum signal activated when the delay value of the delay unit reaches the minimum value.
11. The method of claim 10,
And generates the control signal having the same value as the comparison signal when the minimum signal is deactivated, and generates a control signal having a first value when the minimum signal is activated.
12. The method of claim 11,
The delay unit
Wherein the delay value decreases in response to the control signal having the first value and the delay value increases in response to the control signal having the second value.
The reference clock is delayed by a delay value adjusted in response to the comparison result of the comparison clock and the feedback clock to generate an output clock. When the delay value does not reach the minimum value, the reference clock is transmitted to the comparison clock, A delay locked loop for transmitting a divided clock obtained by dividing the frequency of the reference clock by N when the value reaches the minimum value, to the comparison clock;
A path information generator for generating path information corresponding to a delay value of a path through which the input signal passes through the integrated circuit, the delay value of the path including a delay value equal to the delay value of the delay locked loop; And
A delay unit for delaying the input signal using the latency value of the input signal and the path information,
/ RTI &gt;
14. The method of claim 13,
The delay locked loop
Deactivates the frequency dividing clock when its delay value does not reach the minimum value, and activates the frequency dividing clock when the delay value of the own clock reaches the minimum value.
14. The method of claim 13,
The delay unit
And delaying the input signal in response to delay information generated by subtracting the value of the path information from the latency value.
14. The method of claim 13,
The route information generating unit
And when the delay fixing operation of the delay locked loop is completed, generates the path information.
14. The method of claim 13,
Wherein the path information and the delay information have values in units of clocks.
A delay locked loop for delaying a reference clock to generate an output clock, wherein a delay value is a minimum value and then a delay value of the delay unit is maintained;
A path information generator for generating path information corresponding to a delay value of a path through which the input signal passes through the integrated circuit, the delay value of the path including a delay value equal to the delay value of the delay locked loop; And
A delay unit for delaying the input signal using the latency value of the input signal and the path information,
/ RTI &gt; 14. The method of claim 13,
The route information generating unit
And when the delay fixing operation of the delay locked loop is completed, generates the path information.
KR1020120153040A 2012-12-26 2012-12-26 Delay lock loop and latency control circuit including the same KR20140083367A (en)

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