JP2006012246A - Fifo memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a FIFO memory device which allows a system in a data transmission side to confirm data in a desired place out of data of which the number of registered data has been confirmed, without enlarging a circuit scale or complicating processing. <P>SOLUTION: The FIFO memory device is provided with; an n-stage shift register 2 (n is an integer equal to or larger than 2) for successively shifting data supplied from a system 100 in the data transmission side; a first selection means 5 to which outputs of the first to n-th stages of the shift register 2 are inputted; a counting means 3 which is counted up at each time of supply of a write enable signal from the system 100 and is counted down at each time of supply of a read enable signal from a system 200 in a data reception side; and a second selection means 4 to which outputs of the first to n-th stages of the shift register 2 are inputted and a count output of the counting means 3 is supplied as a control signal for selecting an output of a corresponding stage of the shift register 2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a first-in first-out (FIFO) memory device, and more particularly, to a circuit size reduction or the like.

  When transferring data between two systems operating asynchronously with each other, a FIFO memory is provided between the systems, and the system on the data transmission side writes the data to the FIFO memory at an appropriate timing, and the receiving side In general, the system reads data from the FIFO memory at an appropriate timing.

  As the FIFO memory, the transmitting system sequentially increments the write address signal and writes the data to the RAM, and the receiving system increments the read address signal and reads the data from the RAM. There has been a conventional one (see, for example, Patent Document 1).

  FIG. 5 is a block diagram showing a configuration example of such a conventional FIFO memory. Here, the transmission system is the control device 100 that transmits a command, and the reception system is the execution device 200 that executes the command.

  The FIFO memory 51 includes a RAM 52, a write counter 53, a read counter 54, and a FIFO status circuit 55. The RAM 52 can store data in units of predetermined bits at addresses 0 to (n−1).

  The control device 100 supplies data (here, a command) to the data input terminal DI of the RAM 52 and supplies a write enable signal to the write enable terminal WE and the write counter 53 of the RAM 52 using the operation clock of the control device 100 as a write clock. To do.

  The write counter 53 sets the initial value to 0 and counts up at the timing of the write clock while the write enable signal is supplied. When the count value reaches (n-1), the count value returns to the initial value 0 and the same counting operation is repeated. The count output Cw of the write counter 53 is supplied to the write address terminal WA of the RAM 52 as a write address signal.

  As a result, data is sequentially written from the control device 100 to addresses 0, 1, 2,... FIG. 6A is a timing chart showing an example of this write operation. In this example, the data “A”, “B”, “C”, “D”, “C”, “D” are stored in the RAM 52 by the write address signals “0”, “1”, “2”, “3”. Are written in addresses 0, 1, 2, and 3, respectively.

  The execution device 200 supplies a read enable signal to the read enable terminal RE and the read counter 54 of the RAM 52 using the operation clock of the execution device 200 as a read clock. The read counter 54 sets the initial value to 0 and counts up at the timing of the read clock while the read enable signal is supplied. When the count value reaches (n-1), the count value returns to the initial value 0 and the same counting operation is repeated. The count output Cr of the read counter 54 is supplied to the read address terminal RA of the RAM 52 as a read address signal.

  As a result, the execution device 200 sequentially reads data from the addresses 0, 1, 2,... FIG. 6B is a timing chart showing an example of this read operation in association with the write operation of FIG.

  Count outputs Cw and Cr of the write counter 53 and the read counter 54 are also supplied to the FIFO status circuit 55. In the FIFO status circuit 55, after the count output Cw of the write counter 53 synchronized with the write clock (operation clock of the control device 100) is changed to the read clock (operation clock of the execution device 200) by the clock transfer circuit 56. The comparator 57 compares whether or not the count output Cr of the read counter 54 is the same.

  The comparison result of the comparator 57 is sent to the execution device 200 as information indicating the data registration status (whether there is data that has not yet been read by the execution device 200 among the data written in the RAM 52). The execution device 200 does not supply the read enable signal when the comparison result is Cw = Cr.

  In the FIFO status circuit 55, the count output Cr of the read counter 54 synchronized with the read clock is changed to the write clock by the clock transfer circuit 58, and then subtracted from the count output Cw of the write counter 53 by the subtractor 59. Is done.

The subtraction output of the subtractor 59 is controlled as information indicating the number of registered data (the number of data written in the RAM 52 that has not yet been read by the execution device 200, that is, the number of queued queues for execution). Sent to device 100. When the subtraction output is n (the same number as the number of address addresses in the RAM 52), the control device 100 does not supply new data or a write enable signal.
JP 2001-307476 A (paragraph numbers 0002 to 0010, FIG. 5).

  By the way, on the side of this control device 100, after confirming the number of registered data by the subtraction output of the subtractor 59, what number data among those data is what data (in the queue waiting for execution). There is a case where it is desired to check what data is what number data.

  In the FIFO memory 51, since the read address signal when the execution device 200 last reads data is represented by the count output Cr of the read counter 54, the number of registrations is confirmed based on the count value of the read counter 54. It is possible to read out data in the desired order from the RAM 52 and confirm it. However, if the current count output of the read counter 54 is used as a reference, it may not be possible to confirm the data in the order that was originally desired to be confirmed. This will be described with reference to FIG. 7 (in FIG. 7 and later FIG. 8, the addresses of the RAM 52 are illustrated as addresses 0 to 7 for simplification).

  Assume that the count value of the read counter 54 is 2 as shown in FIG. 7A when the control device 100 confirms the number of registered data. At this time, for example, a read address signal of value 5 obtained by adding 3 to the count output of the read counter 54 corresponds to the data “D”.

  However, as shown in FIG. 7 (b), after the control device 100 confirms the number of registered data, it decides what number of the data is to be confirmed. When the data is read, the count value of the read counter 54 may be counted up to 3. Therefore, for example, it is determined that the third data (originally data “D” as described above) of the data whose number of registrations has been confirmed is to be confirmed, and a value obtained by adding 3 to the count output of the current read counter 54 When the read address signal is supplied to the read address terminal RA of the RAM 52, the data “E” is read from the RAM 52 instead of the data “D”, so that the data in the order originally desired cannot be confirmed.

  Therefore, the control device 100 needs to take one of the following methods (1) and (2) in order to confirm data in a desired order among the data whose number of registrations has been confirmed.

  (1) As shown in FIG. 8, a RAM 101 having the same capacity as the RAM 52 is prepared in the control device 100, and when the number of registered data is confirmed, the count output Cr of the read counter 54 is used as a reference in the RAM 52. The data “A”, “B”, “C”,. Then, after determining which number of data among the data whose number of registrations has been confirmed is to be confirmed, the data is read from the corresponding address address of the RAM 101 (for example, address address 3 when the third data is to be confirmed).

  (2) As shown in FIG. 9, a register 60 for storing the count output Cr of the read counter 54 is provided in the FIFO memory 51, and the count output of the read counter 54 is confirmed when the number of registered data is confirmed. Cr is written into the memory 60. Then, after determining which number of data among the data whose number of registrations has been confirmed is to be confirmed, a read address signal generated on the basis of the count output Cr read from the memory 60 (for example, when confirming the third data) Supplies a read address signal obtained by adding 3 to the count output Cr read from the memory 60 to the read address terminal RA of the RAM 52, and reads the data from the RAM 52.

  However, in the methods (1) and (2), in addition to the RAM 52 which is an original storage device for registering data, dedicated data for confirming data in a desired order among the data whose registered number is confirmed. Since the storage device (RAM 101 and register 60) must be provided in the control device 100 or the FIFO memory 51 to control the storage device, the circuit scale increases and the processing becomes complicated.

  In the present invention, in view of the above-described points, the data transmission side system such as the control device 100 does not incur an increase in circuit scale or processing complexity, and the desired number of pieces of data in which the number of registrations is confirmed. An object of the present invention is to provide a FIFO memory device capable of confirming data in order.

  In order to solve this problem, a FIFO memory device according to the present invention includes an n-stage (n is an integer of 2 or more) shift register that sequentially shifts data supplied from a data transmission side system, and the shift register. The first selection means to which the outputs from the first stage to the nth stage are respectively inputted, and the count is incremented every time the write enable signal is supplied from the transmission side system, and the read reception is enabled from the data reception side system. Counting means that counts down each time a signal is supplied, and outputs from the first stage to the nth stage of the shift register are input, and the count output of the counting means is output from the corresponding stage of the shift register. And a second selection unit that is supplied as a control signal for selecting.

  In this FIFO memory device, data supplied from a system on the data transmission side is written by being sequentially shifted to n stages of shift registers. The outputs from the first stage to the nth stage of the shift register are input to the first selection means and the second selection means.

  Each time the write enable signal is supplied from the transmission system, the counting means counts up, and every time the read enable signal is supplied from the data receiving system, the counting means counts down. The count output of the counting means is supplied to the second selection means as a control signal for selecting the output of the corresponding stage of the shift register, so that the second selection means in the order of the previously written data. Selected.

  Therefore, the receiving system can read data by inputting the selection output of the second selection means. Further, the receiving system can check the data registration status (whether there is data that has not yet been read by the receiving system among the data written in the shift register) by the count output itself of the counting means. it can.

  In addition, the sending system also uses the count output itself of the counting means to register the number of data (the number of data written to the shift register that has not yet been read by the receiving system, that is, the data in the queue waiting for execution). Number).

  In addition, after confirming the number of registered data, the transmitting system wants to confirm what number of those data is what kind of data, and in the shift register stage corresponding to the order. If a control signal for selecting an output is supplied to the first selection means, the data in that order is selected by the first selection means. Therefore, the transmission-side system can confirm the data in the desired order among the data whose number of registrations has been confirmed by inputting the selection output of the first selection means.

  Thus, according to this FIFO memory device, the system on the transmission side receives data in the desired order from among the data whose number of registrations has been confirmed from the shift register itself, which is the original storage device for registering the data. Can be confirmed. That is, in addition to the original storage device for registering data, a dedicated storage device (for example, the RAM 101 in FIG. 8 or the register 60 in FIG. 9) for confirming data in a desired order among the data whose registration number has been confirmed. There is no need to provide it. As a result, the system on the transmission side can confirm data in a desired order among the data for which the number of registrations has been confirmed without increasing the circuit scale or complicating the processing.

  In addition, the receiving system and the transmitting system can confirm the data registration status and the number of data registrations by the count output itself of the counting means, so information indicating the data registration status and the number of data registrations can be determined. There is no need to provide a dedicated circuit (eg, the comparator 57 and the subtractor 59 in FIG. 5) for creating the information to be shown. Therefore, the circuit scale can be reduced also in this respect.

  The transmission side system can write data to the FIFO memory device by supplying data and a write enable signal in the same manner as in the prior art, and the number of registered data in the same manner as in the prior art from the count output of the counting means. Can be confirmed. Also, the receiving system can confirm the data registration status from the count output of the counting means in the same manner as in the prior art, and reads out data from this FIFO memory device by supplying a read enable signal as in the prior art. be able to. In other words, the interface with the FIFO memory device is sufficient for the transmission side system and the reception side system. Therefore, it is possible to easily replace the conventional FIFO memory device.

  In this FIFO memory device, as an example, the clock transfer means for synchronizing the output of the transmission-side system with the operation clock of the reception-side system, the selection output of the second selection means, and the count output of the counting means are transmitted on the transmission side. It is preferable to further include clock transfer means for synchronizing with the operation clock of the system.

  As a result, even if the operation clock of the transmission system and the operation clock of the reception system are asynchronous with each other, data can be transferred from the transmission system to the reception system via this FIFO memory device. In addition, the transmission-side system can confirm the number of registrations, and can confirm data in a desired order among the data for which the number of registrations is confirmed.

  Also, in this FIFO memory device, for example, the counting means changes the count value when the read enable signal is supplied from the receiving system at the same time as the write enable signal is supplied from the transmitting system. It is preferable not to do so.

  As a result, even when data writing by the sending system and data reading by the receiving system are performed at the same time, the receiving system can accurately check the data registration status, and the sending side System will be able to confirm the number of registered data accurately.

  According to the FIFO memory device of the present invention, the data transmission side system confirms the number of registrations without providing a dedicated storage device other than the shift register that is the original storage device for registering data. The data in a desired order can be confirmed. As a result, it is possible to obtain an effect that the system on the data transmission side can confirm the data in the desired order among the data whose number of registrations has been confirmed without increasing the circuit scale or complicating the processing.

  In addition, the receiving system and the transmitting system can confirm the data registration status and the number of data registrations by the count output itself of the counting means, so information indicating the data registration status and the number of data registrations can be determined. There is no need to provide a dedicated circuit for creating the information to be shown. Therefore, the effect that the circuit scale can be reduced also in this respect is obtained.

  Further, since the interface with the FIFO memory device is sufficient for the transmission side system and the reception side system, it is possible to easily replace the conventional FIFO memory device.

  In addition, even if the operation clock of the system on the data transmission side and the operation clock of the system on the data reception side are asynchronous with each other, the system on the data transmission side confirms the number of registrations or confirms the number of registrations. The effect that the data of the desired order among data can be confirmed is acquired.

  Also, when data writing by the data sending system and data reading by the data receiving system are performed simultaneously, the data receiving system can accurately check the data registration status, An effect is obtained that the system on the data transmission side can accurately confirm the number of registered data.

  Hereinafter, the present invention will be specifically described with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a FIFO memory device according to the present invention. Here, as in FIG. 5, the data transmission system is the control device 100 that transmits a command, and the data reception system is the execution device 200 that executes the command. Specific examples of the control device 100 and the execution device 200 include a processor that transmits a command for reading image data from an image memory in a camera-integrated VTR or a digital camera, and executes the command to obtain image data from the image memory. A processor to read out is mentioned.

  The FIFO memory 1 includes a shift register 2, an up / down counter 3, a selector 4, a selector 5, and a clock transfer circuit 6-10. The shift register 2 is an n-stage (n is an integer equal to or greater than 2) shift register, and data input terminals D of D-type flip-flops FF0, FF1,... FF (n−1) having a parallel data number m (for example, 32). And a data output terminal Q are connected in series.

  The control device 100 supplies data (here, 32-bit parallel command), a write enable signal, and a read address signal to the clock transfer circuits 6, 7, and 8 using the operation clock of the control device 100 as a write clock.

  The clock transfer circuits 6 to 8 are circuits for synchronizing (changing) the output of the control device 100 with the read clock that is the operation clock of the execution device 200.

  FIG. 2 is a block diagram illustrating a configuration example of the clock transfer circuits 6 to 8. The clock transfer circuits 6 to 8 are obtained by connecting the data input terminal D of the D-type flip-flop 11 and the data output terminal Q of the D-type flip-flop 12, and output of the control device 100 (data, In the clock transfer circuit 7, a write enable signal is supplied to the data input terminal D of the flip-flop 11 and a write clock is supplied to the clock terminal CK of the flip-flop 11. A read clock is supplied to the clock terminal CK of the D flip-flop 12. Regarding the clock transfer circuit 6, the flip-flops 11 and 12 have the same number of parallel data as the flip-flops FF <b> 0 to FF (n−1) of the shift register 2.

  FIGS. 3A and 3B are timing charts showing an operation example of transferring the data and the write enable signal from the control device 100 to the read clock for the clock transfer circuits 6 and 7, respectively.

  The clock transfer circuits 9 and 10 in FIG. 1 have the same configuration as the clock transfer circuits 6 to 8. However, the clock transfer circuits 9 and 10 are circuits for switching to the write clock, contrary to the clock transfer circuits 6 to 8, and the read clock is supplied to the clock terminal CK of the flip-flop 11 in FIG. The write clock is supplied to the clock terminal CK of the D flip-flop 12.

  The configuration shown in FIG. 2 is merely an example, and a clock transfer circuit having a configuration different from this (for example, a circuit as disclosed in Japanese Patent Laid-Open No. 8-274585 by the applicant) is used as the clock transfer circuit 6. -10 may be used.

  As shown in FIG. 1, the data transferred to the read clock by the clock transfer circuit 6 is supplied to the data input terminal D of the first-stage flip-flop FF0 of the shift register 2. The write enable signal transferred to the read clock by the clock transfer circuit 7 is supplied to the clock terminals CK of the flip-flops FF0 to FFn in each stage of the shift register 2 and also supplied to the up / down counter 3. Outputs of the flip-flops FF0 to FFn at each stage of the shift register 2 are supplied to n selection input terminals of the selectors 4 and 5, respectively.

  The execution device 200 supplies a read enable signal to the up / down counter 3 using the operation clock of the execution device 200 as a read clock. The up / down counter 3 sets the initial value to 0, counts up every time the write enable signal is supplied, and counts down every time the read enable signal is supplied. Further, when the write enable signal and the read enable signal are supplied simultaneously, the up / down counter 3 does not count up or count down, and therefore does not change the count value.

  The count output of the up / down counter 3 causes the selector 4 to select the output of the corresponding stage of the shift register 2 (for example, if the count output is 3, the output of the third stage flip-flop FF2 of the shift register 2 is selected). ) Supplied as a control signal. The selection output of the selector 4 is sent to the execution device 200. The execution device 200 takes in the selection output of the selector 4 at the timing when the read enable signal is supplied.

  Also, the count output of the up / down counter 3 is sent to the execution device 200 as information indicating the data registration status (whether there is any data written in the shift register 2 that has not yet been read by the execution device 200). Sent. The execution device 200 does not supply the read enable signal when the count output is zero.

  Also, the count output of the up / down counter 3 is the number of registered data (the number of data written in the shift register 2 that has not yet been read by the execution device 200, that is, the number of data in the queue waiting for execution). Is transferred to the write clock by the clock transfer circuit 9 and then sent to the control device 100. When the count output is n (the same number as the number of stages of the shift register 2), the control device 100 does not supply new data or a write enable signal.

  The read address signal transferred to the read clock by the clock transfer circuit 8 is supplied to the selector 5 as a selection control signal. The selection output of the selector 5 is transferred to the write clock by the clock transfer circuit 10 and then sent to the control device 100.

  FIG. 4 is a timing chart showing an operation example of the FIFO memory 1. When the first data “A” is supplied from the control device 100 together with the write enable signal, the data “A” and the write enable signal are respectively read by the clock transfer circuits 6 and 7 as read clocks (FIG. 4A). After switching (FIGS. 4B and 4C), the data input terminal D of the first stage flip-flop FF0 of the shift register 2 and the clock terminals CK of the flip-flops FF0 to FFn of each stage of the shift register 2 are supplied. Is done.

  As a result, the data “A” is taken into the first flip-flop FF 0 of the shift register 2. Therefore, the data “A” is supplied from the flip-flop FF 0 to the selection input terminals of the selectors 4 and 5.

  The write enable signal is supplied to the up / down counter 3, and the up / down counter 3 is counted up to 1 (FIG. 4D). As a result, the control signal for selecting the output of the first flip-flop FF0 of the shift register 2 is supplied to the selector 4, so that the data “A” is selected by the selector 4 (FIG. 4 (h)).

  Subsequently, when the second “B” is supplied from the control device 100 together with the write enable signal (FIGS. 4B to 4C), the data “B” is supplied to the first flip-flop of the shift register 2. The data “A” is shifted to the flip-flop FF 1 in the second stage of the shift register 2. Therefore, the data “B” and “A” are supplied from the flip-flops FF0 and FF1 to the selection input terminals of the selectors 4 and 5, respectively.

  Further, the up / down counter 3 is counted up to 2 (FIG. 4D). As a result, the control signal for selecting the output of the second-stage flip-flop FF1 of the shift register 2 is supplied to the selector 4, so that the data “A” is selected by the selector 4 (FIG. 4 (i)).

  Subsequently, when the third “C” is supplied from the control device 100 together with the write enable signal (FIGS. 4B to 4C), the data “C” is stored in the first flip-flop of the shift register 2. The data “B” is shifted to the second-stage flip-flop FF 1 of the shift register 2 and the data “A” is shifted to the third-stage flip-flop FF 2 of the shift register 2. Accordingly, the data “C”, “B”, and “A” are supplied from the flip-flops FF0, FF1, and FF2 to the selection input terminals of the selectors 4 and 5, respectively.

  Further, the up / down counter 3 is counted up to 3 (FIG. 4D). As a result, the control signal for selecting the output of the third flip-flop FF2 of the shift register 2 is supplied to the selector 4, so that the data “A” is selected by the selector 4 (FIG. 4 (j)).

  Thereafter, when a read enable signal is supplied from the execution device 200 (FIG. 4E), data “A” which is a selection output of the selector 4 is taken into the execution device 200 (FIG. 4F). Then, the up / down counter 3 is counted down to 2 (FIG. 4D). As a result, the control signal for selecting the output of the second-stage flip-flop FF1 of the shift register 2 is supplied to the selector 4, so that the data “B” is selected by the selector 4 (FIG. 4 (i)).

  Subsequently, the fourth “D” is supplied from the control device 100 together with the write enable signal (FIGS. 4B to 4C), and at the same time, the read enable signal is supplied from the execution device 200 (FIG. 4B). e)).

  At this time, since the up / down counter 3 does not change the count value, the count value of the up / down counter 3 remains 2 (FIG. 4D). As a result, the data “B” that is the selection output of the selector 4 is taken into the execution device 200 (FIG. 4F).

  Then, the data “D” is taken into the first flip-flop FF 0 of the shift register 2, the data “C” is shifted to the second flip-flop FF 1 of the shift register 2, and the data “B” is shifted to the shift register 2. And the data “A” is shifted to the fourth-stage flip-flop FF3 of the shift register 2. Therefore, the data “D”, “C”, “B”, and “A” are supplied to the selection input terminals of the selectors 4 and 5 from the flip-flops FF0, FF1, FF2, and FF3, respectively. Since the selector 4 remains supplied with the control signal for selecting the output of the second-stage flip-flop FF1 of the shift register 2, the selector 4 selects the data “C” (FIG. 4 (i)).

  Subsequently, when a read enable signal is supplied from the execution device 200 (FIG. 4E), data “C”, which is a selection output of the selector 4, is taken into the execution device 200 (FIG. 4F). Then, the up / down counter 3 is counted down to 1 (FIG. 4D). As a result, the control signal for selecting the output of the first flip-flop FF0 of the shift register 2 is supplied to the selector 4, so that the data “D” is selected by the selector 4 (FIG. 4 (h)).

  Thus, in the FIFO memory 1, data supplied from the control device 100 is written by being sequentially shifted to the n-stage shift register 2. Outputs from the first stage to the nth stage of the shift register 2 are input to the selectors 4 and 5.

  Each time the write enable signal is supplied from the control device 100, the up / down counter 3 counts up, and every time the read enable signal is supplied from the execution device 200, the up / down counter 3 counts down. Then, the count output of the up / down counter 3 is supplied to the selector 4 as a control signal for selecting the output of the corresponding stage of the shift register 2, so that the selector 4 selects in the order of the previously written data. .

  Therefore, the execution apparatus 200 can read data by inputting the selection output of the selector 4. Further, the execution device 200 can confirm the registration status of data by the count output itself of the up / down counter 3.

  Further, the control device 100 can also confirm the number of registered data by the count output itself of the up / down counter 3.

  Then, after confirming the number of registered data by the count output of the up / down counter 3, the control device 100 determines what number of those data is what (in the queue waiting for execution). If it is desired to check what data the second data is), a read address signal for selecting the output of the stage of the shift register 2 corresponding to the order is supplied to the selector 5 via the clock transfer circuit 8; Since the data in that order is selected by the selector 5 and input to the control device 100 via the clock transfer circuit 10, the data can be confirmed. FIG. 4G shows an example in which a read address signal for selecting the first stage output of the shift register 2 (for confirming the first data in the queue waiting for execution) is supplied from the control device 100. Is shown.

  As described above, according to the FIFO memory device 1, the control device 100 uses the shift register 2 itself, which is an original storage device for registering data, to store data in a desired order among the data whose number of registrations is confirmed. Can be confirmed. That is, in addition to the original storage device for registering data, a dedicated storage device (for example, the RAM 101 in FIG. 8 or the register 60 in FIG. 9) for confirming data in a desired order among the data whose registration number has been confirmed. There is no need to provide it. Thereby, the control apparatus 100 can confirm the data of the desired order among the data which confirmed the number of registration, without causing the increase in a circuit scale or the complexity of a process.

  Further, the execution device 200 and the control device 100 can confirm the data registration status and the number of data registrations by the count output itself of the up / down counter 3, so that information indicating the data registration status and the number of data registrations can be obtained. There is no need to provide a dedicated circuit (eg, the comparator 57 and the subtractor 59 in FIG. 5) for creating the information to be shown. Therefore, the circuit scale can be reduced also in this respect.

  The control device 100 can write data to the FIFO memory device 1 by supplying data and a write enable signal in the same manner as in the prior art, and can register data from the count output of the up / down counter 3 in the same manner as in the prior art. You can check the number. The execution device 200 can also confirm the data registration status from the count output of the up / down counter 3 in the same manner as in the prior art, and if the read enable signal is supplied in the same manner as in the prior art, the data from the FIFO memory device 1 can be confirmed. Can be read out. That is, for the control device 100 and the execution device 200, the interface with the FIFO memory device 1 is sufficient as the conventional one. Therefore, the conventional FIFO memory device can be easily replaced with the FIFO memory device 1.

  Even if the operation clock of the control device 100 and the operation clock of the execution device 200 are asynchronous with each other, data can be transferred from the control device 100 to the execution device 200 via the FIFO memory device 1 and control can be performed. The apparatus 100 can confirm the number of registrations, and can confirm data in a desired order among the data for which the number of registrations is confirmed.

  Further, the up / down counter 3 does not change the count value when the read enable signal is supplied at the same time as the write enable signal is supplied, so that the control device 100 writes data and the execution device 200 reads data. In the case where the execution is performed simultaneously, the execution device 200 can accurately check the data registration status, and the control device 100 can accurately check the number of data registrations.

  In the above example, the shift register 2 configured by a D-type flip-flop is provided, but an n-stage shift register having an appropriate configuration other than that may be provided.

  Further, in the above example, the command is transferred by the FIFO memory device 1, but the FIFO memory device according to the present invention can be used for transferring not only the command but also any data.

It is a block diagram which shows the structural example of the FIFO memory device based on this invention. FIG. 2 is a block diagram illustrating a configuration example of a clock transfer circuit in FIG. 1. 3 is a timing chart illustrating an operation example of the clock transfer circuit in FIG. 2. 3 is a timing chart showing an operation example of the FIFO memory of FIG. 1. It is a block diagram which shows the structural example of the conventional FIFO memory. 6 is a timing chart showing an operation example of the FIFO memory of FIG. 5. FIG. 6 is a diagram illustrating a state in which the count output of the read counter changes after the number of registrations is confirmed in the FIFO memory of FIG. 5. FIG. 6 is a diagram illustrating a method for confirming data in a desired order among the data whose number of registrations is confirmed in the FIFO memory of FIG. 5. FIG. 6 is a diagram illustrating a method for confirming data in a desired order among the data whose number of registrations is confirmed in the FIFO memory of FIG. 5.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 FIFO memory, 2 Shift register, 3 Up / down counter, 4,5 selector, 6-10 clock transfer circuit, 100 control apparatus, 200 execution apparatus

Claims (3)

An n-stage (n is an integer of 2 or more) shift register that sequentially shifts data supplied from the data transmission system;
First selection means to which outputs from the first stage to the nth stage of the shift register are respectively input;
Counting means that counts up each time a write enable signal is supplied from the transmission system, and counts down every time a read enable signal is supplied from the data reception system;
Second selection means for receiving outputs from the first to n stages of the shift register and supplying the count output of the counting means as a control signal for selecting the output of the corresponding stage of the shift register And a FIFO memory device. The FIFO memory device according to claim 1, wherein
Clock transfer means for synchronizing the output of the transmission-side system with the operation clock of the reception-side system;
A FIFO memory device, further comprising clock transfer means for synchronizing the selection output of the second selection means and the count output of the counting means with an operation clock of the transmission-side system. The FIFO memory device according to claim 1, wherein
The counting means does not change the count value when a read enable signal is supplied from the receiving side system at the same time as a write enable signal is supplied from the transmitting side system. apparatus.

Images