CN116866732A

CN116866732A - Handshaking circuit and data processing method

Info

Publication number: CN116866732A
Application number: CN202310806239.7A
Authority: CN
Inventors: 秦祎繁; 茆文艺
Original assignee: Beijing Eswin Computing Technology Co Ltd; Haining Eswin IC Design Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd; Haining Eswin IC Design Co Ltd
Priority date: 2023-07-03
Filing date: 2023-07-03
Publication date: 2023-10-10

Abstract

The present disclosure provides a handshaking circuit and a data processing method. The handshaking circuit comprises at least one control sub-circuit for receiving a destination preparation signal and a source request signal and outputting a source flag signal according to the destination preparation signal and the source request signal; the filtering sub-circuit is used for receiving the source mark signals from the corresponding control sub-circuit, receiving a plurality of source data based on the source mark signals in a plurality of periods, and carrying out filtering operation on the plurality of source data to obtain target data and outputting the target data under the condition that the quantity of the plurality of source data is determined to meet the preset condition; wherein each control sub-circuit of the at least one control sub-circuit corresponds to one of the at least one filter sub-circuits, each filter sub-circuit of the at least one filter sub-circuit corresponds to one of the at least one control sub-circuits, and each control sub-circuit is electrically connected to the corresponding filter sub-circuit.

Description

Handshaking circuit and data processing method

Technical Field

The present disclosure relates to the field of integrated circuit technology, and more particularly, to a handshaking circuit and a data processing method.

Background

In the field of image processing, an image processing circuit may support a post-drive mode, for example, a post-stage image processing circuit requests data from a preceding stage image processing circuit. The image processing circuit may also support a predecessor mode, for example, the image processing circuit is located at a later stage of the non-memory unit, and receives and processes data from and to the non-memory unit at the previous stage.

The design of the handshaking circuit for the image processing circuit can increase portability of the image processing circuit. For example, a handshake circuit of the image processing circuit is implemented by using Static Random-Access Memory (SRAM) for data temporary storage or using Gate Clock (GCK) to turn off a Clock source. But this increases the overall area of the circuit and reduces the throughput of the circuit.

Disclosure of Invention

The present disclosure provides a handshaking circuit and a data processing method.

According to one aspect of the present disclosure, the present disclosure proposes a handshaking circuit comprising: at least one control sub-circuit for receiving the destination preparation signal and the source request signal, and outputting a source flag signal according to the destination preparation signal and the source request signal; the filtering sub-circuit is used for receiving the source mark signals from the corresponding control sub-circuit, receiving a plurality of source data based on the source mark signals in a plurality of periods, and carrying out filtering operation on the plurality of source data to obtain target data and outputting the target data under the condition that the quantity of the plurality of source data is determined to meet the preset condition; each control sub-circuit of the at least one control sub-circuit corresponds to one of the at least one filter sub-circuits, each filter sub-circuit of the at least one filter sub-circuit corresponds to one of the at least one control sub-circuits, and each control sub-circuit is electrically connected with the corresponding filter sub-circuit.

According to an embodiment of the present disclosure, the control sub-circuit is further configured to output an enable signal according to the destination preparation signal and the source request signal in a preset number of cycles; and the filtering sub-circuit is also used for receiving the permission signal, performing filtering operation on the plurality of source data based on the permission signal to obtain target data, and outputting the target data.

According to an embodiment of the disclosure, the preset condition is that the plurality of source data includes n+m source data, N is a positive integer greater than 1, and M is a positive integer; the control sub-circuit is also used for outputting an allowing signal, a source mark signal and a starting mark signal according to the destination preparation signal and the source request signal in N periods; the filtering subcircuit is also for: receiving a source mark signal, and receiving N source data based on the source mark signal in N periods; receiving an initial mark signal, and copying the 1 st source data for M times based on the initial mark signal in N periods to obtain M1 st source data, wherein the 1 st source data is source data received by a filtering sub-circuit in the 1 st period of the N periods in the N source data; and receiving the permission signal, performing filtering operation on the N source data and the M1 st source data based on the permission signal to obtain target data, and outputting the target data.

According to an embodiment of the present disclosure, the control sub-circuit is further configured to receive a configuration signal and output an end flag signal based on the configuration signal; the filtering sub-circuit is also used for receiving the tail mark signal and carrying out L-th source data based on the tail mark signal in the L+1th period, wherein L is a positive integer; the filtering sub-circuit receives the L-th source data in the L-th period of the L periods based on the configuration signal, wherein the L-th source data is the source data received by the filtering sub-circuit in the L-th period of the L periods in the L-th source data.

According to an embodiment of the present disclosure, the control sub-circuit is configured to output an enable signal having an active level based on the end flag signal.

According to an embodiment of the disclosure, the preset condition is that the plurality of source data includes n+m source data, N is a positive integer greater than 1, and M is a positive integer; the filtering sub-circuit includes: the first triggers are used for receiving the source mark signals and receiving N source data based on the source mark signals in N periods; the first data operation unit is electrically connected with the first triggers respectively, and is used for receiving the initial sign signal, copying the 1 st source data for M times based on the initial sign signal in the N-th period to obtain M1 st source data, outputting N source data and M1 st source data, wherein the 1 st source data is source data received by the filter sub-circuit in the 1 st period of the N periods in the N source data; the cascaded second triggers are respectively and electrically connected with the first data operation unit and are used for receiving N source data and M1 st source data; and the second data operation unit is electrically connected with the plurality of second triggers respectively, and is used for receiving the N source data and the M1 st source data, operating the N source data and the M1 st source data to obtain target data and outputting the target data.

According to the embodiment of the disclosure, the second data operation unit is further configured to receive the permission signal, operate on the N source data and the M1 st source data based on the permission signal, obtain the destination data, and output the destination data.

According to an embodiment of the disclosure, the first data operation unit is further configured to receive an end flag signal, copy the L-th source data based on the end flag signal in the l+1th period, where L is a positive integer; the cascade connection of the plurality of first triggers receives L source data in L periods based on the configuration signal, wherein the L source data is the source data received by the plurality of first triggers in the L periods in the L source data.

According to an embodiment of the present disclosure, the control sub-circuit is further configured to receive a destination preparation signal having an active level and a source request signal having an active level, and output the source preparation signal having the active level according to the destination preparation signal; and outputting a source flag signal having an active level according to the source request signal and the source preparation signal.

According to an embodiment of the present disclosure, the control sub-circuit is further configured to receive a configuration signal, and output an end flag signal having an active level according to the configuration signal; and outputting an enable signal having an active level according to the end flag signal.

According to an embodiment of the disclosure, the control sub-circuit is further configured to receive a reset signal and perform a reset based on the reset signal; and the filter sub-circuit is also used for receiving a reset signal and resetting based on the reset signal.

According to an embodiment of the present disclosure, the control sub-circuit is further configured to receive a configuration signal and output a source preparation signal having an active level according to the configuration signal in case it is determined that there is a null in the cascaded plurality of first flip-flops.

According to an embodiment of the present disclosure, at least one control sub-circuit includes: at least one transmission unit for receiving the destination preparation signal; and the control unit is electrically connected with the at least one transmission unit and is used for receiving the source request signal and the destination preparation signal from the at least one transmission unit.

According to an embodiment of the disclosure, the control unit is electrically connected to the filtering sub-circuit, and the control unit is further configured to output a source flag signal according to the destination preparation signal and the source request signal.

According to an embodiment of the present disclosure, a control unit includes: the first logic operation unit is used for receiving the destination preparation signal and performing logic operation on the destination preparation signal to obtain a source preparation signal; and the second logic operation unit is electrically connected with the first logic operation unit and is used for receiving the source request signal and the source preparation signal and carrying out logic operation on the source request signal and the source preparation signal to obtain the permission signal.

According to an embodiment of the present disclosure, the control unit further includes: a third logic operation unit for receiving the source preparation signal and the source request signal and outputting a source flag signal according to the source preparation signal and the source request signal; a fourth logic operation unit for receiving the destination preparation signal and the source request signal, and outputting a start flag signal according to the destination preparation signal and the source request signal; and a fifth logic operation unit for receiving the configuration signal and outputting an end flag signal according to the configuration signal.

According to another aspect of the embodiments of the present disclosure, there is provided a data processing method, including: receiving a destination preparation signal and a source request signal; outputting a source flag signal according to the destination preparation signal and the source request signal; and receiving a plurality of source data based on the source flag signal for a plurality of periods; under the condition that the quantity of the plurality of source data meets the preset condition, filtering operation is carried out on the plurality of source data to obtain target data; and outputting the destination data.

According to the embodiment of the disclosure, the precursor mode and the postdrive mode of the filter sub-circuit are realized by designing signals received and transmitted by the control sub-circuit. In addition, the handshaking circuit only designs the transmission path of the signal, and does not depend on other circuit structures, so that the portability of the circuit can be improved, the complexity of circuit design is reduced, the area is saved, and the throughput of circuit processing data is improved.

Drawings

The above and other objects, features and advantages of the embodiments of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure taken in conjunction with the accompanying drawings. It should be noted that throughout the appended drawings, like elements are represented by like or similar reference numerals. In the figure:

fig. 1 shows a schematic diagram of a handshake circuit according to an embodiment of the present disclosure;

fig. 2 shows a schematic diagram of a handshake circuit according to another embodiment of the present disclosure;

fig. 3 shows a schematic diagram of a handshake circuit according to another embodiment of the present disclosure;

fig. 4A shows a schematic diagram of a handshake circuit according to another embodiment of the present disclosure;

FIG. 4B shows a schematic diagram of source data input according to an embodiment of the present disclosure;

FIG. 4C shows a schematic diagram of source data input according to another embodiment of the present disclosure;

fig. 5 shows a schematic diagram of a handshake circuit according to another embodiment of the present disclosure; and

fig. 6 shows a flow chart of a data processing method of an embodiment of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments that would be apparent to one of ordinary skill in the art without the benefit of this disclosure are within the scope of this disclosure. In the following description, some specific embodiments are for descriptive purposes only and should not be construed as limiting the disclosure in any way, but are merely examples of embodiments of the disclosure. Conventional structures or constructions will be omitted when they may cause confusion in understanding the present disclosure. It should be noted that the shapes and dimensions of the various components in the figures do not reflect the actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in the embodiments of the present disclosure should be in a general sense understood by those skilled in the art. The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

Furthermore, in the description of embodiments of the present disclosure, the term "connected to" or "connected to" may refer to two components being directly connected, or may refer to two components being connected via one or more other components in an electrical connection or electrical coupling.

Hereinafter, various embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Note that in the drawings, the same reference numerals are given to constituent parts having substantially the same or similar structures and functions, and repeated description thereof will be omitted.

Fig. 1 shows a schematic diagram of a handshake circuit according to an embodiment of the present disclosure. Fig. 1 shows a schematic configuration of a handshaking circuit including 1 control sub-circuit and 1 filtering sub-circuit.

As shown in fig. 1, the handshaking circuit 100 includes a control sub-circuit 101 and a filter sub-circuit 102, the control sub-circuit 101 being electrically connected to the filter sub-circuit 102.

For example, handshaking circuit 100 may be a handshaking core (handshaking core) and filtering sub-circuit 102 may be an intellectual property core (Intellectual Property core, IP core). Both the handshake core and the IP core are portable circuit modules.

In the embodiment of the present disclosure, the control sub-circuit 101 receives the destination preparation signal dest_rdy and the source request signal src_vld, and outputs the source flag signal srcflag according to the destination preparation signal dest_rdy and the source request signal src_vld.

The filter sub-circuit 102 receives the source flag signal srcflag from the control sub-circuit 101, receives a plurality of source data src_data based on the source flag signal srcflag in a plurality of periods, and performs a filter operation on the plurality of source data to obtain the destination data dest_data and outputs the destination data dest_data if it is determined that the number of the plurality of source data src_data satisfies a preset condition.

For example, the plurality of source data src_data may include a plurality of frames of image data to be processed. The multi-frame image data may be input to the filter sub-circuit 102 in the form of three primary color (RGB) data, and the filter sub-circuit 102 performs a filter operation on the input RGB data and outputs the operation result.

For example, the source flag signal src_flag is related to the source data src_data. For example, when it is determined that the level of the source flag signal src_data is an active level (e.g., high level), the input source data src_data is active. The source flag signal srcflag indicates the time at which the source data was received by the filter sub-circuit 102.

For example, in a case where the level of the source flag signal srcfiag is determined to be an active level in a plurality of periods, the filter sub-circuit 102 may receive the source data src_data based on the source flag signal srcfiag. For example, in the 1 st period, when the level of the source flag signal srcfiag is an active level (high level), the filter sub-circuit 102 may receive the 1 st source data src_data based on the source flag signal srcfiag. In the 2 nd period, when the level of the source flag signal srcflag has no active level (low level), the filter sub-circuit 102 either does not receive the source data or does not receive the source data based on the 2 nd source data src_data received by the source flag signal srcfiag. The filter sub-circuit 102 may receive a plurality of source data src_data based on the source flag signal srcfiag when the levels of the source flag signal srcfiag are all active levels for a plurality of consecutive periods.

The source request signal src_vld may be a signal from a circuit of a previous stage of the control sub-circuit 101. Based on the source request signal src_vld, the control sub-circuit 101 may control the filter sub-circuit 102 to receive the source data src_data to implement the precursor mode. The previous stage circuit of the control sub-circuit 101 may have a similar structure to the control sub-circuit 101, or may be a data input terminal externally connected to the control sub-circuit 101.

The destination ready signal dest_rdy may be a signal from a circuit of a subsequent stage of the control sub-circuit 101. Based on the destination ready signal dest_rdy, the control sub-circuit 101 may control the filter sub-circuit 102 to output the destination data dest_data to implement the postdrive mode. The latter circuit of the control sub-circuit 101 may have a similar structure to the control sub-circuit 101, or may be a data output terminal externally connected to the control sub-circuit 101.

In the disclosed embodiment, the Filter sub-circuit 102 may be a Filter IP core. In the operation process, the operation object of the filter IP core is a plurality of data. For example, in one cycle, the filter sub-circuit 102 may receive one source data, and in a consecutive plurality of cycles, the filter sub-circuit 102 may continuously receive a plurality of source data. When the filtering sub-circuit 102 performs an operation with the source data received in the current period as the current operation point, the operation object may include the source data received in the current period, the source data received before the current period, and the source data received after the current period. Therefore, for the source data received in any period, the source data is operated after a certain number of periods are delayed, and the operation result is delayed to be output.

For example, the number of source data received before the current period and the number of source data received after the current period may be determined according to actual operational requirements. For example, the number of source data received before the current period may be denoted front tap, the number of source data received after the current period may be denoted back tap, and the preset condition may be that the number of source data is front tap+back tap+1.

For example, the preset condition may be that the number of source data included in the operand of the filter sub-circuit 102 is 5, where the preset front tap is 2 and the preset back tap is 2. At this time, the operation time of the current operation point source data is delayed by two cycles from the reception time of the current operation point source data, and the output time of the operation result of the current operation point source data is also delayed by two cycles from the reception time of the current operation point source data.

According to the embodiment of the disclosure, the signals received by the control sub-circuit 101 are designed, so that the control sub-circuit 101 and the filtering sub-circuit 102 can process and transmit data only under the control of receiving the signals from the previous stage circuit and/or the next stage circuit, thereby realizing a precursor mode and/or a postamble mode of a data processing process and improving portability of the control sub-circuit 101 and the filtering sub-circuit 102. In addition, the handshaking circuit provided by the present disclosure realizes data transmission only through the control sub-circuit 101 and the filtering sub-circuit 102, so that the complexity and area of the circuit can be reduced.

The control sub-circuit 101 receives the destination preparation signal dest_rdy having an active level and the source request signal src_vld having an active level, and outputs the source preparation signal src_rdy having an active level according to the destination preparation signal dest_rdy. The source flag signal srcflag having an active level is output according to the source request signal src_vld and the source preparation signal src_rdy.

For example, the control sub-circuit 101 receives a source request signal src_vld from a previous stage control sub-circuit. In the case where the level of the source request signal src_vld is determined to be an active level (high level), the control sub-circuit 101 performs a logic operation on the source request signal src_vld, and can obtain the destination request signal dest_vld having an active level.

The control sub-circuit 101 also receives a destination ready signal dest_rdy from a control sub-circuit of a subsequent stage. When the level of the destination request signal dest_vld and the destination preparation signal dest_rdy is the active level (high level), the control sub-circuit 101 performs a logic operation on the destination request signal dest_vld and the destination preparation signal dest_rdy, and can obtain the source preparation signal src_rdy having the active level.

When the source preparation signal src_rdy and the source request signal src_vld are at the active level (high level), the control sub-circuit 101 performs a logic operation on the source preparation signal src_rdy and the source request signal src_vld, and can obtain the source flag signal srcflag having the active level.

For example, the filter sub-circuit 102 may continue to receive the source flag signal for a plurality of periods. The level of the source flag signal srcflag received in a plurality of periods may be toggled between a high level and a low level. For example, the level of the source flag signal srcflag may jump according to the levels of the source preparation signal src_rdy and the source request signal src_vld.

In the embodiment of the disclosure, the control sub-circuit may control the corresponding filtering sub-circuit to perform data operation under the control of signals from the previous stage control sub-circuit and the next stage control sub-circuit. Correspondingly, the filter sub-circuit receives the metadata from the previous stage filter sub-circuit under the control of the source flag signal srcflag from the corresponding control sub-circuit, thereby realizing the precursor/postdriver mode.

In the embodiment of the present disclosure, the control sub-circuit 101 outputs the enable signal filter_den according to the destination preparation signal dest_rdy and the source request signal src_vld for a preset number of periods. The filtering sub-circuit 102 receives the enable signal filter_den, performs a filtering operation on the plurality of source data based on the enable signal filter_den, obtains destination data, and outputs the destination data.

For example, the preset number may be associated with a preset back tap. In the case where the preset back tap is determined to be 2, the preset number may be 1+2=3. For example, in 3 periods, the 1 st period is taken as the current period, the source data received in the 1 st period is taken as the current operation point, and the source data received in the 2 nd and 3 rd periods are taken as 2 source data received after the current period. At this time, the number of source data received by the filtering sub-circuit 102 satisfies the preset back tap, and under the condition that the preset front tap is 0, the filtering sub-circuit 102 may perform a filtering operation on the received 3 source data. In the case where the preset front tap is M, the filter sub-circuit 102 may multiplex the source data received in the 1 st period M times based on the start flag signal firstflag from the control sub-circuit 101 to perform the filter operation on 3+M source data.

For example, in each of 3 periods, the control sub-circuit 101 receives the ready signal dest_rdy and the source request signal src_vld having an active level (e.g., a high level), and may output the source flag signal srcflag having an active level. In this case, the filter sub-circuit 102 may receive valid source data src_data in each period. When it is determined that the control sub-circuit 101 receives the preparation signal dest and the source request signal having an active level (e.g., high level) 3 times, it can be considered that the filtering sub-circuit 102 receives 3 active source data src_data. At this time, the control sub-circuit 101 may output the enable signal filter_den having an active level to the filter sub-circuit 102.

For example, the control sub-circuit 101 may also determine the permission signal filter_den according to the source flag signal srcflag and the backtap of the current operation point source data. For example, in the case where the source flag signal srcflag is determined to be at an active level and the back tap of the current operation point source data is greater than or equal to the preset back tap, the back tap of the current operation point source data received by the filter sub-circuit 102 satisfies the preset back tap, and at this time, the control sub-circuit 101 may output the enable signal filter_den having an active level to the filter sub-circuit 102, so that the filter sub-circuit 102 may perform a data operation on the received source data based on the enable signal filter_den having an active level.

In the embodiment of the disclosure, in the L-th period, when the last source data (L-th source data, L is a positive integer) is input to the filter sub-circuit, the back tap of the L-th source data is 0, and the source data has been all input. At this time, the filtering sub-circuit 102 may multiplex the L-th source data multiple times based on the last flag signal lastflag from the control sub-circuit 101, so that the back tap of the L-th source data satisfies the preset back tap.

In the disclosed embodiments, the source flag signal srcflag may indicate the time at which the source data was received by the filter subcircuit 102. The enable signal filter _ den may indicate the moment at which the filtering sub-circuit 102 starts filtering operations on the received plurality of source data. The start flag signal first flag may indicate multiplexing of the 1 st source data by the filter sub-circuit 102, and the end flag signal lastflag may indicate multiplexing of the L-th source data by the filter sub-circuit 102. The transmission and operation of the source data are respectively controlled by the source flag signal srcflag and the permission signal filter_den, and the multiplexing of the source data is respectively controlled by the start flag signal first flag and the end flag signal lasttflag, so that the dependence on an additional hardware structure can be reduced, and the portability of the control sub-circuit 101 and the filtering sub-circuit 102 can be improved.

In the embodiment of the present disclosure, the control sub-circuit 101 receives the destination preparation signal dest_rdy, and may output the source preparation signal src_rdy according to the destination preparation signal dest_rdy, so that the previous stage circuit of the filtering sub-circuit 102 confirms that the filtering sub-circuit 102 is in a state in which it can receive data. The control sub-circuit 101 receives the source request signal src_vld and the source preparation signal src_rdy, and outputs the destination request signal dest_vld according to the source request signal src_vld and the source preparation signal src_rdy, so that the latter stage circuit of the filter sub-circuit 102 can be made to confirm that the filter sub-circuit 102 is in a state in which it can transmit data, which enables the control sub-circuit 101 and the filter sub-circuit 102 to perform data processing and data transfer with the former stage circuit and the latter stage circuit based on signals from the former stage circuit and the latter stage circuit.

Fig. 2 shows a schematic diagram of a handshake circuit according to another embodiment of the present disclosure.

As shown in fig. 2, handshaking circuit 200 includes a cascade of R control sub-circuits 201 and a cascade of R filter sub-circuits 202, R being a positive integer.

The R control sub-circuits 201 comprise control sub-circuits 1, …, control sub-circuits R, …, control sub-circuits R, r=2, …, R-1. The R filter sub-circuits 202 include filter sub-circuits 1, …, filter sub-circuits R, …, and filter sub-circuit R. Each control sub-circuit is electrically connected with the corresponding filter sub-circuit, and the control sub-circuits 1, …, R, … and R are respectively in one-to-one correspondence with the filter sub-circuits 1, … and R, …, and the control sub-circuits 1, …, R, … and R are respectively electrically connected with the filter sub-circuits 1, … and R, ….

The control sub-circuits 1, …, R, …, R are all similar to the control sub-circuit 101. The filter subcircuits 1, …, R, … are all similar to the filter subcircuit 102. For brevity, this disclosure is not repeated here.

For example, the cascaded R control sub-circuits 201 may be cascaded R handshake cores, and the cascaded R filter sub-circuits 202 may be cascaded R IP cores. For example, the data input terminal 210 is connected to the control sub-circuit 1 and the filter sub-circuit 1, and the data input terminal 210 may be a previous stage circuit of the control sub-circuit 1 and the filter sub-circuit 1. The data output terminal 220 is connected to the control sub-circuit R and the filter sub-circuit R, and the data output terminal 220 may be a circuit of a subsequent stage of the control sub-circuit R and the filter sub-circuit R.

In the disclosed embodiment, the source ready signal src_rdy and the source request signal src_vld are a set of handshake signals, and the destination ready signal dest rdy and the destination request signal dest_vld are a set of handshake signals. The handshake signal is a discontinuous signal. For example, the source ready signal src_rdyr sent by the control sub-circuit r is the destination ready signal dest_rdyr-1 received by the control sub-circuit r-1. The destination request signal dest_vldr sent by the control sub-circuit r is the source request signal src_vldr+1 received by the control sub-circuit r+1. The destination data dest_data r sent by the filter sub-circuit r is the source data src_datar+1 received by the filter sub-circuit r+1.

In the disclosed embodiment, the control sub-circuit 1 may receive a source preparation signal src_rdy2 (destination preparation signal dest_rdyl) from the control sub-circuit 2 and a source request signal src_vldl from the outside (e.g., the data input terminal 210), and output a source flag signal srcflag according to the source preparation signal src_rdy2 and the source request signal src_vldl.

In a plurality of periods, the filter sub-circuit 1 receives a source flag signal srcflag from the control sub-circuit l, receives a plurality of source data src_datl based on the source flag signal srcflag, and performs a filter operation on the plurality of source data src_datl to obtain target data dest_data1 and outputs the target data dest_datl to the filter sub-circuit 2 when it is determined that the number of the source data src_datl satisfies a preset condition.

The control sub-circuit R receives a destination preparation signal dest_rdyr from the outside (e.g., the data output terminal 220) and a destination request signal dest_vlr-1 (source request signal src_vlr) from the control sub-circuit R-1, and outputs a source flag signal srcflag according to the destination preparation signal dest_rdyr and the destination request signal dest_vlr-1.

In a plurality of periods, the filter sub-circuit R receives a source flag signal srcflag, receives a plurality of source data src_data R from the filter sub-circuit R-1 based on the source flag signal srcflag, and performs filter operation on the plurality of source data src_data R to obtain target data dest_data R and outputs the target data dest_dataR under the condition that the number of the plurality of source data src_data R is determined to meet a preset condition.

The destination ready signal dest_rdy and the destination request signal dest_vld generated by the next-stage control sub-circuit can drive the previous-stage control sub-circuit to send handshake signals according to the level state, and drive the previous-stage filtering sub-circuit to process the received source data.

For example, when the level of the source preparation signal src_rdy1 outputted by the control sub-circuit 1 is an active level (e.g., a high level), the source preparation signal src_rdy1 instructs the control sub-circuit 1 to inform the data input terminal 210 that the filtering sub-circuit 1 is in a state ready to receive data. When the level of the source request signal src_vld1 received by the control sub-circuit 1 from the data input terminal 210 is an active level (e.g., a high level), the source request signal src_vld1 instructs the data input terminal 210 to inform the control sub-circuit 1 that the data input terminal 210 requests to transmit source data to the filtering sub-circuit 1.

When the level of the source preparation signal src_rdy2 from the filter sub-circuit 2 received by the control sub-circuit 1 is an active level (e.g., a high level), the source preparation signal src_rdy2 instructs the control sub-circuit 2 to notify the control sub-circuit 1 that the filter sub-circuit 2 is in a state ready to receive data from the filter sub-circuit 1. When the level of the destination request signal dest_vld1 transmitted by the control sub-circuit 1 is an active level (for example, a high level), the destination request signal dest_vldl instructs the control sub-circuit 1 to inform the control sub-circuit 2, and the filter sub-circuit 1 requests transmission of data to the filter sub-circuit 2.

When it is determined that the level of the source preparation signal src_rdyl and the source request signal src_vld1 is high, the level of the source flag signal srcflag transmitted by the control sub-circuit 1 to the filter sub-circuit 1 is also high, and the source data src_data1 received by the filter sub-circuit 1 from the data input terminal 210 is valid data. When it is determined that the level of the destination preparation signal dest_rdy1 and the destination request signal dest_v1dl is high, the destination data dest_data output from the filter sub-circuit 1 is valid data at this time. Upon determining that the level of the enable signal filter_den is high, the filter sub-circuit 1 circuit processes the source data src_data1 from the data input 210.

From the control sub-circuit 1, a request signal having an active level may be sequentially transmitted to the next-stage control sub-circuit according to the connection relationship between the R control sub-circuits 201 cascaded in the handshake circuit 200.

When the filter sub-circuit 1 transmits the operation result dest_data1 to the filter sub-circuit 2, the control sub-circuit 1 transmits the destination request signal dest_vld1 having an active level to the control sub-circuit 2. Under the control of the destination request signal dest_vld1 (source request signal srg _vld2) having an active level, each stage control sub-circuit transmits a source request signal having an active level to the subsequent stage control sub-circuit.

Under the control of the source request signal with an active level and the source preparation signal with an active level, each stage of control sub-circuit transmits the source flag signal srcflag with an active level and the enable signal filter_den to the electrically connected filter sub-circuits, so that each stage of filter sub-circuits transmits the operation result to the subsequent stage of filter sub-circuits, thereby realizing the precursor mode under the control of the signals inside the handshaking circuit 200.

In the embodiment of the present disclosure, in case that it is determined that the data output terminal 220 is in the idle state, the data output terminal 220 transmits the destination ready signal dest_rdyr to the control sub-circuit R, which receives the destination ready signal dest_rdyr, and under the direction of the destination ready signal dest_rdyr, the ready signal src_rdyr having an active level may be generated. The control sub-circuit R outputs a source preparation signal src_rdyr having an active level to the control sub-circuit R-1, the source preparation signal src_rdyr indicating that the control sub-circuit R informs the control sub-circuit r_1 that the filter sub-circuit R is in a state ready to receive data from the filter sub-circuit R-1.

According to the connection relationship between the R control sub-circuits 201 cascaded in the handshake circuit 200, when the data output terminal 220 is in the idle state, the source preparation signal (destination source preparation signal) having an active level may be sequentially transmitted from the control sub-circuit R to the previous stage control sub-circuit, whereby the control sub-circuit 1 operates on the destination source preparation signal dest_rdy1 having an active level, and may generate the source preparation signal src_rdy1 having an active level.

The filter sub-circuit 1 outputs a source preparation signal src_rdy1 having an active level to the external data input terminal 210, causes the data input terminal 210, which is a preceding stage circuit, to confirm that the filter sub-circuit 1 is in a state where it can receive data, and transmits source data to the filter sub-circuit 1.

Under the control of the source preparation signal src_rdy1 having an active level and the source request signal src_vld1 having an active level from the data input terminal 201, each stage of control sub-circuit transmits the source flag signal src flag having an active level and the enable signal filter_den to the electrically connected filter sub-circuits, so that each stage of filter sub-circuits transmits the operation result to the subsequent stage of filter sub-circuits, thereby implementing the back drive mode under the signal control inside the handshake circuit 200.

In the embodiment of the present disclosure, in the case where it is determined that the external data output terminal 220 initiates the data read request, the control sub-circuit R receives the destination preparation signal dest_rdyr having an active level, and outputs the source preparation signal src_rdv R having an active level according to the destination preparation signal dest_rdy R.

For example, after the data output terminal 220 as the subsequent stage circuit issues a data read request to the filter sub-circuit R, the control sub-circuit R operates on the destination preparation signal dest_rdyr having an active level, and may generate the source preparation signal src_rdyr having an active level.

According to the connection relationship between the R control sub-circuits 201 cascaded in the handshake circuit 200, a source preparation signal having an active level is sequentially transmitted from the control sub-circuit R to the previous stage control sub-circuit. Thus, the source preparation signal src_rdy having an active level is outputted to the data input terminal 210 externally connected to the filter sub-circuit 1, and the data input terminal 210 serving as the previous stage circuit confirms that the filter sub-circuit 1 is in a state capable of receiving data, and transmits data to the filter sub-circuit 1, thereby realizing the back drive mode.

In the embodiment of the present disclosure, after the external data output 220 initiates the data read request, the data transmission and processing procedure in the handshake circuit 200 is similar to the data transmission and processing procedure in the handshake circuit 200 when the data output is in the idle state. This disclosure is not repeated for brevity.

In the embodiment of the present disclosure, in the case where it is determined that the source preparation signal src_rdyl has an active level, the control sub-circuit 1 is in an operating state, and at this time, the control sub-circuit 1 sends the source preparation signal src_rdy1 to the data input terminal to be also at the active level. The control sub-circuit 1 also accepts the source request signal src_vld1 from the data input 210, and in case it is determined that the source request signal src_vld1 has an active level, the data input 210 informs the control sub-circuit 1 that data can be sent.

When it is determined that the source preparation signal src_rdy1 and the source request signal src_vld1 are both at the valid level, the control sub-circuit 1 operates on the source preparation signal src_rdy1 and the source request signal src_vld1 to obtain a source flag signal srcflag having the valid level.

The filter sub-circuit 1 receives a source flag signal srcflag having an active level and receives source data src_data from the data input terminal 210 under the direction of the source flag signal srcflag. In the case where it is determined that the back tap of the source data as the current operation point satisfies the preset back tap in a plurality of periods, when the source flag signal srcflag is at the active level, the control sub-circuit 1 may also output the enable signal filter_den having the active level, at which time the filter sub-circuit 1 receives the plurality of source data src_data. The filter sub-circuit 1 receives the enable signal filter_den, starts filtering operation on the plurality of source data under the instruction of the enable signal filter_den, and transmits the operation result to the data filter sub-circuit 2.

In the embodiment of the present disclosure, for the control sub-circuit 1 and the filter sub-circuit 1, when it is determined that the back tap of the source data as the current operation point satisfies the preset back tap, the front tap is smaller than the preset front tap, the filter sub-circuit 1 may multiplex the source data received in the 1 st period based on the start flag signal first flag from the control sub-circuit 1, so that the front tap of the source data of the current operation point satisfies the preset front tap.

In the case where it is determined that the front of the source data as the current operation point satisfies the preset front, and the back is smaller than the preset back, the filter sub-circuit 1 may multiplex the last source data received based on the last flag signal lastflag from the control sub-circuit 1 so that the back of the source data of the current operation point satisfies the preset back.

According to the embodiment of the disclosure, in the cascaded R control sub-circuits of the handshake circuit, continuous transmission of the preparation signal with an active level and the request signal with an active level is realized. Under the control of signals with active levels inside the handshake circuit 200 without control signals generated by SRAM or GCK, the R filter sub-circuits can process and transmit data in sequence, reducing the complexity of the handshake circuit 200. For example, when the next stage filter sub-circuit sends a data request to the previous stage filter sub-circuit or the data output is in an idle state, the control sub-circuit may generate a signal having an active level (e.g., a high level) to implement the precursor mode and the post-driver mode of the handshake circuit. In addition, the filtering sub-circuit 202 may multiplex the received first source data and the last source data based on the start flag signal first flag and the end flag signal lastflag, so that the source data in the filtering sub-circuit 202 continues to perform the data shift action, and the throughput of the handshake circuit 200 is improved.

Fig. 3 shows a schematic diagram of a handshake circuit according to another embodiment of the present disclosure

As shown in fig. 3, handshaking circuit 300 includes a control sub-circuit 301 and a filtering sub-circuit 302. The control sub-circuit 301 and the filter sub-circuit 302 are similar to the control sub-circuit 101 and the filter sub-circuit 102, respectively, shown in fig. 1, and similar parts are not repeated here for the sake of brevity of this disclosure.

In the disclosed embodiment, the control sub-circuit 301 includes a control unit 311 and at least one transmission unit 312. Fig. 3 shows only one transmission unit by way of example, and the control unit 311 is electrically connected to at least one transmission unit 312.

In the disclosed embodiment, the transmission unit 312 receives the destination ready signal dest_rdy. The control unit 311 receives the source request signal src_vld and the destination source signal dest_rdy from the transmission unit 312. The control unit 311 outputs a source flag signal srcflag according to the destination preparation signal dest_rdy and the source request signal src_vld.

In the embodiment of the present disclosure, in the operation process, the operation object of the filter sub-circuit 302 is a plurality of data. For source data received in any period, after a certain number of periods, the filter sub-circuit 302 operates on the source data, and delays outputting the operation result.

For example, the preset back tap is 1, the preset front tap is 1, and the preset condition may be that the number of the plurality of source data is front tap+back tap+1=3. In this case, the operation timing of the current operation point source data is delayed by 1 period from the reception timing of the current operation point source data, and the output timing of the operation result of the current operation point source data is also delayed by 1 period from the reception timing of the current operation point source data.

For example, in the 1 st period, the source flag signal srcflag output by the control unit 311 has an active level based on the source preparation signal src_rdy and the source request signal src_vld having active levels. The filter sub-circuit 302 receives the 1 st source data src_datal under control of the source flag signal srcflag having an active level. At this time, the 1 st source data is smaller than the preset back tap, and the filtering sub-circuit 302 does not perform data operation.

In the 2 nd period, the filter sub-circuit 302 receives the 2 nd source data src_data2 under the control of the source flag signal srcflag having an active level. The back tap of the 1 st source data at this time is equal to the preset back tap, in which case the start source flag signal firstflag output from the control unit 311 to the filter sub-circuit 302 has an active level. Under the control of the start source flag signal first having an active level, the filter sub-circuit 302 copies the 1 st source data src_data1 1 times when the front tap of the 1 st source data is equal to the preset front tap.

In the 2 nd cycle, the filter sub-circuit 302 may perform a data operation to output the destination data dest_data.

In the embodiment of the present disclosure, in the case where the timing at which the filter sub-circuit 302 outputs the destination data dest_data is different from the timing at which the control unit 311 outputs the destination request signal dest_vld, the control unit 311 is connected in series with at least one transmission unit 312 such that the timing at which the control sub-circuit 301 outputs the destination request signal dest_vld to the subsequent stage control sub-circuit is synchronized with the timing at which the filter sub-circuit 302 outputs the source data to the subsequent stage filter sub-circuit.

For example, in the case where the preset back tap is 1, the timing at which the control unit 311 outputs the destination request signal dest_vld may be delayed by one cycle from the timing at which the filter sub-circuit 302 outputs the source data to the subsequent stage filter sub-circuit, so that a transmission unit 312 may be connected in series to the control unit 311, the transmission unit 312 being electrically connected to the subsequent stage control sub-circuit, which synchronizes the timing at which the transmission unit 312 outputs the destination request signal dest_vld to the subsequent stage control sub-circuit with the timing at which the filter sub-circuit 302 outputs the source data to the subsequent stage filter sub-circuit.

Fig. 4A shows a schematic diagram of a handshake circuit according to another embodiment of the present disclosure.

As shown in fig. 4A, handshaking circuit 400 includes a control sub-circuit 401 and a filtering sub-circuit 402. The control sub-circuit 401 and the filtering sub-circuit 402 are similar to the control sub-circuit 101 and the filtering sub-circuit 102, respectively, shown in fig. 1, and similar parts are not repeated here for the sake of brevity of this disclosure.

In the embodiment of the present disclosure, the control sub-circuit 401 includes a control unit 411, a transmission unit 412, and a transmission unit 413. The control unit 411 is similar to the control unit 311 shown in fig. 3, and the transmission unit 412 and the transmission unit 413 are similar to the transmission unit 312 shown in fig. 3, and similar parts are not repeated here for brevity of this disclosure.

In the embodiment of the present disclosure, the filtering sub-circuit 402 includes a plurality of first flip-flops 421, a first data operation unit 422, a plurality of second flip-flops 423, and a second data operation unit 424, i being a positive integer.

The plurality of first flip-flops 421 are cascaded, and the plurality of second flip-flops 423 are cascaded. The plurality of first flip-flops 421 are electrically connected to the output terminals of the first data operation unit 422, the plurality of second flip-flops 423 are electrically connected to the output terminals of the first data operation unit 422, and the plurality of second flip-flops 423 are electrically connected to the input terminals of the second data operation unit 424.

For example, the cascade of the plurality of first flip-flops 421 may include a first flip-flop d1_1, a first flip-flop d1_2, a first flip-flop d1_3, and a first flip-flop d1_4, the cascade of the i+1 plurality of second flip-flops 423 may include a second flip-flop d2_1, a second flip-flop d2_2, a second flip-flop d2_3, a second flip-flop d2_4, and a second flip-flop d2_5, and the plurality of second flip-flops 423 may be flip-flops that operate in parallel. The number of first and second flip-flops 421 and 423 shown in fig. 4 is merely illustrative.

In the embodiment of the present disclosure, the preset condition is that the number of the plurality of source data is n+m, back tap=n-1, front tap=m.

For example, the plurality of first flip-flops 421 in cascade receive the source flag signal srcflag, and N source data are received based on the source flag signal srcflag in N periods. For example, the level of the source flag signal srcflag is an active level (high level) for N periods. At this time, the back tap of the 1 st source data received by the plurality of first flip-flops 421 in the 1 st period is equal to the preset back tap, and the level of the start flag signal first flag received by the first data operation unit 422 is an active level (high level). The 1 st source data is source data received by the plurality of first flip-flops 421 in the 1 st period of the N periods among the N source data.

In the nth period, the first data operation unit 422 performs M copies of the 1 st source data based on the start flag signal first flag to obtain M1 st source data, and outputs N source data and M1 st source data. The cascaded plurality of second flip-flops 423 receives N source data and M1 st source data. The second data operation unit 424 receives the N source data and the M1 st source data from the cascaded second flip-flops 423, performs an operation on the N source data and the M1 st source data to obtain destination data, and outputs destination data dest_data.

For example, in the N period, in the case where the back tap of the 1 st source data is equal to the preset back tap and the source flag signal srcflag is at the active level, the level of the enable signal filter_den received by the second data operation unit 424 has the active level (high level). Based on the permission signal filter_den, the second data operation unit 424 performs an operation on the N source data and the M1 st source data to obtain destination data, and outputs the destination data dest_data.

In any period, in the case where it is determined that the source preparation signal sre _rdy and the source request signal sre _vld both have an active level, the control sub-circuit 401 outputs the source flag signal srcflag having an active level. The plurality of first flip-flops 421 receive the source data src_data under the indication of the source flag signal srcflag having an active level.

In the embodiment of the present disclosure, the number of the plurality of first flip-flops 421 and the number of the plurality of second flip-flops 423 are related to a preset condition. For example, when the preset condition is that the number of the plurality of source data is m+n, the filtering sub-circuit 402 may include I first flip-flops 421 and i+1 second flip-flops 423, where i+1=m+n, N is less than or equal to I, and M is less than or equal to I.

For example, the preset condition for the first data operation unit 422 to perform the filtering operation is that the number of input source data is 5, and the plurality of first flip-flops 421 may include 4 first flip-flops (first flip-flop d1_l, first flip-flop d1_2, first flip-flop d1_3, and first flip-flop d1_4), and the plurality of second flip-flops 423 may include 5 second flip-flops (second flip-flop d2_1, second flip-flop d2_2, second flip-flop d2_3, second flip-flop d2_4, and second flip-flop d1_5).

Within 5 periods, 5 source data are sequentially shifted into the plurality of first flip-flops 421. For example, in the 1 st period, the first data operation unit 422 may read the 1 st source data from the point a. In the 2 nd period, the 2 nd source data is input to the plurality of first flip-flops 421, which causes the 1 st source data to be moved forward, and the 1 st source data to be moved into the first flip-flop d1_1, at which time the first data operation unit 422 may read the 2 nd source data and the 1 st source data from the a-point and the B-point, respectively. In the 3 rd period, the 3 rd source data is input to the plurality of first flip-flops 421, which causes both the 1 st source data and the 2 nd source data to be moved forward, the 1 st source data to be moved into the first flip-flop d1_2, and the 2 nd source data to be written into the first flip-flop d1_1, and at this time, the first data operation unit 422 may read the 3 rd source data, the 2 nd source data, and the 1 st source data from the a point, the B point, and the C point, respectively. In the 4 th period, the 4 th source data is input to the plurality of first flip-flops 421, which causes the 1 st source data, the 2 nd source data, and the 3 rd source data to be sequentially moved forward, the 1 st source data to be moved into the first flip-flop d1_3, the 2 nd source data to be moved into the first flip-flop d1_2, and the 3 rd source data to be written into the first flip-flop d1_1, and at this time, the first data operation unit 422 may read the 4 th source data, the 3 rd source data, the 2 nd source data, and the 1 st source data from the a point, the B point, the C point, and the D point, respectively. In the 5 th period, the 5 th source data is input to the plurality of first flip-flops 421, which causes the 1 st source data, the 2 nd source data, the 3 rd source data, and the 4 th source data to be sequentially moved forward, the 1 st source data to be moved into the first flip-flop d1_4, the 2 nd source data to be moved into the first flip-flop d1_3, the 3 rd source data to be moved into the first flip-flop d1_2, and the 4 th source data to be written into the first flip-flop d1_1, at which time the first data operation unit 422 may read the 5 th source data, the 4 th source data, the 3 rd source data, the 2 nd source data, and the 1 st source data from the point a, the point B, the point C, the point D, and the point E, respectively.

In the 5 th period, the first data operation unit 422 receives the 5 th source data from the previous stage filtering sub-circuit, and acquires 4 source data input in the previous 4 periods from the 4 first flip-flops, and writes the 5 source data into the second flip-flop d2_1, the second flip-flop d2_2, the second flip-flop d2_3, the second flip-flop d2_4, and the second flip-flop d2_5, respectively.

In any period, in the case where it is determined that the source data to which the first flip-flop is written satisfies the preset front tap and the preset back tap, the control sub-circuit 401 outputs the enable signal filter_den having an active level. The second data operation unit 402 performs an operation on 5 source data under the instruction of the enable signal filter_den having an active level, to obtain the destination data dest_data.

For example, the preset back tap is 2, the preset front tap is 2, and the current operation point is the 3 rd source data. In the 3 rd period, the 1 st source data is stored in the first flip-flop d1_2, the 2 nd source data is stored in the first flip-flop d1_1, and the 3 rd source data is from the previous stage filtering sub-circuit. At this time, the back tap of the 3 rd source data is 0, and the front tap is 2. In the 5 th period, the 1 st source data is stored in the first trigger d1_4, the 2 nd source data is stored in the first trigger d1_3, the 3 rd source data is stored in the first trigger d1_2, the 4 th source data is stored in the first trigger D1-1, and the previous stage circuit transmits the 5 th source data, and at this time, the back tap of the 3 rd source data is 2, and the front tap is 2.

In 5 periods, in the case where the source preparation signal src_rdy and the source request signal src_ yld each have an active level, the control sub-circuit 401 outputs the source flag signal srcflag having an active level so that the wave filtering sub-circuit 402 can receive 5 source data.

In the 5 th period, the second data operation unit 424 performs operation on 5 source data in the 5 second flip-flops 423 under the instruction of the enable signal filter_den having an active level to obtain the destination data dest_data, where the destination data is the destination data corresponding to the 3 rd source data. The output timing of the destination data is delayed by 2 cycles from the timing of the corresponding source data input.

Fig. 4B shows a schematic diagram of source data input according to an embodiment of the present disclosure, and fig. 4C shows a schematic diagram of source data input according to another embodiment of the present disclosure. The process of inputting source data into the plurality of first flip-flops is schematically illustrated with reference to fig. 4A, 4B and 4C. Fig. 4B and 4C show that each column of data is source data that can be acquired from points a, B, C, D, and E shown in fig. 4A in a certain period T.

In the embodiment of the disclosure, when the back tap of the current operation point meets the preset back tap, the current operation point source data can be copied, so that the front tap of the current operation point meets the preset front tap.

In the embodiment of the present disclosure, the filter sub-circuit 402 shown in fig. 4A is an n+m tap filter IP core, the preset condition for performing data processing by the filter sub-circuit 402 is that the number of source data is n+m, N is a positive integer greater than 1, and M is a positive integer. The front tap is preset as M, and the back tap is preset as N-1. The preset front tap may be equal to the preset back tap by N-1, or may not be equal to the preset back tap. According to actual operation requirements, one tap between the preset front tap and the preset back tap can be determined to be zero.

The control sub-circuit 401 receives the destination preparation signal dest_rdy and the source request signal src_vld for N periods, and outputs the enable signal filter_den, the source flag signal, and the start flag signal fistflag according to the destination preparation signal dest_rdy and the source request signal src_vld.

The filter sub-circuit 402 receives the source flag signal srcflag for N periods and receives N source data based on the source flag signal srcflag.

In the nth period, the front tap of the 1 st source data is 0 and the back tap is N-1, and the start flag signal first flag received by the filter sub-circuit 402 has an active level (high level). Based on the start flag signal first flag, the filter sub-circuit 402 performs M copies of the 1 st source data to obtain M1 st source data, where the 1 st source data is source data received in the 1 st period of the N periods of the N source data.

After the copying of the 1 st source data is completed, the front tap of the 1 st source data is M, and the back tap is N-1. The level of the enable signal filter_den received by the filter sub-circuit 402 is an active level (high level), and based on the enable signal filter_den, a filter operation is performed on the N source data and the M1 st source data to obtain destination data, and the destination data is output.

For example, the filter sub-circuit 402 shown in fig. 4A is a 5tap filter IP core, and the preset condition for performing data processing by the filter sub-circuit 402 is that the number of source data is 5, the preset front tap is 2, and the preset back tap is 2. Since the preset back tap=2, the operation time of the current operation point source data is delayed by 2 periods compared to the reception time of the current operation point source data, and the output time of the operation result of the current operation point source data is also delayed by 2 periods compared to the reception time of the current operation point source data, the control sub-circuit 401 includes two transmission units, and the control unit 411 is connected in series with the transmission unit 412 and the transmission power supply 413.

As shown in fig. 4B, in the period T1, the control sub-circuit 401 receives the destination preparation signal dest_rdy having an active level and the source request signal src_vld having an active level, and the control sub-circuit has an active level according to the source flag signal srcflag output by the destination preparation signal dest_rdv and the source request signal src_vld. Under the direction of the source flag signal srcflag, source data 0 is written to the plurality of first flip-flops 421. The first data operation unit may acquire the source data 0 from the point a shown in fig. 4A. At this time, neither front tap nor back tap of the source data 0 satisfies the preset front tap nor the preset back tap, and the control unit 411 outputs the destination request signal dest_vld to the transmission unit 412.

In the period T2, under the instruction of the source flag signal srcflag having an active level, the source data 1 is written to the plurality of first flip-flops 421, the source data 0 is written to the first flip-flop d1_1, and the first data operation unit may acquire the source data 1 and the source data 0 from the points a and B shown in fig. 4A, respectively. At this time, neither front tap nor back tap of the source data 0 satisfies the preset front tap nor the preset back tap, and the transmission unit 412 outputs the destination request signal dest_vld to the transmission unit 413.

In the period T3, under the instruction of the source flag signal srcflag having an active level, the source data 2 is written to the plurality of first flip-flops 421, the source data 0 is moved to the first flip-flop d1_2, the source data 1 is written to the first flip-flop d1_1, and the first data operation unit may acquire the source data 2, the source data 1, and the source data 0 from the points a, B, and C shown in fig. 4A, respectively. At this time, the back tap of the source data 0 is 2, the front tap is 0, and the transmission unit 413 outputs the destination request signal dest_vld to the control sub-circuit of the subsequent stage.

The control sub-circuit 401 outputs the enable signal filter den and the start flag signal firstflag having active levels according to the destination preparation signal dest_rdy having active levels and the source request signal src_vld having active levels.

For example, the control sub-circuit 401 may be provided with a counter that records the number of periods in which the levels of the destination preparation signal dest_rdy and the source request signal src_vld received by the control sub-circuit 401 are at an active level (high level). For example, the counter may also record the front tap and the back tap of the current operation point, so that the control sub-circuit 401 may output the enable signal filter_den with an active level and the start flag signal first flag with an active level according to the front tap and the back tap of the current operation point recorded by the counter.

For example, in the case where the back tap is equal to the preset back tap and the front tap is smaller than the preset front tap, the start flag signal firstflag output by the control sub-circuit 401 has an active level.

As shown in fig. 4C, under the indication of the start flag signal first flag having an active level, the first data operation unit 422 may copy the source data 0 twice, to obtain two copy source data 0, and use the two copy source data 0 as the front map of the original source data 0, where the front map of the source data 0 is 2.

With the source data 0 as an operation point of the current period, the first data operation unit 422 writes 5 source data (21 000) into the second flip-flop d2_1, the second flip-flop d2_2, the second flip-flop d2_3, the second flip-flop d2_4, and the second flip-flop d2_5, respectively. Under the instruction of the enable signal filter_den having the active level, the second data operation unit 424 acquires 5 source data (2 1 00 0) from the second flip-flop d2_1, the second flip-flop d2_2, the second flip-flop d2_3, the second flip-flop d2_4, and the second flip-flop d2_5, performs operation on the 5 source data (2 1 00 0) to obtain destination data of the source data 0, and outputs the destination data of the source data 0 to the next stage of filter sub-circuit.

As shown in fig. 4B, at a period T4, under the indication of the source flag signal srcflag having an active level, the source data 3 is written to the plurality of first flip-flops 421, the source data 0 is moved to the first flip-flop d1_3, the data 1 is moved to the first flip-flop d1_2, the source data 2 is written to the first flip-flop d1_1, and the first data operation unit may acquire the source data 3, the source data 2, the source data 1, and the source data 0 from the points a, B, C, and D shown in fig. 4A, respectively. At this time, the back tap of the source data 1 is 2, and the front tap is 1. The enable signal filter_den and the start flag signal firstflag output from the control sub-circuit 401 have active levels.

As shown in fig. 4C, under the indication of the start flag signal first flag having an active level, the first data operation unit 422 may copy the source data 0 once, obtain 1 copy source data 0, and use the original source data 0 and 1 copy source data 0 as the front ttap of the source data 1, where the front ttap of the source data 1 is 2.

With the source data l as an operation point of the current period, the first data operation unit 422 writes 5 source data (321 00) into the second flip-flop d2_1, the second flip-flop d2_2, the second flip-flop d2_3, the second flip-flop d2_4, and the second flip-flop d2_5. Under the instruction of the enable signal filter_den having the active level, the second data operation unit 424 acquires 5 source data (321 00) from the second flip-flop d2_1, the second flip-flop d2_2, the second flip-flop d2_3, the second flip-flop d2_4, and the second flip-flop d2_5, and performs an operation on the 5 source data (321 00) to obtain destination data of the source data 1.

In the period T5, the source data 4 is written into the plurality of first flip-flops 421 under the instruction of the source flag signal srcflag having the active level, the source data 0 is moved to the first flip-flop d1_4, the data 1 is moved to the first flip-flop d1_3, the data 0 is moved to the first flip-flop d1_2, and the source data 4 is written into the first flip-flop d1_1, at which time the back tap of the source data 2 is 2 and the front tap is 2. The first data operation unit 422 may acquire source data 4, source data 3, source data 2, source data 1, and source data 0 from points a, B, C, D, and E shown in fig. 4A, respectively. The enable signal filter _ den output by the control sub-circuit 401 has an active level.

With the source data 2 as the operation point of the current period, the first data operation unit 422 may acquire 5 source data (4321 0) from the a, B, C, D, and E points shown in fig. 4A, and write the 5 source data into the second flip-flop d2_1, the second flip-flop d2_2, the second flip-flop d2_3, the second flip-flop d2_4, and the second flip-flop d2_5, respectively. Under the instruction of the enable signal filter_den having the active level, the second data operation unit 424 acquires 5 source data (4 321 0) from the second flip-flop d2_1, the second flip-flop d2_2, the second flip-flop d2_3, the second flip-flop d2_4, and the second flip-flop d2_5, and performs an operation on the 5 source data (4 321 0) to obtain destination data of the source data 2.

In the embodiment of the present disclosure, the number of the start flag signals first flag outputted by the control sub-circuit 401 is equal to the preset front tap. For example, the start flag signal first flag output by the control sub-circuit 401 may include first flag [0] and first flag [1]. For example, in period T3, first flag [0] has an active level (high level), first flag [1] has an inactive level (low level), and first flag [0] instructs filter sub-circuit 402 to copy source data 0 in first flip-flop d1_2. In the period T4, the first flag [0] has an inactive level (low level), the first flag [1] has an active level (high level), and the first flag [1] instructs the filter sub-circuit 402 to copy the source data 0 in the first flip-flop d1_3.

In the period T5 to T10, the source data in the first flip-flop d1_1 is sequentially removed, and the data in the first flip-flop D1 2, the first flip-flop D1 3, and the first flip-flop d1_4 are sequentially moved to the first flip-flop of the previous stage in the cascade. The source data 4, the source data 5, the source data 6, the source data 7, the source data 8 and the source data 9 are sequentially sent to the first trigger d1_1, and the front tap and the back tap of the current operation point source data 2, the current operation point source data 3, the current operation point source data 4, the current operation point source data 5, the current operation point source data 6 and the current operation point source data 7 respectively meet the preset front tap and the preset back tap.

In the period T5 to the period T10, after each input of the source data, an operation may be performed, and the destination data may be output, and the waiting state no longer exists in the filter sub-circuit 402, so that the filter sub-circuit realizes pipeline output. Wherein the filter sub-circuit 402 is in a wait state during periods T1 and T2.

In the period T11 and the period T12, the backtap of the current operation point source data 8 and the current operation point source data 9 do not satisfy the preset backtap.

In the embodiment of the present disclosure, the control sub-circuit 401 shown in fig. 4A also receives the configuration signal cfg and outputs the last flag signal lastflag based on the configuration signal cfg. The filter sub-circuit 402 receives the last flag signal lastflag and copies the L-th source data based on the last flag signal lastflag in the l+1th period, L being a positive integer. Based on the configuration signal cfg, the filter sub-circuit 402 may receive L source data in L periods, where the L-th source data is source data received by the filter sub-circuit 402 in the L-th period of the L periods.

For example, the first data operation unit 422 receives the last flag signal lastflag and copies the L-th source data based on the last flag signal in the l+1th period. Based on the configuration signal cfg, the cascaded first flip-flops receive L source data in L periods, and the L-th source data is the source data received in the L-th period in the L periods in the L source data.

For example, the configuration signals cfg include a width configuration signal cfg_width and a height configuration signal cfg_height. For example, the source data may be image data, and the width configuration signal cfg_width and the height configuration signal cfg_height may limit the width and height, respectively, of the image data that the filter sub-circuit 402 accumulates to be received. For example, the configuration signal cfg may be input from an external register or may be generated from an internal register of the control sub-circuit 401.

For example, the configuration signal cfg shown in fig. 4A is a width configuration signal cfg_width, which limits the maximum cumulative number of source data received by the filter sub-circuit to 10, where L is 10.

As shown in fig. 4B, in the period T10, the accumulated number of source data received by the filter sub-circuit 402 is 10. At period T11, the filter sub-circuit 402 no longer receives new source data, as indicated by the configuration signal cfg having an active level.

In the disclosed embodiment, based on the configuration signal cfg, the control sub-circuit 401 determines that the last source data 9 in the period T10 is input to the filter sub-circuit 402. Since the filtering sub-circuit 402 still needs to continue to perform data operation, the source preparation signal src_rdy output by the control sub-circuit 401 still remains in a high level state in a subsequent period, so that no idle trigger exists on the datapath of the whole data transmission channel, and high throughput of the circuit is realized.

In this case, based on the source preparation signal src_rdy having an active level, the control sub-circuit 401 outputs the source flag signal src flag also having an active level. The source data in the first plurality of triggers still moves from stage to stage. The source data 6 is moved to the first flip-flop d1_4, the source data 7 is moved to the first flip-flop d1_3, the source data 8 is written to the first flip-flop d1_2, the source data 9 is moved to the first flip-flop d1_1, and the first data operation unit 422 may acquire the source data 9, the source data 8, the source data 7, and the source data 6 from points B, C, D, and E shown in fig. 4A, respectively. At this time, the backstatap of the current operation point source data 8 is 1, and the front is 2.

In the case where it is determined that the configuration signal cfg indicates that the filter sub-circuit 402 integrates the number of received source data to the maximum value, the last flag signal lastflag output by the control sub-circuit 401 has an active level. For example, when the configuration signal cfg indicates that the number of source data accumulated and received by the filter sub-circuit 402 reaches a maximum value, the last flag signal lastflag output by the control sub-circuit 401 has an active level in a case where the front tap is equal to the preset front tap and the back tap is smaller than the preset back tap.

As shown in fig. 4C, under the instruction of the last flag signal lastflag having an active level, the first data operation unit 422 may copy the source data 9 once, obtain 1 copy source data 9, and use 1 copy source data 9 and the original source data 9 as the back tap of the source data 8, where the back tap of the source data 8 is 2.

With the source data 8 as the operation point of the current period, the first data operation unit 422 writes 5 source data (99876) into the second flip-flop d2_1, the second flip-flop d2_2, the second flip-flop d2_3, the second flip-flop d2_4, and the second flip-flop d2_5, respectively.

The control sub-circuit 401 outputs the enable signal filter_den having an active level based on the last flag signal lastflag. For example, in the case where it is determined that the output last flag signal lastflag has an active level, the filter sub-circuit 402 is considered to be still in an operating state, and the enable signal filter_den output by the control sub-circuit 401 still has an active level, so that the filter sub-circuit 402 continues to perform data operation.

Under the instruction of the enable signal filter_den having the active level, the second data operation unit 424 acquires 5 source data (99876) from the second flip-flop d2_1, the second flip-flop d2_2, the second flip-flop d2_3, the second flip-flop d2_4, and the second flip-flop d2_5, and performs an operation on the 5 source data (99876) to obtain destination data of the source data 8.

At period T12, the filter sub-circuit 402 no longer receives new source data, as indicated by the configuration signal cfg having an active level. Based on the source preparation signal src_rdy having an active level, the control sub-circuit 401 outputs a source flag signal srcflag also having an active level. The source data in the first plurality of triggers still moves from stage to stage. The source data 7 is moved to the first flip-flop d1_4, the source data 8 is moved to the first flip-flop d1_3, and the source data 9 is written to the first flip-flop d1_2.

The first data operation unit 422 may acquire the source data 9, the source data 8, and the source data 7 from points C, D, and E shown in fig. 4A, respectively. At this time, the back tap of the current operation point source data 9 is 0, and the front tap is 2. The control sub-circuit 401 may output an end flag signal lastflag having an active level based on the configuration signal cfg.

As shown in fig. 4C, the first data operation unit 422 may copy the source data 9 twice under the indication of the last flag signal lastflag having an active level, to obtain two copy source data 9, and use the two copy source data 9 as the backup of the original source data 9, where the backup of the source data 9 is 2.

With the source data 9 as the operation point of the current cycle, the first data operation unit 422 writes 5 source data (99987) into the second flip-flop d2_1, the second flip-flop d2_2, the second flip-flop d2_3, the second flip-flop d2_4, and the second flip-flop d2_5, respectively.

Under the instruction of the enable signal filter_den having the active level, the second data operation unit 424 acquires 5 source data (99987) from the second flip-flop d2_1, the second flip-flop d2_2, the second flip-flop d2_3, the second flip-flop d2_4, and the second flip-flop d2_5, and performs an operation on the 5 source data (99987) to obtain destination data of the source data 9.

In the embodiment of the present disclosure, the number of the start flag signals lastflag outputted by the control sub-circuit 401 is equal to the preset back tap. For example, the start flag signal lastflag output by the control sub-circuit 401 may include lastflag [0] and lastflag [1]. For example, in the period T11, lastflag [0] has an active level (high level), lastflag [1] has an inactive level (low level), and lastflag [0] instructs the filter sub-circuit 402 to copy the source data 9 in the first flip-flop d1_1. In the period T12, lastflag [0] has an inactive level (low level), lastflag [1] has an active level (high level), and lastflag [1] instructs the filter sub-circuit 402 to copy the source data 9 in the first flip-flop d1_2.

In the embodiment of the present disclosure, the first data operation unit 422 shown in fig. 4A may include a plurality of logic operation units, for example, a multiplication operation unit, an addition operation unit, a subtraction operation unit, and the like, which may be used to perform logic operations on a plurality of source data in the plurality of first flip-flops 421, respectively. The second data operation unit 424 shown in fig. 4A may include an addition unit for adding a plurality of source data stored in a plurality of second flip-flops 423 to obtain one destination data.

The first data operation unit 422 may further include a multiplexer MUX. The multiplexer may determine a target trigger from among the plurality of first triggers 421 and copy the source data stored in the target trigger to obtain a plurality of copy source data. For example, the multiplexer copies the source data 9 in the first flip-flop d1_1 under the instruction of lastflag [0] having an active level. This allows the filter sub-circuit 402 to continuously filter the input source data from period T3 to period T12, improving the throughput of the handshaking circuit. In addition, by using a plurality of cascaded flip-flops, the flip-flop of the previous stage can continuously perform data exchange shift to the flip-flop of the next stage, and high throughput of the handshake circuit can be realized.

In the disclosed embodiment, the control sub-circuit 40l also receives a height configuration signal cfg_height. For example, when the height configuration signal cfg_height is 1, the height configuration signal cfg_height indicates that the height of the image data accumulated and received by the filter sub-circuit 402 is smaller than the maximum value, the level of the source preparation signal src_rdy output by the control sub-circuit 401 may be always in an active level state.

For example, when the height configuration signal cfg_height is 1, in the case where it is determined that there is a vacancy in the plurality of first flip-flops in cascade, the source preparation signal output by the control sub-circuit 401 has an active level. For example, in the period T1 to the period T4, there is an idle first flip-flop among the plurality of first flip-flops 421, and the source preparation signal output from the control sub-circuit 401 has an active level.

In the embodiment of the present disclosure, the preset back tap and the preset front tap are both 2, and when the width configuration signal cfg_width indicates that the maximum value of the width of the image data accumulated and received by the filter sub-circuit 402 is 10, the filter sub-circuit 402 completes processing one line of image data in the period T1 to the period T12.

When the height configuration signal cfgheight is 1, the handshake circuit 400 may continue to calculate the input image data of the previous line in the period T1-period T4. In period T11-period T12, handshaking circuit 400 may allow for the input of the next row of image data.

Fig. 5 shows a schematic diagram of a handshake circuit according to another embodiment of the present disclosure.

As shown in fig. 5, handshaking circuit 500 includes a control sub-circuit 501 and a filtering sub-circuit 502. The control sub-circuit 501 and the filter sub-circuit 502 are similar to the control sub-circuit 401 and the filter sub-circuit 402, respectively, shown in fig. 4A, and similar parts are not repeated here for brevity of this disclosure.

In the embodiment of the present disclosure, the control sub-circuit 501 includes a control unit 511 and a transmission unit 512. The control unit 511 may include a first logic operation unit 5111, a second logic operation unit 5112, a third flip-flop 5113, a third logic operation unit 5114, a fourth logic operation unit 5115, and a fifth logic operation unit 5116.

The first logic operation unit 5111 receives the destination ready signal dest_rdy, and performs a logic operation on the destination ready signal dest_rdy to obtain the source ready signal src_rdy.

The second logic operation unit 5112 is electrically connected to the first logic operation unit 5111, and the second logic operation unit 5112 receives the source request signal src_vld and the source preparation signal src_rdy, and performs logic operation on the source request signal src_vld and the source preparation signal src_rdy to obtain the permission signal filter_den.

The third flip-flop 5113 is electrically connected to the second logic operation unit 5112, and the third flip-flop 5113 receives the enable signal filter_den and outputs the destination request signal dest_vld according to the enable signal filter_den. The third flip-flop 5113 outputs the destination request signal dest_vld having an active level, under the instruction of the enable signal filter_den having an active level.

The first logic operation unit 5111 further receives the destination request signal dest_vld from the third flip-flop 5113, and performs a logic operation on the destination ready signal dest_rdy and the destination request signal dest_vld to obtain the source ready signal src_rdy.

For example, the logical operation performed by the first logical operation unit 5111 may be src_rdy=dest_rdy| (| dest_vld). "||" denotes an OR operation, "|! "means no operation, and the active level may be high. For example, in the case where it is determined that the level of the destination preparation signal dest_rdy is high or the level of the destination request signal dest_vld is low at this time, the source preparation signal src_rdy output by the first logic operation unit 5111 is high.

For example, when the data output terminal transmits a data request to the filter sub-circuit 502, the level of the destination preparation signal dest_rdy received by the control sub-circuit 501 is high. When the data output terminal is in an idle state, the level of the destination request signal dest_vld generated by the control sub-circuit 501 is low.

The second logic operation unit 5112 receives the source request signal src_vld and the source preparation signal src_rdy, and performs a logic operation on the source request signal src_vld and the source preparation signal src_rdy to obtain the enable signal filter_den.

For example, the logical operation performed by the second logical operation unit 5112 may be filter_den= (srcflag = (hcnt > = tapb)) || (lastflag = (destflag). "& =" means and operation, and "> =" means greater than or equal to. For example, in the case where it is determined that the source flag signal src_rdy is at a high level (the level of the source preparation signal src_rdy is at a high level and the level of the source request signal src_vld is at a high level) and the back tap (hcnt) of the current operation point source data is greater than or equal to the preset back tap (tapb), the enable signal filter_den output by the second logic operation unit 5112 is at a high level. Alternatively, in the case where it is determined that the level of the last flag signal lastflag is high and the level of the destination flag signal destflag is high (the level of the destination preparation signal dest_rdy is high and the level of the destination request signal dest_vld is high), the permission signal filter_den output by the second logic operation unit 5112 is high. The filter sub-circuit 502 starts processing the source data src_data under the instruction of the enable signal filter_den having a high level.

The third logic operation unit 5114 receives the source preparation signal src_rdy and the source request signal src_vld, and outputs a source flag signal srcfiag according to the source preparation signal src_rdy and the source request signal src_vld. For example, the logic operation performed by the third logic operation unit 5114 may be srcflag=src_rdy & & src_vld, the source preparation signal src_rdy is determined by the destination preparation signal dest_rdy, and in the case where it is determined that the level of the source preparation signal src_rdy is high and the level of the source request signal src_vld is high at this time, the source flag signal srcflag output by the third logic operation unit 5114 is high. The filter sub-circuit 502 starts receiving valid source data src_data under the instruction of the source flag signal srcflag having a high level.

For example, the third logic operation unit 5114 may further output the destination flag signal destflag according to the destination preparation signal dest_rdy and the destination request signal dest_vld. The logic operation performed by the third logic operation unit 5114 may also be destflag=dest_rdy & & dest_vld, and in the case where it is determined that the level of the destination preparation signal dest_rdy is high and the level of the destination request signal dest_vld is high at this time, the destination flag signal destflag that the third logic operation unit 5114 will output is high. The filter sub-circuit 502 may output valid destination data dest_data under the instruction of the destination flag signal destflag having a high level.

The fourth logic operation unit 5115 receives the destination preparation signal dest_rdy and the source request signal src_vld, and outputs the start flag signal firstflag according to the destination preparation signal dest_rdy and the source request signal src_vld. For example, when it is determined that the back tap of the current operation point source data of the filter sub-circuit 502 satisfies the preset back tap according to the source preparation signal src_rdy and the source request signal src_vld, the start flag signal first output by the fourth logic operation unit 5115 is at a high level. Under the instruction of the start flag signal first flag with a high level, the filter sub-circuit 502 copies the source data input in the 1 st period to obtain copy source data, so that the front tap of the current operation point source data meets the preset front tap.

The fifth logic unit 5116 receives the configuration signal cfg and outputs the last flag signal lastflag according to the configuration signal cfg. For example, in a case where it is determined that the number of source data received by the filter sub-circuit 502 has accumulated to the maximum value according to the configuration signal cfg, the last flag signal lastflag output by the fifth logic operation unit 5116 is high level. Under the instruction of the last flag signal lastflag with a high level, the filter sub-circuit 502 stops receiving new source data, and copies the source data input last to obtain copied data, so that the back tap of the source data of the current operation point meets the preset back tap.

The filter sub-circuit 502 is electrically connected to the second logic operation unit 5112, the third logic operation unit 5114, the fourth logic operation unit 5115, and the fifth logic operation unit 5116, respectively. The filter sub-circuit 502 may receive a source flag signal srcflag, an enable signal filter_den, a start flag signal first flag, and an end flag signal lastflag.

In the embodiment of the present disclosure, the transmission unit 512 includes a sixth logic operation unit 5121, a seventh logic operation unit, and a fourth flip-flop 5123.

For example, the sixth logic unit 5121 is electrically connected to the first logic unit 5111. The sixth logical operation unit 5121 is similar to the first logical operation unit 5111. For example, the sixth logic operation unit 5121 receives the destination ready signal dest_rdy and performs a logic operation on the destination ready signal dest_rdy to obtain the source ready signal src_rdy. The logical operation performed by the sixth logical operation unit 5121 may also be src_rdy=dest_rdy| (| dest_vld). For example, in the case where it is determined that the level of the destination preparation signal dest_rdy is high or the level of the destination request signal dest_vld is low at this time, the source preparation signal src_rdy output by the sixth logic operation unit 5121 is high.

For example, the seventh logic operation unit 5122 is electrically connected to the sixth logic operation unit 5121 and the third flip-flop 5113, and the seventh logic operation unit 5122 is similar to the second logic operation unit 5112. For example, the seventh logic operation unit 5122 receives the source request signal src_vld and the source preparation signal src_rdy, and performs a logic operation on the source request signal src_vld and the source preparation signal src_rdy to obtain the destination request signal dest_vld.

For example, the fourth flip-flop 5123 is electrically connected to the seventh logical operation unit 5122. The fourth flip-flop 5123 receives the destination request signal dest_vld and outputs the destination request signal dest_vld to the control sub-circuit of the subsequent stage.

In the embodiment of the present disclosure, the control sub-circuit 501 also receives a reset signal ip_clr and performs reset based on the reset signal. The filter sub-circuit 502 also receives a reset signal ip_clr and resets based on the reset signal.

For example, the second logic operation unit 5112 receives the reset signal ip_clr, and resets the enable signal filter den under the instruction of the reset signal ip_clr, so that the level of the enable signal filter den is in a state of an inactive level (low level). The filter sub-circuit 502 also receives a reset signal and resets the data within the filter sub-circuit 502 (first flip-flop and second flip-flop) under control of the reset signal ip_clr. Under the control of the reset signal ip_clr, the signal output by the second logic operation unit 5112 and the data output by the filter sub-circuit 502 can be reset at the same time.

In the embodiment of the present disclosure, when the level of the reset signal ip_clr is an active level (e.g., high level), the handshake circuit 500 is reset as a whole. At this time, the enable signal filter_den output from the second logic operation unit 5112 is at a low level, and the filter sub-circuit 502 is suspended.

In the disclosed embodiment, the signal received by the third flip-flop 5113 is related to the data output condition of the filter sub-circuit 502. For example, when the level of the reset signal ip_clr is an active level (e.g., a high level), the enable signal filter_den output by the second logic operation unit 5112 is a low power-on, and the signal of the third flip-flop 5113 is also a low level, and the filter sub-circuit 502 does not output data.

For example, in a case where it is determined that the level of the enable signal filter_den is an active level (e.g., a high level), the signal input to the third flip-flop 5113 is also a high level, and at this time, the filter sub-circuit 502 may output data. For example, when it is determined that the levels of the destination preparation signal dest_rdy and the destination request signal dest_vld are simultaneously active levels (e.g., high levels), the filter sub-circuit 502 may output data and make the signal input to the third flip-flop 5113 also low level.

In other application scenarios, the active level of the signal input to the third flip-flop 5113 is the same as the active level of the destination request signal dest_v1d.

In the disclosed embodiment, when the level of the reset signal ip_clr is an active level, the reset signal ip_clr has the highest priority, and the signals in the handshake circuit 500 are all reset. When the levels of the enable signal filter_den, the ready signal dest_rdy, and the request signal dest_vld are also active at the same time, the handshake circuit preferentially performs the operation of the enable signal filter_den to control the third flip-flop 5113 such that the signal input to the third flip-flop 5113 is also high, and at this time, the filter sub-circuit 502 outputs data.

In the embodiment of the present disclosure, the ready signal dest and the request signal dest_vld generated by the control sub-circuit of the last stage of the handshake circuit 500 may drive the control sub-circuit of the previous stage to send handshake signals according to the level state, so as to drive the processing sub-circuit of the previous stage to process the received source data.

In the embodiment of the present disclosure, when the source preparation signal src_rdy output from the first logic operation unit 5111 is at an active level, the filter sub-circuit 502 may be indicated to the previous stage circuit to be in a state allowing the input of source data. For example, when the destination ready signal dest_rdy received by the first logic operation unit 5111 is at an active level, the next stage circuit can receive data, and at this time, there is a spare position on the data path datapath of the handshake circuit, and new source data can be input into the filtering sub-circuit. At this time, the source ready signal src_rdy outputted from the first logic operation unit 5111 is set to 1 (active level). For example, when the last source data is input into the filtering sub-circuit, there is source data that is not used as the current operation point in the filtering sub-circuit, so that the filtering sub-circuit performs the operation of copying the last input source data, so that the first trigger of the filtering sub-circuit is written with the copied source data in the next period, and the handshaking circuit is considered to be still in a state of receiving data, the source preparation signal src_rdy output by the first logic operation unit 5111 is set to 1 (active level), so that the data is stored in the triggers in the data channel datapath of the handshaking circuit, and high throughput of the handshaking circuit is realized.

As shown in fig. 6, the data processing method of this embodiment may be applied to a handshake circuit according to an embodiment of the present disclosure. The data processing method of this embodiment includes operations S610 to S650.

In operation S610, a destination preparation signal and a source request signal are received.

In operation S620, a source flag signal is output according to the destination preparation signal and the source request signal.

In operation S630, a plurality of source data are received based on the source flag signal for a plurality of periods.

In operation S640, in the case where it is determined that the number of the plurality of source data satisfies the preset condition, a filtering operation is performed on the plurality of source data to obtain the destination data.

In operation S650, destination data is output.

In the embodiment of the present disclosure, operations S610 and S620 are performed by the control sub-circuit 101, corresponding to the operations performed by the control sub-circuit 101, and operations S630 to S650 are performed by the filtering sub-circuit 102, corresponding to the operations performed by the filtering sub-circuit 102, and are not repeated herein for brevity.

According to the embodiment of the disclosure, the transmission process of the preparation signal and the request signal is designed, so that the control sub-circuit and the filtering sub-circuit can process and transmit the data only under the control of the preparation signal and/or the request signal, thereby realizing the precursor mode and/or the postdriver mode of the handshaking circuit and improving the portability of the control sub-circuit and the filtering sub-circuit. In addition, the data processing method provided by the disclosure can reduce the complexity and area of the circuit by only processing and transmitting the data through the preparation signal and/or the request signal.

It should be noted that in the above description, the technical solutions of the embodiments of the present disclosure are shown by way of example only, but it is not meant that the embodiments of the present disclosure are limited to the above steps and structures. Steps and structures may be modified or omitted as necessary, where possible. Thus, certain steps and elements are not necessary to practice the general inventive concepts of the embodiments of the present disclosure.

The disclosure has been described with reference to the preferred embodiments. It should be understood that various other changes, substitutions, and alterations can be made by those skilled in the art without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of the embodiments of the present disclosure is not limited to the specific embodiments described above, but should be defined by the appended claims.

Claims

1. A handshaking circuit, comprising:

at least one control sub-circuit for receiving a destination preparation signal and a source request signal, and outputting a source flag signal according to the destination preparation signal and the source request signal; and

the filtering sub-circuit is used for receiving the source mark signals from the corresponding control sub-circuit, receiving a plurality of source data based on the source mark signals in a plurality of periods, and carrying out filtering operation on the plurality of source data to obtain target data and outputting the target data under the condition that the quantity of the plurality of source data is determined to meet the preset condition;

Wherein each control sub-circuit of the at least one control sub-circuit corresponds to one of the filter sub-circuits of the at least one filter sub-circuit, each filter sub-circuit of the at least one filter sub-circuit corresponds to one of the control sub-circuits of the at least one control sub-circuit, and each control sub-circuit is electrically connected to the corresponding filter sub-circuit.

2. The handshaking circuit of claim 1, wherein,

the control sub-circuit is further configured to output an enable signal according to the destination preparation signal and the source request signal in a preset number of cycles; and

the filtering sub-circuit is also used for receiving the permission signal, performing filtering operation on the plurality of source data based on the permission signal to obtain the target data, and outputting the target data.

3. The handshake circuit of claim 1, wherein the preset condition is that the number of the plurality of source data is n+m, N is a positive integer greater than 1, and M is a positive integer;

the control sub-circuit is further used for outputting an allowing signal, a source mark signal and a start mark signal according to the destination preparation signal and the source request signal in N periods; and

The filter subcircuit is further configured to:

receiving the source mark signal, and receiving N source data based on the source mark signal in N periods;

receiving the initial mark signal, and copying the 1 st source data for M times based on the initial mark signal in the N-th period to obtain M1 st source data, wherein the 1 st source data is the source data received by the filter sub-circuit in the 1 st period of the N periods in the N source data; and

and receiving the permission signal, carrying out filtering operation on the N source data and the M1 st source data based on the permission signal to obtain the target data, and outputting the target data.

4. The handshaking circuit of claim 3 wherein,

the control sub-circuit is also used for receiving a configuration signal and outputting an end mark signal based on the configuration signal; and

the filtering sub-circuit is further configured to receive the end flag signal, copy the L source data based on the end flag signal in the l+1st period, where L is a positive integer;

based on the configuration signal, the filtering sub-circuit receives L source data in L periods, wherein the L-th source data is the source data received by the filtering sub-circuit in the L periods in the L source data.

5. The handshaking circuit of claim 4, wherein,

the control sub-circuit is further configured to output the enable signal having an active level based on the end flag signal.

6. The handshake circuit of claim 1, wherein the preset condition is that the number of the plurality of source data is n+m, N is a positive integer greater than 1, and M is a positive integer; the filtering sub-circuit includes:

a plurality of first triggers in cascade for receiving the source flag signal, and receiving N source data based on the source flag signal in N periods;

the first data operation unit is electrically connected with the plurality of first triggers respectively and is used for receiving the initial sign signals, copying the 1 st source data for M times based on the initial sign signals in the N-th period to obtain M1 st source data, outputting the N source data and the M1 st source data, wherein the 1 st source data is the source data received by the filter sub-circuit in the 1 st period of the N periods in the N source data;

the cascaded second triggers are respectively and electrically connected with the first data operation unit and are used for receiving the N source data and the M1 st source data; and

And the second data operation unit is electrically connected with the second triggers respectively and is used for receiving the N source data and the M1 st source data, operating the N source data and the M1 st source data to obtain the target data and outputting the target data.

7. The handshaking circuit of claim 6 wherein the

The second data operation unit is further configured to receive an enable signal, and based on the enable signal, perform operation on the N source data and the M1 st source data to obtain the destination data, and output the destination data.

8. The handshaking circuit of claim 6, wherein,

the first data operation unit is further used for receiving an end mark signal, copying the L-th source data based on the end mark signal in the L+1st period, wherein L is a positive integer;

based on a configuration signal, the cascaded first triggers receive L source data in L periods, wherein the L source data is the source data received by the first triggers in the L periods in the L source data.

9. The handshaking circuit of any of claims 1-8 wherein the control sub-circuit is further configured to:

Receiving a destination preparation signal with an active level and a source request signal with an active level, and outputting the source preparation signal with the active level according to the destination preparation signal; and

and outputting a source flag signal having an active level according to the source request signal and the source preparation signal.

10. The handshaking circuit of claim 4 or 8 wherein the control sub-circuit is further configured to:

receiving the configuration signal, and outputting an end mark signal with an effective level according to the configuration signal; and

and outputting an allowable signal with an active level according to the tail flag signal.

11. The handshaking circuit of claim 1, wherein,

the control sub-circuit is also used for receiving a reset signal and resetting based on the reset signal; and

the filter sub-circuit is also used for receiving a reset signal and resetting based on the reset signal.

12. The handshaking circuit of claim 6, wherein the control sub-circuit is further configured to:

and receiving the configuration signal, and outputting a source preparation signal with an active level according to the configuration signal under the condition that the empty space exists in the cascaded first triggers.

13. The handshaking circuit of claim 1 wherein the at least one control sub-circuit comprises:

at least one transmission unit for receiving the destination preparation signal;

and a control unit electrically connected with the at least one transmission unit, the control unit being configured to receive the source request signal and a destination preparation signal from the at least one transmission unit.

14. The handshaking circuit of claim 13 wherein the control unit is electrically coupled to the filtering sub-circuit, the control unit further configured to output a source flag signal based on the destination ready signal and the source request signal.

15. The handshaking circuit of claim 13 wherein the control unit comprises:

the first logic operation unit is used for receiving the destination preparation signal and carrying out logic operation on the destination preparation signal to obtain a source preparation signal; and

and the second logic operation unit is electrically connected with the first logic operation unit and is used for receiving the source request signal and the source preparation signal, and performing logic operation on the source request signal and the source preparation signal to obtain an permission signal.

16. The handshaking circuit of claim 15 wherein the control unit further comprises:

a third logic operation unit, configured to receive the source preparation signal and the source request signal, and output the source flag signal according to the source preparation signal and the source request signal;

a fourth logic operation unit for receiving the destination preparation signal and the source request signal, and outputting a start flag signal according to the destination preparation signal and the source request signal; and

and the fifth logic operation unit is used for receiving the configuration signal and outputting an end mark signal according to the configuration signal.

17. A data processing method, comprising:

receiving a destination preparation signal and a source request signal;

outputting a source flag signal according to the destination preparation signal and the source request signal; and

receiving a plurality of source data based on the source flag signal over a plurality of periods;

under the condition that the quantity of the source data meets the preset condition, filtering operation is carried out on the source data to obtain target data; and

and outputting the destination data.