JP2006004465A - Optical disk device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical disk device capable of reducing electric power consumption without degrading reproduction signal quality during high-speed reproduction of data recorded on an optical disk. <P>SOLUTION: The optical disk device is equipped with an A/D converter conversion section 7 for sampling a reproduction signal from the optical disk 1 based on a reproduction channel clock (CK), a serial-parallel conversion section 101 for converting the sampled reproduction signal to a parallel reproduction signal of an n system, a 1/n clock generation section 8 for generating the 1/n clock of the reproduction channel block, and a phase comparison section 104 for comparing the phases of the parallel reproduction signal and the reproduction channel phase by operating on the 1/n clock, and controls the reproduction channel clock by the output from the phase comparison section. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an apparatus for reproducing a signal from an optical disk, and more particularly to an optical disk apparatus that suitably performs high-speed reproduction processing.

  Viterbi, which is one of the partial response method and the maximum likelihood decoding method (Maximum Rifflid), is a sample of multi-bit digital signals as a method for processing digital signals reproduced from an optical disk medium, compared to the conventional binarization method. A PRML (Partial Response Maximum Likelihood) signal system combining decoders has been proposed. This PRML signal system realizes a reproduction system that does not require a high frequency component by intentionally adding waveform interference as the recording density in the linear recording direction increases, and by probability calculation considering waveform interference, This is a method for improving the quality of reproduced data.

  When performing digital data demodulation using PRML signal processing using a reproduction clock synchronized with the channel bit frequency of the digital data recorded on the medium, the frequency of the reproduction clock becomes high during high-speed reproduction. Depending on the power consumption of the digital circuit increases.

  Therefore, for example, the method disclosed in Patent Document 1 employs a PRML signal system, and reproduces a sample obtained by sampling with a clock having a half frequency of the channel bit frequency (1/2 clock) for the purpose of reducing power consumption. Offset correction control is performed while interpolating offset information in the amplitude direction of the missing time in the signal. Further, phase synchronization control is performed while interpolating the phase error information of the missing time. Partial response adaptive equalization is performed on the reproduction signal that has been offset-corrected in the amplitude direction and phase-synchronized (phase error interpolation half-rate method).

JP2003-36612A (page 4-5)

  In partial response adaptive equalization, the absolute value of a multilevel signal is acquired and data is reproduced, and therefore, if the thinned data is interpolated and used, the error rate may deteriorate. That is, in the half rate method disclosed in Patent Document 1, since missing information is interpolated, an error may occur between the data and the true data. If there is an error in the interpolated data, the quality of the reproduction signal will deteriorate unless accurate interpolation is performed by the interpolation circuit.

  Further, the phase error interpolation half-rate method disclosed in Patent Document 1 does not describe the correspondence to a clock of 1/2 or less. Further, since it is based on the principle that data can be demodulated when sampled at a half rate by the sampling theorem, the MTF (Mutual Trans Function) characteristic which is an optical reproduction characteristic is distributed in a band of 1/4 or less of the channel bit frequency. If it is, it is difficult to adopt.

  On the other hand, when the PRML signal processing method is incorporated in an LSI, an AD conversion unit and a DA conversion unit that are analog parts are required. For example, assuming a 16-times DVD-RAM system, the channel clock frequency is 466.88 MHz (1-times 29.18 MHz). Even if the AD converter corresponding to this is relatively realizable, it is expected that the DA converter is difficult to realize.

  In order to solve the above-described problems, an object of the present invention is to reduce the power consumption without reducing the quality of a reproduced signal during high-speed reproduction of data recorded on an optical disk medium.

  Another object of the present invention is to provide a reproducing apparatus with high feasibility in consideration of characteristics of an LSI process and analog parts.

  In the present invention, in order to solve the above-described problem, an analog / digital conversion unit that samples a signal reproduced from an optical disk based on a reproduction channel clock, and a reproduction signal sampled by the analog / digital conversion unit are represented by n (n is 2 or more). Obtained by a serial / parallel converter that operates with a 1 / n clock and a 1 / n clock that generates 1 / n clock of a reproduction channel clock. And a phase comparison unit that compares the phases of the parallel reproduction signal and the reproduction channel clock, and the reproduction channel clock is controlled by a phase error output from the phase comparison unit.

  Furthermore, in the present invention, an offset correction unit that operates with a 1 / n clock and corrects an offset of a reproduction signal sampled by an analog-digital conversion unit, and operates with a 1 / n clock and outputs a phase error from a phase comparison unit And a loop filter unit that integrates and smoothes.

  The present invention further includes a 1 / n clock selection unit that selects the number n of parallel reproduction signals to be converted by the serial / parallel conversion unit and the n value of the 1 / n clock generated by the 1 / n clock generation unit. did.

  With this configuration, the power consumption is reduced by converting the serial signal into n parallel signals and reducing the signal processing clock frequency to 1 / n. In addition, since data is not thinned at the time of sampling, an error associated with thinning basically does not occur.

  During high-speed reproduction of data recorded on an optical disk medium, it is possible to reduce the power consumption during signal processing without degrading the reproduction signal quality.

  The present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a first embodiment of an optical disc apparatus according to the present invention. As signal processing, a phase-locked loop of PLL (Phase-Locked Loop) is used to extract a synchronized clock signal and a multi-valued signal, and a signal reproduction method is adopted by a PRML (Partial Response Maximum Likelihood) circuit. Yes.

  Here, 1 is an optical disk such as a DVD-RAM in which prepit portions and data portions are alternately arranged, 2 is a spindle motor, 3 is an optical head (PU), 4 is an I / V converter, and 5 is a wobble signal processor. It is. An RF data processing unit 6 includes an auto gain control (AGC) unit 61, a high pass filter (HPF) unit 62, and an equalizer (EQ) unit 63. 7 is an analog-to-digital converter (A / D converter), 8 is a channel bit rate 1 / n clock generator, 9 is a current controlled oscillator (ICO), 10 is a PLL unit that operates with a 1 / n clock, Reference numeral 11 denotes a demodulated signal processing unit. The PLL unit 10 includes a serial / parallel conversion unit 101, an offset correction unit 102, a wide capture unit 103, a phase comparison unit 104, a loop filter unit 105, and a digital / analog conversion unit (D / A conversion unit) 106. A control unit 12 includes a 1 / n clock selection unit 121, and 13 is a host device.

  The optical disk 1 is held and rotated by a spindle motor 2, and the optical head 3 forms a semiconductor laser that emits laser light for recording or reproducing information, and light from the semiconductor laser is formed as a light spot on the disk surface. And an optical detector for performing light spot control such as information reproduction and autofocus and track tracking using reflected light from the optical disk 1, and recording information on the optical disk 1, Information on the optical disc 1 is reproduced. The optical disk device is connected to a host device 13 such as a personal computer or a workstation, and commands, information data from the host device 13 are recorded, reproduced, and seeked through a control unit 12 including a microcomputer. Execute.

  Next, the operation of the reproduction process will be described. The host device 13 instructs the control unit 12 to start reproduction, receives a signal from the optical head 3, and the I / V conversion unit 4 converts the current / voltage converted reproduction signal into the wobble processing unit 5 and the RF data processing. Output to unit 6.

  The wobble signal processing unit 5 extracts a wobble signal corresponding to the periodically wobbling recording guide groove (wobble) of the disk, and outputs a wobble clock as a binary signal synchronized with this signal.

  An automatic gain control (AGC) 61 in the RF data processing unit 6 performs gain control so that the amplitude of the signal from the I / V conversion unit 4 becomes constant. The high pass filter (HPF) 62 is provided to eliminate low frequency DC fluctuations included in the reproduction signal. In the case of DVD-RAM, in order to reproduce the address of the header part, it is necessary to reduce the DC fluctuation of the header part, and a cutoff frequency (Fc) adjustment unit that switches the cutoff frequency of the HPF high is provided. The cut-off frequency is several kHz to several tens of kHz. The cut-off frequency is set so that the DC level after passing through the scratch on the disk returns to normal.

  The equalizer (EQ) 63 corrects the attenuation of the high frequency component due to the optical characteristics. In the PRML system, the degree of influence on a plurality of bits is set to a value determined by the PR class, and the degree of interference between bits is controlled. For example, when PR (1, 2, 2, 1) is used, the characteristic of the equalizer 63 is corrected so as to be close to the frequency characteristic of PR (1, 2, 2, 1). In the case of 8-16 modulated DVD data using PR (1, 2, 2, 1), the output sampled by the A / D converter described later is 0, 1, 3, 5, 6 Only the intermediate value of the five values is a possible value. Details will be described later.

  The PLL circuit 10 generates a reproduction clock for reproducing address data and user data from the RF signal that has passed through the RF data processing unit 6. The reproduction clock here refers to a channel bit rate clock (CK) for sampling data of the A / D converter 7 and a channel bit rate 1 / n clock (1 / nCK) for operating the digital circuit in the PLL 10. It is. The channel bit rate clock (CK) is also used when the serial / parallel converter 101 converts data from channel bit rate serial data to n parallel data.

  The reproduction signal is sampled into a multi-bit digital signal by the A / D conversion unit 7 and reproduced by the demodulated signal processing unit 11. The demodulated signal processing unit 11 is reproduced by a PRML signal system that combines a Viterbi decoder, which is one of a partial response system and a maximum likelihood decoding system (maximum live-cliff).

  In the PRML signal system, since the sampled multi-bit digital signal value is meaningful in Viterbi decoding, it is important that the phase of the recovered clock is synchronized with the phase of the clock component of the recovered signal. Further, it is necessary to stably output the reproduction clock without the PLL unit 10 being unlocked due to a disturbance such as scratches or noise on the optical disk.

  Even if the RF data processing unit cannot detect a flaw, the flaw is detected (not shown), the output of the phase comparison unit 104 is set to 0 so that the PLL unit 10 is not unlocked, and the loop filter 105 is integrated. And the output of the integrator of the offset correction unit 102 are held, and the oscillation frequency of the ICO unit 9 is held.

  The PLL circuit 10 that generates the reproduction clock is a digital PLL that controls the frequency of the oscillator by a digital value by the DA converter 106. From the signal whose offset has been corrected by the offset correction unit 102, a phase error before and after the zero cross point is extracted by the phase comparison unit 104, noise is removed by the loop filter 105, and the ICO 9 is oscillated via the D / A conversion unit 106. . The sampling clock (CK) of the A / D conversion unit 7 is generated by the output of the ICO 9, and the data reproduction clock (1 / nCK) is generated by the 1 / n clock generation unit 8. The clock frequency for data reproduction (1 / nCK) generated by the 1 / n clock generator 8 can be confirmed by monitoring it externally as shown in the figure.

  When an LSI for generating a high-frequency clock is built in the LSI, a current control oscillator (ICO) 9 is used as a pair with the D / A converter 106. When the frequency is not high, a voltage controlled oscillator (VCO) may be used.

  The wide capture 103 is a PLL circuit function for obtaining a so-called wide capture function in which the capture range and the lock range are expanded. The wide capture 103 compares the wobble clock output from the wobble processing unit 5 with the channel clock (CK) generated by the PLL. When operating at high speed, 1 / n clocks may be compared. Control is performed so that the channel clock frequency matches the wobble clock which is the reference frequency, and the PLL 10 is frequency-locked at high speed. After the frequency is locked, the phase comparator 104 performs phase locking.

  The A / D converter 7 samples data with the channel clock (CK). The A / D converter 7 satisfies high-speed specifications that operate at the channel bit rate. The serial / parallel converter 101 converts sampling data from serial data to n parallel data. After conversion to parallel data, the PLL component is operated at 1 / n clock (1 / nCK) of the channel bit rate.

  When operated at 1 / n clock of the channel bit rate, the components whose circuit configuration is changed depending on the value of n (2 or more) are the phase comparison unit 104 that requires data before and after the zero cross point, and the channel The offset correction unit 102 requires data for each clock. The phase comparison unit 104 and the offset correction unit 102 will be described in detail later.

  On the other hand, when operating at 1 / n clock of the channel bit rate, an IIR (Infinite Impulse Response) filter that performs an integration operation is used for components that do not require a change in circuit configuration depending on the value of n (when 2 or more). The loop filter 105 or the like has a low operating speed.

  In the present embodiment, in order to operate with 1 / n clock, attention was paid to the following points.

  In order to operate with 1 / n clock, n flip-flops (FF) that have been operated with the channel clock are required. When n becomes large, the response of the PLL loop is deteriorated or the worst lock is not achieved. Therefore, the upper limit n (max) of n is determined in consideration of the response characteristics of the PLL loop from the maximum operating frequency, the number of bits of the A / D converter and the D / A converter, the frequency sensitivity of the ICO, etc. Circuit configuration. When it is desired to operate at n or less, the 1 / n clock selection unit 121 selects a desired i below n via the host device 13 and the PLL circuit 10 that operates at the selected 1 / i clock did.

  Further, in the 8-16 modulation system, the input waveform has a minimum width of 3T, and when operated with a 1/4 channel clock, there are two zero cross points of the phase comparator 104. When adding the outputs of the four phase comparators, carry is taken into consideration.

  According to the present embodiment, the power consumption can be reduced because the 1 / n clock is used for high-speed reproduction. Further, since sampled data is not thinned out, no error occurs and reproduction signal quality does not deteriorate.

  At present, it is difficult to operate the D / A conversion unit built in the LSI with the highest channel clock (for example, DVD-RAM × 16). It is expected that higher speed will be achieved by the evolution of the LSI process in the future. According to the present embodiment, when dealing with the progress of such analog parts, only the analog part is replaced and the digital part is switched to operate at a desired 1 / n clock without redesigning the PLL. Can do. That is, according to the present embodiment, it is possible to provide a PLL circuit that can be used without changing the circuit configuration even if the characteristics of the LSI process and analog parts change.

Hereinafter, each component of a present Example is demonstrated in detail.
(1) A / D converter 7
First, the input waveform of the A / D converter 7 will be described. A signal matching the input range of the A / D converter 7 is input from the RF data processor 6 to the A / D converter 7. For example, the standard input of the A / D converter 7 is about 1/2 to 3/4 of the input range.

  FIG. 2A shows PR (1, 2, 2, 1) waveform 3T-7T signals. Here, for example, the 4T signal is a signal in which the bit string written on the disk repeats “0000111100001111...”. When this signal is passed through PR (1, 2, 2, 1), the “1111” portion is output in the order of “1221” as described below. That is, it becomes the sum of “01221”, “001221”, “0001221”, “0000021”, and becomes “013565651. Thus, only the five values “0, 1, 3, 5, 6” are possible values.

  It is necessary to input the equalized signal to the Viterbi decoder in the demodulated signal processing unit 11. The equalization may be performed by the EQ 63 of the RF data processing unit 6 or may be performed in the demodulated signal processing unit 11. In the 8-16 modulation method used in the DVD standard, a 3T to 14T signal is input from the analog front end unit (AFE) to the AD conversion unit. In FIG. 2A, the center value of the amplitude is 3. The RF data processing unit 6 performs differential input to the A / D conversion unit 7 so that the center value 3 becomes the center zero of the output of the A / D conversion unit.

  FIG. 2B shows a standard output amplitude waveform (when a 4T signal is input) of the A / D converter (7 bits). A channel clock (CK) is generated by the PLL, and the A / D converter 7 samples the reproduction data by the channel clock. The sampling point takes a value between “0, 1, 3, 5, 6” shown in FIG. In FIG. 2B, the center DC3 of 0 to 6 is expressed as 0 (zero) of the output of the A / D converter, 3 or more is expressed as (+), and 3 or less is expressed as (−).

  The reason for taking a value between “0, 1, 3, 5, 6” shown in FIG. 2A is that the amplitude difference before and after the positive / negative switching point is set to 0 by the phase comparison unit 104 described later. This is because the DPLL controls the phase of the clock. In the figure, ◎ indicates data sampled with a clock (channel clock CK) of the channel frequency of the reproduction data.

  The center input DC value of the A / D converter 104 is 0 at the output. Considering the input range of the A / D converter at the center of 0 (zero), the standard input to the A / D converter is determined. When the A / D conversion unit is 7 bits, the A / D output takes values from −64 to +64 when expressed in 2's complement.

FIG. 3 is a block diagram showing an embodiment of the optical disk apparatus according to the present invention (when n = 4, 1/4 clock is used). FIG. 3 includes the serial / parallel converter 101 when n = 4.
(2) Serial-parallel converter 101
F1 to F5 and D1 to D5 indicate flip-flops. P1 to P4 indicate the phase comparison unit 104, respectively. The data is latched by F1 for each channel clock via the A / D converter 7 that samples the data by the channel clock (CK). The data obtained at F1 is further latched at F2. Similarly, the data of F3, F4, and F5 are latched.

  Thereafter, D1 to D5 are latched with a 1/4 clock (1/4 CK), thereby converting the serial data output from F1 to F5 into five parallel data. The five systems of data (1) to (5) are input to the four systems of phase comparator 104. On the other hand, the four systems of data (1) to (4) are input to the offset correction unit 102 to perform calculation. Further, the four systems of data (1) to (4) are input to the PRML circuit and reproduced as binary data by the PRML circuit. The loop filter 105 operates with the same circuit configuration as when n = 1, with only the clock set to ¼. Since the loop filter uses an IIR filter and the integration operation may be slow, there is no need to change the circuit configuration. The D / A converter 106 is also operated with a clock that satisfies the operation specifications.

  With such a configuration, power consumption can be reduced and the PLL can be operated without thinning out necessary data.

  Next, the operation will be described. FIG. 5 is an outline of data and clocks at the time of serial-parallel conversion when n = 4 and a 1/4 clock is used.

  Channel data (CK), channel clock synchronization counter ckcnt [1: 0], 1/4 clock, serial data xdt0 [6: 0] obtained by latching 7-bit data output from the A / D converter with the channel clock in order from the top Data xdt1 [6: 0] obtained by further latching xdt0 [6: 0] with the channel clock, data xdt2 [6: 0] obtained by further latching xdt1 [6: 0] with the channel clock, and the like. The same applies to xdt3 [6: 0] to xdt4 [6: 0].

  In addition, when ckcnt [1: 0] = 3, data xdt0_lat [6: 0] to xdt4_lat [6: 0] obtained by latching xdt0 [6: 0] to xdt4 [6: 0] with a quarter clock is shown. .

  The 1/4 clock is generated from the channel clock synchronization counter. Latch with ckcnt [1: 0] = 3 and then latch with 1/4 clock. With this configuration, in the case of LSI, it is possible to design with a margin for the data setup time and hold time.

  In serial / parallel conversion of data, it is necessary to always latch the data latched by the channel clock with a quarter clock. The clock skew (clock variation) between FFs is automatically adjusted with a layout tool. In order to automatically adjust the layout, if the channel clock is a high frequency (DVD-RAM × 16 × speed 466.88 MHz, cycle is 2.14 ns), design should be made in consideration of the 1/4 clock and channel clock skew. Otherwise, the data latched by the channel clock (7 bits × 5) is not latched by the 1/4 clock, and the PLL does not operate normally.

According to this configuration, if the delay of the ¼ clock is two cycles (2T) or less, the phase relationship between the clock and the data can be performed without any problem, and serial / parallel conversion can be performed without fail.
(3) Phase comparison unit 104
FIG. 6A shows the phase comparison unit 104 when operating with a channel clock. For the output of the A / D converter 106, the multiplication result of the data X0 without the sign bit delayed by one clock and the sign bit Y1 and the result of the multiplication of the data X1 without the sign bit and the sign bit Y0 delayed by one clock. Is subtracted. Thereby, the phase error can be expressed as an amplitude error (FIG. 6B).

  This calculation may be performed between channel clocks. When the channel clock is high speed, it is difficult to perform operations between channel clocks.

  FIG. 2B shows the 4T signal output of the A / D converter 7 and shows the operation of the phase comparator. When the phase is behind the reproduction data, the output of the phase comparison unit becomes negative. On the other hand, when the phase is ahead of the reproduction data, the output of the phase comparator becomes positive.

  FIG. 7 shows a phase comparator when operating with a quarter clock. The four phase comparison units shown in FIG. 6A are arranged in parallel, and the calculation is performed during 1/4 clock. When operating with a 1/4 clock, data before and after latching with a channel clock and a sign are received, and an operation is performed between 1/4 clocks.

  In this configuration, the A / D conversion unit output data sampled by the channel clock is processed in parallel using four P1 to P4, and the four data are added and latched without thinning out the data. Output to the loop filter.

  Thereby, the phase error before and after the zero cross point can be output accurately, and the PLL loop can be operated stably.

(4) Offset correction unit 102
Next, the offset correction unit 102 in FIG. 3 will be described. The signal input to the A / D conversion unit is offset-corrected by the offset correction unit 102 so that the DSV (Digital Sum Value) becomes zero. DVD-RAM data is 8-16 modulated, and when data with 3 or 14 consecutive 0s or 1s restricted is reproduced with an ideal device, the DC average value of the reproduced signal is constant. It is always constant within the range. Such a signal is called a DC-free signal. More specifically, DC-free means that the DSV becomes 0 when a value greater than the center value of the reproduction signal is (+) and a value smaller than the center value is (−), and these are added for a certain period.

  FIG. 8A shows an example of the offset correction unit 102 when operating with a channel clock. The offset correction unit 102 is configured by an IIR (Infinite Impulse Response) filter. The output signal is delayed by one clock by a delay circuit (flip-flop) and processed by adding to the input signal. When the offset is not present in the input signal, the DSV is 0, so the output of the IIR filter is 0. If the input code continues to be (+), the output increases with time. If the input code continues to be (-), the output decreases with time. The speed of integration can be varied by the input coefficient 1 / k.

  FIG. 8B shows another example of the offset correction unit 102 when operating with a channel clock. FIG. 8B is a diagram in which a limiter is added after the A / D output of FIG. Since numerical values with large fluctuations such as maximum and minimum amplitudes may give an error to the offset correction output, it is better to use (b) except for offset correction after a flaw.

  The calculation shown in FIG. 8 can be performed between channel clocks. A value of power of 2 is set as the value of k. When this value is large, the number of operation bits increases, and when the channel clock is fast, it is difficult to perform operations between channel clocks. For example, when a value of 2 to the power of k is used, in the case of an A / D converter output 7 bits, (7 + k) bits are calculated.

  FIG. 9 shows an example of the offset correction unit 102 when operating with a quarter clock. In this example, four limiters of the offset correction circuit shown in FIG. 8B are arranged in parallel, and the calculation is performed in 1/4 clock. When operating with a 1/4 clock, the data latched with the channel clock is received and an operation is performed between 1/4 clocks.

  In this configuration, the data after A / D conversion is not thinned out, but is processed in parallel using four limiters, the four data are added, latched, and output to the IIR filter. The integrated signal that is the output of the IIR filter is subtracted from the output of the A / D converter, and is output to the demodulated signal processor 11 and the phase comparator 104 in the next stage. Such an offset correction circuit is called duty feedback.

  Rough offset correction can be realized by this circuit (duty feedback), but fine offset requires correction by detecting signals before and after the zero cross point of the phase comparison unit and jitter feedback (not shown). Jitter-feedback, unlike duty feedback, does not require data for each channel clock, and therefore integrates data every ¼ clock.

(5) Wide capture 103
Next, the wide capture 103 in FIG. 3 will be described. When the frequency of the clock component included in the reproduction signal and the frequency of the reproduction clock generated by the PLL are greatly different, there is a possibility that phase synchronization cannot be pulled in (cannot be locked) or that the frequency is pseudo-locked to a different frequency. In order to avoid this, the clock generated by the PLL is brought close to the frequency of the clock component of the reproduction signal by wide capture so that the phase can be locked immediately after the frequency is locked.

  FIG. 10 shows an example of a wide capture operating at 1 / n clock in the optical disc apparatus of the present invention. The reference clock counter controls the count start of the reproduction clock counter (reset). The wide capture 103 compares the frequency of the wobble clock with the reproduction channel clock frequency of the ICO 9 output, and outputs a frequency error. Basically, the ICO 9 is controlled so that the reproduction channel clock has the same frequency as the wobble clock.

  When the PLL loop operates with 1 / n clock, wide capture also operates with 1 / n clock. In the case of wide capture synchronized with the wobble clock, the wobble clock output from the wobble processing unit 5 is also output in conjunction with 1 / n and input to the wide capture 103. In addition, when the wobble clock is 1/4 of the reproduction clock and a constant value, the wide capture is operated at a low frequency by changing the division ratio (1 / m) on the wobble clock side in the wide capture. Can do.

  It can be used with media such as DVD-RAM and DVD ± R / RW having wobbles other than DVD-ROM. A DVD-ROM disc or the like that does not have wobble uses a wide capture that detects a specific synchronization signal SYNC always included in the reproduction data and locks it to the frequency of the reproduction clock depending on the size of the SYNC width. The SYNC signal is a 14T-width signal in the case of DVD, and a 11T + 11T signal in the case of CD. Also, a wide capture is used that detects the SYNC cycle and locks it to the frequency of the recovered clock. In this type of wide capture, the frequency error may be output with 1 / n clock.

FIG. 4 is a block diagram showing a third embodiment of the optical disk apparatus of the present invention (when n = 2, 1/2 clock is used). Differences from the configuration of FIG. 3 are the following two points.
1) The outputs of the phase comparison units P3 and P4 are fixed to zero.
2) Inputs (3) and (4) of the offset correction unit 102 are set to 0 input.

  In this way, a PLL that uses a 1/2 clock can be operated simply by adding a switch that fixes 0 to a configuration that uses a 1/4 clock. (1) The data of (2) is input to the PRML circuit, and is reproduced as binary data by the PRML circuit. Decoding may be performed by inputting the data of (1) to (4) to the PRML circuit and processing at 1/3 rate or 1/4 rate. The PRML circuit has more logic calculations to be processed in one clock than the PLL circuit. This is because even if the PLL circuit operates at ½ rate, the PRML circuit may not operate at ½ rate.

  When the D / A converter 106 operates with a 1/2 clock, it can be used with this configuration. Since the loop delay is smaller than when the 1/4 clock is used, the operation is more stable.

Similarly, when n = 3, operation is performed at 1/3 rate by setting with a switch as follows.
1) The output of the phase comparator P4 is fixed to zero.
2) The input of (4) of the offset correction unit 102 is set to 0 input.
Since the loop delay is smaller than when the ¼ clock is used, the operation is more stable.

  In each of the above-described embodiments, the PLL circuit of 1/2 rate, 1/3 rate, and 1/4 rate where n is 4 or less has been described. If further high-speed operation is required, the same operation can be performed by using a high-speed A / D converter even when n = 5 or more, performing serial-parallel conversion, and operating the subsequent circuit at 1 / n.

  Further, when higher speed operation is required or when the A / D converter does not operate at the channel bit rate, it can be realized by using two A / D converters alternately.

  FIG. 11 shows a fourth embodiment of the optical disk apparatus of the present invention. The sampling clock of the first A / D converter 71 uses the rising edge of the half clock (1 / 2CK), and the sampling clock of the second A / D converter 72 is the half clock (1 / 2CK). Use the falling edge. That is, the sampling clock of the first analog-digital conversion unit and the sampling clock of the second analog-digital conversion unit are 180 degrees out of phase. The two half-rate data can be operated in the same manner as in the third embodiment by directly inputting the two half-rate data to the phase comparison unit 104 that operates with 1/2 clock of n = 2 without performing serial-parallel conversion. Thereby, the reproduction performance of digital data recorded on the optical disk medium can be improved and the power consumption can be reduced, and a circuit configuration in consideration of the characteristics of the LSI process and analog parts can be realized.

  In the above embodiment, a DVD disk has been described as an example. However, the scope of application of the present invention is not limited to a DVD-RAM, DVD ± R / RW, DVD-ROM, or the like. The present invention can be similarly applied to an optical disc apparatus such as a blu-ray disc.

1 is a block diagram showing a first embodiment of an optical disc apparatus of the present invention. The figure which shows an example of the input-output waveform in an A / D conversion part. The figure which shows the 2nd Example (1/4 clock use) of the optical disk apparatus of this invention. The figure which shows the 3rd Example (use of 1/2 clock) of the optical disk apparatus of this invention. Operation explanatory diagram in serial-parallel converter (using 1/4 clock). The figure which shows an example of a phase comparison part. The figure which shows an example of a phase comparison part (1/4 clock use). The figure which shows an example of an offset correction part. The figure which shows an example of an offset correction part (1/4 clock use). The figure which shows an example of a wide capture. The figure which shows the 4th Example of the optical disk apparatus of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Optical disk, 2 ... Spindle motor, 3 ... Optical head, 4 ... I / V conversion part, 5 ... Wobble processing part, 6 ... RF data processing part, 7 ... A / D conversion part, 8 ... 1 / n clock generation , 9... Current control oscillation unit (ICO), 10... PLL unit operating with 1 / n clock, 11... Demodulated signal processing unit, 12... Control unit, 13. , 62 ... High pass filter (HPF) unit, 63 ... Equalizer (EQ) unit, 101 ... Serial to parallel conversion unit, 102 ... Offset correction unit, 103 ... Wide capture unit, 104 ... Phase comparison unit, 105 ... Loop filter unit, 106 ... D / A converter, 121 ... 1 / n clock selector.

Claims (7)

In an optical disc apparatus for reproducing a signal from an optical disc,
An analog-to-digital converter that samples a signal reproduced from an optical disk based on a reproduction channel clock;
A serial / parallel converter that converts the reproduction signal sampled by the analog / digital converter to an n (n is an integer of 2 or more) system parallel reproduction signal;
A 1 / n clock generator for generating a 1 / n clock of the reproduction channel clock;
A phase comparison unit that operates with the 1 / n clock and compares the phase of the parallel reproduction signal obtained by the serial-parallel conversion unit and the reproduction channel clock;
An optical disc apparatus, wherein the reproduction channel clock is controlled by a phase error output from the phase comparator. The optical disk apparatus according to claim 1, wherein
An offset correction unit that operates at the 1 / n clock and corrects an offset of a reproduction signal sampled by the analog-digital conversion unit;
A loop filter unit that operates with the 1 / n clock and integrates and smoothes the phase error output from the phase comparison unit;
An optical disc apparatus, wherein the reproduction channel clock is controlled by an output from the loop filter section. The optical disc apparatus according to claim 1 or 2,
And a 1 / n clock selection unit for selecting the number n of parallel reproduction signals converted by the serial / parallel conversion unit and the n value of the 1 / n clock generated by the 1 / n clock generation unit. Optical disk device. The optical disk apparatus according to claim 3, wherein
A wobble signal processing unit that extracts a wobble signal from the recording guide groove of the optical disc and outputs a 1 / n wobble clock having a frequency of 1 / n in synchronization with the wobble signal;
A wide capture for frequency-synchronizing the 1 / n clock of the reproduction channel clock to the 1 / n wobble clock,
The optical disk apparatus, wherein the 1 / n clock selection unit selects an n value of a 1 / n wobble clock output from the wobble signal processing unit. The optical disk apparatus according to claim 3, wherein
The phase comparison unit includes n phase comparison units that output a phase error of an adjacent reproduction signal with respect to (n + 1) reproduction signals sampled by the analog-digital conversion unit,
The optical disc apparatus, wherein the offset correction unit has n types of offset correction means for n reproduction signals sampled by the analog-digital conversion unit. The optical disk apparatus according to claim 5, wherein
When the 1 / n clock selection unit can select the number n of parallel reproduction signals and further select the number i (i is an integer smaller than n),
Of the n phase comparison means of the phase comparison unit, the (ni) system output is fixed to 0,
Of n offset correction means of the offset correction unit, (ni) the output of the system is fixed to 0,
An optical disc apparatus characterized by the above. In an optical disc apparatus for reproducing a signal from an optical disc,
A first analog-to-digital converter that samples a signal reproduced from an optical disk based on a half clock of a reproduction channel clock;
A signal reproduced from the optical disc is sampled based on a clock that is 1/2 clock of the reproduction channel clock and is 180 degrees out of phase with the sampling clock of the first analog-digital converter. An analog-digital converter,
A 1 / n clock generator for generating a 1 / n clock of the reproduction channel clock;
A phase comparator that operates at the 1 / n clock and compares the phase of the reproduced signal sampled by the first and second analog-digital converters with the phase of the reproduced channel clock;
An optical disc apparatus, wherein the reproduction channel clock is controlled by a phase error output from the phase comparator.

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