JP2006004312A - Signal processing device and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform normal signal processing without being affected by delay variation in a device between routes. <P>SOLUTION: This signal processing device comprises a signal processing circuit for applying signal processing to an input signal from the other circuit or the other device in reference with a clock, a phase adjustment circuit for adjusting the phase of the clock, and a control means that varies the phase adjustment amount of the phase adjustment circuit while monitoring the state of an output signal outputted by applying the signal processing in the signal processing circuit, detects an error phase point at which the signal processing circuit cannot establish a setup/hold condition and generates an error, and determines the phase adjustment amount so as to avoid the error phase point. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention performs image formation of one line in the main scanning direction according to image data with reference to a dot clock serving as a reference of pixels for image formation, and performs image formation for each line in the main scanning direction in the sub-scanning direction. In particular, the present invention relates to a signal processing apparatus and an image forming apparatus used to form an image for one page. In particular, the apparatus includes a plurality of signal processing circuits, and each of the signal processing circuits is synchronized with a clock. The present invention relates to a signal processing apparatus and an image forming apparatus in a state in which transmission and reception and processing are performed.

  Various apparatuses such as signal processing apparatuses and image forming apparatuses have a plurality of signal processing circuits (signal processing units, signal processing boards, signal processing devices), and perform processing while exchanging signals with these plurality of signal processing circuits. Is configured to run.

  Here, the plurality of signal processing circuits are disposed between different devices, the signal processing circuits disposed on different substrates of the same device, and disposed on the same substrate of the same device. Various cases such as a signal processing circuit are conceivable.

  In this signal processing apparatus, in order to perform reliable signal processing and data exchange, the plurality of signal processing circuits need to be driven by clocks having the same frequency and the same timing.

  In signal transmission between signal processing circuits, inter-path devices such as a buffer for complementing the drive capability of the signal processing circuit and an inverting circuit for compensating the input / output logic of the signal processing circuit are arranged. It is generally done.

  Although this inter-path device is a simple operation such as a buffer or inverting circuit, since the high-speed signal is processed between the signal processing circuits, the delay time that occurs in this inter-path device changes, so setup and hold The condition may not be met and an error may occur.

  Here, the setup condition is the minimum time for stabilizing the input signal within a certain time before the clock input, and the hold condition is the minimum time for holding the input signal for a certain time after the clock input. .

  Here, FIG. 6 shows an example when the setup condition is satisfied, and (1) satisfies the setup condition with sufficient stabilization time. FIG. 7 shows an example in which the setup condition is not satisfied, and (2) shows a state in which the setup condition is not satisfied due to an insufficient stabilization time.

  Such an error that prevents the setup / hold condition from being met may occur due to various factors such as a change in the parts manufacturer of the device between paths due to a design change, a lot change of the same part due to a difference in the acquisition time of the devices between paths. is there.

  When such a problem occurs, it is common practice to add more inter-path devices for timing adjustment or to return to parts of the same manufacturer or lot as the original parts. Yes.

As described above, when the setup / hold condition cannot be satisfied, it is dealt with by changing the parts, and there is no prior art to deal with by electrical processing. A technique for controlling the delay time by changing the length of the signal line between the signal processing circuits is described, for example, in Patent Document 1 below.
Japanese Patent Laid-Open No. 10-234110 (first page, FIG. 1)

  In order to process the same data at the same timing (data exchange, signal processing) by the plurality of signal processing circuits described above, it is not sufficient for each signal processing circuit to perform signal processing at the same timing, and the path between the signal processing circuits. It is necessary to consider the delay time of the inter-device (buffer, logic inversion circuit). In order to satisfy the setup and hold conditions, it is necessary to strictly consider the parts manufacturer and the acquisition time of the inter-path device so that the delay time does not change.

  However, it is not easy to strictly manage small and simple inter-path devices such as buffers and logic inversion circuits due to design changes during trial production and mass production, or mass production processes.

  In addition, there may be a problem in that a minute change that is not announced for an inter-path device cannot be grasped by the side that designs and manufactures the signal processing circuit and the image forming apparatus.

  In addition, even if the same equipment is used, the length of the bundles may change due to changes in the substrate layout of the signal processing circuit within the same equipment, or the delay may change even with bundles of the same length due to changes in materials. Changes may occur depending on the situation.

  For this reason, even if the device was operating without any problems at the time of initial design, the delay caused by the change of the device between paths (intentional change or unintentional change) changes, which causes problems in the signal processing operation. Can occur.

  The present invention has been made to solve the above-described problems, and its purpose is to perform signal processing capable of performing normal signal processing without being affected by a change in delay time in an inter-path device. An apparatus and an image forming apparatus are provided.

That is, the present invention as means for solving the problems is as described below.
(1) The invention according to claim 1 is a signal processing circuit for performing signal processing on an input signal from another circuit or another device on the basis of a clock, and a phase adjusting circuit for adjusting the phase of the clock. The signal processing circuit monitors the status of the output signal that is output and changes the phase adjustment amount of the phase adjustment circuit so that the signal processing circuit does not satisfy the setup / hold condition And a control means for determining the phase adjustment amount so as to avoid the error phase point.

  According to the present invention, the phase adjustment amount with respect to the clock of the phase adjustment circuit is changed while monitoring the state of the output signal output by the signal processing circuit, and the signal processing circuit does not satisfy the setup / hold condition. An error phase point that generates an error is detected, and control is performed to determine a phase adjustment amount so as to avoid the error phase point.

  (2) The invention according to claim 2 is a signal processing circuit for performing signal processing on an input signal from another circuit or another device on the basis of a clock, and a phase adjustment circuit for adjusting the phase of the input signal And changing the phase adjustment amount of the phase adjustment circuit while monitoring the state of the output signal that is output by being subjected to signal processing by the signal processing circuit, so that the signal processing circuit does not satisfy the setup / hold condition. And a control unit that detects an error phase point that generates an error and determines the phase adjustment amount so as to avoid the error phase point.

  According to the present invention, the signal processing circuit can satisfy the setup / hold condition by changing the phase adjustment amount with respect to the input signal of the phase adjustment circuit while monitoring the state of the output signal output by the signal processing circuit. An error phase point that causes an error is detected, and control is performed to determine the phase adjustment amount so as to avoid the error phase point.

  (3) In the invention according to claim 3, the phase adjustment circuit delays a signal to be phase-adjusted to generate a plurality of delay signals having different delay times, and at least two in synchronization with the clock. A synchronization detection unit that detects two delay signals, and a delay signal selection unit that selects and outputs a predetermined delay signal from the delay chain unit according to the determination by the control unit, the control unit, 2. The phase of a delay signal obtained by adding a half clock period to the detected error phase point is determined as an amount to be phase-adjusted by the phase adjustment circuit. 2. The signal processing device according to 2.

  In the present invention, the delay chain unit delays the signal to be phase-adjusted to generate a plurality of delay signals having different delay times, and the synchronization detection unit detects at least two delay signals synchronized with the clock. When the predetermined delay signal is selected and output by the delay signal selection unit, the phase of the delay signal obtained by adding a clock 1/2 cycle to the error phase point detected as an error is adjusted. It is determined as an amount to be phase adjusted by the circuit.

  (4) In the invention according to claim 4, each part of the signal processing circuit, the phase adjustment circuit and the control means is constituted by a digital circuit. A signal processing apparatus according to claim 1.

  In the present invention, each part of the signal processing device including the signal processing circuit, the phase adjustment circuit, and the control means is composed of a digital circuit, so that the phase that avoids the error phase point detected as causing an error in each part. Adjustment can be performed easily, accurately and digitally.

  (5) The invention according to claim 5 is a signal processing circuit for performing signal processing relating to image formation on an input signal from another circuit or another device with reference to the clock, and phase adjustment of the clock. While monitoring the state of the phase adjustment circuit and the output signal output after being processed by the signal processing circuit, the phase adjustment amount of the phase adjustment circuit is changed, and the signal processing circuit satisfies the setup / hold condition. An image forming apparatus comprising: a control unit that detects an error phase point that does not satisfy the error and generates an error, and determines the phase adjustment amount so as to avoid the error phase point.

  According to the present invention, the phase adjustment amount with respect to the clock of the phase adjustment circuit is changed while monitoring the state of the output signal output by the signal processing circuit, and the signal processing circuit does not satisfy the setup / hold condition. An error phase point that generates an error is detected, and control is performed to determine a phase adjustment amount so as to avoid the error phase point.

  (6) The invention according to claim 6 is a signal processing circuit for performing signal processing related to image formation on an input signal from another circuit or another device on the basis of a clock, and phase adjustment of the input signal And a phase adjustment amount of the phase adjustment circuit is changed while monitoring a state of an output signal output after being processed by the signal processing circuit. An image forming apparatus comprising: a control unit that detects an error phase point that does not satisfy the condition and generates an error, and determines the phase adjustment amount so as to avoid the error phase point.

  According to the present invention, the signal processing circuit can satisfy the setup / hold condition by changing the phase adjustment amount with respect to the input signal of the phase adjustment circuit while monitoring the state of the output signal output by the signal processing circuit. An error phase point that causes an error is detected, and control is performed to determine the phase adjustment amount so as to avoid the error phase point.

  (7) In the invention according to claim 7, the phase adjustment circuit delays a signal to be phase-adjusted to generate a plurality of delay signals having different delay times, and at least two in synchronization with the clock. A synchronization detection unit that detects two delay signals, and a delay signal selection unit that selects and outputs a predetermined delay signal from the delay chain unit according to the determination by the control unit, the control unit, 6. The phase of a delay signal obtained by adding a clock 1/2 period to the detected error phase point is determined as an amount to be phase-adjusted by the phase adjustment circuit. 6. The image forming apparatus according to 6.

  In the present invention, the delay chain unit delays the signal to be phase-adjusted to generate a plurality of delay signals having different delay times, and the synchronization detection unit detects at least two delay signals synchronized with the clock. When the predetermined delay signal is selected and output by the delay signal selection unit, the phase of the delay signal obtained by adding a clock 1/2 cycle to the error phase point detected as an error is adjusted. It is determined as an amount to be phase adjusted by the circuit.

  (8) In the invention according to claim 8, each part of the signal processing circuit, the phase adjustment circuit, and the control means is constituted by a digital circuit. An image forming apparatus as described above.

  In the present invention, each part of the signal processing device including the signal processing circuit, the phase adjustment circuit, and the control means is constituted by a digital circuit, so that the error phase point detected as an error in each part is detected. The phase adjustment can be easily and accurately performed digitally.

As described above, according to the present invention, the following effects can be obtained.
(1) In the first aspect of the present invention, the signal processing circuit changes the phase adjustment amount with respect to the clock of the phase adjustment circuit while monitoring the state of the output signal that is output after being subjected to signal processing by the signal processing circuit. An error phase point that generates an error without satisfying the setup and hold condition is detected, and control is performed to determine the phase adjustment amount so as to avoid the error phase point.

  Such clock phase adjustment makes it possible to satisfy the setup / hold condition, and to perform normal signal processing without being affected by a change in delay time in the device between paths.

  (2) In the invention according to claim 2, the signal processing circuit changes the phase adjustment amount with respect to the input signal of the phase adjustment circuit while monitoring the state of the output signal that is output by the signal processing circuit. Detects an error phase point that generates an error without satisfying the setup / hold condition, and performs control to determine the phase adjustment amount so as to avoid the error phase point.

  Such a phase adjustment of the input signal makes it possible to satisfy the setup / hold condition, and to perform normal signal processing without being affected by a change in the delay time in the inter-path device.

  (3) In the invention according to claim 3, a plurality of delay signals having different delay times are generated by delaying the signal to be phase-adjusted by the delay chain unit, and at least two delay signals synchronized with the clock are detected by the synchronization detection unit. When the delay signal selection unit selects and outputs a predetermined delay signal from the delay chain unit, a delay obtained by adding a clock 1/2 cycle to the error phase point detected as causing an error The phase of the signal is determined as an amount to be phase adjusted by the phase adjustment circuit.

  In this way, the setup / hold condition is stabilized by adjusting the phase of the clock or input signal by adjusting the phase of the error phase point that generates the error plus the clock 1/2 period as the amount to be adjusted. Therefore, normal signal processing can be performed without being affected by a change in delay time in the device between paths.

  (4) In the invention according to claim 4, since each part of the signal processing device including the signal processing circuit, the phase adjustment circuit, and the control means is composed of a digital circuit, it is detected that an error occurs in each part. Therefore, it is possible to easily and accurately perform the phase adjustment to avoid the error phase point. By using this digital circuit, each part can be configured at low cost. Furthermore, the configuration with a digital circuit makes it possible to obtain a single chip. As a result, the wiring length can be shortened, the control can be facilitated, and the accuracy can be further improved.

  (5) In the invention according to claim 5, the signal processing circuit changes the phase adjustment amount with respect to the clock of the phase adjustment circuit while monitoring the state of the output signal output by the signal processing circuit. An error phase point that generates an error without satisfying the setup and hold condition is detected, and control is performed to determine the phase adjustment amount so as to avoid the error phase point.

  Such clock phase adjustment makes it possible to satisfy the setup / hold condition, and to perform normal signal processing without being affected by a change in delay time in the device between paths.

  (6) In the invention according to claim 6, the signal processing circuit changes the phase adjustment amount with respect to the input signal of the phase adjustment circuit while monitoring the state of the output signal output by the signal processing circuit. Detects an error phase point that generates an error without satisfying the setup / hold condition, and performs control to determine the phase adjustment amount so as to avoid the error phase point.

  Such a phase adjustment of the input signal makes it possible to satisfy the setup / hold condition, and to perform normal signal processing without being affected by a change in the delay time in the inter-path device.

  (7) In the invention according to claim 7, a plurality of delay signals having different delay times are generated by delaying a signal to be phase-adjusted by the delay chain unit, and at least two delay signals synchronized with the clock are detected by the synchronization detection unit. When the delay signal selection unit selects and outputs a predetermined delay signal from the delay chain unit, a delay obtained by adding a clock 1/2 cycle to the error phase point detected as causing an error The phase of the signal is determined as an amount to be phase adjusted by the phase adjustment circuit.

  In this way, the setup / hold condition is stabilized by adjusting the phase of the clock or input signal by adjusting the phase of the error phase point that generates the error plus the clock 1/2 period as the amount to be adjusted. Therefore, normal signal processing can be performed without being affected by a change in delay time in the device between paths.

  (8) In the invention according to claim 8, since each part of the signal processing device including the signal processing circuit, the phase adjustment circuit, and the control means is composed of a digital circuit, it is detected that an error occurs in each part. In addition, the phase adjustment for the error phase point can be easily and accurately performed digitally. By using this digital circuit, each part can be configured at low cost. Furthermore, the configuration with a digital circuit makes it possible to obtain a single chip. As a result, the wiring length can be shortened, the control can be facilitated, and the accuracy can be further improved.

  Hereinafter, specific examples of the best mode for carrying out the present invention (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. Here, an embodiment of an image forming apparatus having a plurality of signal processing devices is taken as a specific example.

<Overview of signal processing apparatus of this embodiment>
In the image forming apparatus 1000 of this embodiment, the signal processed by the signal processing apparatus 1100 is further processed by the signal processing apparatus 1200. The output of the signal processing device 1100 is supplied to the input of the signal processing device 1200 via inter-path devices 1012 to 1014 such as buffers and logic inversion circuits. Further, the same clock as that of the signal processing apparatus 1100 is supplied to the signal processing apparatus 1200 via an inter-path device 1011 such as a buffer or a logic inversion circuit.

  Note that the signal processing device 1200 is configured to have the characteristic configuration of the present embodiment. That is, a signal processing circuit 1220 that performs signal processing on an input signal from another circuit or another device on the basis of a clock, a phase adjustment circuit 1210 that adjusts the phase of the clock, and the signal processing circuit 1220 An error in which the signal processing circuit 1220 changes the phase adjustment amount of the phase adjustment circuit 1210 while monitoring the state of the output signal output after the signal processing, and the signal processing circuit 1220 does not satisfy the setup / hold condition and generates an error. And a control unit 1201 that detects a phase point and determines a phase adjustment amount for a clock or an input signal so as to avoid the error phase point.

  Here, a state in which the phase adjustment circuit 1210 is disposed only in the signal processing device 1200 is shown, but a similar phase adjustment circuit may exist in the signal processing device 1100 as well. Here, a state in which the embodiment is applied to the signal processing device 1200 affected by the inter-path devices 1011 to 1014 is shown.

  Here, the inter-path devices 1011 to 1014 include a buffer for supplementing the drive capability of the signal processing circuit and an inverting circuit for supplementing the input / output logic of the signal processing circuit in signal transmission between the signal processing circuits. , And so on.

  Further, in the phase adjustment circuit 1210, a delay chain section 1211 that generates a plurality of delay signals having different delay times by finely delaying the clock, and at least two delay signals synchronized with the clock from among a large number of delay signals As a delay detection unit 1212 that detects (synchronization detection), a synchronization switching unit 1213 that performs synchronization switching, and a delay signal selection unit that selects and outputs a phase-adjusted clock from among a large number of delay signals A selector 1214 and a table 1215 in which various data are stored are included.

  Further, as will be described later, the control unit 1201 determines the phase of the delayed signal obtained by adding a clock 1/2 cycle to the error phase point at which the signal processing circuit generates an error without satisfying the setup / hold condition. The amount of phase adjustment is determined by the adjustment circuit 1210.

The image forming apparatus 1000 including the signal processing apparatus 1200 has the characteristics described in the following (1) to (3).
(1) While monitoring the state of the output signal output by the signal processing circuit, the phase adjustment amount with respect to the clock of the phase adjustment circuit is changed so that the signal processing circuit does not satisfy the setup / hold condition. An error phase point that generates an error is detected, and control is performed to determine the phase adjustment amount so as to avoid the error phase point. Such clock phase adjustment makes it possible to satisfy the setup / hold condition, and to perform normal signal processing without being affected by a change in delay time in the device between paths.

  (2) A signal to be phase-adjusted is delayed by the delay chain unit to generate a plurality of delay signals having different delay times, and at least two delay signals synchronized with the clock are detected by the synchronization detection unit. When a predetermined delay signal is selected and output by the delay signal selector, the phase of the delay signal obtained by adding a 1/2 clock cycle to the error phase point detected as causing an error To determine the amount of phase adjustment. In this way, the setup / hold condition is stabilized by adjusting the phase of the clock or input signal by adjusting the phase of the error phase point that generates the error plus the clock 1/2 period as the amount to be adjusted. Therefore, normal signal processing can be performed without being affected by a change in delay time in the device between paths.

  (3) Since each part of the signal processing device including the signal processing circuit, the phase adjustment circuit, and the control means is composed of a digital circuit, the phase adjustment avoids the error phase point detected as an error in each part. Can be easily and accurately performed digitally. By using this digital circuit, each part can be configured at low cost. Furthermore, the configuration with a digital circuit makes it possible to obtain a single chip. As a result, the wiring length can be shortened, the control can be facilitated, and the accuracy can be further improved.

<Detailed description of signal processing device>
Hereinafter, embodiments of the signal processing apparatus of the present invention will be described in detail.
(A) Delay signal generation:
Here, the delay chain unit 1211 includes delay elements such as inverters in a chain shape so that delay signals having slightly different phases can be generated at least for one clock cycle or more, preferably about two cycles. It is preferable that they are connected in cascade.

  For example, as shown in FIG. 2, a circuit in which delay elements (delay cells # 1 to #n) having a minute delay time with respect to a clock cycle are arranged in a chain shape, and a delay signal of each delay element is transmitted. Output.

  FIG. 2 shows a circuit of the delay chain unit 1211 that receives a clock. The output that does not pass through the delay cell is DL0, the output that passes through one stage of the delay cell (delay cell # 1) is DL1, and the delay cell is two stages. The output passing through (delay cell # 1 to delay cell # 2) is DL2, and the output passing through n delay cells (delay cell # 1 to delay cell #n) is DLn. As for this delay chain section, the delay element is connected to the inversion logic with a minute delay value such as an inverter in the subsequent stage of the delay element, thereby minimizing duty collapse and making the output interval of each stage as fine as possible. It is desirable to use a circuit and layout.

  FIG. 3 shows a state of a delay signal obtained by the circuit configuration of the delay chain unit 1211 in FIG. 2. FIG. 3A shows a clock (DL0) without delay, which is input to the phase adjustment circuit 1210. Is equal to the clock. In the following, the number after the DL indicates the number of delay stages. The output through one delay cell is DL1, the output through two delay cells is DL2, the output through 100 delay cells is DL100, and the delay cell is The output through 200 stages is DL200. Here, DL0, DL100, and DL200 are shown in phase.

(B) Synchronization detection:
In the signal processing apparatus of the present embodiment, when performing phase adjustment, the phase of the delayed signal obtained by adding a clock 1/2 cycle to the detected error phase point is determined as an amount to be phase adjusted by the phase adjustment circuit. It is characterized by that. Then, as a clock ½ cycle, ½ of the number of delay signal stages (synchronization stage number) corresponding to one clock cycle is used.

  The synchronization detection unit 1212 is detection means for detecting the number of stages (synchronization points) of the delay signal synchronized with the clock (DL0) in which no delay occurs in the delay signal group (FIG. 1 (1)), The synchronization point information (FIG. 1 (2)) is output to the control unit 1201.

  Here, the synchronization detection unit 1212 uses the first synchronization point information SP1 synchronized with the clock (DL0) first and the clock (DL0) second in the delay signal group (FIG. 1 (1)). It is preferable that the synchronized second synchronization point information SP2 can be output.

  Note that there is a possibility that the delay times of the plurality of delay signals from the delay chain unit 1211 have changed due to changes in the delay times of the individual delay cells due to the influence of temperature changes and the like. Therefore, in this way, the number of stages indicating how many delay signals are included in a predetermined non-fluctuating time (in this embodiment, a clock cycle) is detected.

  In this way, even if the delay time of each delay cell changes due to a temperature change, there is an advantage that the entire device is not affected at all by using an index of the number of delay stages at a time that does not change. is there. Therefore, it is not necessary to use expensive parts for the delay cell itself.

  In the example of FIG. 3, the DL100 at the 100th stage coincides with the DL200 at the 200th stage with respect to DL0. Therefore, SP1 = 100 and SP2 = 200. The synchronization detection unit 1212 outputs the SP1 and SP2 as synchronization point information to the control unit 1201. Note that the control unit 1201 calculates, from this synchronization point information, the number of delay signal stages (number of synchronization stages) PRD = 100 in one clock cycle.

(C) Error phase point detection:
Error phase point detection is performed in accordance with an instruction from the control unit 1201 when the image forming apparatus is activated or idle (not in operation).

  First, the control unit 1201 compares an input signal to the signal processing circuit 1220 and an output signal from the signal processing circuit 1220 to determine whether an error has occurred in the signal processing of the signal processing circuit 1220 (S1 in FIG. 4). .

  If no error occurs in the signal processing of the signal processing circuit 1220 (YES in S1 in FIG. 4), it is considered that the setup condition is satisfied with a sufficient stabilization time as shown in FIG. 6A (FIG. 5A). (See (b)).

  Here, the control unit 1201 gives an instruction to the synchronization switching unit 1213, and selects and outputs the delay signal DL99 whose phase is advanced from the delay signal DL100 synchronized with DL0 equal to the clock at that time from the selector 1214 ( FIG. 4S3, FIG. 5 (c)).

  Then, the control unit 1201 compares the input signal of the signal processing circuit 1220 that operates using the delayed signal DL99 with the advanced phase as a clock with the output signal from the signal processing circuit 1220, and an error occurs in the signal processing of the signal processing circuit 1220. It is determined whether it has occurred (S4 in FIG. 4).

  If no error has occurred in the signal processing of the signal processing circuit 1220 (NO in FIG. 4 S4), it is considered that the setup condition is satisfied with a sufficient stabilization time as shown in FIG. Then, an instruction is given to the synchronization switching unit 1213, and the selector 1214 selects and outputs the delayed signal DL98 having a more advanced phase (FIG. 4S3, FIG. 5 (d)).

  Then, the control unit 1201 compares the input signal of the signal processing circuit 1220 that operates using the delayed signal DL98 having the advanced phase as a clock with the output signal from the signal processing circuit 1220, and an error occurs in the signal processing of the signal processing circuit 1220. It is determined whether it has occurred (S4 in FIG. 4).

  In this way, the delayed signals (FIGS. 5E, 5F,...) Sequentially advanced from the state where no error has occurred to the state where the error occurs are used as clocks (FIGS. 4S3 and S4). ).

  Then, the control unit 1201 determines the first delay signal confirmed by the control unit 1201 that an error has occurred as an error phase point (S7 in FIG. 4). The control unit 1201 stores this error phase point information in the table 1215 (FIG. 1 (3)).

  If an error occurs in the signal processing of the signal processing circuit 1220 in the first determination (NO in S1 in FIG. 4), the setup condition is not satisfied due to an insufficient stabilization time as shown in FIG. 7 (2). Conceivable.

  In this case, the control unit 1201 gives an instruction to the synchronization switching unit 1213, and selects and outputs the delayed signal DL1 whose phase is delayed from DL0 equal to the clock at that time from the selector 1214 (S5 in FIG. 4).

  Then, the control unit 1201 compares the input signal of the signal processing circuit 1220 that operates using the delayed signal DL1 whose phase is delayed as a clock with the output signal from the signal processing circuit 1220, and an error occurs in the signal processing of the signal processing circuit 1220. It is determined whether it has occurred (S6 in FIG. 4).

  If the error is not solved by the signal processing of the signal processing circuit 1220 (NO in FIG. 4 S6), it is considered that the setup condition is not satisfied due to insufficient stabilization time as shown in FIG. 7 (2). 1201 gives an instruction to the synchronization switching unit 1213, and the selector 1214 selects and outputs the delayed signal DL2 whose phase is delayed (S5 in FIG. 4).

  Then, the control unit 1201 compares the input signal of the signal processing circuit 1220 that operates using the delayed signal DL2 delayed in phase as the clock with the output signal from the signal processing circuit 1220, and an error occurs in the signal processing of the signal processing circuit 1220. It is determined whether it has not been resolved (S6 in FIG. 4).

In this way, a delayed signal whose phase is sequentially delayed is used as a clock from the state where an error has occurred to the state where the error is eliminated (S5 and S6 in FIG. 4).
Then, the control unit 1201 determines the delay signal immediately before the first delay signal confirmed by the control unit 1201 that the error has been resolved as an error phase point (S7 in FIG. 4). The control unit 1201 stores this error phase point information in the table 1215 (FIG. 1 (3)).

(D) Correction amount calculation:
Here, based on the synchronization point information (FIG. 4S8, FIG. 1 (2)) from the synchronization detector 1212 and the error phase point information read from the table 1215 (FIG. 4S7, FIG. 1 (3)), The control unit 1201 obtains the phase adjustment amount (FIG. 1 (4)). Based on this phase adjustment amount, the synchronization switching unit 1213 outputs a select signal (FIG. 1 (5)) indicating which phase of the delay signal should be selected from the delay signal group (FIG. 1 (1)). To do.

  Here, the control unit 1201 should adjust the phase of the delayed signal obtained by adding 1/2 of the number of synchronization stages (1/2 clock cycle) to the detected error phase point by the phase adjustment circuit 1210. The amount is determined (S9 in FIG. 4).

  Here, since the error phase point is a timing at which an error starts to occur, adding a half of the clock period to the timing (delaying the phase) has sufficient margin for error occurrence before and after that. It can be timing.

  In this way, the phase of the clock or the input signal is adjusted by setting the phase of 1/2 of the number of synchronization stages (1/2 cycle of the clock) to the phase to be adjusted with respect to the error phase point causing the error. The hold condition can be satisfied in a stable state, and normal signal processing can be performed without being affected by the change in delay time in the device between paths.

  That is, the number of stages of the delay signal to be selected by the selector 1214 is determined from the number of stages of the delayed signal at the detected error phase point and 1/2 of the number of synchronization stages PRD as the phase adjustment amount. Note that the control unit 1201 also stores phase adjustment amount information in the table 1215. Here, in relation to the phase adjustment amount, the number of stages of the delayed signal at the detected error phase point, information about the number of stages of 1/2 of the number of synchronization stages PRD, information about the number of stages of the delayed signal to be selected by the selector 1214, Is stored in the table 1215.

(E) Pulse selection, clock output:
The selector 1214 receives the select signal (FIG. 1 (5)) from the synchronization switching unit 1213, selects a delay signal having a corresponding phase from the delay signal group (FIG. 1 (1)), and generates a clock (FIG. 1 (6) )) To the signal processing circuit 1220.

(F) Operation:
(F-1) Through the processes (A) to (E) described above, the phase adjustment amount is determined in accordance with an instruction from the control unit 1201 when the image forming apparatus is activated or idle (not operating). . Then, in relation to the phase adjustment amount, the number of stages of the delayed signal at the detected error phase point, the information on the number of synchronization stages PRD (or the information on the number of stages of 1/2 of the PRD), and the delay signal to be selected by the selector 1214 The table number is stored in the table 1215.

  (F-2) During normal operation, while referring to the information on the phase adjustment amount stored in the table 1215 in (F-1) above, applying the normal synchronization stage number and performing phase adjustment Operate. That is, the ratio of the delay stage number of the PRD and the error phase point at the time of determining the phase adjustment amount is applied to the normal synchronization stage number, and the error phase point expected at that time, the stage number of 1/2 of the synchronization stage number at that time, is obtained. The phase adjustment is performed by calculating the number of stages of delay signals to be selected by the selector 1214 at that time.

  In this way, even if the delay time of each delay element in the delay chain section changes during actual operation, using the indicator of the number of delay stages in the time (clock cycle) that does not change will affect the entire device. There is an advantage that there is no. Therefore, it is not necessary to use expensive components for the delay cell itself when obtaining the phase adjustment amount and when performing phase adjustment according to the obtained phase adjustment amount.

<Other embodiments>
In the above description of the embodiment, the phase adjustment circuit 1210 is applied to the clock to adjust the phase of the clock. Actually, it is only necessary to adjust the phase between the input signal to the signal processing circuit 1220 and the clock, so that the phase adjustment circuit 1210 can be operated on the input signal of the signal processing circuit 1220. It is also possible to cause the phase adjustment circuit 1210 to act on both the input signal of the signal processing circuit 1220 and the clock to generate a relative phase difference. In either case, the setup / hold condition can be satisfied in a stable state by performing the phase control so as to satisfy the phase adjustment amount described above.

1 is a configuration diagram illustrating an overall electrical configuration of a signal processing apparatus according to an embodiment of the present invention. It is a block diagram which shows the electric constitution of the principal part of the signal processing apparatus of one Embodiment of this invention. It is a time chart explaining the operation state of the signal processing apparatus of one Embodiment of this invention. It is a flowchart explaining the operation state of the signal processing apparatus of one Embodiment of this invention. It is a time chart explaining the operation state of the signal processing apparatus of one Embodiment of this invention. It is a time chart explaining the operation state of the conventional signal processing apparatus. It is a time chart explaining the operation state of the conventional signal processing apparatus.

Explanation of symbols

1000 signal processing device 1100 signal processing device 1200 signal processing device 1210 phase adjustment circuit 1220 signal processing circuit

Claims (8)

A signal processing circuit that performs signal processing on an input signal from another circuit or another device with reference to a clock; and
A phase adjustment circuit for adjusting the phase of the clock;
While monitoring the state of the output signal that has been processed by the signal processing circuit, the phase adjustment amount of the phase adjustment circuit is changed, and the signal processing circuit does not satisfy the setup / hold condition and generates an error. Control means for detecting an error phase point that occurs and determining the phase adjustment amount so as to avoid the error phase point;
A signal processing apparatus comprising: A signal processing circuit that performs signal processing on an input signal from another circuit or another device with reference to a clock; and
A phase adjustment circuit for adjusting the phase of the input signal;
While monitoring the state of the output signal that has been processed by the signal processing circuit, the phase adjustment amount of the phase adjustment circuit is changed, and the signal processing circuit does not satisfy the setup / hold condition and generates an error. Control means for detecting an error phase point that occurs and determining the phase adjustment amount so as to avoid the error phase point;
A signal processing apparatus comprising: The phase adjustment circuit delays a signal to be phase-adjusted to generate a plurality of delay signals having different delay times, a synchronization detection unit that detects at least two delay signals synchronized with the clock, A delay signal selection unit that selects and outputs a predetermined delay signal from the delay chain unit according to the determination by the control means,
The control means determines the phase of the delayed signal obtained by adding a clock ½ period to the detected error phase point as an amount to be phase adjusted by the phase adjustment circuit.
The signal processing apparatus according to claim 1, wherein the signal processing apparatus is a signal processing apparatus. Each part of the signal processing circuit, the phase adjustment circuit and the control means is composed of a digital circuit,
The signal processing device according to claim 1, wherein the signal processing device is a signal processing device. A signal processing circuit that performs signal processing related to image formation on an input signal from another circuit or another device with reference to a clock; and
A phase adjustment circuit for adjusting the phase of the clock;
While monitoring the state of the output signal that has been processed by the signal processing circuit, the phase adjustment amount of the phase adjustment circuit is changed, and the signal processing circuit does not satisfy the setup / hold condition and generates an error. Control means for detecting an error phase point that occurs and determining the phase adjustment amount so as to avoid the error phase point;
An image forming apparatus comprising: A signal processing circuit that performs signal processing related to image formation on an input signal from another circuit or another device with reference to a clock; and
A phase adjustment circuit for adjusting the phase of the input signal;
While monitoring the state of the output signal that has been processed by the signal processing circuit, the phase adjustment amount of the phase adjustment circuit is changed, and the signal processing circuit does not satisfy the setup / hold condition and generates an error. Control means for detecting an error phase point that occurs and determining the phase adjustment amount so as to avoid the error phase point;
An image forming apparatus comprising: The phase adjustment circuit delays a signal to be phase-adjusted to generate a plurality of delay signals having different delay times, a synchronization detection unit that detects at least two delay signals synchronized with the clock, A delay signal selection unit that selects and outputs a predetermined delay signal from the delay chain unit according to the determination by the control means,
The control means determines the phase of the delayed signal obtained by adding a clock ½ period to the detected error phase point as an amount to be phase adjusted by the phase adjustment circuit.
The image forming apparatus according to claim 5, wherein the image forming apparatus is an image forming apparatus. Each part of the signal processing circuit, the phase adjustment circuit and the control means is composed of a digital circuit,
The image forming apparatus according to claim 5, wherein the image forming apparatus is an image forming apparatus.

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